TW201607040A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.

Description

Semiconductor device and method of manufacturing same

The present invention relates to an integrated circuit device, and more particularly to a semiconductor device and a method of fabricating the same.

In recent years, due to the rapid development of communication devices such as mobile communication devices and personal communication devices, wireless communication products such as mobile phones and base stations have shown significant growth. Among wireless communication products, high voltage components of a lateral double diffused metal oxide semiconductor (LDMOS) device are often used as components of a radio frequency (900 MHz-2.4 GHz) circuit.

The lateral double-diffused MOS device not only has a high operating bandwidth, but also has high output power due to its ability to withstand higher breakdown voltages, and is therefore suitable for use as a power amplifier for wireless communication products. In addition, since the lateral double-diffused metal oxide semiconductor (LDMOS) device can be formed by using a conventional complementary metal oxide semiconductor (CMOS) process technology, the fabrication technology is relatively mature and can be made by using a cheaper tantalum substrate.

For RF circuit component applications, lateral double-diffused MOS devices require low gate-to-drain capacitance to improve their maximum operating frequency. In addition, the lateral double-diffused MOS device also requires a source-drain resistance value (ie, Ron). However, in order to obtain a low source-drain resistance value (Ron), it is necessary to increase The drift region and the gate interface of the lateral double-diffused MOS device will increase the gate-drain capacitance value. Accordingly, there is a need for a preferred lateral double diffused MOS device that combines the desired low gate-drain capacitance value with a low source-drain resistance value (Ron).

According to an embodiment, the present invention provides a semiconductor device comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer formed on the semiconductor substrate having the first conductivity type; a gate structure; On a portion of the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type; and a second doped region disposed on Adjacent to the semiconductor layer of the gate structure opposite to the second side of the first side, having a second conductivity type opposite to the first conductivity type; a third doping region disposed at the first One of the doped regions has the second conductivity type; a fourth doped region is disposed in one of the second doped regions, having the second conductivity type; and the plurality of fifth doped regions are separated Provided in the plurality of portions of the second doped region, having the first conductivity type, wherein the fifth doped regions are located between the fourth doped region and the gate structure; a sixth doping a region disposed under the first doped region An inner semiconductor layer, the contact with the semiconductor substrate; and an electrical contact, the third doped region is formed in the inner one of the first doped region, the doped region in contact with the sixth.

According to another embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a semiconductor layer on the semiconductor substrate having the first conductivity type; forming a a gate structure on one of the semiconductor layers; forming a first doped region adjacent to Having the first conductivity type in the semiconductor layer on a first side of the gate structure; forming a second doped region adjacent to the second side of the gate structure opposite to the first side a second conductivity type opposite to the first conductivity type; forming a third doped region in one of the first doped regions, having the second conductivity type; forming a fourth doping The region has a second conductivity type opposite to the first conductivity type in one of the second doping regions; forming a plurality of fifth doping regions in the plurality of portions of the second doping region, having the a first conductivity type, wherein the fifth doped regions are formed between the fourth doped region and the gate structure; forming an insulating layer in the second doped region, the gate structure and the third Forming a trench in one of the third doped region and the first doped region to expose a portion of the semiconductor layer under the first doped region; performing an ion a planting process for implanting a plurality of dopants of the first conductivity type to expose the semiconductor layer Forming a sixth doped region in the semiconductor layer, wherein the sixth doped region physically contacts the semiconductor substrate; and forming a conductive contact in the trench, wherein the conductive contact physically contacts the sixth doping Area.

The above described objects, features and advantages of the present invention will become more apparent and understood.

100‧‧‧Semiconductor substrate

102‧‧‧Semiconductor layer

104‧‧‧gate dielectric layer

106‧‧‧ gate electrode

108‧‧‧ Cover layer

108a‧‧‧ Main body

108b‧‧‧protrusion

110‧‧‧Ion implantation process

112‧‧‧Doped area

114‧‧‧ Cover layer

116‧‧‧Ion implantation process

118‧‧‧Doped area

120‧‧‧ Cover layer

122‧‧‧Ion implantation process

124‧‧‧Doped area

126‧‧‧Doped area

128‧‧‧Doped area

130‧‧‧Insulation

132‧‧‧ openings

134‧‧‧ trench

136‧‧‧Ion implantation process

138‧‧‧Doped area

140‧‧‧ Conductive layer

142‧‧‧ Conductive layer

144‧‧‧Interlayer dielectric layer

146‧‧‧ trench

148‧‧‧ Conductive layer

300‧‧‧ etching process

302‧‧‧ trench

304‧‧‧Insulation

G‧‧‧ gate structure

Figures 1, 3, 6, 9, 12, 15, 18, 21 and 24 are a series of top views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention; and Figure 2 is a cross-sectional view, Shows a section along line 2-2 of Figure 1 Figure 4 is a schematic cross-sectional view showing a section along line 4-4 of Figure 3; Figure 5 is a schematic cross-sectional view showing a section along line 5-5 of Figure 3 Figure 7 is a schematic cross-sectional view showing a section along the line 7-7 of Figure 6; Figure 8 is a schematic cross-sectional view showing a section along the line 8-8 of Figure 6; Figure 10 is a schematic cross-sectional view showing a section along the line 10-10 of Figure 8; Figure 11 is a schematic cross-sectional view showing a section along the line 11-11 of Figure 8; Figure 13 A cross-sectional view showing a section along a line 13-13 in Fig. 12; Fig. 14 is a cross-sectional view showing a section along a line 14-14 of Fig. 12; Fig. 16 is a The cross-sectional view shows a section along the line 16-16 in Figure 15; Figure 17 is a cross-sectional view showing a section along the line 17-17 in Figure 15; Figure 19 is a section , showing a section along the line 19-19 of Figure 18; Figure 20 is a section diagram showing the 18th Figure line 20-20 Figure 2 is a cross-sectional view showing a section along line 22-22 of Figure 21; and Figure 23 is a section showing a section along line 23-23 of Figure 21 Figure 25 is a schematic cross-sectional view showing a section along line 25-25 of Figure 24; and Figure 26 is a schematic cross-sectional view showing a section along line 26-26 of Figure 24; Figures 27, 30 and 33 are a series of top views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention; and Figure 28 is a cross-sectional view showing the line 28-28 along line 27 Figure 1 is a cross-sectional view showing a section along the line 29-29 in Figure 27; and Figure 31 is a schematic cross-sectional view showing one of the line segments 31-31 along the 30th figure. Fig. 32 is a cross-sectional view showing a section along the line 32-32 in Fig. 30; Fig. 34 is a schematic cross-sectional view showing a section along the line 34-34 in Fig. 33. And Figure 35 is a schematic cross-sectional view showing the line segment 35- along line 33 35 one profile situation.

Please refer to a series of schematic diagrams of FIGS. 1-26 to illustrate a method of fabricating a semiconductor device according to an embodiment of the present invention, wherein the first, third, sixth, ninth, twelve, fifteenth, eighteenth, twenty-first and twenty-fourth diagrams are A series of top view diagrams, while the 2nd, 4-5, 7-8, 10-11, 13-14, 16-17, 19-20, 22-23, and 25-26 plans show the first along the first , 3, 6, 9, 12, 15, 18, 21 and 24 in the picture 2, 2, 4-4, 5-5, 7-7, 8-8, 10-10, 11-11, 13-13, A schematic cross-sectional view of one of the 14-14, 16-16, 17-17, 19-19, 20-20, 22-22, 23-23, and 25-25, 26-26 segments, and respectively shown in the semiconductor device The production situation of one of the intermediate stages of the manufacturing method. A semiconductor device formed by the exemplary method of Figures 1-26 can be used as a lateral double diffused metal oxide semiconductor (LDMOS) device suitable for radio frequency circuit (RF) components.

Referring to Figures 1-2, first, a semiconductor substrate 100 such as a germanium substrate is provided. In one embodiment, the semiconductor substrate 100 has a first conductivity type such as a P-type and a range of 1E-3 ohm-cm (Ω-cm) to 10E-3 ohm-cm (Ω-cm). Resistivity. Next, a semiconductor layer 102 such as a silicon layer is formed on the semiconductor substrate 100 by one of methods such as epitaxial growth. The semiconductor layer 102 may be doped with a dopant of a first conductivity type such as a P-type, and has a resistivity of about 0.2 ohm-cm (Ω-cm) to 0.9 ohm-cm (Ω-cm). . In one embodiment, the resistivity of the semiconductor layer 102 is greater than the resistivity of the semiconductor substrate 100.

Next, one of the gate structure G is patterned on one of the semiconductor layers 102 along one direction of the Y direction in FIG. The gate structure G mainly includes a gate dielectric layer 104 and a gate electrode 106 sequentially formed on one portion of the semiconductor layer 102. Gate The gate dielectric layer 104 and the gate electrode 106 of the structure G may be formed using a conventional gate process, and the fabrication thereof will not be described in detail herein for the sake of simplicity. In one embodiment, the gate dielectric layer 104 may comprise a dielectric material such as hafnium oxide, and the gate electrode 106 may comprise a conductive material such as polycrystalline germanium or a combination of polycrystalline germanium and other materials such as metal or germanide.

Referring to FIGS. 3-5, a patterned mask layer 108 is formed on the semiconductor layer 102, and then an ion implantation process 110 is performed to form a doped region 112 on one side of the gate structure G (eg, In the left side of the semiconductor layer 102.

As shown in Figures 3-5, the patterned mask layer 108 includes a bulk portion 108a and a plurality of protrusion portions 108b associated therewith. The body portion 108a of the patterned mask layer 108 covers the gate structure G and portions of the semiconductor layer 102 on the right side of the gate structure G. Viewed from above, the projections 108b joined to the main body portion 108a are formed in a strip-like pattern and are formed separately on portions of the semiconductor layer adjacent to the left side of the gate structure G. The protrusions 108b extend along one of the X directions as in FIG. 3, and the direction is perpendicular to one of the gate structures G. In one embodiment, the patterned mask layer 108 can include a masking material such as a resist, such that the patterned mask layer 108 can be formed by processes such as lithography and etching (all not shown).

In addition, the dopants of the second conductivity type (eg, N-type) opposite to the first conductivity type are implanted in the ion implantation process 110 into portions of the semiconductor layer 102 exposed by the patterned mask layer 108. Within the semiconductor layer 102, a doped region 112 having a second conductivity type is formed. Yu Yishi In the embodiment, the doping region 112 has a dopant concentration of about 5E11 atoms/cm 2 to 9E13 atoms/cm 2 .

Referring to FIGS. 6-8, after removing the patterned mask layer 108 as shown in FIGS. 3-5, a patterned mask layer 114 is formed on the semiconductor layer 102 and then an ion implantation is performed. The process 116 is formed to form a doped region 118 in one of the semiconductor layers 102 on the other side (eg, the right side) of the gate structure G.

As shown in FIGS. 6-8, the patterned mask layer 114 covers portions of the gate structure G and the semiconductor layer 102 on the left side of the gate structure G. In one embodiment, the patterned mask layer 114 can include a masking material such as a resist, such that the patterned mask layer 114 can be formed by processes such as lithography and etching (all not shown).

In addition, the dopant of the first conductivity type (eg, P-type) is implanted into the portion of the semiconductor layer 102 exposed by the patterned mask layer 114 in the ion implantation process 116, and further in the semiconductor layer 102. A doped region 118 having a second conductivity type is formed in the portion. In one embodiment, the doped region 118 has a dopant concentration of about 1E12 atoms/cm<2> to 5E14 atoms/cm<2>.

Referring to FIGS. 9-11, after removing the patterned mask layer 114 shown in FIGS. 6-8, a patterned mask layer 120 is formed on the semiconductor layer 102 and then an ion implantation is performed. The process 122 is formed to form a doped region 124 within a plurality of portions of the semiconductor layer 102 on the left side of the gate structure G.

As shown in FIGS. 9-11, the patterned mask layer 120 covers the gate structure G, the doped region 112 and the doped region 118, and is exposed between the gate structure G and the doped region 112. a plurality of portions of the semiconductor layer 102 The doped regions 124 may be alternately formed in portions of the semiconductor layer 102 adjacent to the left side of the gate structure G and have a rectangular profile from above. In the ion implantation process, a first conductivity type dopant such as a P-type is implanted into a plurality of portions of the semiconductor layer 102 exposed by the patterned mask layer 120, thereby forming a number having the first conductivity type. The doped regions 124 are within a plurality of portions of the semiconductor layer 102 on the left side of the gate structure G. In one embodiment, the doped region 124 has a dopant concentration of about 5E11-9E13 atoms/cm 2 .

Referring to FIGS. 12-14, after removing the patterned mask layer 120 as shown in FIGS. 9-11, a patterned mask layer (not shown) is formed on the semiconductor substrate 102 and then performed. An ion implantation process (not shown) forms a doped region 126 and a doped region 128 within the doped regions 112 and 118 on opposite sides of the gate structure G, respectively. In one embodiment, the doped region 128 is formed in one of the doped regions 118, and the doped region 126 is formed in one of the doped regions 116 and has a second doping type such as an N-type and The ion implantation concentration of 1E14 atoms/cm 2 to 8E15 atoms/cm 2 , and the ion implantation process for forming the doping regions 126 and 128 may be ion implantation perpendicular to one surface of the semiconductor layer 102 . In one embodiment, the doped region 112 can serve as a drift region, and the doped regions 128 and 126 can serve as a source region and a drain region, respectively.

Furthermore, the structure as shown in FIGS. 12-14 may include a super junction structure formed by a plurality of doping regions 112 and a plurality of doping regions 124 staggeredly disposed on the semiconductor layer 102 along the Y direction ( Super-junction structure). The width of the doped region 112 in the super junction structure along the Y direction may be the same or different from the width of the doped region 124. Similarly, a spacing between the doped regions 112 of the super junction structure along the Y direction and between the doped regions 124 The distance can be the same or different.

Referring to FIGS. 15-17, an insulating layer 130 is then formed on the semiconductor layer 102 to conformably cover the top surface of the semiconductor layer 102 and the sidewalls and top surfaces of the gate structure G. Next, a patterning process (not shown) is performed to form an opening 132 in one of the insulating layers 130. As shown in FIGS. 15-17, the opening 132 exposes a portion of the doped region 128 such that the other portions of the semiconductor layer 102 and the top surface of the gate structure G are still covered by the insulating layer 130. In one embodiment, the insulating layer 130 may include an insulating material such as hafnium oxide and tantalum nitride, and it may be formed by a method such as chemical vapor deposition. An etch process (not shown) is then performed, using the patterned insulating layer 130 having openings 132 as an etch mask to form a trench 134 within the semiconductor layer 102 exposed for the opening 132. As shown in FIGS. 16-17, trench 134 is formed to have a depth that substantially penetrates one of doped regions 128 and 118.

Referring to FIGS. 18-20, the insulating layer 130 is used as an implantation mask to perform an ion implantation process 136 for implanting a first conductivity type dopant such as a P-type to a semiconductor layer exposed by the trench 134. A doped region 138 is formed in one of the portions of the semiconductor layer 102 between the doped region 118 and the semiconductor substrate 100. In one embodiment, doped region 138 has a first conductivity type, such as a P-type, and a dopant concentration of about 7E13-9E15 atoms/cm 2 . In one embodiment, the dopant concentration in the doped region 138 can be greater than the dopant concentration in the semiconductor layer 102.

Referring to Figures 21-23, a plurality of layers of conductive material are then deposited over the structure as shown in Figures 18-20, and then patterned to form a conductive layer 140 and a conductive layer 142. As shown in Figures 21-23, the conductive layer 140 conforms to the terrain. The surface of the insulating layer 130 is formed on the surface and the bottom surface of the semiconductor layer 102 exposed by the trench 134 and a plurality of sidewalls. Conductive layer 142 is formed on the surface of conductive layer 140 and fills trenches 134. As shown in FIGS. 22-23, the patterned conductive layers 140 and 142 are formed on the insulating layer 130 adjacent to the trench 134, and extend over the bottom surface of the trench 134 and a plurality of sidewalls to cover the semiconductor layer. 102 and the surface of the doped regions 128 and 118 exposed by the trench 134, and the conductive layers 140 and 142 also cover the gate structure G and a portion of the doped region 112 adjacent to the gate structure G. However, conductive layers 140 and 142 do not cover doped region 126. Portions of conductive layers 140 and 142 formed in trenches 134 can be used as conductive contacts. At this time, the doping region 138 physically contacts the bottom surface of the conductive layer 140 formed in the trench 134. In one embodiment, the conductive layer 140 may include a conductive material such as titanium-titanium nitride alloy (Ti-TiN), and the conductive layer 142 includes a conductive material such as tungsten.

Referring to Figures 24-26, a dielectric material such as cerium oxide or spin on glass (SOG) is deposited over the conductive layer 142 and the semiconductor layer 102, such that the dielectric material covers the conductive layer 142 and the insulating layer. 130 and gate structure G, thereby forming an interlayer dielectric layer 144 having a generally flat top surface. A trench 146 is then formed in one of the interlayer dielectric layer 144 and the insulating layer 130 over one of the doped regions 126 by an implementation of a patterning process (not shown) including a lithography and etching process. And trench 146 exposes one of doped regions 146. Next, a conductive layer 148 is deposited on the interlayer dielectric layer 144 and filled with trenches 146 to contact the doped regions 126. Conductive layer 148 formed in trench 146 can serve as a conductive contact. In an embodiment, the conductive layer 146 may comprise a conductive material such as titanium-titanium nitride alloy or tungsten. Thus, as shown in Figures 24-26, A lateral double diffused metal oxide semiconductor (LDMOS) device suitable for use in radio frequency (RF) circuit components in accordance with an embodiment of the present invention is generally completed.

In one embodiment, the gate structure G and the doped regions 126 and 128 of the semiconductor device as shown in FIGS. 25-26 may be electrically connected (not shown), and the region having the first conductivity type is The P-type region, and the region of the second conductivity type are N-type regions, such that the formed semiconductor device is an N-type lateral double-diffused metal oxide semiconductor (n-type LDMOS) device. At this time, the doping region 128 can serve as a source region, and the doping region 126 can serve as a drain region.

In an embodiment, during operation of the semiconductor device as shown in FIGS. 24-26, a current (not shown) may be caused to flow laterally through the gate structure G from its drain terminal (eg, doped region 126). After the lower channel (not shown) flows toward the source terminal (eg, doped region 128), then the doped region 118, the conductive layers 140 and 142, and the doped region 138 are guided to reach the semiconductor substrate 100, thus A source wire bond is not required and the semiconductor device can have a reduced thermal resistance.

In addition, in the semiconductor device shown in FIGS. 24-26, the doping regions 112 and 118 are connected to the gate structure G and the pn doped region including the staggered arrangement (refer to FIG. 12-14). The surface structure is formed after it is formed. Therefore, the semiconductor device can have low gate-dipper capacitance values, low source-drain resistance values, and high breakdown voltage electrical characteristics.

Please refer to a series of schematic diagrams of FIGS. 27-35 for illustrating a method of fabricating a semiconductor device according to another embodiment of the present invention, wherein FIGS. 27, 30 and 35 are schematic views of a top view, and FIGS. 28-29, Plans such as 31-32 and 34-35 show 28-28, 29-29, 31-31, 32-32 along the 27th, 30th, and 33th, respectively. A schematic cross-sectional view of one of the 34-34 and 35-35 line segments, respectively, for display in the intermediate stage of one of the manufacturing methods of the semiconductor device. A semiconductor device formed by the exemplary method of Figures 27-35 can be used as a lateral double diffused metal oxide semiconductor (LDMOS) device suitable for radio frequency circuit (RF) components.

Please refer to Figures 27-29 for the structure shown in Figures 6-8 and the relevant process. Next, after removing the patterned mask layer 114 as shown in FIGS. 6-8, a mask layer 120 patterned in the same manner as shown in FIGS. 9-11 is formed on the semiconductor substrate 102 and the gate. On the structure G, a plurality of portions of the semiconductor layer 102 which are alternately formed between the gate structure G and the doping region 112 are exposed. Next, an etching process 300 is performed to remove portions of the semiconductor layer 102 exposed by the patterned mask layer 120 to form a plurality of trenches 302 in the doped region 112. Viewed from above, the trenches 302 have a strip-like pattern and expose one portion of the semiconductor layer 102, respectively.

Please refer to Figure 30-32 for an ion implantation process (not shown), using the patterned mask layer shown in Figure 27-29 as the implant mask to implant the first P-like pattern. A dopant of a conductivity type is formed on sidewalls of portions of the semiconductor layer 102 exposed for such trenches 302, thereby forming a doped region 302. Then, after the patterned mask layer 120 is removed, the trenches 302 are filled with an insulating material such as yttria, thereby forming an insulating layer 304 within the trenches 302. The top surface of the insulating layer 304 is coplanar with the semiconductor layer 102 and the doped regions 112 formed therein. As shown in Fig. 30, the ion implantation process can be a tilt implantation process, so that the doped region 302 can be formed with a hollow rectangular profile from above.

Please refer to Figures 33-35 and then for the knot as shown in Figures 30-33. The related processes as shown in Figures 12-26 are constructed to form a semiconductor device as shown in Figures 33-35.

In one embodiment, the gate structure G and the doped regions 126 and 128 of the semiconductor device as shown in FIGS. 33-35 may be electrically coupled (not shown), and the region having the first conductivity type is The P-type region, and the region of the second conductivity type are N-type regions, such that the formed semiconductor device is an N-type lateral double-diffused metal oxide semiconductor (n-type LDMOS) device. At this time, the doping region 128 can serve as a source region, and the doping region 126 can serve as a drain region.

In one embodiment, during operation of the semiconductor device as shown in FIGS. 33-35, a current (not shown) may be caused to flow laterally from its drain terminal (eg, doped region 126) through the gate structure G. After the lower channel (not shown) flows toward the source terminal (eg, doped region 128), then the doped region 118, the conductive layers 140 and 142, and the doped region 138 are guided to reach the semiconductor substrate 100, thus A source wire bond is not required, and the semiconductor device can have a lower thermal resistance.

In addition, in the semiconductor device as shown in FIGS. 33-35, the doping regions 112 and 118 are connected to the gate structure G and the pn doped region including the staggered arrangement (refer to FIG. 12-14). The surface structure is formed after it is formed. Therefore, the semiconductor device can have low gate-dipper capacitance values, low source-drain resistance values, and high breakdown voltage electrical characteristics.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Semiconductor substrate

102‧‧‧Semiconductor layer

104‧‧‧gate dielectric layer

106‧‧‧ gate electrode

112‧‧‧Doped area

118‧‧‧Doped area

124‧‧‧Doped area

126‧‧‧Doped area

128‧‧‧Doped area

130‧‧‧Insulation

134‧‧‧ trench

138‧‧‧Doped area

140‧‧‧ Conductive layer

142‧‧‧ Conductive layer

144‧‧‧Interlayer dielectric layer

146‧‧‧ trench

148‧‧‧ Conductive layer

G‧‧‧ gate structure

Claims (16)

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer formed on the semiconductor substrate having the first conductivity type; and a gate structure disposed on a portion of the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type; a second doped region disposed adjacent to the gate structure relative to the a second conductivity type opposite to the first conductivity type in the semiconductor layer on the second side of the first side; a third doped region disposed in one of the first doped regions, having the a second conductivity type; a fourth doped region disposed in one of the second doped regions, having the second conductivity type; and a plurality of fifth doped regions disposed separately from the second doped region a plurality of portions having the first conductivity type, wherein the fifth doped regions are located between the fourth doped region and the gate structure; and a sixth doped region disposed at the first doping region Within one of the semiconductor layers under the interfering region, contacting the Conductor substrate; and an electrical contact, the third doped region is formed in the inner one of the first doped region, the doped region in contact with the sixth. The semiconductor device of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 1, wherein the third doped region is a source region and the fourth doped region is a drain region. The semiconductor device of claim 1, wherein the fifth doped regions and the second doped regions adjacent thereto form a super junction structure. The semiconductor device of claim 1, wherein the fifth doped regions have a rectangular outline as viewed from above. The semiconductor device of claim 1, wherein the fifth doped regions have a hollow rectangular outline as viewed from above. The semiconductor device of claim 6, further comprising an insulating layer formed in the plurality of portions of the semiconductor layer, wherein the insulating layer is surrounded by one of the fifth doped regions. The semiconductor device of claim 1, wherein the conductive contact comprises a first conductive layer and a second conductive layer surrounded by the first conductive layer. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a semiconductor layer on the semiconductor substrate having the first conductivity type; forming a gate structure on a portion of the semiconductor layer Forming a first doped region in the semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type; forming a second doped region adjacent to the gate structure relative to the a second conductivity type of the semiconductor layer opposite to the first conductivity type in the semiconductor layer on the second side of the first side; Forming a third doped region in one of the first doped regions, having the second conductivity type; forming a fourth doped region in one of the second doped regions, having opposite to the first conductive region a second conductivity type of the type; forming a plurality of fifth doped regions in the plurality of portions of the second doped region, having the first conductivity type, wherein the fifth doped regions are formed in the fourth Between the doped region and the gate structure; forming an insulating layer on the second doped region, the gate structure and one of the third doped regions; forming a trench in the third doped region And exposing a portion of the semiconductor layer under the first doped region to a portion of the first doped region; performing an ion implantation process to implant a plurality of dopants of the first conductivity type Forming a sixth doped region in the semiconductor layer exposed by the semiconductor layer, wherein the sixth doped region physically contacts the semiconductor substrate; and forming a conductive contact in the trench, wherein the conductive contact The entity contacts the sixth doped region. The method of fabricating a semiconductor device according to claim 9, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of fabricating a semiconductor device according to claim 9, wherein the third doped region is a source region and the fourth doped region is a drain region. The method of fabricating a semiconductor device according to claim 9, wherein the fifth doped regions and the second doped regions adjacent thereto form a super junction structure. The method of fabricating a semiconductor device according to claim 9, wherein the fifth doped regions have a rectangular outline as viewed from above. The method of fabricating a semiconductor device according to claim 9, wherein the fifth doped regions have a hollow rectangular outline as viewed from above. The method for fabricating a semiconductor device according to claim 9, further comprising forming an insulating layer in the plurality of portions of the semiconductor layer, wherein the insulating layer is surrounded by one of the fifth doped regions . The method of fabricating a semiconductor device according to claim 9, wherein the conductive contact comprises a first conductive layer and a second conductive layer surrounded by the first conductive layer.