TW201606733A - Gate driving method of a display and driving module - Google Patents

Abstract

A gate driving method of a display includes: respectively providing a plurality of scan signal sets to a plurality of scan line sets in sequence, wherein each of the scan signal sets includes a plurality of scan signals respectively transmitted to a plurality of scan lines of a corresponding scan line set; and respectively performing a plurality of trimming operations for the scan signals to reduce the high voltage levels of the scan signals. A plurality of first time intervals between the time points of the rising edges of the scan signals and the starting time points of the corresponding trimming operations or a plurality of second time intervals between the time points of the rising edges of the scan signals and the ending time points of the corresponding trimming operations are gradually increased or decreased for the different scan signal sets. A driving module is also provided.

Description

Gate driving method and driving module of display

The invention relates to a driving method and a driving module, and in particular to a gate driving method of a display and a driving module for driving the display.

Display technology has been continuously improved in recent years. In addition to providing users with good picture quality, it is also able to move towards space saving and low power consumption. For example, liquid crystal displays have become a mainstream in the market because they can produce high image quality and at the same time achieve thinning and power saving requirements, and have largely replaced traditional cathode ray tubes (CRTs).

In addition, today's displays are generally mostly flat-panel displays, so when the screen size increases, the thickness of the display does not increase much. In this way, this feature of the flat panel display is suitable for the development of a large-screen display to provide users with higher visual enjoyment, but does not occupy too much space in the city.

However, as the display progresses toward a large screen, the impedance of the wire on array (WOA) increases due to the elongated conductive traces on the display panel, and the leakage current of the thin film transistor also increases. As a result, it will easily lead to display Horizontal strips of different brightness appear on the screen, which makes the picture uneven.

In order to solve the above problem, it can be achieved by fine-tuning or redesigning the display panel of the display panel process, but such a solution will take a lot of time and greatly increase the production cost.

The present invention provides a gate driving method for a display, which can solve the problem of horizontal strip regions of different brightness of a display screen in a simple and low-cost manner.

The present invention provides a drive module that provides a solution to the problem of horizontal strip zones of different brightness of display screens in a simple, low-cost manner.

An embodiment of the invention provides a gate driving method for a display. The display includes a plurality of scan lines, and the scan lines are sequentially divided into a plurality of scan line groups. The gate driving method of the display includes: sequentially providing a plurality of scan signal groups to the scan line groups, wherein each scan signal group includes a plurality of scan signals respectively transmitted to a plurality of scan lines of a corresponding scan line group And performing multiple chamfering operations on the scan signals to reduce the high voltage level of the scan signals. a plurality of second time intervals between a plurality of first time intervals between the rising edges of the scan signals and the start times of the respective chamfering operations, respectively, or the respective end times of the chamfering operations For different scan signal groups, it is sequentially incremented or decremented.

An embodiment of the invention provides a driving module for driving a display Device. The display includes a plurality of scan lines, which are sequentially divided into a plurality of scan line groups. The driving module comprises a plurality of gate drivers, a power supply and a control unit. The gate drivers sequentially provide a plurality of scan signal groups to the scan line groups, and each of the scan signal groups includes a plurality of scan signals respectively transmitted to the plurality of scan lines of a corresponding scan line group. The power supply is configured to provide a high level signal and a low level signal to the gate drivers, and the gate drivers form the scan signals by switching the high level signal and the low level signal. The control unit transmits a chamfer control signal to the gate drivers or power supplies to perform a plurality of chamfering operations on the scan signals, thereby reducing the high voltage level of the scan signals. a plurality of second time intervals between a plurality of first time intervals between the rising edges of the scan signals and the start times of the respective chamfering operations, respectively, or the respective end times of the chamfering operations For different scan signal groups, it is sequentially incremented or decremented.

In an embodiment of the invention, the chamfer control signal is an output enable signal transmitted to the gate drivers, and the second time interval is sequentially incremented or decremented for different scan signal groups. This is achieved by delivering output enable signals having different pulse widths to the gate drivers in different time periods.

In an embodiment of the invention, the chamfering operations performed on the scan signals are respectively performed by the corresponding chasing drivers for chamfering the high-level signals, and the magnitudes of the second time intervals are The distance from the gate drivers of the corresponding gate drivers to the power supply lines of the power supply is as far as possible. And decrement.

In an embodiment of the invention, the scanning signals are separately performed The chamfering operation is achieved by the power supply chamfering operation of the high-level signal, and the magnitude of the second time interval is corresponding to the distance of the gate driver to the conductive line of the power supply corresponding to the power supply. It is incremented from the farthest order.

In an embodiment of the invention, the chamfer control signal is a gate driver clock signal transmitted to the gate drivers, and the first time interval is sequentially incremented or decremented for different scan signal groups. This is achieved by transferring gate driver clock signals having different pulse widths to the gate drivers in different time periods.

In an embodiment of the invention, the magnitude of the first time intervals is increased in order of the distance from the respective gate drivers to the conductive lines of the power supply, respectively.

In an embodiment of the invention, the chamfering control signal is a gate pulse modulation signal transmitted to the power supply, and the chamfering operations performed on the scanning signals respectively are timings of the signals modulated by the corresponding gate pulses. The chamfering operation of the high-level signal is achieved.

In an embodiment of the invention, the sequential increment or decrement of the first time intervals for different scan signal groups is performed by separately transmitting gate pulse modulations having different pulse widths in different time periods. The signal to the power supply is achieved by chamfering the high level.

In an embodiment of the invention, the size of the first time intervals The distances of the corresponding gate drivers to the conductive lines of the power supply are reduced from the farthest order.

In an embodiment of the invention, the display is a liquid crystal display.

Gate driving method and driving module of display of embodiment of the present invention a plurality of first intervals between a plurality of first time intervals between the rising edges of the scanning signals and the starting times of the chamfering operations respectively corresponding to the respective cutting operations The two time intervals are sequentially incremented or decremented for different scan signal groups, so that a relatively uniform feedthrough voltage can be generated in different horizontal strip regions of the display, thereby making the display screen more uniform. In this way, the problem of horizontal strips with different brightness on the display screen can be effectively solved on the driving end, that is, the problem can be solved in a relatively simple, time-saving and cost-saving manner.

The above described features and advantages of the invention will be apparent from the following description.

100, 100d‧‧‧ display

200, 200d‧‧‧ drive module

210, 210a, 210b, 210c, 210d, 210da, 210db, 210dc‧‧‧ gate drivers

220, 220d‧‧‧ power supply

230‧‧‧Control unit

240‧‧‧Source Driver

300‧‧‧LCD panel

310‧‧‧ scan line

320‧‧‧Signal line

330‧‧‧Optoelectronics

332‧‧‧ gate

334‧‧‧ source

336‧‧‧汲polar

340‧‧‧Common electrode

B‧‧‧ points

Cgd‧‧‧ parasitic capacitance

Clc‧‧ liquid crystal capacitor

CPV‧‧‧ gate driver clock signal

Cst‧‧‧ storage capacitor

D, D’‧‧‧Information Signal

G, G1, G2, G3‧‧‧ scan line group

I _D ‧‧‧汲polar discharge current

OE‧‧‧ output enable signal

OE2‧‧ ‧ gate pulse modulation signal

P, P1, P2, P3‧‧‧

S, S1, S2, S3‧‧‧ scan signal group

SC, SC', SC1', SC1", SC2', SC2", SC3', SC3" ‧ ‧ scan signals

STV‧‧‧ gate driver start pulse

T1, T1a, T1b, T1c, T1d, T1da, T1db, T1dc‧‧‧ first time interval

T2, T2a, T2b, T2c, T2d, T2da, T2db, T2dc‧‧‧ second time interval

Vcom, Vcom’‧‧‧ shared voltage

VD‧‧‧ bungee voltage signal

VGH‧‧‧ high level signal

VGL‧‧‧ low level signal

VH, VSH‧‧‧ high voltage level

VL, VL1, VL2, VL3, VSL‧‧‧ low voltage level

W1, W11, W12, W13, W2, W21, W22, W23, W3, W31, W32, W33‧‧‧ pulse width

ΔV1, ΔV1', ΔV2, ΔV2', ΔV3, ΔV3'‧‧‧ difference

ΔV _FT ‧‧‧feedthrough voltage

1A is a block diagram of a display in accordance with an embodiment of the present invention.

FIG. 1B illustrates the relationship between the scan line and the gate driver and the relationship between the data line and the source driver in the display of FIG. 1A.

2 is a signal waveform diagram for driving the display of FIG. 1A.

3A is a start pulse signal and transmission of a gate driver in the display of FIG. 1A The waveform of the output enable signal to the gate driver is corresponding to the time period of the different gate drivers in FIG. 1A.

FIG. 3B is a schematic diagram showing waveforms of scanning signals of different scanning signal groups in the display of FIG. 1A with their rising edges of positive pulses as a starting point. FIG.

4A is a circuit diagram of one pixel in the display of FIG. 1A.

4B is a signal waveform diagram of another comparative embodiment for driving the liquid crystal display panel of FIG. 1A.

4C is an enlarged view of a chamfered scan signal of FIG. 2.

4D is a waveform diagram of scan signals at different time periods in a further comparative embodiment of the liquid crystal display panel of FIG. 1A.

4E is a schematic diagram of a display screen generated by the scan signal of FIG. 4D.

5A is a waveform diagram of a gate driver start pulse signal and a gate driver clock signal transmitted to a gate driver in a display corresponding to a different gate driver in FIG. 1A in another embodiment of the present invention.

FIG. 5B is a schematic diagram showing waveforms of scanning signals of different scanning signal groups in the display of FIG. 1A with their rising edges of positive pulses as a starting point. FIG.

6A is a block diagram of a display in accordance with another embodiment of the present invention.

Figure 6B is a signal waveform diagram for driving the display of Figure 6A.

FIG. 7 is a waveform diagram of scan signals for different periods of time in another comparative embodiment of the liquid crystal display panel of FIG. 6A.

8A is a diagram showing the gate driver start pulse signal in the display of FIG. 6A and the output enable signal transmitted to the gate driver in a gate drive different from that in FIG. 6A. Waveform of the time period of the device.

FIG. 8B is a waveform diagram of the scanning signals of different scanning signal groups in the display of FIG. 6A superimposed with the rising edges of their respective positive pulses as a starting point. FIG.

FIG. 9A is a waveform diagram of a gate driver start pulse signal, a gate pulse modulation signal, and a high level signal in a display corresponding to different gate drivers 210d of FIG. 6A in a display according to still another embodiment of the present invention.

FIG. 9B is a waveform diagram of the scanning signals of different scanning signal groups in the display of FIG. 6A superimposed with the rising edges of their respective positive pulses as a starting point. FIG.

1A is a block diagram of a display according to an embodiment of the present invention, and FIG. 1B is a diagram showing relationship between a scan line and a gate driver and a relationship between a data line and a source driver in the display of FIG. 1A, and FIG. 2 is used to drive FIG. 1A. The signal waveform diagram of the display, FIG. 3A corresponds to the gate driver start pulse signal in the display of FIG. 1A corresponding to the output enable signal to gate drivers transmitted to the gate driver. FIG. 3B is a waveform diagram of a period of different gate drivers in FIG. 1A, and FIG. 3B is a waveform diagram in which the scan signals of different scan signal groups in the display of FIG. 1A are superimposed with the rising edges of their respective positive pulses.

Referring to FIG. 1A to FIG. 1B, FIG. 2 and FIG. 3A to FIG. 3B, the driving module 200 of the embodiment is used to drive a display 100. In this embodiment, the display is, for example, a liquid crystal display, and the driving module 200 is used to drive the liquid crystal display panel 300 for display. The display 100 includes a plurality of scan lines 310, which are sequentially ordered It is divided into a plurality of scanning line groups G, such as scanning line groups G3, G2, and G1. The driving module 200 includes a plurality of gate drivers 210 (eg, gate drivers 210c, 210b, and 210a), a power supply 220, and a control unit 230. The gate drivers 210 sequentially provide a plurality of scan signal groups S to the scan line groups G, and each scan signal group S includes a plurality of scans respectively transmitted to the plurality of scan lines 310 of a corresponding scan line group G. Signal SC.

The power supply 220 is configured to provide a high level signal VGH and a low level signal VGL to the gate drivers 210, and the gate drivers 210 form the high level signal VGH and the low level signal VGL. Scan signal SC. The control unit 230 transmits a chamfer control signal to the gate driver 210 or the power supply 220 to perform a plurality of chamfering operations on the scan signals SC, thereby reducing the high voltage level VH of the scan signals SC. The high voltage level VH of the scan signals SC is provided by the high level signal VGH, and the low voltage level VL of the scan signals SC is provided by the low level signal VGL. In this embodiment, the control unit 230 is a timing controller, and the chamfer control signal is an output enable signal OE that is transmitted to the gate driver 210.

a plurality of second intervals between a plurality of first time intervals T1 between the rising edges of the scan signals SC and the start times of the chamfering operations respectively corresponding to the respective end times of the chamfering operations The time interval T2 is sequentially incremented or decremented for different scan signal groups S. In this embodiment, these second time intervals T2 are sequentially delivered for different scan signal groups S. Less. In this embodiment, the second time interval T2c of the scan signal SC of the scan signal group S transmitted in the scan line group G3 is greater than the second time interval of the scan signal SC of the scan signal group S transmitted in the scan line group G2. T2b, and the second time interval T2b of the scan signal SC of the scan signal group S transmitted in the scan line group G2 is greater than the second time interval T2a of the scan signal SC of the scan signal group S transmitted in the scan line group G1, such as Figure 3B is depicted.

4A is a circuit diagram of a pixel in the display of FIG. 1A, FIG. 4B FIG. 4C is an enlarged view of a chamfered scan signal of FIG. 2, and FIG. 4D is a liquid crystal display for driving the FIG. 1A. FIG. In another comparative embodiment of the panel, the waveform of the scanning signal at different time periods is shown, and FIG. 4E is a schematic diagram of the display screen generated by the scanning signal of FIG. 4D. Referring to FIG. 1A and FIG. 4A , the liquid crystal display panel 300 has a plurality of signal lines 320 , a plurality of transistors 330 , and a common electrode 340 in addition to the plurality of scan lines 310 . The gate 332 of each transistor 330 is coupled to a scan line 310. The source 334 of each transistor 330 is coupled to a signal line 320, the drain 336 of each transistor 330 (and to the drain 336). a pixel capacitor Clc is formed between the pixel electrode and the common electrode 340 (for example, a common electrode layer located on the opposite substrate) through a liquid crystal layer, and the drain 336 of each transistor 330 (and connected to the drain 336) A storage capacitor Cst is formed between the pixel electrode and the common electrode 340 (for example, a common line on the thin film transistor array substrate, which is electrically connected to the common electrode layer of the opposite substrate). Further, a parasitic capacitance Cgd naturally exists between the scan line 310 and the drain of the transistor 330 that is in contact therewith.

On the other hand, the driving module 200 further includes at least one source driver 240 (exemplified by a plurality of source drivers 240 in FIGS. 1A and 1B ), and the source driver 240 respectively provides a plurality of data signals D to the scans. Line 310. In this embodiment, the scan lines 310 are sequentially divided into groups, and the source drivers 240 are respectively coupled to different sets of scan lines 310. As shown in FIG. 4B, when any scan line 310 transmits the square wave scan signal SC' of FIG. 4B to the gate 332 of a corresponding transistor 330, a corresponding data line 320 transmits the square wave as shown in FIG. 4B. The data signal D' is to the source 334 of the transistor 330. When the voltage level of the gate 332 is at the high voltage level VH, the transistor 330 is turned on, and the data signal D' from the source charges the storage capacitor Cst and the liquid crystal capacitor Clc, so that the voltage of the drain 336 rises to the data signal. D' high voltage level VSH. The voltage signal at the drain 336 is the drain voltage signal VD. However, when the scan signal SC' changes from the high voltage level VH to the low voltage level VL, due to the capacitive coupling of the parasitic capacitance Cgd, the actual voltage of the drain 336 drops by a voltage at this time, and this voltage is Feedthrough voltage ΔV _FT .

The magnitude of the feedthrough voltage ΔV _FT can be calculated by the following formula (1):

However, due to the impedance of the scan line 310, the square wave scanning signal SC' is gradually deformed during the transfer of the scan line 310. Therefore, the scanning signal SC of the embodiment adopts a square wave signal with a chamfered angle, and the point B of the waveform after the chamfering mainly determines the magnitude of the feedthrough voltage ΔV _FT . Since the difference between the voltage at point B and the low voltage level VL is smaller than the difference between the high voltage level VH and the low voltage level VL, and the chamfered square wave signal is deformed during the transmission of the scan line 310, The difference between the point at which the magnitude of the feedthrough voltage ΔV _FT is mainly determined and the low voltage level VL is close to the difference between the voltage at point B and the low voltage level VL. In this way, the common voltage Vcom' of the common electrode 340 at the center of the amplitude of the positive and negative periods of the data signal D' can be adjusted downward by ΔV _FT to Vcom, so that the value of the common voltage Vcom is the data signal. The high voltage level of the positive cycle VSH minus the feedthrough voltage ΔV _FT and the low voltage level VSL of the negative cycle minus the intermediate value of the voltage obtained after the feedthrough voltage ΔV _FT , so that the positive and negative cycle The amplitude of the voltage difference is the same without causing flicker on the screen.

However, the low level signal VGL is transferred from the power supply 220 to a different one. The distance of the conductive lines through which the gate driver 210 travels is different, resulting in varying degrees of impedance. In FIG. 1A, the length of the conductive line from the power supply 220 to the gate driver 210c is greater than the length of the electric line from the power supply 220 to the gate driver 210b, and the length of the conductive line from the power supply 220 to the gate driver 210b. The length of the conductive line is greater than the power supply 220 to the gate driver 210a. Because the longer the conductive line generates a larger impedance, the low voltage level VL3 corresponding to the scanning signal SC3' of the scanning signal group G3 is higher than the scanning signal corresponding to the scanning signal group G2, as shown in FIG. 4D. The low voltage level VL2 of SC2' is closer to the zero level (ie, the ground level), and the low voltage level VL2 is closer to the zero level than the low voltage level VL1 of the scan signal SC1' corresponding to the scan signal group G1. . Since the low voltage levels VL1, VL2 and VL3 are both below the zero level, VL3>VL2>VL1. Further, if the transistor 330 in the liquid crystal display panel 300 has a leakage current, it is likely to cause such a result.

On the other hand, in the embodiment, the chamfering operations performed on the scanning signals SC are performed by the corresponding chasing drivers 210 to perform the chamfering operation on the high-level signal VGH, for example, by A chamfering circuit in the gate driver 210, which is well known to those skilled in the art, is achieved in the art. For example, the chamfering effect of lowering the high voltage level VH can be achieved by operating the discharge characteristics in the saturation region by a transistor (for example, a MOS field effect transistor). The drain discharge current I _D generated by this discharge characteristic satisfies the following formula (2): I _D = K × ( VGN - VL ) ² (2)

Wherein, VGN is a control voltage applied to a gate of the MOS field effect transistor, and VL is a low voltage level when the low level signal VGL is transmitted to the gate driver 210 including the MOS field effect transistor. Bit VL, and K is a proportional constant.

As can be seen from the above formula (2), since the lower the voltage level VL received by the gate driver 210 farther from the power supply 220 is, the smaller the discharge current I _{D is} , that is, the slower the discharge rate is, that is, the shaving The absolute value of the slope of the angle is smaller. In this embodiment, the absolute value of the chamfer slope of the scan signal SC3' is smaller than the absolute value of the chamfer slope of the scan signal SC2', and the absolute value of the chamfer slope of the scan signal SC2' is smaller than the chamfer of the scan signal SC1'. The absolute value of the slope.

Combining the above two effects, that is, the low voltage level VL will produce different values at different gate drivers 210 depending on the length of the conductive path and the transistor leakage current, and due to the difference in the low voltage level VL. The difference in the discharge rate causes the voltages at the B point of the scanning signals SC3', SC2', and SC1' to be different, which causes the voltages B and V1 of the scanning signals SC3', SC2', and SC1' to be low. The differences ΔV3', ΔV2', and ΔV1' of the bits VL3, VL2, and VL1 are different.

In the present embodiment, the degree of decrease in the low voltage level VL is smaller than the degree of decrease in the chamfer of the high voltage level VH due to the drop in the low voltage level, so in the present embodiment, ΔV3'> ΔV2 '>ΔV1'. In this way, when (VH-VL) in the equation (1) is replaced by ΔV3', ΔV2', and ΔV1', respectively, different feedthrough voltages ΔV _FT3 corresponding to the scan line groups G3, G2, and G1 are obtained, ΔV _FT2 and ΔV _FT1 are different results. In the present embodiment, ΔV _FT3 > ΔV _FT2 > ΔV _FT1 , such that the display area AA of the display 100 corresponds to different scan line groups G3, G2, and G1, respectively. The horizontal strip regions A3, A2, and A1 have inconsistent brightness and are liable to cause flickering of the screen.

In order to solve this problem, please refer to FIG. 3A and FIG. 3B again. In this embodiment, the second time interval T2c of the scan signal SC of the scan signal group S transmitted in the scan line group G3 is larger than that in the scan line group G2. The second time interval T2b of the scan signal SC of the transmitted scan signal group S, and the second time interval T2b of the scan signal SC of the scan signal group S transmitted in the scan line group G2 is greater than the scan transmitted in the scan line group G1 The second time interval T2a of the scan signal SC of the signal group S, corresponding to the voltages of the B points of the scan signal groups S3, S2 and S1 of the different scan line groups G3, G2 and G1 and their corresponding low voltage levels VL3, VL2 The difference between VL1 and VL1 is relatively close or substantially equal, that is, the second time interval T2 of the scanning signal SC having the larger absolute value of the chamfer slope is shorter. In this way, the feedthrough voltages ΔV _FT corresponding to the different scanning line groups G3, G2, and G1 can be made uniform, and the horizontal band regions having different brightnesses can be eliminated or can not be perceived by the eyes. In addition, since the feedthrough voltage ΔV _{FT of the} entire liquid crystal display panel 300 is relatively uniform, the common voltage Vcom can be adjusted to the center value of the positive and negative periods of the voltage signal received by the drain 336, thereby effectively suppressing or eliminating the picture. Flashing.

In other words, in the present embodiment, the magnitudes of the second time intervals T2 are decreased in descending order of the distances of the gate drivers 210 to the conductive lines of the power supply 220 corresponding thereto (ie, T2c>). T2b>T2a).

In this embodiment, the sequential increment or decrement of these second time intervals T2 for different scan signal groups S is by different time periods P (in the present embodiment, for example, periods P1, P2). And P3) is achieved by transmitting output enable signals OE having different pulse widths W3, W2, and W1 to the gate drivers 210, respectively. These different pulse widths W3, W2 and W1 of the output enable signal OE can be achieved by a suitable pulse width modulation mechanism.

Referring to FIG. 1A, FIG. 2 and FIG. 3A, the control unit 230 transmits a gate driver start pulse (STV) STV to the first gate driver 210c to define a frame time. Starting, and from this time, the gate drivers 210c, 210b, and 210a sequentially transmit the scan signal groups S3, S2, and S1 to the scan line groups G3, G2, and G1, respectively, and the scan signals SC in each of the scan signal groups S are also The scan lines 310 are sequentially transferred to the corresponding scan line groups G, respectively. In addition, the control unit 230 transmits a gate driver clock signal (CPV) CPV to the gate driver 210, and the gate driver 210 determines the output to the scan line 310 according to each pulse of the gate driver clock signal CPV. Scanning the pulse time of the signal SC, that is, switching the scan signal SC to The time of the high voltage level VH. The 4th to 8th waveforms in FIG. 2 are sequentially the scanning signals SC on the adjacent first 5 scanning lines 310.

In addition, in order to avoid the scanning signals received by the adjacent two scan lines 310 The positive pulse of the SC is too close to cause a crosstalk phenomenon between the two scan lines 310, and the control unit 230 transmits the output enable signal OE to the gate driver 310, wherein the positive pulse time (ie, the output) is at the output enable signal OE. When the enable signal OE is at a high level, the gate driver 210 switches the voltage level higher than the low voltage level VL back to the low voltage level VL, and the switching operation can be utilized by those having ordinary knowledge in the field. The well-known switching circuit is achieved, and will not be described here. In this way, by outputting the appropriate pulse width of the positive pulse time of the enable signal OE, the positive pulses of the two scan signals SC of the adjacent two scan lines 310 can be separated at an appropriate time interval to avoid or suppress the phase. Crosstalk between adjacent scan lines 310.

In addition, in the embodiment, the start time of the chamfering operation is corresponding to the gate The rising edge of the positive pulse of the polar drive clock signal CPV, and the rising edge time of the positive pulse of the output enable signal OE is the end time of the positive pulse corresponding to the scan signal SC, that is, the end time corresponding to the chamfering operation It is also the time B corresponding to the scan signal.

In this way, the output is enabled by the P3, P2, and P1 at different times. The rising edge of the positive pulse of the number OE is adjusted in the positive time direction or the negative time direction, so that the time elapsed by the chamfering operation can be changed, and the length of the second time T2 can be changed. In the present embodiment, the pulse width W3 < W2 < W1, so that T2c > T2b > T2a can be made.

FIG. 5A is a gate driver in a display according to another embodiment of the present invention; The waveform of the gate driver start pulse signal and the gate driver clock signal transmitted to the gate driver in the period corresponding to the different gate driver in FIG. 1A, and FIG. 5B is different in the display of FIG. 1A. The waveform diagram of the scan signal group of the scan signal group is superimposed with the rising edge of each positive pulse as a starting point. Referring to FIG. 1A, FIG. 5A and FIG. 5B, in the embodiment, the chamfering control signals are the gate driver clock signals CPV transmitted to the gate drivers 210, and the first time intervals T1 are different for the scanning signal groups. The sequential increment or decrement in the case of S is achieved by transmitting gate driver clock signals CPV having different pulse widths W31, W21 and W11 to the gate drivers 210 in different time periods P, respectively. These different pulse widths W31, W21 and W11 of the gate driver clock signal CPV can be achieved by a suitable pulse width modulation mechanism.

In addition, in this embodiment, the first time interval T1c corresponding to the scan signal group S3 is smaller than the first time interval T1b corresponding to the scan signal group S2, and the first time interval T1b corresponding to the scan signal group S2 is smaller than corresponding to The first time interval T1a of the signal group S1 is scanned. In other words, the magnitude of these first time intervals T1 is increased in the order of the distance from the gate drivers 210 to the conductive lines of the power supply 220, respectively, which are respectively corresponding to each other. That is to say, the falling edge of the positive pulse of the gate driver clock signal CPV is sequentially adjusted from the period P3 to the period P1 to the positive time direction, so that the first time T1 can be gradually extended in sequence.

In this way, the difference between the point B of the scanning signal groups S3, S2 and S1 and the corresponding low voltage levels VL3, VL2 and VL1 can be relatively consistent, thereby effectively eliminating or suppressing the horizontal band of different brightness of the display picture. Area.

In the driving module 200 of the display 100 of the above embodiment, a plurality of first time intervals T1 or corresponding to each of the rising edges of the scanning signals SC and the start times of the corresponding chamfering operations respectively correspond to The plurality of second time intervals T2 between the end times of the chamfering operations are sequentially incremented or decremented for different sets of scan signals, and thus may be more consistent in different horizontal strip regions of the display 100. The feedthrough voltage, in turn, makes the display more uniform. In this way, the problem of horizontal strips with different brightness on the display screen can be effectively solved on the driving end, that is, the problem can be solved in a relatively simple, time-saving and cost-saving manner.

6A is a block diagram of a display according to another embodiment of the present invention, and FIG. 6B FIG. 7 is a waveform diagram of a scanning signal used to drive the display of FIG. 6A in another comparative embodiment, and FIG. 8A is a display of FIG. 6A. The gate driver start pulse signal and the output enable signal transmitted to the gate driver are in a waveform corresponding to the different gate drivers in FIG. 6A, and FIG. 8B is a different scan signal group in the display of FIG. 6A. The waveform of the scan signal is superimposed with the rising edge of its respective positive pulse as a starting point.

Referring to FIG. 6A and FIG. 6B, the display 100d and its driving module 200d of the present embodiment are similar to the display 100 of FIG. 1A and its driving module 200, and the differences between the two are as follows. In the display 100d of the present embodiment, the chamfering circuit is located at the power supply 220d (ie, external chamfer), which is different from the chamfering circuit of the display 100 of FIG. 1A in each of the gate drivers 210 (ie, internal chamfering) ). The chamfering circuit located in the power supply 220d can be implemented by a chamfering circuit known to those skilled in the art. In the embodiment, the chamfering operations performed on the scanning signals SC are performed by the power supply 220d to perform the chamfering operation on the high-level signal VGH. The operation principle of the chamfering circuit in the power supply 220d can be the same as that of the chamfering circuit in the gate driver 210 of FIG. 1A, that is, the discharge characteristic is generated by the transistor operating in the saturation region to generate the drain Discharge current I _D . At this time, since the voltage (for example, the low voltage level VL) referenced by the control voltage VGN applied to the gate of the transistor is only one, the absolute value of the chamfer slope of the high-level signal VGH generated is in a graph. The period of each of the frame times is the same, so the absolute value of the chamfer slope of the high level signal VGH transmitted to the different gate drivers 210d (eg, the gate drivers 210dc, 210db, and 210da) is also substantially the same.

In addition, in the embodiment, the chamfering control signal is a gate pulse modulation signal OE2 transmitted to the power supply 220d, and the chamfering operations performed on the scanning signals SC respectively are performed by corresponding The timing of the gate pulse modulation signal OE2 is achieved by chamfering the high level signal VGH. In this embodiment, as shown in FIG. 6B, the time of the rising edge of the positive pulse of the gate pulse modulation signal OE2 is the start time corresponding to the chamfering operation. At this time, the level of the high level signal VGH gradually decreases from the high voltage level VH, and until the falling edge of the positive pulse of the gate pulse modulation signal OE2, the level of the high level signal VGH is Also cut back to the high voltage level VH. In this way, when the gate driver 210d switches the scan signal SC to the high level signal VGH and the low level signal VGL according to the gate driver clock signal CPV, the chamfered sweep can be generated. Trace number SC.

On the other hand, the control unit 230 also transmits the output enable signal OE to the gate driver 210d. Therefore, as in the embodiment of FIG. 2, the time of the rising edge of the positive pulse of the output enable signal OE also corresponds to the chamfer of the scan signal SC. stop the time. In addition, the sixth to ninth waveforms in FIG. 6B are sequentially the scanning signals SC on the adjacent first four scanning lines 310.

Referring to FIG. 7, since the lengths of the conductive lines of the power supply 220d to the gate drivers 210d are different, the low voltage of the scan signal SC3" output by the gate driver 210dc (which is farthest from the power supply 220d) is caused. The level VL3 is closer to the zero level than the low voltage level VL2 of the scan signal SC2" output by the gate driver 210db (which is second away from the power supply 220d), and the gate driver 210db (which is next to the power supply) 220d) The low voltage level VL2 of the output scan signal SC2" is closer to the zero level than the low voltage level VL1 of the scan signal SC1" output by the gate driver 210da (which is closest to the power supply 220d). Since the voltage levels VL3, VL2 and VL1 are all negative, VL3>VL2>VL1. Further, as described above, since the absolute value of the chamfer slope is fixed in the case of external chamfering, in a comparative embodiment, if the enable signal OE and the gate pulse are output in different periods P When the pulse widths of the modulation signals OE2 are the same, the difference ΔV3, ΔV2, and ΔV1 between the point B of each of the scanning signals SC3", SC2", and SC1" and the corresponding low voltage levels VL3, VL2, and VL1 are not equal. For example, ΔV3 > ΔV2 > ΔV1. The unequalities of the differences ΔV3, ΔV2, and ΔV1 result in different feedthrough voltages, which in turn produce horizontal band regions of different brightness.

Therefore, in the present embodiment, the size of these second time intervals T2d follows The distances of the respective gate drivers 210d to the power supply lines of the power supply 220d, which are respectively corresponding, are increased from the farthest order. For example, as shown in FIG. 8B, the second time T2dc corresponding to the scan signal group S3 of the gate driver 210dc is smaller than the second time T2db corresponding to the scan signal group S2 of the gate driver 210db, and corresponds to the gate. The second time T2db of the scan signal group S2 of the driver 210db is smaller than the second time T2da corresponding to the scan signal group S1 of the gate driver 210da.

In this embodiment, it can be adjusted in different periods P3, P2, and P1. The magnitude of the pulse widths W32, W22, and W12 of the output enable signal OE (for example, the time at which the rising edge of the positive pulse is adjusted) can change the magnitude of the second time T2d in the different periods P3, P2, and P1. In the present embodiment, W32>W22>W12. In this way, the difference between the voltage level of the B point of each of the scanning signal groups S3, S2, and S1 and the corresponding low voltage levels VL3, VL2, and VL1 can be consistent, thereby effectively suppressing or eliminating different brightness in the picture. The problem of horizontal strips.

9A is a gate driver in a display according to still another embodiment of the present invention. The waveforms of the start pulse signal, the gate pulse modulation signal and the high level signal in the period corresponding to the different gate drivers 210d in FIG. 6A, and FIG. 9B is the scanning signals of different scanning signal groups in the display of FIG. 6A. A schematic diagram of waveforms superimposed with the rising edges of their respective positive pulses as a starting point. Referring to FIG. 6A, FIG. 9A and FIG. 9B, this embodiment also adopts the architecture of the display 100d of FIG. 6A, and the difference from the embodiment of FIGS. 8A and 8B is as follows. In this embodiment, the sequential increment or decrement of these first time intervals T1d for different scan signal groups S3, S2, S1 is The gate pulse modulation signal OE2 having different pulse widths W33, W23, W13 is respectively transferred to the power supply 220d in different time periods P3, P2, P1 to achieve chamfering of the high level. The different pulse widths of the gate pulse modulation signal OE2 can be realized by an appropriate pulse width modulation mechanism.

In the present embodiment, the magnitudes of these first time intervals T1d are decremented in order of their distance from the gate drivers 210d to the conductive lines of the power supply 220d, respectively. For example, the first time T1dc corresponding to the scan signal group S3 of the gate driver 210dc is greater than the first time T1db corresponding to the scan signal group S2 of the gate driver 210db, and corresponds to the scan signal group S2 of the gate driver 210db. The first time T1db is greater than the first time T1da corresponding to the scan signal group S1 of the gate driver 210da.

In this embodiment, the pulse widths W33, W23, and W13 of the gate pulse width modulation signal OE2 in the different periods P3, P2, and P1 can be adjusted (for example, the time for adjusting the rising edge of the positive pulse). It is possible to change the size of the first time T1d in the different periods P3, P2 and P1. In the present embodiment, W33 < W23 < W13. In this way, the difference between the voltage level of the B point of each of the scanning signal groups S3, S2, and S1 and the corresponding low voltage levels VL3, VL2, and VL1 can be consistent, thereby effectively suppressing or eliminating different brightness in the picture. The problem of horizontal strips.

In some embodiments, a gate driving method of the display is also proposed, which can be implemented by the driving modules 200, 200d in the above embodiments. The gate driving method of the display includes: sequentially providing a plurality of scanning signal groups S to the scanning line groups G (as shown in FIG. 1A and FIG. 1B ), and each scanning signal group S includes respectively And transmitting a plurality of scan signals SC of the plurality of scan lines 310 of the corresponding scan line group G; and performing a plurality of chamfering operations on the scan signals SC to reduce the high voltage level VH of the scan signals. a plurality of second intervals between a plurality of first time intervals T1 between the rising edges of the scan signals SC and the start times of the chamfering operations respectively corresponding to the respective end times of the chamfering operations The time interval T2 is sequentially incremented or decremented for different scan signal groups S. The gate driving method of the display of these embodiments has been described in detail in the above embodiments. For details, refer to the above embodiments, and the description thereof will not be repeated.

In summary, the gate driving method of the display of the embodiment of the present invention And the driving module, between the plurality of first time intervals between the rising edge of the scanning signals and the starting times of the corresponding chamfering operations respectively or the ending times of the corresponding chamfering operations respectively The plurality of second time intervals are sequentially incremented or decremented for different scan signal groups, so that a relatively uniform feedthrough voltage can be generated in different horizontal strip regions of the display, thereby making the display screen more uniform. In this way, the problem of horizontal strips with different brightness on the display screen can be effectively solved on the driving end, that is, the problem can be solved in a relatively simple, time-saving and cost-saving manner.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

B‧‧‧ points

S1, S2, S3‧‧‧ scan signal group

T2, T2a, T2b, T2c‧‧‧ second time interval

VL1, VL2, VL3‧‧‧ low voltage level

Claims (20)

A gate driving method for a display, the display includes a plurality of scan lines, the scan lines are sequentially divided into a plurality of scan line groups, and the gate driving method of the display comprises: sequentially providing a plurality of scan signal groups to the Each of the scan signal groups includes a plurality of scan signals respectively transmitted to a plurality of scan lines of the corresponding scan line group; and respectively performing a plurality of chamfer operations on the scan signals to reduce a high voltage level of the scan signals, wherein a plurality of first time intervals between the rising edges of the scan signals and the start times of the chamfering operations respectively corresponding to the respective cuts The plurality of second time intervals between the end times of the angular operations are sequentially incremented or decremented for different sets of scan signals. The gate driving method of the display of claim 1, wherein the scan signal groups are respectively output from a plurality of gate drivers, and the second time intervals are different for the plurality of scan signal groups. The sequential increment or decrement is achieved by respectively transmitting output enable signals having different pulse widths to the gate drivers in different time periods. The gate driving method of the display of claim 2, wherein the scan signal groups are respectively output from a plurality of gate drivers, and each of the driving signals is switched by a gate driver from a power supply. The high-level signal of the device is formed by a low-level signal, and the chamfering operations performed on the scanning signals are performed by the corresponding gate drivers for chamfering the high-level signal. The size of the second time intervals is reduced in descending order of the distances of the gate drivers to the conductive lines of the power supply respectively. The gate driving method of the display of claim 2, wherein the scan signal groups are respectively output from a plurality of gate drivers, and each of the driving signals is switched by a gate driver from a power supply. The high-level signal of the device is formed by a low-level signal, and the chamfering operations performed on the scanning signals by the power supply are performed by chamfering the high-level signal, and The magnitudes of the second time intervals are increased in order of the distance from the gate drivers to the conductive lines of the power supply, respectively. The gate driving method of the display of claim 1, wherein the scanning signal groups are respectively output from a plurality of gate drivers, and the first time intervals are different for the plurality of scanning signal groups. The sequential increment or decrement is achieved by respectively transmitting gate driver clock signals having different pulse widths to the gate drivers in different time periods. The method for driving a gate of a display according to claim 5, wherein the scan signal groups are respectively output from a plurality of gate drivers, and each of the drive signals is switched by a gate driver from a power supply. a high-level signal and a low-level signal are formed, and the first time intervals are different in distance from the corresponding gate drivers to the conductive lines of the power supply Incremented in the nearest order. The gate driving method of the display according to claim 1, The scan signal groups are respectively outputted from a plurality of gate drivers, and each of the driving signals is formed by a gate driver switching a high level signal and a low level signal from a power supply, and The chamfering operations performed on the scan signals by the power supply are performed by chamfering the high-level signal. The gate driving method of the display of claim 7, wherein the first time interval is sequentially incremented or decremented for different scan signal groups by different time periods. The gate pulse modulation signals having different pulse widths are respectively transmitted to the power supply to achieve the chamfering of the high level. The gate driving method of the display of claim 8, wherein the first time interval is different in size from the distance between the gate drivers and the conductive lines of the power supply Decrease in ascending order. The gate driving method of the display of claim 1, wherein the display is a liquid crystal display. A driving module is configured to drive a display, the display includes a plurality of scanning lines, and the scanning lines are sequentially divided into a plurality of scanning line groups, and the driving module comprises: a plurality of gate drivers, which are respectively provided in sequence Scanning signal groups to the scan line groups, and each of the scan signal groups includes a plurality of scan signals respectively transmitted to a plurality of scan lines of the corresponding scan line group; a power supply for providing a high a level signal and a low level signal to the gate drivers, and the gate drivers form the scan signals by switching the high level signal and the low level signal; a control unit that transmits a chamfer control signal to the gate drivers or the power supply to perform a plurality of chamfering operations on the scan signals, thereby reducing a high voltage level of the scan signals, wherein the control unit a plurality of second intervals between a plurality of first time intervals between the rising edges of the scan signals and the start times of the chamfering operations respectively corresponding to the start times of the chamfering operations respectively The time interval is sequentially incremented or decremented for different scan signal groups. The driving module of claim 11, wherein the chamfering control signal is an output enable signal transmitted to the gate drivers, and the second time intervals are different for the plurality of scanning signal groups. In this case, the sequential increment or decrement is achieved by respectively transmitting the output enable signals having different pulse widths to the gate drivers in different time periods. The driving module of claim 12, wherein the chamfering operations performed on the scanning signals by the corresponding gate drivers are performed by chamfering the high-level signals. And the size of the second time intervals decreases in the order of the distance from the gate drivers to the conductive lines of the power supply, respectively. The driving module of claim 12, wherein the chamfering operations performed on the scanning signals are performed by the power supply device to perform a chamfering operation on the high-level signal, and the The magnitudes of the second time intervals are increased in order of the distance from the respective gate drivers to the conductive lines of the power supply. The driving module of claim 11, wherein the chamfering The control signal is a gate driver clock signal transmitted to the gate drivers, and the first time interval is sequentially incremented or decremented for different scan signal groups by different time periods. This is achieved by respectively transmitting the gate driver clock signals having different pulse widths to the gate drivers. The driving module of claim 15, wherein the first time intervals are as close as possible to the distances of the gate drivers to the conductive lines of the power supply respectively. Increase in order. The driving module of claim 11, wherein the chamfering control signal is a gate pulse modulation signal transmitted to the power supply, and the chamfering operations performed on the scanning signals respectively are The high-level signal is chamfered by the timing of the gate pulse modulation signal. The driving module of claim 17, wherein the first time interval is sequentially incremented or decremented for different scan signal groups by being respectively transmitted in different multiple time periods. The gate pulse modulation signals of different pulse widths are achieved by the power supply to the chamfering of the high level. The driving module of claim 18, wherein the first time intervals are different in size from the distances of the gate drivers to the conductive lines of the power supply respectively. Decrease in order. The driving module of claim 11, wherein the display is a liquid crystal display.