TW201603067A - Three-dimension symmetrical vertical transformer - Google Patents
Three-dimension symmetrical vertical transformer Download PDFInfo
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- TW201603067A TW201603067A TW103130990A TW103130990A TW201603067A TW 201603067 A TW201603067 A TW 201603067A TW 103130990 A TW103130990 A TW 103130990A TW 103130990 A TW103130990 A TW 103130990A TW 201603067 A TW201603067 A TW 201603067A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Power Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Of Transformers For General Uses (AREA)
Abstract
Description
本發明是有關於一種變壓器,且特別是有關於一種三維對稱型垂直變壓器。 This invention relates to a transformer, and more particularly to a three-dimensional symmetric vertical transformer.
積體電路製程利用前段製程可以將各種被動元件(Integrated passive device,IPD)實施於晶片中。晶片中的電感及變壓器為常見的被動元件,且已被廣泛應用在各種射頻積體電路上,如低雜訊放大器(low noise amplifier,LNA)、壓控震盪器(voltage-controlled oscillator,VCO)、注入鎖定式除頻器(injection-locked frequency divider,ILFD)、及功率放大器(power amplifier,PA)等。雖然將電感及變壓器實現於晶片內可以減少外部元件數目,但是這些晶片中的被動元件往往佔用大量之晶片面積,在昂貴的前段製程中造成本的增加。 The integrated circuit process utilizes the front-end process to implement various integrated passive devices (IPDs) in the wafer. Inductors and transformers in the chip are common passive components, and have been widely used in various RF integrated circuits, such as low noise amplifier (LNA), voltage-controlled oscillator (VCO). Injection-locked frequency divider (ILFD), power amplifier (PA), and the like. Although the implementation of inductors and transformers in a wafer can reduce the number of external components, passive components in these wafers tend to occupy a large amount of wafer area, resulting in an increase in expensive front-end processes.
封裝技術的發展由TSOP(Thin small outline packaging)、CSP(Chip scale package)、WLP(Wafer level package)等技術演進至PoP(Stacked package on package)。半導體電路設計時常面臨技 術瓶頸,例如類比電路與數位電路不易透過晶片系統(System on chip,SoC)製程整合在一起。又或者,即便將類比電路與數位電路整合在SoC,又將會有成本太高及特性無法最佳化等問題。系統級封裝(System in package,SiP)可以將不同的元件透過封裝技術進行整合。但是當封裝需求變得更複雜的時候,SiP技術也遭遇到運作速度、功耗和尺寸等設計上的瓶頸。 The development of the packaging technology has evolved from a technology such as TSOP (Thin small outline packaging), CSP (Chip scale package), WLP (Wafer level package) to PoP (Stacked package on package). Semiconductor circuit design often faces technology Bottlenecks, such as analog circuits and digital circuits, are not easily integrated through a system on chip (SoC) process. Or, even if the analog circuit and the digital circuit are integrated into the SoC, there will be problems such as too high cost and inability to optimize the characteristics. System in package (SiP) can integrate different components through packaging technology. But as packaging requirements become more complex, SiP technology also encounters bottlenecks in design speed, power consumption, and size.
三維積體電路(three-dimension integrated circuit,3DIC) 技術可以有效增加產品效能、減低功耗、降低成本、縮小體積及整合異質IC。3DIC可視為SoC、SiP的另一條出路。3DIC可以讓不同功能性質,甚至不同基板的晶片,各自應用最適合的製程分別製作後,再利用矽穿孔(Through silicon via,TSV)技術進行立體堆疊來整合。3DIC不僅縮短金屬導線長度及接線電阻,也能減少晶片面積,具有體積小、整合度高、效率高、耗電量及成本更低的優點。進行立體堆疊前,不同晶片層通常以各自最適合的前段製程(積體電路製程)完成電路或系統。在完成不同晶片層後,所述不同晶片層再以TSV、導電凸塊(Bump)及重新分佈金屬層(Re-distributed layer,RDL)相互堆疊而完成後段製程(封裝製程)的堆疊步驟。利用後段製程來完成各種被動元件(Integrated passive device,IPD),不僅可以有效率的利用後段製程面積,亦可以將原本在前段製程實施的被動元件由後段製程來實現。由後段製程實現被動元件,可以節省較為昂貴的前段製程面積,進而達到成本下降的優勢。 Three-dimension integrated circuit (3DIC) Technology can effectively increase product performance, reduce power consumption, reduce costs, reduce size, and integrate heterogeneous ICs. 3DIC can be regarded as another way out for SoC and SiP. 3DIC allows different functional properties, even wafers of different substrates, to be fabricated separately for the most suitable process, and then integrated by stereo silicon via (TSV) technology. 3DIC not only shortens the length of metal wires and wiring resistance, but also reduces the wafer area. It has the advantages of small size, high integration, high efficiency, low power consumption and lower cost. Prior to stereoscopic stacking, different wafer layers typically complete the circuit or system with their respective suitable front-end processes (integral circuit processing). After the different wafer layers are completed, the different wafer layers are stacked on each other with TSVs, conductive bumps, and redistributed layers (RDLs) to complete the stacking process of the back-end process (packaging process). The use of the back-end process to complete various passive components (IPD) can not only efficiently utilize the back-end process area, but also implement the passive components originally implemented in the front-end process by the back-end process. Passive components are realized by the latter process, which can save the expensive front-end process area and thus achieve the advantage of cost reduction.
除了節省面積的考量,尚有雜訊的技術課題。為了降低 共模雜訊,所以電路結構通常設針成差動型式,以提高其差動增益並抑制其共模雜訊增益。為此,被動元件通常需配合差動型式的需求而強調其對稱性結構。若將變壓器應用於差動型式,更需強調其對稱性的結構,使電路具有較佳的差動操作特性。 In addition to the consideration of saving area, there are still technical issues of noise. In order to reduce Common mode noise, so the circuit structure is usually set to a differential type to increase its differential gain and suppress its common mode noise gain. For this reason, passive components usually need to emphasize the symmetry structure in accordance with the requirements of the differential type. If the transformer is applied to the differential type, it is more important to emphasize the symmetrical structure, so that the circuit has better differential operating characteristics.
本發明提供一種變壓器,可以實現三維垂直之對稱型變壓器。所述變壓器可以應用於不同晶片之間的垂直信號耦合傳輸。所述變壓器可以節省晶片面積。 The invention provides a transformer, which can realize a three-dimensional vertical symmetrical transformer. The transformer can be applied to vertical signal coupling transmission between different wafers. The transformer can save wafer area.
本發明的一實施例提供中,上述的變壓器包括主線圈(primary coil)以及副線圈(secondary coil)。主線圈包括第一電性路徑與第二電性路徑分別位於變壓器的投影面上一對稱線的不同側。第一電性路徑與第二電性路徑的第一端分別作為主線圈的第一端與第二端。第一電性路徑的第二端於該對稱線處連接第二電性路徑的第二端。第一電性路徑包括被配置於第一基底的第一部份路徑與被配置於第二基底的第二部份路徑。第一部份路徑與第二部份路徑之間以矽穿孔(through silicon via,TSV)相互連接。第二電性路徑包括被配置於第一基底的第三部份路徑與被配置於第二基底的第四部份路徑。第三部份路徑與第四部份路徑之間以TSV相互連接。副線圈包括第三電性路徑與第四電性路徑分別位於該投影面上該對稱線的不同側。第三電性路徑與第四電性路徑 的第一端分別作為副線圈的第一端與第二端。第三電性路徑的第二端於該對稱線處連接第四電性路徑的第二端。第三電性路徑包括被配置於第一基底的第五部份路徑與被配置於第二基底的第六部份路徑。第五部份路徑與第六部份路徑之間以TSV相互連接。第四電性路徑包括被配置於第一基底的第七部份路徑與被配置於第二基底的第八部份路徑。第七部份路徑與第八部份路徑之間以TSV相互連接。 According to an embodiment of the present invention, the transformer includes a primary coil and a secondary coil. The main coil includes a first electrical path and a second electrical path respectively on different sides of a line of symmetry of the projection surface of the transformer. The first ends of the first electrical path and the second electrical path respectively serve as first and second ends of the primary coil. The second end of the first electrical path connects the second end of the second electrical path at the line of symmetry. The first electrical path includes a first partial path disposed on the first substrate and a second partial path disposed on the second substrate. The first portion of the path and the second portion of the path are interconnected by a through silicon via (TSV). The second electrical path includes a third partial path disposed on the first substrate and a fourth partial path disposed on the second substrate. The third part of the path and the fourth part of the path are connected to each other by TSV. The secondary coil includes a third electrical path and a fourth electrical path respectively located on different sides of the symmetry line on the projection surface. Third electrical path and fourth electrical path The first ends are respectively used as the first end and the second end of the secondary coil. The second end of the third electrical path connects the second end of the fourth electrical path at the line of symmetry. The third electrical path includes a fifth partial path disposed on the first substrate and a sixth partial path disposed on the second substrate. The fifth part of the path and the sixth part of the path are connected to each other by TSV. The fourth electrical path includes a seventh partial path disposed on the first substrate and an eighth partial path disposed on the second substrate. The seventh part of the path is connected to the eighth part of the path by TSV.
基於上述,本發明實施例可以利用TSV之垂直路徑以及不同基底的平面路徑來實現對稱型的所述變壓器(例如三維垂直之對稱型N:1變壓器或是三維對稱型1:1變壓器)。因此,所述變壓器可以節省晶片面積。再者,所述變壓器可以應用於不同晶片之間的垂直信號耦合傳輸。 Based on the above, the embodiment of the present invention can realize the symmetric transformer (for example, a three-dimensional vertical symmetric N:1 transformer or a three-dimensional symmetric 1:1 transformer) by using a vertical path of the TSV and a planar path of different substrates. Therefore, the transformer can save wafer area. Furthermore, the transformer can be applied to vertical signal coupling transmissions between different wafers.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100‧‧‧變壓器 100‧‧‧Transformer
110‧‧‧主線圈 110‧‧‧main coil
120‧‧‧副線圈 120‧‧‧second coil
210‧‧‧第一電性路徑 210‧‧‧First electrical path
211‧‧‧第一部份路徑 211‧‧‧ first part of the path
211_1‧‧‧第一導線段 211_1‧‧‧First wire segment
211_2‧‧‧第二導線段 211_2‧‧‧second wire segment
212‧‧‧第二部份路徑 212‧‧‧Second part of the path
212_1‧‧‧第三導線段 212_1‧‧‧third wire segment
220‧‧‧第二電性路徑 220‧‧‧Second electrical path
221‧‧‧第三部份路徑 221‧‧‧ third part of the path
221_1‧‧‧第四導線段 221_1‧‧‧fourth wire segment
221_2‧‧‧第五導線段 221_2‧‧‧ fifth wire segment
222‧‧‧第四部份路徑 222‧‧‧ fourth part of the path
222_1‧‧‧第六導線段 222_1‧‧‧6th wire segment
230‧‧‧第三電性路徑 230‧‧‧ Third electrical path
231‧‧‧第五部份路徑 231‧‧‧The fifth part of the path
231_1‧‧‧第一導線段 231_1‧‧‧First wire segment
232‧‧‧第六部份路徑 232‧‧‧Sixth part of the path
232_1‧‧‧第二導線段 232_1‧‧‧second wire segment
240‧‧‧第四電性路徑 240‧‧‧fourth electrical path
241‧‧‧第七部份路徑 241‧‧‧The seventh part of the path
241_1‧‧‧第三導線段 241_1‧‧‧third wire segment
242‧‧‧第八部份路徑 242‧‧‧The eighth part of the path
242_1‧‧‧第四導線段 242_1‧‧‧fourth wire segment
250‧‧‧對稱線 250‧‧ symmetry line
260‧‧‧第一基底 260‧‧‧First base
270‧‧‧第二基底 270‧‧‧second base
301‧‧‧第一矽穿孔 301‧‧‧ first perforation
302‧‧‧第二矽穿孔 302‧‧‧Second Piercing
303‧‧‧第三矽穿孔 303‧‧‧ third hole perforation
304‧‧‧第四矽穿孔 304‧‧‧fourth perforation
305‧‧‧第一矽穿孔 305‧‧‧ first perforation
306‧‧‧第二矽穿孔 306‧‧‧Second Piercing
510‧‧‧第一電性路徑 510‧‧‧First electrical path
511‧‧‧第一部份路徑 511‧‧‧ first part of the path
511_1‧‧‧第一導線段 511_1‧‧‧First wire segment
511_2‧‧‧第二導線段 511_2‧‧‧Second wire segment
511_3‧‧‧第三導線段 511_3‧‧‧ third conductor segment
512‧‧‧第二部份路徑 512‧‧‧ second part of the path
512_1‧‧‧第四導線段 512_1‧‧‧fourth wire segment
512_2‧‧‧第五導線段 512_2‧‧‧5th wire segment
520‧‧‧第二電性路徑 520‧‧‧Second electrical path
521‧‧‧第三部份路徑 521‧‧‧ third part of the path
521_1‧‧‧第六導線段 521_1‧‧‧6th wire segment
521_2‧‧‧第七導線段 521_2‧‧‧ seventh wire segment
521_3‧‧‧第八導線段 521_3‧‧‧8th wire segment
522‧‧‧第四部份路徑 522‧‧‧Fourth path
522_1‧‧‧第九導線段 522_1‧‧‧ninth wire segment
522_2‧‧‧第十導線段 522_2‧‧‧10th wire segment
530‧‧‧第三電性路徑 530‧‧‧ Third electrical path
531‧‧‧第五部份路徑 531‧‧‧The fifth part of the path
531_1‧‧‧第一導線段 531_1‧‧‧First wire segment
532‧‧‧第六部份路徑 532‧‧‧Sixth part of the path
532_1‧‧‧第二導線段 532_1‧‧‧Second wire segment
540‧‧‧第四電性路徑 540‧‧‧fourth electrical path
541‧‧‧第七部份路徑 541‧‧‧The seventh part of the path
541_1‧‧‧第三導線段 541_1‧‧‧third wire segment
542‧‧‧第八部份路徑 542‧‧‧The eighth part of the path
542_1‧‧‧第四導線段 542_1‧‧‧fourth wire segment
550‧‧‧對稱線 550‧‧ symmetry line
581‧‧‧第一矽穿孔 581‧‧‧ first perforation
582‧‧‧第二矽穿孔 582‧‧‧Second Piercing
583‧‧‧第三矽穿孔 583‧‧‧ Third hole perforation
584‧‧‧第四矽穿孔 584‧‧‧fourth perforation
585‧‧‧第五矽穿孔 585‧‧‧ fifth perforation
586‧‧‧第六矽穿孔 586‧‧‧ sixth hole perforation
587‧‧‧第一矽穿孔 587‧‧‧ first perforation
588‧‧‧第二矽穿孔 588‧‧‧Second Piercing
589‧‧‧第一矽穿孔 589‧‧‧ first perforation
590‧‧‧第二矽穿孔 590‧‧‧Second Piercing
710‧‧‧第一電性路徑 710‧‧‧First electrical path
711‧‧‧第一部份路徑 711‧‧‧ first part of the path
711_1‧‧‧第一導線段 711_1‧‧‧First wire segment
711_2‧‧‧第二導線段 711_2‧‧‧Second wire segment
711_3‧‧‧第三導線段 711_3‧‧‧third wire segment
711_4‧‧‧第四導線段 711_4‧‧‧fourth wire segment
712‧‧‧第二部份路徑 712‧‧‧ second part of the path
712_1‧‧‧第五導線段 712_1‧‧‧5th wire segment
712_2‧‧‧第六導線段 712_2‧‧‧6th wire segment
712_3‧‧‧第七導線段 712_3‧‧‧ seventh conductor segment
720‧‧‧第二電性路徑 720‧‧‧second electrical path
721‧‧‧第三部份路徑 721‧‧‧ third part of the path
721_1‧‧‧第八導線段 721_1‧‧‧8th wire segment
721_2‧‧‧第九導線段 721_2‧‧‧ninth wire segment
721_3‧‧‧第十導線段 721_3‧‧‧10th wire segment
721_4‧‧‧第十一導線段 721_4‧‧‧Eleventh wire segment
722‧‧‧第四部份路徑 722‧‧‧Fourth path
722_1‧‧‧第十二導線段 722_1‧‧‧12th wire segment
722_2‧‧‧第十三導線段 722_2‧‧‧13th wire segment
722_3‧‧‧第十四導線段 722_3‧‧‧fourteenth wire segment
730‧‧‧第三電性路徑 730‧‧‧ Third electrical path
731‧‧‧第五部份路徑 731‧‧‧The fifth part of the path
731_1‧‧‧第一導線段 731_1‧‧‧First wire segment
732‧‧‧第六部份路徑 732‧‧‧Sixth part of the path
732_1‧‧‧第二導線段 732_1‧‧‧Second wire segment
740‧‧‧第四電性路徑 740‧‧‧fourth electrical path
741‧‧‧第七部份路徑 741‧‧‧The seventh part of the path
741_1‧‧‧第三導線段 741_1‧‧‧third wire segment
742‧‧‧第八部份路徑 742‧‧‧The eighth part of the path
742_1‧‧‧第四導線段 742_1‧‧‧fourth wire segment
750‧‧‧對稱線 750‧‧ symmetry line
781‧‧‧第一矽穿孔 781‧‧‧ first perforation
782‧‧‧第二矽穿孔 782‧‧‧Second Piercing
783‧‧‧第三矽穿孔 783‧‧‧ third hole perforation
784‧‧‧第四矽穿孔 784‧‧‧fourth perforation
785‧‧‧第五矽穿孔 785‧‧‧ fifth perforation
786‧‧‧第六矽穿孔 786‧‧‧ sixth hole perforation
787‧‧‧第七矽穿孔 787‧‧‧ seventh hole perforation
788‧‧‧第八矽穿孔 788‧‧‧ eighth piercing
789‧‧‧第九矽穿孔 789‧‧‧ninth piercing
790‧‧‧第十矽穿孔 790‧‧‧10th perforation
791‧‧‧第十一矽穿孔 791‧‧‧11th perforation
792‧‧‧第十二矽穿孔 792‧‧‧Twelfth perforation
793‧‧‧第一矽穿孔 793‧‧‧ first perforation
794‧‧‧第二矽穿孔 794‧‧‧Second Piercing
901‧‧‧第一矽穿孔 901‧‧‧ first perforation
902‧‧‧第二矽穿孔 902‧‧‧Second Piercing
903‧‧‧第一矽穿孔 903‧‧‧ first perforation
904‧‧‧第二矽穿孔 904‧‧‧Second Piercing
910‧‧‧第一電性路徑 910‧‧‧First electrical path
911‧‧‧第一部份路徑 911‧‧‧ first part of the path
911_1‧‧‧第二導線段 911_1‧‧‧second wire segment
912‧‧‧第二部份路徑 912‧‧‧ second part of the path
912_1‧‧‧第一導線段 912_1‧‧‧First wire segment
920‧‧‧第二電性路徑 920‧‧‧Second electrical path
921‧‧‧第三部份路徑 921‧‧‧ third part of the path
921_1‧‧‧第四導線段 921_1‧‧‧fourth wire segment
922‧‧‧第四部份路徑 922‧‧‧Fourth path
922_1‧‧‧第三導線段 922_1‧‧‧third wire segment
930‧‧‧第三電性路徑 930‧‧‧ Third electrical path
931‧‧‧第五部份路徑 931‧‧‧The fifth part of the path
931_1‧‧‧第一導線段 931_1‧‧‧First wire segment
932‧‧‧第六部份路徑 932‧‧‧Sixth part of the path
932_1‧‧‧第二導線段 932_1‧‧‧second wire segment
940‧‧‧第四電性路徑 940‧‧‧fourth electrical path
941‧‧‧第七部份路徑 941‧‧‧The seventh part of the path
941_1‧‧‧第三導線段 941_1‧‧‧third wire segment
942‧‧‧第八部份路徑 942‧‧‧The eighth part of the path
942_1‧‧‧第四導線段 942_1‧‧‧fourth wire segment
950‧‧‧對稱線 950‧‧ symmetry line
Port1‧‧‧主線圈的第一端 Port1‧‧‧ first end of the main coil
Port2‧‧‧主線圈的第二端 Port 2‧‧‧ second end of the main coil
Port3‧‧‧副線圈的第一端 The first end of the port 3‧‧‧ secondary coil
Port4‧‧‧副線圈的第二端 The second end of the port 4‧‧‧ secondary coil
圖1是依照本發明實施例說明一種變壓器的電路示意圖。 1 is a circuit diagram illustrating a transformer in accordance with an embodiment of the present invention.
圖2是依照本發明一實施例說明圖1所示變壓器的佈局結構的立體透視示意圖。 2 is a perspective, perspective view showing the layout of the transformer of FIG. 1 in accordance with an embodiment of the present invention.
圖3是依照本發明實施例說明圖2所示變壓器的佈局結構的組合(assembling)示意圖。 3 is a schematic view showing the assembly of the layout structure of the transformer shown in FIG. 2 according to an embodiment of the present invention.
圖4是依照本發明實施例說明圖2所示變壓器的佈局結構的垂直投影示意圖。 4 is a schematic vertical plan view showing the layout structure of the transformer shown in FIG. 2 according to an embodiment of the present invention.
圖5是依照本發明另一實施例說明圖1所示變壓器的佈局結構的組合示意圖。 FIG. 5 is a schematic diagram showing the combination of the layout structure of the transformer shown in FIG. 1 according to another embodiment of the present invention.
圖6是依照本發明實施例說明圖5所示變壓器的佈局結構的垂直投影示意圖。 FIG. 6 is a schematic vertical plan view showing the layout structure of the transformer shown in FIG. 5 according to an embodiment of the invention.
圖7是依照本發明又一實施例說明圖1所示變壓器的佈局結構的組合示意圖。 FIG. 7 is a schematic diagram showing the combination of the layout structure of the transformer shown in FIG. 1 according to still another embodiment of the present invention.
圖8是依照本發明實施例說明圖7所示變壓器的佈局結構的垂直投影示意圖。 FIG. 8 is a schematic vertical plan view showing the layout structure of the transformer shown in FIG. 7 according to an embodiment of the present invention.
圖9是依照本發明再一實施例說明圖1所示變壓器的佈局結構的立體透視示意圖。 FIG. 9 is a perspective, perspective view showing the layout of the transformer of FIG. 1 according to still another embodiment of the present invention.
圖10是依照本發明實施例說明圖9所示變壓器的佈局結構的垂直投影示意圖。 FIG. 10 is a schematic vertical plan view showing the layout structure of the transformer shown in FIG. 9 according to an embodiment of the present invention.
在本案說明書全文(包括申請專利範圍)中所使用的「耦 接」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似 部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。 "Coupling" used in the full text of this prospectus (including the scope of patent application) The term "接接" can refer to any direct or indirect means of attachment. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, wherever possible, the same referenced elements/components/steps in the drawings and embodiments represent the same or similar section. Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.
圖1是依照本發明實施例說明一種變壓器100的電路示意圖。變壓器100包括主線圈(primary coil)110以及副線圈(secondary coil)120。藉由感應磁場的傳輸,相互接近的主線圈110以及副線圈120可以相互傳輸電能。例如,主線圈110的第一端Port1與第二端Port2的電能可以傳輸至副線圈120的第一端Port3與第二端Port4。藉由決定主線圈110的線圈數量以及副線圈120的線圈數量二者的比例,可以設定主線圈110以及副線圈120的電壓比。在本發明中主線圈可為一次側線圈,而副線圈可為二次側線圈。凡在本發明之創作精神所包含的設計,一或多數個線圈均為本發明創作精神的範圍。 1 is a circuit diagram illustrating a transformer 100 in accordance with an embodiment of the present invention. The transformer 100 includes a primary coil 110 and a secondary coil 120. By the transmission of the induced magnetic field, the main coil 110 and the sub coil 120 which are close to each other can transmit electric energy to each other. For example, the electrical energy of the first end Port1 and the second end Port2 of the primary coil 110 may be transmitted to the first end Port3 and the second end Port4 of the secondary coil 120. The voltage ratio of the primary coil 110 and the secondary coil 120 can be set by determining the ratio of the number of coils of the primary coil 110 and the number of coils of the secondary coil 120. In the present invention, the primary coil may be a primary side coil, and the secondary coil may be a secondary side coil. In the design encompassed by the inventive spirit of the present invention, one or more of the coils are within the scope of the inventive spirit.
圖2是依照本發明一實施例說明圖1所示變壓器100的佈局結構的立體透視示意圖。圖3是依照本發明實施例說明圖2所示變壓器100的佈局結構的組合(assembling)示意圖。圖4是依照本發明實施例說明圖2所示變壓器100的佈局結構的垂直投影示意圖。請參照圖2至圖4,變壓器100包括主線圈110以及副線圈120。主線圈110包括第一電性路徑210與第二電性路徑220。 第一電性路徑210與第二電性路徑220分別位於變壓器100的投影面(如圖4所示)上一對稱線250的不同側。第一電性路徑210的第一端與第二電性路徑220的第一端分別作為主線圈110的第一端Port1與第二端Port2。第一電性路徑210的第二端於對稱線 250處連接第二電性路徑220的第二端。其中,第一電性路徑210與第二電性路徑220相互對稱於對稱線250,如圖4所示。 2 is a perspective, perspective view showing the layout of the transformer 100 of FIG. 1 in accordance with an embodiment of the present invention. FIG. 3 is a schematic view showing an assembly of the layout structure of the transformer 100 shown in FIG. 2 according to an embodiment of the present invention. 4 is a schematic vertical plan view showing the layout structure of the transformer 100 shown in FIG. 2 according to an embodiment of the present invention. Referring to FIGS. 2 to 4 , the transformer 100 includes a primary coil 110 and a secondary coil 120 . The main coil 110 includes a first electrical path 210 and a second electrical path 220. The first electrical path 210 and the second electrical path 220 are respectively located on different sides of a symmetric line 250 on the projection surface of the transformer 100 (shown in FIG. 4). The first end of the first electrical path 210 and the first end of the second electrical path 220 respectively serve as the first end Port1 and the second end Port2 of the main coil 110. The second end of the first electrical path 210 is on the line of symmetry The second end of the second electrical path 220 is connected at 250. The first electrical path 210 and the second electrical path 220 are mutually symmetric with respect to the symmetry line 250, as shown in FIG.
第一電性路徑210包括被配置於第一基底260上的第一部份路徑211與被配置於第二基底270上的第二部份路徑212。第一部份路徑211與第二部份路徑212之間以矽穿孔(through silicon via,TSV)相互連接。第二電性路徑220包括被配置於第一基底260上的第三部份路徑221與被配置於第二基底270上的第四部份路徑222。第三部份路徑221與第四部份路徑222之間以矽穿孔相互連接。 The first electrical path 210 includes a first partial path 211 disposed on the first substrate 260 and a second partial path 212 disposed on the second substrate 270. The first portion of the path 211 and the second portion of the path 212 are connected to each other by a through silicon via (TSV). The second electrical path 220 includes a third partial path 221 disposed on the first substrate 260 and a fourth partial path 222 disposed on the second substrate 270. The third partial path 221 and the fourth partial path 222 are connected to each other by a meandering hole.
副線圈120包括第三電性路徑230與第四電性路徑240。第三電性路徑230與第四電性路徑240分別位於投影面(如圖4所示)上對稱線250的不同側。第三電性路徑230的第一端與第四電性路徑240的第一端分別作為副線圈120的第一端Port3與第二端Port4。第三電性路徑230的第二端於對稱線250處連接第四電性路徑240的第二端。其中,第三電性路徑230與第四電性路徑240相互對稱於對稱線250,如圖4所示。 The secondary coil 120 includes a third electrical path 230 and a fourth electrical path 240. The third electrical path 230 and the fourth electrical path 240 are respectively located on different sides of the symmetry line 250 on the projection surface (as shown in FIG. 4). The first end of the third electrical path 230 and the first end of the fourth electrical path 240 respectively serve as the first end Port 3 and the second end Port 4 of the sub coil 120. The second end of the third electrical path 230 is connected to the second end of the fourth electrical path 240 at a line of symmetry 250. The third electrical path 230 and the fourth electrical path 240 are mutually symmetric with respect to the symmetry line 250, as shown in FIG.
第三電性路徑230包括被配置於第一基底260的第五部份路徑231與被配置於該第二基底270的第六部份路徑232。第五部份路徑231與該第六部份路徑232之間以矽穿孔相互連接。第四電性路徑240包括被配置於第一基底260的第七部份路徑241與被配置於第二基底270的第八部份路徑242。第七部份路徑241與第八部份路徑242之間以矽穿孔相互連接。 The third electrical path 230 includes a fifth partial path 231 disposed on the first substrate 260 and a sixth partial path 232 disposed on the second substrate 270 . The fifth portion of the path 231 and the sixth portion of the path 232 are connected to each other with a meandering hole. The fourth electrical path 240 includes a seventh partial path 241 disposed on the first substrate 260 and an eighth partial path 242 disposed on the second substrate 270. The seventh portion of the path 241 and the eighth portion of the path 242 are connected to each other by a meandering hole.
於本實施例中所述變壓器100的佈局結構可以應用於含有矽穿孔的任何類型積體電路。在一些實施例中,所述變壓器100的佈局結構可能應用於雙層(或更多層)之晶片堆疊。舉例來說(但不限於此),第一基底260與第二基底270可能分別為三維晶片堆疊(three-dimensional chip-stacking structure)中的不同晶片。第一部份路徑211、第三部份路徑221、第五部份路徑231與第七部份路徑241可以被配置在第一基底260(上層晶片)的重新分佈金屬層(Re-distributed layer,RDL),而第二部份路徑212、第四部份路徑222、第六部份路徑232與第八部份路徑242可以被配置在第二基底270(下層晶片)的重新分佈金屬層。 The layout structure of the transformer 100 in this embodiment can be applied to any type of integrated circuit including germanium perforations. In some embodiments, the layout structure of the transformer 100 may be applied to a two-layer (or more layers) wafer stack. For example, but not limited to, the first substrate 260 and the second substrate 270 may each be different wafers in a three-dimensional chip-stacking structure. The first partial path 211, the third partial path 221, the fifth partial path 231 and the seventh partial path 241 may be disposed on a redistributed metal layer (Re-distributed layer) of the first substrate 260 (upper layer wafer). RDL), and the second partial path 212, the fourth partial path 222, the sixth partial path 232, and the eighth partial path 242 may be disposed on the redistribution metal layer of the second substrate 270 (lower layer wafer).
在另一些實施例中,所述變壓器100的佈局結構可能應用於單層晶片中。舉例來說(但不限於此),第一基底260與第二基底270可能分別為同一晶片中不同的重新分佈金屬層。在此假設第一基底260與第二基底270分別為所述同一晶片中的第一重新分佈金屬層(例如上層重新分佈金屬層)與第二重新分佈金屬層(例如下層重新分佈金屬層)。基此,第一部份路徑211、第三部份路徑221、第五部份路徑231與第七部份路徑241可以被配置在所述同一晶片中的第一重新分佈金屬層,而第二部份路徑212、第四部份路徑222、第六部份路徑232與第八部份路徑242可以被配置在所述同一晶片中的第二重新分佈金屬層。 In other embodiments, the layout structure of the transformer 100 may be applied to a single layer wafer. For example, but not limited to, the first substrate 260 and the second substrate 270 may each be a different redistribution metal layer in the same wafer. It is assumed herein that the first substrate 260 and the second substrate 270 are respectively a first redistribution metal layer (eg, an upper redistribution metal layer) and a second redistribution metal layer (eg, a lower redistribution metal layer) in the same wafer. Accordingly, the first partial path 211, the third partial path 221, the fifth partial path 231 and the seventh partial path 241 may be disposed on the first redistributed metal layer in the same wafer, and the second The partial path 212, the fourth partial path 222, the sixth partial path 232, and the eighth partial path 242 may be disposed in a second redistribution metal layer in the same wafer.
當該第一部份路徑211的電流方向為沿對稱線250的第一方向時,第二部份路徑212的電流方向為沿對稱線250的第二 方向,第三部份路徑221的電流方向為所述第二方向,而第四部份路徑222的電流方向為所述第一方向。所述第一方向不同於所述第二方向,例如,所述第一方向與所述第二方向互為反方向。 另外,當第五部份路徑231的電流方向為所述第一方向時,第六部份路徑232的電流方向為所述第二方向,第七部份路徑241的電流方向為所述第二方向,而第八部份路徑242的電流方向為所述第一方向。 When the current direction of the first partial path 211 is the first direction along the symmetry line 250, the current direction of the second partial path 212 is the second along the symmetry line 250. In the direction, the current direction of the third partial path 221 is the second direction, and the current direction of the fourth partial path 222 is the first direction. The first direction is different from the second direction, for example, the first direction and the second direction are opposite to each other. In addition, when the current direction of the fifth partial path 231 is the first direction, the current direction of the sixth partial path 232 is the second direction, and the current direction of the seventh partial path 241 is the second direction. The direction, and the current direction of the eighth partial path 242 is the first direction.
於圖2至圖4所示實施例中,主線圈110的第一部份路徑211包括第一導線段211_1與第二導線段211_2,而主線圈110的第二部份路徑212包括第三導線段212_1。第一導線段211_1的第一端作為主線圈110的第一端Port1。第一導線段211_1的第二端經由第一矽穿孔301連接至第三導線段212_1的第一端。第三導線段212_1的第二端經由第二矽穿孔302連接至第二導線段211_2的第一端。在一實施例中,第一導線段211_1可為彎曲線段,第二導線段211_2可為U型線段之一半呈L線段,及第三導線段212_1可為直線段。 In the embodiment shown in FIG. 2 to FIG. 4, the first partial path 211 of the main coil 110 includes a first wire segment 211_1 and a second wire segment 211_2, and the second partial path 212 of the primary coil 110 includes a third wire. Segment 212_1. The first end of the first wire segment 211_1 serves as the first end Port1 of the main coil 110. The second end of the first wire segment 211_1 is connected to the first end of the third wire segment 212_1 via the first turnout 301. The second end of the third wire segment 212_1 is connected to the first end of the second wire segment 211_2 via the second turnout 302. In one embodiment, the first wire segment 211_1 may be a curved line segment, the second wire segment 211_2 may be one of the U-shaped segments and the L-line segment, and the third wire segment 212_1 may be a straight segment.
主線圈110的第三部份路徑221包括第四導線段221_1與第五導線段221_2,而主線圈110的第四部份路徑222包括第六導線段222_1。第四導線段221_1的第一端作為主線圈110的第二端Port2。第四導線段221_1的第二端經由第三矽穿孔303連接至第六導線段222_1的第一端。第六導線段222_1的第二端經由第四矽穿孔304連接至第五導線段221_2的第一端。第五導線段 221_2的第二端於對稱線250處連接第二導線段211_2的第二端。在一實施例中,第四導線段221_1可為彎曲線段,第五導線段221_2可為U型線段之一半呈L線段並與第二導線段211_2連接呈U型線段,及第六導線段222_1可為直線段。第五導線段221_2可與第二導線段211_2連接呈U型線段。 The third partial path 221 of the main coil 110 includes a fourth wire segment 221_1 and a fifth wire segment 221_2, and the fourth partial path 222 of the primary coil 110 includes a sixth wire segment 222_1. The first end of the fourth wire segment 221_1 serves as the second end Port2 of the main coil 110. The second end of the fourth wire segment 221_1 is connected to the first end of the sixth wire segment 222_1 via the third turnout 303. The second end of the sixth wire segment 222_1 is connected to the first end of the fifth wire segment 221_2 via the fourth turn aperture 304. Fifth wire segment The second end of 221_2 is connected to the second end of the second wire segment 211_2 at the symmetry line 250. In an embodiment, the fourth wire segment 221_1 can be a curved line segment, and the fifth wire segment 221_2 can be one of the U-shaped segments and an L-line segment and connected to the second wire segment 211_2 to form a U-shaped segment, and the sixth wire segment 222_1 Can be a straight line segment. The fifth wire segment 221_2 can be connected to the second wire segment 211_2 as a U-shaped line segment.
副線圈120的第五部份路徑231包括第一導線段231_1,而第六部份路徑232包括第二導線段232_1。第一導線段231_1的第一端作為副線圈120的第一端Port3。第一導線段231_1的第二端經由第一矽穿孔305連接至第二導線段232_1的第一端。副線圈120的第七部份路徑241包括第三導線段241_1,而第八部份路徑242包括第四導線段242_1。第三導線段241_1的第一端作為副線圈120的第二端Port4。第三導線段241_1的第二端經由第二矽穿孔306連接至第四導線段242_1的第一端。第四導線段242_1的第二端連接第二導線段232_1的第二端。在一實施例中,第一導線段231_1可為彎曲線段,而第二導線段232_1可為U型線段之一半呈L線段。第三導線段241_1可為彎曲線段,而第四導線段242_1可為U型線段之一半呈L線段並與第二導線段232_1連接呈U型線段。在一實施例中,第一導線段231_1設置於第一導線段211_1與第二導線段211_2間,而第三導線段241_1設置於第四導線段221_1與第五導線段221_2間。在一實施例中,第二導線段232_1連接第四導線段242_1形成U型線段,且第二導線段232_1連接第四導線段242_1形成U型線段設置於第三導線段 212_1與第六導線段222_1間。 The fifth partial path 231 of the secondary coil 120 includes a first wire segment 231_1 and the sixth partial path 232 includes a second wire segment 232_1. The first end of the first wire segment 231_1 serves as the first end Port3 of the secondary coil 120. The second end of the first wire segment 231_1 is connected to the first end of the second wire segment 232_1 via the first turnout 305. The seventh partial path 241 of the secondary coil 120 includes a third wire segment 241_1, and the eighth partial path 242 includes a fourth wire segment 242_1. The first end of the third wire segment 241_1 serves as the second end Port 4 of the secondary coil 120. The second end of the third wire segment 241_1 is coupled to the first end of the fourth wire segment 242_1 via a second turnout 306. The second end of the fourth wire segment 242_1 is connected to the second end of the second wire segment 232_1. In an embodiment, the first wire segment 231_1 may be a curved line segment, and the second wire segment 232_1 may be one of the U-shaped segments and an L-line segment. The third wire segment 241_1 may be a curved line segment, and the fourth wire segment 242_1 may be one of the U-shaped segments and an L-line segment and connected to the second wire segment 232_1 as a U-shaped segment. In one embodiment, the first wire segment 231_1 is disposed between the first wire segment 211_1 and the second wire segment 211_2, and the third wire segment 241_1 is disposed between the fourth wire segment 221_1 and the fifth wire segment 221_2. In an embodiment, the second wire segment 232_1 is connected to the fourth wire segment 242_1 to form a U-shaped line segment, and the second wire segment 232_1 is connected to the fourth wire segment 242_1 to form a U-shaped segment disposed on the third wire segment. 212_1 is between the sixth wire segment 222_1.
為了降低共模雜訊,所以系統電路通常設針成差動型式,以提高其差動增益並抑制其共模雜訊增益。為此,被動元件為了配合差動信號而強調其對稱性結構。若以對稱線250為其變壓器中心線,則對稱線250的左右為鏡像對稱之佈局,可以得知本實施例所述三維積體電路(3DIC)之三維對稱型垂直變壓器100具有良好的對稱性結構。因此,變壓器100適合應用於差動架構的電路設計之中。由圖2至圖4所示實施例觀之,其主線圈110及副線圈120的圈數比例為2:1,因此圖2至圖4所示變壓器100為圈數比2:1之變壓器。本實施例利用3DIC製程中的矽穿孔(TSV)之垂直路徑以及不同基底(晶片)的平面路徑來實現對稱型的變壓器100。因此,變壓器100可以節省晶片面積。再者,所述變壓器100可應用於不同晶片之間的垂直信號耦合傳輸。 In order to reduce common mode noise, the system circuit is usually set to a differential type to increase its differential gain and suppress its common mode noise gain. To this end, the passive component emphasizes its symmetrical structure in order to match the differential signal. If the symmetry line 250 is the center line of the transformer, the left and right sides of the symmetry line 250 are mirror symmetrical, and it can be known that the three-dimensional symmetrical vertical transformer 100 of the three-dimensional integrated circuit (3DIC) of the present embodiment has good symmetry. structure. Therefore, the transformer 100 is suitable for use in the circuit design of the differential architecture. 2 to 4, the ratio of the number of turns of the primary coil 110 and the secondary coil 120 is 2:1, so the transformer 100 shown in FIGS. 2 to 4 is a transformer having a turns ratio of 2:1. This embodiment implements a symmetrical transformer 100 by utilizing the vertical path of the turns of the turns (TSV) in the 3DIC process and the planar path of the different substrates (wafers). Therefore, the transformer 100 can save wafer area. Furthermore, the transformer 100 can be applied to vertical signal coupling transmissions between different wafers.
無論如何,圖1所示變壓器100的實施方式不應受限於圖2至圖4所示實施例。舉例來說,圖5是依照本發明另一實施例說明圖1所示變壓器100的佈局結構的組合示意圖。圖6是依照本發明實施例說明圖5所示變壓器100的佈局結構的垂直投影示意圖。請參照圖5至圖6,變壓器100包括主線圈110以及副線圈120。主線圈110包括第一電性路徑510與第二電性路徑520。第一電性路徑510與第二電性路徑520分別位於變壓器100的投影面(如圖6所示)上一對稱線550的不同側。第一電性路徑510的第一端與第二電性路徑520的第一端分別作為主線圈110的第 一端Port1與第二端Port2。第一電性路徑510的第二端於對稱線550處連接第二電性路徑520的第二端。其中,第一電性路徑510與第二電性路徑520相互對稱於對稱線550,如圖6所示。副線圈120包括第三電性路徑530與第四電性路徑540。第三電性路徑530與第四電性路徑540分別位於投影面(如圖6所示)上對稱線550的不同側。第三電性路徑530的第一端與第四電性路徑540的第一端分別作為副線圈120的第一端Port3與第二端Port4。第三電性路徑530的第二端於對稱線550處連接第四電性路徑540的第二端。其中,第三電性路徑530與第四電性路徑540相互對稱於對稱線550,如圖6所示。圖5至圖6所示變壓器100、第一電性路徑510、第二電性路徑520、第三電性路徑530與第四電性路徑540可以參照圖2至圖4所示變壓器100、第一電性路徑210、第二電性路徑220、第三電性路徑230與第四電性路徑240的相關說明而類推之,故不再贅述。 In any event, the embodiment of transformer 100 shown in FIG. 1 should not be limited to the embodiment shown in FIGS. 2 through 4. For example, FIG. 5 is a schematic diagram showing the combination of the layout structure of the transformer 100 shown in FIG. 1 according to another embodiment of the present invention. FIG. 6 is a schematic vertical plan view showing the layout structure of the transformer 100 shown in FIG. 5 according to an embodiment of the invention. Referring to FIGS. 5-6 , the transformer 100 includes a primary coil 110 and a secondary coil 120 . The main coil 110 includes a first electrical path 510 and a second electrical path 520. The first electrical path 510 and the second electrical path 520 are respectively located on different sides of a line of symmetry 550 on the projection surface of the transformer 100 (shown in FIG. 6). The first end of the first electrical path 510 and the first end of the second electrical path 520 respectively serve as the main coil 110 One end is Port1 and the second end is Port2. The second end of the first electrical path 510 is coupled to the second end of the second electrical path 520 at a line of symmetry 550. The first electrical path 510 and the second electrical path 520 are symmetric with each other on the symmetry line 550, as shown in FIG. 6. The secondary coil 120 includes a third electrical path 530 and a fourth electrical path 540. The third electrical path 530 and the fourth electrical path 540 are respectively located on different sides of the symmetry line 550 on the projection surface (as shown in FIG. 6). The first end of the third electrical path 530 and the first end of the fourth electrical path 540 serve as the first end Port 3 and the second end Port 4 of the secondary coil 120, respectively. The second end of the third electrical path 530 is coupled to the second end of the fourth electrical path 540 at a line of symmetry 550. The third electrical path 530 and the fourth electrical path 540 are symmetric with each other on the symmetry line 550, as shown in FIG. 6. The transformer 100, the first electrical path 510, the second electrical path 520, the third electrical path 530, and the fourth electrical path 540 shown in FIG. 5 to FIG. 6 can refer to the transformer 100 and the first embodiment shown in FIG. 2 to FIG. The descriptions of an electrical path 210, a second electrical path 220, a third electrical path 230, and a fourth electrical path 240 are analogous and will not be described again.
第一電性路徑510包括被配置於第一基底260上的第一部份路徑511與被配置於第二基底270上的第二部份路徑512。第二電性路徑520包括被配置於第一基底260上的第三部份路徑521與被配置於第二基底270上的第四部份路徑522。第三電性路徑530包括被配置於第一基底260上的第五部份路徑531與被配置於第二基底270上的第六部份路徑532。第四電性路徑540包括被配置於第一基底260上的第七部份路徑541與被配置於第二基底270上的第八部份路徑542。於本實施例中(但不限於此),第一部份 路徑511、第三部份路徑521、第五部份路徑531與第七部份路徑541被配置在第一基底260(上層晶片)的重新分佈金屬層(RDL),而第二部份路徑512、第四部份路徑522、第六部份路徑532與第八部份路徑542被配置在第二基底270(下層晶片)的重新分佈金屬層。 The first electrical path 510 includes a first partial path 511 disposed on the first substrate 260 and a second partial path 512 disposed on the second substrate 270. The second electrical path 520 includes a third partial path 521 disposed on the first substrate 260 and a fourth partial path 522 disposed on the second substrate 270. The third electrical path 530 includes a fifth partial path 531 disposed on the first substrate 260 and a sixth partial path 532 disposed on the second substrate 270. The fourth electrical path 540 includes a seventh partial path 541 disposed on the first substrate 260 and an eighth partial path 542 disposed on the second substrate 270. In this embodiment (but not limited to), the first part The path 511, the third partial path 521, the fifth partial path 531 and the seventh partial path 541 are disposed on the redistribution metal layer (RDL) of the first substrate 260 (upper wafer), and the second partial path 512 The fourth partial path 522, the sixth partial path 532 and the eighth partial path 542 are disposed on the redistribution metal layer of the second substrate 270 (lower layer wafer).
於圖5至圖6所示實施例中,主線圈110的第一部份路徑511包括第一導線段511_1、第二導線段511_2與第三導線段511_3,而主線圈110的第二部份路徑512包括第四導線段512_1與第五導線段512_2。第一導線段511_1的第一端作為主線圈110的第一端Port1。第一導線段511_1的第二端經由第一矽穿孔581連接至第四導線段512_1的第一端。第四導線段512_1的第二端經由第二矽穿孔582連接至第二導線段511_2的第一端。第二導線段511_2的第二端經由第三矽穿孔583連接至第五導線段512_2的第一端。第五導線段512_2的第二端經由第四矽穿孔584連接至第三導線段511_3的第一端。在一實施例中,第一導線段511_1可為彎曲線段,第二導線段511_2可為U型線段,第三導線段511_3可為U型線段之一半呈L線段,而第四導線段512_1及第五導線段512_2可為直線段。 In the embodiment shown in FIG. 5 to FIG. 6, the first partial path 511 of the main coil 110 includes a first wire segment 511_1, a second wire segment 511_2 and a third wire segment 511_3, and the second portion of the main coil 110. The path 512 includes a fourth wire segment 512_1 and a fifth wire segment 512_2. The first end of the first wire segment 511_1 serves as the first end Port1 of the main coil 110. The second end of the first wire segment 511_1 is connected to the first end of the fourth wire segment 512_1 via the first turns 581. The second end of the fourth wire segment 512_1 is connected to the first end of the second wire segment 511_2 via the second turnout 582. The second end of the second wire segment 511_2 is coupled to the first end of the fifth wire segment 512_2 via a third turn aperture 583. The second end of the fifth wire segment 512_2 is coupled to the first end of the third wire segment 511_3 via a fourth turn aperture 584. In an embodiment, the first wire segment 511_1 may be a curved line segment, the second wire segment 511_2 may be a U-shaped wire segment, and the third wire segment 511_3 may be one of the U-shaped segments and an L-line segment, and the fourth wire segment 512_1 and The fifth wire segment 512_2 can be a straight segment.
主線圈110的第三部份路徑521包括第六導線段521_1、第七導線段521_2與第八導線段521_3,而主線圈110的第四部份路徑522包括第九導線段522_1與第十導線段522_2。第六導線段521_1的第一端作為主線圈110的第二端Port2。第六導線段521_1 的第二端經由第五矽穿孔585連接至第九導線段522_1的第一端。第九導線段522_1的第二端經由第六矽穿孔586連接至第七導線段521_2的第一端。第七導線段521_2的第二端經由第七矽穿孔587連接至第十導線段522_2的第一端。第十導線段522_2的第二端經由第八矽穿孔588連接至第八導線段521_3的第一端。第八導線段521_3的第二端於對稱線550處連接第三導線段511_3的第二端。在一實施例中,第六導線段521_1可為彎曲線段,第七導線段521_2可為U型線段,第八導線段521_3可為U型線段之一半呈L線段,而第九導線段522_1與第十導線段522_2可為直線段。第八導線段521_3可與第三導線段511_3連接呈U型線段。 The third partial path 521 of the main coil 110 includes a sixth wire segment 521_1, a seventh wire segment 521_2 and an eighth wire segment 521_3, and the fourth partial path 522 of the primary coil 110 includes a ninth wire segment 522_1 and a tenth wire. Segment 522_2. The first end of the sixth wire segment 521_1 serves as the second end Port2 of the main coil 110. Sixth wire segment 521_1 The second end is connected to the first end of the ninth wire segment 522_1 via a fifth turn aperture 585. The second end of the ninth wire segment 522_1 is coupled to the first end of the seventh wire segment 521_2 via a sixth turn puncturing 586. The second end of the seventh wire segment 521_2 is connected to the first end of the tenth wire segment 522_2 via a seventh turnout 587. The second end of the tenth wire segment 522_2 is connected to the first end of the eighth wire segment 521_3 via the eighth turn puncturing 588. The second end of the eighth wire segment 521_3 is connected to the second end of the third wire segment 511_3 at a line of symmetry 550. In an embodiment, the sixth wire segment 521_1 may be a curved line segment, the seventh wire segment 521_2 may be a U-shaped wire segment, and the eighth wire segment 521_3 may be one of the U-shaped segments and an L-line segment, and the ninth wire segment 522_1 is The tenth wire segment 522_2 can be a straight segment. The eighth wire segment 521_3 may be connected to the third wire segment 511_3 as a U-shaped line segment.
副線圈120的第五部份路徑531包括第一導線段531_1,而第六部份路徑532包括第二導線段532_1。第一導線段531_1的第一端作為副線圈120的第一端Port3。第一導線段531_1的第二端經由第一矽穿孔589連接至第二導線段532_1的第一端。副線圈120的第七部份路徑541包括第三導線段541_1,而第八部份路徑542包括第四導線段542_1。第三導線段541_1的第一端作為副線圈120的第二端Port4。第三導線段541_1的第二端經由第二矽穿孔590連接至第四導線段542_1的第一端。第四導線段542_1的第二端連接第二導線段532_1的第二端。在一實施例中,第一導線段531_1可為彎曲線段,而第二導線段532_1可為U型線段之一半呈L線段。第三導線段541_1可為彎曲線段,而第四導線 段542_1可為U型線段之一半呈L線段並與第二導線段532_1連接呈U型線段。在一實施例中,第一導線段531_1設置於第二導線段511_2與第三導線段511_3間,而第三導線段541_1設置於第七導線段521_2與第八導線段521_3間。在一實施例中,第二導線段532_1連接第四導線段542_1形成U型線段,且第二導線段532_1連接第四導線段542_1形成U型線段設置於第五導線段512_2與第十導線段522_2間。 The fifth partial path 531 of the secondary coil 120 includes a first wire segment 531_1 and the sixth partial path 532 includes a second wire segment 532_1. The first end of the first wire segment 531_1 serves as the first end Port3 of the secondary coil 120. The second end of the first wire segment 531_1 is connected to the first end of the second wire segment 532_1 via the first turnout 589. The seventh partial path 541 of the secondary coil 120 includes a third wire segment 541_1, and the eighth partial path 542 includes a fourth wire segment 542_1. The first end of the third wire segment 541_1 serves as the second end Port4 of the secondary coil 120. The second end of the third wire segment 541_1 is connected to the first end of the fourth wire segment 542_1 via the second turn-by-hole 590. The second end of the fourth wire segment 542_1 is connected to the second end of the second wire segment 532_1. In an embodiment, the first wire segment 531_1 may be a curved line segment, and the second wire segment 532_1 may be one of the U-shaped segments and an L segment. The third wire segment 541_1 can be a curved line segment and the fourth wire The segment 542_1 may be an L-line segment of one of the U-shaped line segments and connected to the second wire segment 532_1 as a U-shaped line segment. In one embodiment, the first wire segment 531_1 is disposed between the second wire segment 511_2 and the third wire segment 511_3, and the third wire segment 541_1 is disposed between the seventh wire segment 521_2 and the eighth wire segment 521_3. In an embodiment, the second wire segment 532_1 is connected to the fourth wire segment 542_1 to form a U-shaped line segment, and the second wire segment 532_1 is connected to the fourth wire segment 542_1 to form a U-shaped segment disposed on the fifth wire segment 512_2 and the tenth wire segment. 522_2.
若以對稱線550為其變壓器中心線,則對稱線550的左右為鏡像對稱之佈局,可以得知圖5至圖6所示三維積體電路(3DIC)之三維對稱型垂直變壓器100具有良好的對稱性結構。因此,圖5至圖6所示變壓器100適合應用於差動架構的電路設計之中。由圖5至圖6所示實施例觀之,其主線圈110及副線圈120的圈數比例為3:1,因此圖5至圖6所示變壓器100為圈數比3:1之變壓器。本實施例利用3DIC製程中的矽穿孔(TSV)之垂直路徑以及不同基底(晶片)的平面路徑來實現對稱型的變壓器100。因此,變壓器100可以節省晶片面積。再者,所述變壓器100可應用於不同晶片之間的垂直信號耦合傳輸。 If the symmetry line 550 is the center line of the transformer, the left and right sides of the symmetry line 550 are mirror symmetrical, and it can be known that the three-dimensional symmetrical vertical transformer 100 of the three-dimensional integrated circuit (3DIC) shown in FIGS. 5 to 6 has good performance. Symmetrical structure. Therefore, the transformer 100 shown in FIGS. 5 to 6 is suitable for use in the circuit design of the differential architecture. 5 to 6, the ratio of the number of turns of the primary coil 110 and the secondary coil 120 is 3:1, so that the transformer 100 shown in FIGS. 5 to 6 is a transformer having a turns ratio of 3:1. This embodiment implements a symmetrical transformer 100 by utilizing the vertical path of the turns of the turns (TSV) in the 3DIC process and the planar path of the different substrates (wafers). Therefore, the transformer 100 can save wafer area. Furthermore, the transformer 100 can be applied to vertical signal coupling transmissions between different wafers.
圖7是依照本發明又一實施例說明圖1所示變壓器100的佈局結構的組合示意圖。圖8是依照本發明實施例說明圖7所示變壓器100的佈局結構的垂直投影示意圖。請參照圖7至圖8,變壓器100包括主線圈110以及副線圈120。主線圈110包括第一電性路徑710與第二電性路徑720。第一電性路徑710與第二電性 路徑720分別位於變壓器100的投影面(如圖8所示)上一對稱線750的不同側。第一電性路徑710的第一端與第二電性路徑720的第一端分別作為主線圈110的第一端Port1與第二端Port2。第一電性路徑710的第二端於對稱線750處連接第二電性路徑720的第二端。其中,第一電性路徑710與第二電性路徑720相互對稱於對稱線750,如圖8所示。副線圈120包括第三電性路徑730與第四電性路徑740。第三電性路徑730與第四電性路徑740分別位於投影面(如圖8所示)上對稱線750的不同側。第三電性路徑730的第一端與第四電性路徑740的第一端分別作為副線圈120的第一端Port3與第二端Port4。第三電性路徑730的第二端於對稱線750處連接第四電性路徑740的第二端。其中,第三電性路徑730與第四電性路徑740相互對稱於對稱線750,如圖8所示。 圖7至圖8所示變壓器100、第一電性路徑710、第二電性路徑720、第三電性路徑730與第四電性路徑740可以參照圖2至圖4所示變壓器100、第一電性路徑210、第二電性路徑220、第三電性路徑230與第四電性路徑240的相關說明而類推之,故不再贅述。 FIG. 7 is a schematic diagram showing the combination of the layout structure of the transformer 100 shown in FIG. 1 according to still another embodiment of the present invention. FIG. 8 is a schematic vertical plan view showing the layout structure of the transformer 100 shown in FIG. 7 according to an embodiment of the present invention. Referring to FIGS. 7-8 , the transformer 100 includes a primary coil 110 and a secondary coil 120 . The main coil 110 includes a first electrical path 710 and a second electrical path 720. First electrical path 710 and second electrical Paths 720 are respectively located on different sides of a line of symmetry 750 on the projection surface of transformer 100 (shown in Figure 8). The first end of the first electrical path 710 and the first end of the second electrical path 720 respectively serve as the first end Port1 and the second end Port2 of the main coil 110. The second end of the first electrical path 710 is coupled to the second end of the second electrical path 720 at a line of symmetry 750. The first electrical path 710 and the second electrical path 720 are mutually symmetric with respect to the symmetric line 750, as shown in FIG. The secondary coil 120 includes a third electrical path 730 and a fourth electrical path 740. The third electrical path 730 and the fourth electrical path 740 are respectively located on different sides of the symmetry line 750 on the projection surface (as shown in FIG. 8). The first end of the third electrical path 730 and the first end of the fourth electrical path 740 respectively serve as the first end Port 3 and the second end Port 4 of the secondary coil 120. The second end of the third electrical path 730 is coupled to the second end of the fourth electrical path 740 at a line of symmetry 750. The third electrical path 730 and the fourth electrical path 740 are mutually symmetric with respect to the symmetric line 750, as shown in FIG. The transformer 100, the first electrical path 710, the second electrical path 720, the third electrical path 730, and the fourth electrical path 740 shown in FIG. 7 to FIG. 8 can refer to the transformer 100 and the first embodiment shown in FIG. 2 to FIG. The descriptions of an electrical path 210, a second electrical path 220, a third electrical path 230, and a fourth electrical path 240 are analogous and will not be described again.
第一電性路徑710包括被配置於第一基底260上的第一部份路徑711與被配置於第二基底270上的第二部份路徑712。第二電性路徑720包括被配置於第一基底260上的第三部份路徑721與被配置於第二基底270上的第四部份路徑722。第三電性路徑730包括被配置於第一基底260上的第五部份路徑731與被配置於 第二基底270上的第六部份路徑732。第四電性路徑740包括被配置於第一基底260上的第七部份路徑741與被配置於第二基底270上的第八部份路徑742。於本實施例中(但不限於此),第一部份路徑711、第三部份路徑721、第五部份路徑731與第七部份路徑741被配置在第一基底260(上層晶片)的重新分佈金屬層(RDL),而第二部份路徑712、第四部份路徑722、第六部份路徑732與第八部份路徑742被配置在第二基底270(下層晶片)的重新分佈金屬層。 The first electrical path 710 includes a first partial path 711 disposed on the first substrate 260 and a second partial path 712 disposed on the second substrate 270. The second electrical path 720 includes a third partial path 721 disposed on the first substrate 260 and a fourth partial path 722 disposed on the second substrate 270. The third electrical path 730 includes a fifth partial path 731 disposed on the first substrate 260 and configured to be A sixth partial path 732 on the second substrate 270. The fourth electrical path 740 includes a seventh partial path 741 disposed on the first substrate 260 and an eighth partial path 742 disposed on the second substrate 270. In the present embodiment, but not limited thereto, the first partial path 711, the third partial path 721, the fifth partial path 731 and the seventh partial path 741 are disposed on the first substrate 260 (upper layer wafer) a redistribution metal layer (RDL), and the second partial path 712, the fourth partial path 722, the sixth partial path 732, and the eighth partial path 742 are disposed on the second substrate 270 (lower layer wafer) Distribution of metal layers.
於圖7至圖8所示實施例中,主線圈110的第一部份路徑711包括第一導線段711_1、第二導線段711_2、第三導線段711_3與第四導線段711_4,而主線圈110的第二部份路徑712包括第五導線段712_1、第六導線段712_2與第七導線段712_3。第一導線段711_1的第一端作為主線圈110的第一端Port1。第一導線段711_1的第二端經由第一矽穿孔781連接至第五導線段712_1的第一端。第五導線段712_1的第二端經由第二矽穿孔782連接至第二導線段711_2的第一端。第二導線段711_2的第二端經由第三矽穿孔783連接至第六導線段712_2的第一端。第六導線段712_2的第二端經由第四矽穿孔784連接至第三導線段711_3的第一端。第三導線段711_3的第二端經由第五矽穿孔785連接至第七導線段712_3的第一端。第七導線段712_3的第二端經由第六矽穿孔786連接至第四導線段711_4的第一端。在一實施例中,第一導線段711_1可為彎曲線段,第二導線段711_2與第三導線 段711_3可為U型線段,第四導線段711_4可為U型線段之一半呈L線段,而第五導線段712_1、第六導線段712_2與第七導線段712_3可為直線段。 In the embodiment shown in FIG. 7 to FIG. 8, the first partial path 711 of the main coil 110 includes a first wire segment 711_1, a second wire segment 711_2, a third wire segment 711_3 and a fourth wire segment 711_4, and the main coil The second partial path 712 of 110 includes a fifth wire segment 712_1, a sixth wire segment 712_2, and a seventh wire segment 712_3. The first end of the first wire segment 711_1 serves as the first end Port1 of the main coil 110. The second end of the first wire segment 711_1 is connected to the first end of the fifth wire segment 712_1 via the first turn-by-hole 781. The second end of the fifth wire segment 712_1 is connected to the first end of the second wire segment 711_2 via the second turns 782. The second end of the second wire segment 711_2 is connected to the first end of the sixth wire segment 712_2 via a third turnout 783. The second end of the sixth wire segment 712_2 is coupled to the first end of the third wire segment 711_3 via a fourth turn aperture 784. The second end of the third wire segment 711_3 is coupled to the first end of the seventh wire segment 712_3 via a fifth turn aperture 785. The second end of the seventh wire segment 712_3 is connected to the first end of the fourth wire segment 711_4 via a sixth turn aperture 786. In an embodiment, the first wire segment 711_1 can be a curved line segment, the second wire segment 711_2 and the third wire The segment 711_3 may be a U-shaped line segment, and the fourth wire segment 711_4 may be one of the U-shaped segments and an L-line segment, and the fifth wire segment 712_1, the sixth wire segment 712_2, and the seventh wire segment 712_3 may be straight segments.
主線圈110的第三部份路徑721包括第八導線段721_1、第九導線段721_2、第十導線段721_3與第十一導線段721_4,主線圈110的第四部份路徑722包括第十二導線段722_1、第十三導線段722_2與第十四導線段722_3。第八導線段721_1的第一端作為主線圈110的第二端Port2。第八導線段721_1的第二端經由第七矽穿孔787連接至第十二導線段722_1的第一端。第十二導線段722_1的第二端經由第八矽穿孔788連接至第九導線段721_2的第一端。第九導線段721_2的第二端經由第九矽穿孔789連接至第十三導線段722_2的第一端。第十三導線段722_2的第二端經由第十矽穿孔790連接至第十導線段721_3的第一端。第十導線段721_3的第二端經由第十一矽穿孔791連接至第十四導線段722_3的第一端。第十四導線段722_3的第二端經由第十二矽穿孔792連接至第十一導線段721_4的第一端。第十一導線段721_4的第二端於對稱線750處連接第四導線段711_4的第二端。在一實施例中,第八導線段721_1可為彎曲線段,第九導線段721_2與第十導線段721_3可為U型線段,第十一導線段721_4可為U型線段之一半呈L線段,而第十二導線段722_1、第十三導線段722_2與第十四導線段722_3可為直線段。第十一導線段721_4可與第四導線段711_4連接呈U型線段。 The third partial path 721 of the main coil 110 includes an eighth wire segment 721_1, a ninth wire segment 721_2, a tenth wire segment 721_3 and an eleventh wire segment 721_4, and the fourth partial path 722 of the main coil 110 includes the twelfth wire. The wire segment 722_1, the thirteenth wire segment 722_2, and the fourteenth wire segment 722_3. The first end of the eighth wire segment 721_1 serves as the second end Port2 of the main coil 110. The second end of the eighth wire segment 721_1 is connected to the first end of the twelfth wire segment 722_1 via a seventh turn 787. The second end of the twelfth wire segment 722_1 is connected to the first end of the ninth wire segment 721_2 via the eighth turn 788. The second end of the ninth wire segment 721_2 is connected to the first end of the thirteenth wire segment 722_2 via a ninth turn aperture 789. The second end of the thirteenth wire segment 722_2 is connected to the first end of the tenth wire segment 721_3 via the tenth turn 790. The second end of the tenth wire segment 721_3 is connected to the first end of the fourteenth wire segment 722_3 via the eleventh turn aperture 791. The second end of the fourteenth wire segment 722_3 is connected to the first end of the eleventh wire segment 721_4 via the twelfth turn 792. The second end of the eleventh wire segment 721_4 is connected to the second end of the fourth wire segment 711_4 at a line of symmetry 750. In an embodiment, the eighth wire segment 721_1 may be a curved line segment, the ninth wire segment 721_2 and the tenth wire segment 721_3 may be U-shaped segments, and the eleventh wire segment 721_4 may be one of the U-shaped segments and an L-line segment. The twelfth wire segment 722_1, the thirteenth wire segment 722_2, and the fourteenth wire segment 722_3 may be straight segments. The eleventh wire segment 721_4 may be connected to the fourth wire segment 711_4 as a U-shaped line segment.
副線圈120的第五部份路徑731包括第一導線段731_1,而副線圈120的第六部份路徑732包括第二導線段732_1。第一導線段731_1的第一端作為副線圈120的第一端Port3。第一導線段731_1的第二端經由第一矽穿孔793連接至第二導線段732_1的第一端。副線圈120的第七部份路徑741包括第三導線段741_1,而副線圈120的第八部份路徑742包括第四導線段742_1。第三導線段741_1的第一端作為副線圈120的第二端Port4。第三導線段741_1的第二端經由第二矽穿孔794連接至第四導線段742_1的第一端。第四導線段742_1的第二端連接第二導線段732_1的第二端。在一實施例中,第一導線段731_1可為彎曲線段,而第二導線段732_1可為U型線段之一半呈L線段。第三導線段741_1可為彎曲線段,而第四導線段742_1可為U型線段之一半呈L線段並與第二導線段732_1連接呈U型線段。在一實施例中,第一導線段731_1設置於第三導線段711_3與第四導線段711_4間,而第三導線段741_1設置於第十導線段721_3與第十一導線段721_4間。在一實施例中,第二導線段732_1連接第四導線段742_1形成U型線段,且第二導線段732_1連接第四導線段742_1形成U型線段設置於第七導線段712_3與第十四導線段722_3間。 The fifth partial path 731 of the secondary coil 120 includes a first wire segment 731_1, and the sixth partial path 732 of the secondary coil 120 includes a second wire segment 732_1. The first end of the first wire segment 731_1 serves as the first end Port3 of the secondary coil 120. The second end of the first wire segment 731_1 is connected to the first end of the second wire segment 732_1 via the first turns 793. The seventh partial path 741 of the secondary coil 120 includes a third wire segment 741_1, and the eighth partial path 742 of the secondary coil 120 includes a fourth wire segment 742_1. The first end of the third wire segment 741_1 serves as the second end Port4 of the secondary coil 120. The second end of the third wire segment 741_1 is coupled to the first end of the fourth wire segment 742_1 via a second turn-by-hole 794. The second end of the fourth wire segment 742_1 is connected to the second end of the second wire segment 732_1. In an embodiment, the first wire segment 731_1 may be a curved line segment, and the second wire segment 732_1 may be one of the U-shaped segments and an L-line segment. The third wire segment 741_1 may be a curved line segment, and the fourth wire segment 742_1 may be one of the U-shaped segments and an L-line segment and connected to the second wire segment 732_1 as a U-shaped segment. In one embodiment, the first wire segment 731_1 is disposed between the third wire segment 711_3 and the fourth wire segment 711_4, and the third wire segment 741_1 is disposed between the tenth wire segment 721_3 and the eleventh wire segment 721_4. In an embodiment, the second wire segment 732_1 is connected to the fourth wire segment 742_1 to form a U-shaped wire segment, and the second wire segment 732_1 is connected to the fourth wire segment 742_1 to form a U-shaped segment disposed on the seventh wire segment 712_3 and the fourteenth wire. Section 722_3.
若以對稱線750為其變壓器中心線,則對稱線750的左右為鏡像對稱之佈局,可以得知圖7至圖8所示三維積體電路(3DIC)之三維對稱型垂直變壓器100具有良好的對稱性結構。因此,圖7至圖8所示變壓器100適合應用於差動架構的電路設 計之中。由圖7至圖8所示實施例觀之,其主線圈110及副線圈120的圈數比例為4:1,因此圖7至圖8所示變壓器100為圈數比4:1之變壓器。本實施例利用3DIC製程中的矽穿孔(TSV)之垂直路徑以及不同基底(晶片)的平面路徑來實現對稱型的變壓器100。因此,變壓器100可以節省晶片面積。再者,所述變壓器100可應用於不同晶片之間的垂直信號耦合傳輸。 If the symmetry line 750 is the transformer center line, the left and right sides of the symmetry line 750 are mirror symmetrical layouts, and it can be known that the three-dimensional symmetrical vertical transformer 100 of the three-dimensional integrated circuit (3DIC) shown in FIGS. 7 to 8 has good performance. Symmetrical structure. Therefore, the transformer 100 shown in FIGS. 7 to 8 is suitable for the circuit design of the differential architecture. In the calculation. As seen from the embodiment shown in Figs. 7 to 8, the ratio of the number of turns of the primary coil 110 and the secondary coil 120 is 4:1, so that the transformer 100 shown in Figs. 7 to 8 is a transformer having a turns ratio of 4:1. This embodiment implements a symmetrical transformer 100 by utilizing the vertical path of the turns of the turns (TSV) in the 3DIC process and the planar path of the different substrates (wafers). Therefore, the transformer 100 can save wafer area. Furthermore, the transformer 100 can be applied to vertical signal coupling transmissions between different wafers.
圖9是依照本發明再一實施例說明圖1所示變壓器100的佈局結構的立體透視示意圖。圖10是依照本發明實施例說明圖9所示變壓器100的佈局結構的垂直投影示意圖。請參照圖9至圖10,變壓器100包括主線圈110以及副線圈120。主線圈110包括第一電性路徑910與第二電性路徑920。第一電性路徑910與第二電性路徑920分別位於變壓器100的投影面(如圖10所示)上一對稱線950的不同側。第一電性路徑910的第一端與第二電性路徑920的第一端分別作為主線圈110的第一端Port1與第二端Port2。第一電性路徑910的第二端於對稱線950處連接第二電性路徑920的第二端。其中,第一電性路徑910與第二電性路徑920相互對稱於對稱線950,如圖10所示。副線圈120包括第三電性路徑930與第四電性路徑940。第三電性路徑930與第四電性路徑940分別位於投影面(如圖10所示)上對稱線950的不同側。第三電性路徑930的第一端與第四電性路徑940的第一端分別作為副線圈120的第一端Port3與第二端Port4。第三電性路徑930的第二端於對稱線950處連接第四電性路徑940的第二端。其中, 第三電性路徑930與第四電性路徑940相互對稱於對稱線950,如圖10所示。圖9至圖10所示變壓器100、第一電性路徑910、第二電性路徑920、第三電性路徑930與第四電性路徑940可以參照圖2至圖4所示變壓器100、第一電性路徑210、第二電性路徑220、第三電性路徑230與第四電性路徑240的相關說明而類推之,故不再贅述。 FIG. 9 is a perspective, perspective view showing the layout of the transformer 100 of FIG. 1 according to still another embodiment of the present invention. FIG. 10 is a schematic vertical plan view showing the layout structure of the transformer 100 of FIG. 9 according to an embodiment of the present invention. Referring to FIGS. 9-10 , the transformer 100 includes a primary coil 110 and a secondary coil 120 . The main coil 110 includes a first electrical path 910 and a second electrical path 920. The first electrical path 910 and the second electrical path 920 are respectively located on different sides of a symmetric line 950 on the projection surface of the transformer 100 (as shown in FIG. 10). The first end of the first electrical path 910 and the first end of the second electrical path 920 respectively serve as the first end Port1 and the second end Port2 of the main coil 110. The second end of the first electrical path 910 is connected to the second end of the second electrical path 920 at a line of symmetry 950. The first electrical path 910 and the second electrical path 920 are symmetric with each other on the symmetric line 950, as shown in FIG. The secondary coil 120 includes a third electrical path 930 and a fourth electrical path 940. The third electrical path 930 and the fourth electrical path 940 are respectively located on different sides of the symmetric line 950 on the projection surface (as shown in FIG. 10). The first end of the third electrical path 930 and the first end of the fourth electrical path 940 respectively serve as the first end Port 3 and the second end Port 4 of the secondary coil 120. The second end of the third electrical path 930 is coupled to the second end of the fourth electrical path 940 at a line of symmetry 950. among them, The third electrical path 930 and the fourth electrical path 940 are symmetric with each other from the symmetry line 950, as shown in FIG. The transformer 100, the first electrical path 910, the second electrical path 920, the third electrical path 930, and the fourth electrical path 940 shown in FIG. 9 to FIG. 10 can refer to the transformer 100 and the first embodiment shown in FIG. 2 to FIG. The descriptions of an electrical path 210, a second electrical path 220, a third electrical path 230, and a fourth electrical path 240 are analogous and will not be described again.
第一電性路徑910包括被配置於第一基底260上的第一部份路徑911與被配置於第二基底270上的第二部份路徑912。第二電性路徑920包括被配置於第一基底260上的第三部份路徑921與被配置於第二基底270上的第四部份路徑922。第三電性路徑930包括被配置於第一基底260上的第五部份路徑931與被配置於第二基底270上的第六部份路徑932。第四電性路徑940包括被配置於第一基底260上的第七部份路徑941與被配置於第二基底270上的第八部份路徑942。於本實施例中(但不限於此),第一部份路徑911、第三部份路徑921、第五部份路徑931與第七部份路徑941被配置在第一基底260(上層晶片)的重新分佈金屬層(RDL),而第二部份路徑912、第四部份路徑922、第六部份路徑932與第八部份路徑942被配置在第二基底270(下層晶片)的重新分佈金屬層。 The first electrical path 910 includes a first partial path 911 disposed on the first substrate 260 and a second partial path 912 disposed on the second substrate 270. The second electrical path 920 includes a third partial path 921 disposed on the first substrate 260 and a fourth partial path 922 disposed on the second substrate 270. The third electrical path 930 includes a fifth partial path 931 disposed on the first substrate 260 and a sixth partial path 932 disposed on the second substrate 270. The fourth electrical path 940 includes a seventh partial path 941 disposed on the first substrate 260 and an eighth partial path 942 disposed on the second substrate 270. In the present embodiment, but not limited thereto, the first partial path 911, the third partial path 921, the fifth partial path 931 and the seventh partial path 941 are disposed on the first substrate 260 (upper layer wafer) The redistribution metal layer (RDL), and the second partial path 912, the fourth partial path 922, the sixth partial path 932, and the eighth partial path 942 are disposed on the second substrate 270 (lower layer wafer) Distribution of metal layers.
於圖9至圖10所示實施例中,主線圈110的第二部份路徑912包括第一導線段912_1,主線圈110的第一部份路徑911包括第二導線段911_1。第一導線段912_1的第一端作為主線圈110 的第一端Port1。第一導線段912_1的第二端經由第一矽穿孔901連接至該第二導線段911_1的第一端。主線圈110的第四部份路徑922包括第三導線段922_1,主線圈110的第三部份路徑921包括第四導線段921_1。第三導線段922_1的第一端作為主線圈110的第二端。第三導線段922_1的第二端經由第二矽穿孔902連接至該第四導線段921_1的第一端。第四導線段921_1的第二端連接該第二導線段911_1的第二端。在一實施例中,第一導線段912_1與第三導線段922_1可為彎曲線段,而第二導線段911_1與第四導線段921_1可為O型線段之一半呈U線段。第二導線段911_1可與第四導線段921_1連接呈O型線段。 In the embodiment shown in FIGS. 9-10, the second partial path 912 of the primary coil 110 includes a first wire segment 912_1, and the first partial path 911 of the primary coil 110 includes a second wire segment 911_1. The first end of the first wire segment 912_1 serves as the main coil 110 The first end of Port1. The second end of the first wire segment 912_1 is connected to the first end of the second wire segment 911_1 via the first turns 901. The fourth partial path 922 of the primary coil 110 includes a third wire segment 922_1, and the third partial path 921 of the primary coil 110 includes a fourth wire segment 921_1. The first end of the third wire segment 922_1 serves as the second end of the main coil 110. The second end of the third wire segment 922_1 is connected to the first end of the fourth wire segment 921_1 via a second turn-by-hole 902. The second end of the fourth wire segment 921_1 is connected to the second end of the second wire segment 911_1. In an embodiment, the first wire segment 912_1 and the third wire segment 922_1 may be curved line segments, and the second wire segment 911_1 and the fourth wire segment 921_1 may be U-shaped segments of one of the O-shaped segments. The second wire segment 911_1 can be connected to the fourth wire segment 921_1 as an O-shaped segment.
副線圈120的第五部份路徑931包括第一導線段931_1,而副線圈120的第六部份路徑932包括第二導線段932_1。第一導線段931_1的第一端作為副線圈120的第一端Port3。第一導線段931_1的第二端經由第一矽穿孔903連接至第二導線段932_1的第一端。副線圈120的第七部份路徑941包括第三導線段941_1,而副線圈120的第八部份路徑942包括第四導線段942_1。第三導線段941_1的第一端作為副線圈120的第二端Port4。第三導線段941_1的第二端經由第二矽穿孔904連接至第四導線段942_1的第一端。第四導線段942_1的第二端連接第二導線段932_1的第二端。在一實施例中,第一導線段931_1與第三導線段941_1可為彎曲線段,而第二導線段932_1與第四導線段942_1可為O型線段之一半呈U線段。在一實施例中,第二導線段932_1與第四導 線段942_1連接呈O型線段,且此O型線段設置於第一導線段912_1與第三導線段922_1間。在一實施例中,第二導線段911_1連接第四導線段921_1形成O型線段設置於第一導線段931_1與第三導線段941_1間。 The fifth partial path 931 of the secondary coil 120 includes a first wire segment 931_1, and the sixth partial path 932 of the secondary coil 120 includes a second wire segment 932_1. The first end of the first wire segment 931_1 serves as the first end Port3 of the secondary coil 120. The second end of the first wire segment 931_1 is connected to the first end of the second wire segment 932_1 via the first turn-by-hole 903. The seventh partial path 941 of the secondary coil 120 includes a third wire segment 941_1, and the eighth partial path 942 of the secondary coil 120 includes a fourth wire segment 942_1. The first end of the third wire segment 941_1 serves as the second end Port4 of the secondary coil 120. The second end of the third wire segment 941_1 is connected to the first end of the fourth wire segment 942_1 via the second turn-by-hole 904. The second end of the fourth wire segment 942_1 is connected to the second end of the second wire segment 932_1. In an embodiment, the first wire segment 931_1 and the third wire segment 941_1 may be curved line segments, and the second wire segment 932_1 and the fourth wire segment 942_1 may be U-shaped segments of one of the O-shaped segments. In an embodiment, the second wire segment 932_1 and the fourth guide The line segment 942_1 is connected as an O-shaped line segment, and the O-shaped line segment is disposed between the first wire segment 912_1 and the third wire segment 922_1. In an embodiment, the second wire segment 911_1 is connected to the fourth wire segment 921_1 to form an O-shaped segment disposed between the first wire segment 931_1 and the third wire segment 941_1.
在一實施例中,主線圈110與副線圈120部分地電性路徑等等可分別位於不同投影位置。 In an embodiment, the main coil 110 and the secondary coil 120 may be partially electrically routed or the like at different projection positions.
綜上所述,若以對稱線950為其變壓器中心線,則對稱線950的左右為鏡像對稱之佈局,可以得知圖9至圖10所示三維積體電路(3DIC)之三維對稱型垂直變壓器100具有良好的對稱性結構。因此,圖9至圖10所示變壓器100適合應用於差動架構的電路設計之中。由圖9至圖10所示實施例觀之,其主線圈110及副線圈120的圈數比例為1:1,因此圖9至圖10所示變壓器100為圈數比1:1之變壓器。本實施例利用3DIC製程中的矽穿孔(TSV)之垂直路徑以及不同基底(晶片)的平面路徑來實現對稱型的變壓器100。因此,變壓器100可以節省晶片面積。再者,所述變壓器100可應用於不同晶片之間的垂直信號耦合傳輸。 In summary, if the symmetry line 950 is the center line of the transformer, the left and right sides of the symmetry line 950 are mirror symmetrical layouts, and the three-dimensional symmetrical vertical form of the three-dimensional integrated circuit (3DIC) shown in FIG. 9 to FIG. 10 can be known. The transformer 100 has a good symmetrical structure. Therefore, the transformer 100 shown in FIGS. 9 to 10 is suitable for use in the circuit design of the differential architecture. As seen from the embodiment shown in Figs. 9 to 10, the ratio of the number of turns of the primary coil 110 and the secondary coil 120 is 1:1, so that the transformer 100 shown in Figs. 9 to 10 is a transformer having a turns ratio of 1:1. This embodiment implements a symmetrical transformer 100 by utilizing the vertical path of the turns of the turns (TSV) in the 3DIC process and the planar path of the different substrates (wafers). Therefore, the transformer 100 can save wafer area. Furthermore, the transformer 100 can be applied to vertical signal coupling transmissions between different wafers.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧變壓器 100‧‧‧Transformer
110‧‧‧主線圈 110‧‧‧main coil
120‧‧‧副線圈 120‧‧‧second coil
210‧‧‧第一電性路徑 210‧‧‧First electrical path
211‧‧‧第一部份路徑 211‧‧‧ first part of the path
211_1‧‧‧第一導線段 211_1‧‧‧First wire segment
211_2‧‧‧第二導線段 211_2‧‧‧second wire segment
212‧‧‧第二部份路徑 212‧‧‧Second part of the path
212_1‧‧‧第三導線段 212_1‧‧‧third wire segment
220‧‧‧第二電性路徑 220‧‧‧Second electrical path
221‧‧‧第三部份路徑 221‧‧‧ third part of the path
221_1‧‧‧第四導線段 221_1‧‧‧fourth wire segment
221_2‧‧‧第五導線段 221_2‧‧‧ fifth wire segment
222‧‧‧第四部份路徑 222‧‧‧ fourth part of the path
222_1‧‧‧第六導線段 222_1‧‧‧6th wire segment
230‧‧‧第三電性路徑 230‧‧‧ Third electrical path
231‧‧‧第五部份路徑 231‧‧‧The fifth part of the path
231_1‧‧‧第一導線段 231_1‧‧‧First wire segment
232‧‧‧第六部份路徑 232‧‧‧Sixth part of the path
232_1‧‧‧第二導線段 232_1‧‧‧second wire segment
240‧‧‧第四電性路徑 240‧‧‧fourth electrical path
241‧‧‧第七部份路徑 241‧‧‧The seventh part of the path
241_1‧‧‧第三導線段 241_1‧‧‧third wire segment
242‧‧‧第八部份路徑 242‧‧‧The eighth part of the path
242_1‧‧‧第四導線段 242_1‧‧‧fourth wire segment
250‧‧‧對稱線 250‧‧ symmetry line
260‧‧‧第一基底 260‧‧‧First base
270‧‧‧第二基底 270‧‧‧second base
Port1‧‧‧主線圈的第一端 Port1‧‧‧ first end of the main coil
Port2‧‧‧主線圈的第二端 Port 2‧‧‧ second end of the main coil
Port3‧‧‧副線圈的第一端 The first end of the port 3‧‧‧ secondary coil
Port4‧‧‧副線圈的第二端 The second end of the port 4‧‧‧ secondary coil
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JP2009503909A (en) * | 2005-08-04 | 2009-01-29 | ザ リージェンツ オブ ザ ユニヴァーシティ オブ カリフォルニア | Interleaved three-dimensional on-chip differential inductor and transformer |
KR101444708B1 (en) * | 2009-12-15 | 2014-09-26 | 한국전자통신연구원 | Inductor |
US9406738B2 (en) * | 2011-07-20 | 2016-08-02 | Xilinx, Inc. | Inductive structure formed using through silicon vias |
US9111933B2 (en) * | 2012-05-17 | 2015-08-18 | International Business Machines Corporation | Stacked through-silicon via (TSV) transformer structure |
-
2014
- 2014-09-09 TW TW103130990A patent/TWI590269B/en active
- 2014-10-10 CN CN201410530860.6A patent/CN105304607B/en active Active
- 2014-12-05 EP EP14196615.0A patent/EP2966661A3/en not_active Withdrawn
Also Published As
Publication number | Publication date |
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CN105304607B (en) | 2018-11-23 |
EP2966661A3 (en) | 2016-01-20 |
EP2966661A2 (en) | 2016-01-13 |
TWI590269B (en) | 2017-07-01 |
CN105304607A (en) | 2016-02-03 |
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