TW201602805A - Server and device for analyzing a signal thereof - Google Patents

Abstract

A server includes a hard disk drive, a plurality of indicator, at least a jumper, and a logic array. The logic array is coupled to the jumper and includes a plurality of analyzing modules. The logic array selects one of the analyzing modules in accordance with the configuration of the jumper. The selected analyzing module analyzes an input signal and outputs a decoded signal. The indicator is operated in responsive to the decoded signal to represent the status of the hard disk drive.

Description

Server and its signal analysis device

The present invention relates to a server and a signal analyzing device thereof, and more particularly to a server having a signal analyzing device capable of analyzing a plurality of group input signals.

As technology advances, hardware technology is becoming more mature. Many hardware devices are not limited to accessing data, but can perform many different functions. However, if the user wants to know from the outside the function or working state of the current hardware device, it is necessary to obtain the relevant information of the hardware through the display signal on the back panel.

However, the signal parsing chip on the conventional backplane can only parse one group of input signals. If the user needs to use other groups of input signals, the signal parsing chip must be replaced to parse the input signals of other groups. However, the signal analysis chip is often bonded to the backplane. If the signal analysis chip is replaced, the backplane must be replaced together, and the cost is a heavy burden for the user. In more detail, the hard disk backplane parses the state of the hard disk connected thereto by a serial general purpose input input (SGPIO). Since the conventional signal analysis chip can only parse a set of SGPIO signals, Reduces versatility and causes inconvenience.

In view of the above problems, the present invention provides a server and a signal analysis device thereof, which can analyze various input signals of a plurality of groups by an external setting mechanism, so as to help the user not have to lose The group of incoming signals is different, that is, the signal analysis device in the server is replaced.

According to an embodiment, the server includes a plurality of hard disks, a plurality of indicator elements, at least one jumper, and a logic array, the logic array is coupled to the at least one jumper and includes a plurality of analysis modules, the logic array Selecting, according to the at least one jumper, one of the corresponding parsing modules, and the corresponding parsing module parses an input signal as a decoded signal, and the indicating components display the hard disc according to the decoded signal. Working status.

According to an embodiment, the server further includes a storage controller (Storage Controller), the storage controller is coupled to the hard disks, and the storage controller sends the input signal to the logic array.

According to an embodiment, the server further includes a hard disk backplane, the hard disk backplane is coupled to the hard disks, and the at least one jumper, the logic array and the indicating components are disposed on the hard disk backplane.

According to an embodiment, the server further includes a mother board, a central processing unit, and an interposer board. The central processor is disposed on the motherboard, and the storage control is performed. The memory board is disposed between the motherboard and the hard disk backplane, and the memory controller is coupled between the central processing unit and the hard disk.

According to an embodiment, the number of the jumpers is n, and the jumpers can form different jumper signals of less than or equal to 2 ⁿ groups, and the number of the parsing modules is less than or equal to 2 ⁿ .

According to an embodiment, the signal analysis device includes at least one jumper and a logic array, the logic array includes a plurality of analysis modules, and the logic array selects one of the corresponding analysis modules based on the at least one jumper. The input signal is parsed by the corresponding parsing module as the decoded signal.

In summary, the present invention can analyze the received input signals of a plurality of different groups through the signal analysis device, and display the status according to the decoded decoded signals, so that the user does not need to have different groups of input signals, that is, Replace the signal analyzer or backplane; for servers with different configurations, The input signals are often different, but the application of the present invention, based on the jumper selection corresponding parsing module, the signal parsing device of the present invention is highly versatile for servers of different configurations.

The description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

10a, 10b‧‧‧ hard disk

20‧‧‧hard disk backplane

22‧‧‧Signal analysis device

24a, 24b‧‧‧ indicating components

26‧‧‧Logic Array

26a, 26b‧‧‧ stitches

27a, 27b‧‧‧ Analytical Module

28a, 28b‧‧‧ Jumper

29a, 29b‧‧‧Resistors

30‧‧‧Adapter plate

32‧‧‧Storage Controller

40‧‧‧ motherboard

42‧‧‧Central processor

90‧‧‧Input signal

92‧‧‧Decoding signal

1 is a functional block diagram of a server in accordance with an embodiment of the present invention.

2 is a flow chart of a signal parsing method according to an embodiment of the present invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to [FIG. 1], and [FIG. 1] is a functional block diagram of a server according to an embodiment of the present invention. The server includes a plurality of hard disk drives (HDD) 10a, 10b, a hard disk backplane (HDD Backboard) 20, an interposer board 30, and a mother board 40.

The hard disk 10a, 10b may be, but is not limited to, any storage device, such as any computer storable medium.

The hard disk backplane 20 includes signal analysis means 22 and indicator elements 24a, 24b. The signal parsing device 22 includes a logic array 26, and at least one jumper 28a, 28b, a logic array The at least one jumper 28a, 28b is coupled to the at least one jumper 28a, 28b to parse one of the received input signals 90 to generate a decoded signal 92.

The aforementioned logic array 26 can be, but is not limited to, a complex programmable logic device (CPLD), or any other device that can resolve signals.

The logic array 26 can include a plurality of analysis modules 27a, 27b. The logic array 26 selects one of the corresponding analysis modules 27a, 27b based on the at least one jumper 28a, 28b, and the corresponding analysis module 27a, 27b analyzes the input signal 90 to become the decoded signal 92, and the indicating elements 24a, 24b display the working states of the hard disks 10a, 10b according to the decoded signal 92.

The input signal 90 may be from the hard disk 10a, 10b. The input signal 90 may be, but not limited to, a serial general purpose input input (SGPIO) or a general purpose output input signal (GPIO), and the input signal 90 may have information indicating the state of the hard disk. The parsing modules 27a, 27b parse the hard disk status information in the input signal 90 and output the decoded signal 92.

The jumpers 28a, 28b can be used with other electronic components as input signals to the logic array 26, which can be, but are not limited to, resistors 29a, 29b. As shown, the jumpers 28a, 28b will default (normal) In the off state, when the jumper (cover) of the jumpers 28a, 28b is placed on the jumpers 28a, 28b, the jumpers 28a, 28b are turned on. The logic array 26 selects one of the corresponding parsing modules 27a, 27b according to the configuration of the jumpers 28a, 28b or the jumper signal, and parses the input signal 90 for the decoding by the corresponding parsing modules 27a, 27b. Signal 92. One of the configurations corresponds to a jumper signal.

The logic array 26 includes at least one pin 26a, 26b. Each of the jumpers 28a, 28b is connected to a pin 26a, 26b. The on/off state of each of the jumpers 26a, 26b is used to control the corresponding connection. The pins 28a, 28b are at a logic high or logic low so that the logic array 26 selects one of the analysis modules 27a, 27b to resolve the input signal according to the potential of the at least one of the pins 26a, 26b. The number 90 is the decoded signal 92.

Furthermore, if two jumpers 28a, 28b are taken as an example, each of the jumpers 28a, 28b has two states (also called an on-off state): a conduction state or an off state, when the jumper When the 28a, 28b are in the on state, the pins 26a, 26b are at a logic low level, and when the jumpers 28a, 28b are in the off state, the pins 26a, 26b are at a logic high level. Since each of the jumpers 28a, 28b has two states, the two jumpers 28a, 28b can form a total of four configurations or four types of jumper signals, which are logically represented as 00, 01, respectively. 10, 11, these four configurations correspond to one parsing module 27a, 27b, that is, two jumpers 28a, 28b, at most four parsing modules 27a, 27b, the same, three The jumpers 28a, 28b can be matched with at most 8 parsing modules 27a, 27b (i.e., ²³ ). More precisely, when the number of jumpers 28a, 28b is n, the jumpers 28a, 28b has a configuration (or jumper signal) that is less than or equal to 2 ⁿ groups, and the number of the analysis modules 27a, 27b is less than or equal to 2 ⁿ .

Then, the logic array 26 selects one of the corresponding parsing modules 27a, 27b according to the configuration of the jumpers 28a, 28b or the jumper signal, and parses the input signal 90 by the corresponding parsing modules 27a, 27b. Become the decoded signal 92.

The decoding signal 92 is coupled to the indicating elements 24a, 24b. The decoding signal 92 can be outputted by a plurality of output pins, each of which is coupled to an indicating element 24a, 24b. Each of the indicating elements 24a, 24b can represent a hard The status of the disc, such as but not limited to whether there is power (ON or OFF), reading, and writing.

In addition, the decoded signal 92 can also be another serial signal, such as but not limited to RS232 (Interface Standard for Serial Data Communication), and the indicator elements 24a, 24b further include a control element to convert the decoded signal 92 into The signals of the indicating elements 24a, 24b are driven.

Furthermore, the indicator component can also be, but not limited to, a seven segment display, Light emitting diode (LED), liquid crystal display, and the like.

The foregoing server may include a storage controller (32), the storage controller 32 is coupled to the hard disks 10a, 10b, and the storage controller 32 sends the input signal 90 to the signal analyzing device 22 (logical array 26). . The storage controller may be, but not limited to, a small attached computer system interface (SAS expander, Serial attached SCSI (small computer system interface)), a south bridge chip, or a serial advanced technology attachment (SATA) expander.

The hard disk backplane 20 is coupled to the hard disks 10a, 10b. The at least one jumper 28a, 28b, the logic array and the indicating components 24a, 24b are disposed on the hard disk backplane 20.

The central processing unit 42 is disposed on the motherboard 40. The storage controller 32 is disposed on the adapter board 30. The adapter board 30 is coupled between the motherboard 40 and the hard disk backplane 20, and the storage is The controller 32 is coupled between the central processing unit 42 and the hard disks 10a, 10b.

In order to make the signal analysis device 22 of the present invention more familiar to those skilled in the art, the following is a further description of the signal analysis method of the present invention. Please refer to [FIG. 1] and [FIG. 2] together, and [FIG. 2] is a flowchart of a signal parsing method according to an embodiment of the present invention. As shown in FIG. 2, in step S600, the memory controller 32 transmits an input signal 90 to the logic array 26 of the parsing device 22. In step S602, the logic array 26 detects the configuration of the jumpers 28a, 28b. In step S604, the logic array 26 selects a corresponding analysis module (for example, the analysis module 27a) from the analysis modules 27a, 27b according to the configuration of the jumpers 28a, 28b. In step S606, the analysis module 27a parses the input signal 90 to generate a decoded signal 92 to the indicator elements 24a, 24b. In step S608, the indication elements 24a, 24b provide a status indication in accordance with the decoded signal 92, which may be the aforementioned hard disk status.

In summary, the present invention can receive input signals, and the logic array 26 selects the corresponding analysis modules 27a, 27b according to the configuration of the set jumpers 28a, 28b to parse the decoded signal 92, so that the user does not need to The signal analyzing device 22 is replaced because the input signal group or the server hardware configuration is different.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10a, 10b‧‧‧ hard disk

20‧‧‧hard disk backplane

22‧‧‧Signal analysis device

24a, 24b‧‧‧ indicating components

26‧‧‧Logic Array

26a, 26b‧‧‧ stitches

27a, 27b‧‧‧ Analytical Module

28a, 28b‧‧‧ Jumper

29a, 29b‧‧‧Resistors

30‧‧‧Adapter plate

32‧‧‧Storage Controller

40‧‧‧ motherboard

42‧‧‧Central processor

90‧‧‧Input signal

92‧‧‧Decoding signal

Claims (20)

A server includes: at least one jumper; and a logic array coupled to the at least one jumper, the logic array parses one of the received input signals to generate a decoded signal. The server of claim 1, wherein the server further comprises a plurality of hard disks and a plurality of indicating elements, the logic array comprising a plurality of analyzing modules, wherein the logic array selects corresponding ones based on the at least one jumper In the analysis module, the input signal is parsed by the corresponding parsing module, and the indicating components display the working states of the hard disks according to the decoded signals. The server of claim 1, wherein the server further comprises a plurality of hard disks and a plurality of indicator elements, the logic array comprising a plurality of analysis modules, the logic array being according to a group of the at least one jumper And the corresponding parsing module is configured to parse the input signal into the decoded signal, and the indicating components display the working states of the hard disks according to the decoded signal. The server of claim 2 or 3, wherein the server further includes a storage controller (Storage Controller), the storage controller is coupled to the hard disks, and the storage controller sends the input signal to the logic array . The server of claim 4, wherein the storage controller is a small computer system interface expander, a south bridge chip, or a serial advanced technology accessory expander. The server of claim 2 or 3, further comprising a hard disk backplane, the hard disk backplane coupled to the hard disks, the at least one jumper, the logic array and the indicating components are disposed on the hard disk Hard disk backplane. The server of claim 6, further comprising a mother board, a central processing unit, and an interposer board, wherein the central processor is disposed at the server a memory board is disposed between the motherboard and the hard disk backplane, the memory controller is coupled to the central processing unit and the hard disk between. The server of claim 2, wherein the number of the jumpers is n, the jumpers can form different jumper signals of less than or equal to 2 ⁿ groups, and the number of the parsing modules is less than or equal to 2 ⁿ . The server of claim 3, wherein the number of the jumpers is n, the jumpers have a configuration different from or equal to 2 ⁿ groups, and the number of the parsing modules is less than or equal to 2 ⁿ . The server of claim 2 or 3, wherein the number of the jumpers is n, and the number of the parsing modules is no more than 2 ⁿ . The server of claim 1, 2 or 3, wherein the logic array is a complex programmable logic device (CPLD). The server of claim 1, 2 or 3, wherein the input signal is a serial general purpose input input (SGPIO). The server of claim 2, wherein the logic array comprises at least one pin, each of the jumpers is connected to the pin, and the on/off state of each of the jumpers is used to control the pin of the corresponding connection. The logic array is at a logic high level or a logic low level, so that the logic array selects one of the analysis modules to parse the input signal as the decoded signal according to the potential of the at least one pin. A signal analysis device includes: at least one jumper; and a logic array coupled to the at least one jumper, the logic array parses one of the received input signals to generate a decoded signal. The signal analysis device of claim 14, wherein the logic array comprises a plurality of parsing modules, and the logic array selects one of the corresponding parsing modules based on the at least one jumper, corresponding to the solution The module analyzes the input signal as the decoded signal. The signal analysis device of claim 15, wherein the number of the jumpers is n, and the jumpers can form different jumper signals of less than or equal to 2 ⁿ groups, and the number of the parsing modules is less than or Equal to 2 ⁿ . The signal analysis device of claim 15, wherein the number of the jumpers is n, and the jumpers have different configurations of less than or equal to 2 ⁿ groups, and the number of the parsing modules is less than or equal to 2 ⁿ . The method of claim 15, 16, or 17, wherein the logic array is a complex programmable logic device (CPLD). The signal analysis device of claim 15, wherein the input signal is a serial general purpose input input (SGPIO). The signal analysis device of claim 15, wherein the logic array comprises at least one pin, each of the jumpers is connected to the pin, and the on/off state of each of the jumpers is used to control the corresponding connection. The pin is at a logic high level or a logic low level, so that the logic array selects one of the parsing modules to parse the input signal as the decoded signal according to the potential of the at least one pin.