TW201546809A - The method of prevent write time degradation for non-volatile bits long-term cycling - Google Patents

Abstract

The present disclosure provides a method of prevent write time degradation for non-volatile bits long-term cycling. The method comprises setting a first non-volatile status register and at least a corresponding second non-volatile status register; determining whether the erase time of the first non-volatile status register exceeds a upper limit time in the erase phase of the write/erase cycle; replacing the first non-volatile status register by the second non-volatile status register to be accessed in the next write/erase cycle; wherein the first non-volatile status register and the second non-volatile status register are the flash cells. Accordingly, the life time of the non-volatile cells in array could be extended.

Description

Method for preventing write time degradation of long-term non-volatile cells

The present invention relates to a state register, and more particularly to a method for preventing write time degradation of non-volatile bits of a long-term cycle applied to a state register.

Non-volatile memory such as flash memory is often used in memory elements of electronic devices for storing firmware or data. In general, access to non-volatile memory is customized with associated instruction and instruction formats. Depending on the model of the non-volatile memory, the command format may be different, and the read time, write time, read voltage, write voltage, etc. of the non-volatile memory are specified.

However, in non-volatile memory such as flash memory, each memory cell may undergo degradation after long-term recycling, and the time for writing (or erasing) is increased. When the writing (or erasing) time increases beyond the specification, the memory cells used may not be normally written (or erased), and the access to the memory cells is disabled, and the memory cells are rendered unfunctioning.

Traditionally, in order to solve the problem of memory cell degradation in flash memory, a channel length or a programming voltage of a bit line can be used for each memory cell. Alternatively, to compensate for the degradation caused by long-term cycling, a higher erase voltage, a stronger erase field, more erase steps, or a state register with a lower threshold voltage (Vt) can be used. . However, the setting of the erase voltage is limited by the voltage limit of the bit state "1", the magnitude of the erase electric field and the number of erase steps Limited by the device's own breakdown constraint, and the threshold voltage of the state register affects the ability to remember data. Therefore, how to prevent the degradation caused by long-term recycling of non-volatile memory and prolong the service life of non-volatile memory are the research directions of those skilled in the art.

Embodiments of the present invention provide a method for preventing write time degradation of long-term circulating non-volatile cells, applied to a non-volatile cell array having a mini array to extend the lifetime of a non-volatile cell array.

Embodiments of the present invention provide a method for preventing write time degradation of a non-volatile bit of a long-term cycle, the method comprising the following steps. First, a first non-volatile state register and a corresponding at least one second non-volatile state register are provided. Then, it is determined whether the erasing time of the first non-volatile state register exceeds the upper limit time during the erasing phase of the erasing cycle. When the erasing time of the first non-volatile state register exceeds the upper limit time, the second non-volatile state register is accessed in place of the first non-volatile state register at the next strobe cycle. The first non-volatile state register and the second non-volatile state register are flash cells.

In summary, the embodiments of the present invention provide a method for preventing write time degradation of a non-volatile bit in a long-term cycle. When the erasing time of the non-volatile state register used exceeds the upper limit time, Use an alternative non-volatile state register to extend the life of the non-volatile cell array.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

S100, S110, S120, S130, S200, S210, S220, S101, S111, S112, S113, S114, S115, S116, S120a, S120b, S131, S132, S133, S134, S140, S310, S320, S330, S340, S350, S360‧‧‧ step process

NVBSEL1‧‧‧ first non-volatile flag

NVBSEL2‧‧‧ second non-volatile flag

FIG. 1 is a flowchart of a write command to a state register according to an embodiment of the present invention.

2 is a representation of each element of a write state register provided by an embodiment of the present invention; Schematic diagram of the state.

FIG. 3 is a flowchart of a method for preventing write time degradation of a non-volatile bit of a long-term cycle according to an embodiment of the present invention.

4 is a flow diagram of the method of FIG. 3 applied to a write status register.

FIG. 5 is a flowchart of reading a state register according to an embodiment of the present invention.

[Embodiment of Method for Preventing Degradation of Write Time for Non-Volatile Bits of Long-Term Circulation]

The method for preventing write time degradation of long-term circulating non-volatile cells provided by this embodiment can extend the service life of the non-volatile memory device for frequent reading of non-volatile memory. For example, when designing the write (or erase) time of each memory cell from the beginning to less than the specification of 40 milliseconds, so that the memory cell can be accessed three times every ten seconds. Ensure that the write (or erase) time for operations within ten years is less than 70 milliseconds.

The method of this embodiment is applied to the memory cells of the state register. Before the method of the embodiment is described, the manner of writing the state register will be described. The status register may have a plurality of bits, each bit connected to a bit line, and all bits are connected to form a word line. Please refer to FIG. 1. FIG. 1 is a flowchart of a write command to a state register according to an embodiment of the present invention. In general, a write cycle includes a pre-program phase, an erase phase, a program phase, and a reset phase when a write command is issued to the state register. First in step S100, a pre-programming phase is performed. Next, in step S110, an erasing phase is performed. Then, in step S120, a programming phase is performed. Finally, in step S130, a reset phase is performed.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the state of each element of the write state register provided by the embodiment of the present invention. The first non-volatile state register and the second non-volatile state register respectively have a plurality of non-volatile bits, and the non-volatile bits Less than or equal to ten bits to form a mini-array.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the state of each element of the write state register provided by the embodiment of the present invention. The state of each element of the write state register described in this embodiment is for illustrative purposes only and is not intended to limit the present invention. It is common knowledge in the art to modify the bit or the representative state of the state register in accordance with the specification of the memory and related prior art techniques. According to FIG. 2, the first non-volatile state register and the second non-volatile state register of the embodiment may have, for example, six non-volatile bits and two volatile bits. The six non-volatile bits are a seventh bit (bit 7, represented by SWRD), a sixth bit (bit 6 , represented by QE), a fifth bit (bit 5, represented by BP3), and a fourth bit. The element (bit4, represented by BP2), the third bit (bit3, represented by BP1), and the second bit (bit2, represented by BP0). The seventh bit represents the state of the Status Register Write Protect (SWRD). The sixth bit represents the state in which a plurality of pins (e.g., four pins) are allowed to be input. The fifth bit (BP3), the fourth bit (BP2), the third bit (BP1), and the second bit (PB0), for example, are used to define a memory when there is no hardware write prevention. The protected area corresponds to Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) instruction. The two volatile bits include the first bit represented by WEL and the zeroth bit represented by WIP. The first bit is the Write Enable Latch (WEL) bit to indicate whether the non-volatile memory cell can allow programming/erase/write status register instructions. The feature bit is a Write in Progess (WIP) bit that represents the program of the program/erase/write state register instruction that the volatile memory cell is processing.

The method of this embodiment mainly sets a corresponding flag for the non-volatile state register to be used, according to the setting of the flag in the erasing phase, the programming phase or the reset phase of an erasing cycle. Wipe the corresponding non-volatile state register. Please refer to FIG. 3. FIG. 3 is a flowchart of a method for preventing write time degradation of a non-volatile bit of a long-term cycle according to an embodiment of the present invention. First, at the step S200. Set a first non-volatile state register and a corresponding at least one second non-volatile state register. Then, in step S210, it is determined whether the erasing time of the first non-volatile state register exceeds the upper limit time in the erasing phase of the erasing cycle. The upper limit time is, for example, 70 milliseconds, but the present invention is not limited thereto. Those skilled in the art can set the upper limit time as needed. When the erasing time of the first non-volatile state register exceeds the upper limit time, the first non-volatile state register is degraded and used at this time, and then step S220 is performed, and the next step is performed. The second non-volatile state register is accessed by the second non-volatile state register instead of the first non-volatile state register. The first non-volatile state register and the second non-volatile state register are flash cells. When the erasing time of the first non-volatile state register does not exceed the upper limit time, step S210 is performed again in the next cycle.

In other words, the first non-volatile state register is the register used when the non-volatile memory is initially used, and the second non-volatile state register is the first non-volatile state register. The status register of the substitute when degraded. A memory device can have a plurality of first non-volatile state registers and a plurality of second non-volatile state registers. Each of the first non-volatile state registers may correspond to at least one second non-volatile state register for use as a substitute. At the same time, the flag setting can be used to dictate the undegraded state register according to the flag.

For details of the operation of writing a command to the status register, refer to the flowchart of FIG. Referring to FIG. 1 and FIG. 4 simultaneously, step S101 corresponds to the pre-programming phase of FIG. 1, and steps S111, S112, S113, S114, S115, and S116 correspond to the erasing phase of FIG. Steps S120a and S120b correspond to the programming phase of FIG. Steps S131, S132, S133, and S134 correspond to the reset phase of FIG.

First, pre-programming is performed in step S101. Then, in step S111, it is determined whether the first non-volatile flag and the second non-volatile flag are the second state ("1"), wherein the first state is "0". For example: setting corresponds to the first non-volatile state The first non-volatile flag NVBSEL1 of the register and the second non-volatile flag NVBSEL2 corresponding to the second non-volatile state register are in a first state ("0"). When the erasing time of the first non-volatile state register does not exceed the upper limit time, the first non-volatile flag NVBSEL1 is set to the second state ("1"). On the other hand, when the erasing time of the first non-volatile state register exceeds the upper limit time, the second non-volatile flag NVBSEL2 is set to the second state ("1"). That is, as shown in FIG. 4, when the first non-volatile flag is in the second state (NVBSEL1 = "1"), step S112 is performed. When the second non-volatile flag is in the second state (NVBSEL2 = "1"), step S116 is performed. In step S116, the word line of the second non-volatile state register is erased.

In step S112, the word line of the first non-volatile state register is erased. In this embodiment, the first non-volatile state register can be erased by a plurality of erase pulses during the erase phase. For example, each erase pulse width may be 4 milliseconds, but the invention is not limited thereto. Next, in step S113, it is determined whether the number of erasures for erasing the first non-volatile state register by the erase pulse is greater than or equal to a predetermined number of times (for example, 15 times). The erase pulse width multiplied by the erase count is equal to the erase time, for example, the punch width is 40 milliseconds multiplied by the erase count 15 times equal to 60 milliseconds. Assuming that the erasing time exceeds 60 milliseconds, the state register is degraded, and the predetermined number of times is set to 15 times. If the number of erasing times is less than 15 times, step S114 is performed to set the temporary storage parameter TO70MS=0. It can still be used to represent the first non-volatile state register. If the number of erasures reaches 15 times (or exceeds 15 times), then step S115 is performed to set the temporary storage parameter TO70MS=1, so as to replace the first non-volatile state register with the second non-volatile state register. Save. In other words, when the number of erasures is greater than or equal to the predetermined number of times, the temporary storage parameter TO70MS is set such that the temporary storage parameter corresponds to the first non-volatile state register, so that the first non-volatile state is in the programming phase. The scratchpad is programmed. When the erasing frequency is small for a predetermined number of times, the temporary storage parameter TO70MS is set such that the temporary storage parameter corresponds to the second non-volatile state register, so that the second non-volatile state register is programmed during the programming phase. .

Next, in the programming phase, after step S114 is performed, step S120a is performed. In step S120a, the word line of the first non-volatile state register is programmed with the first non-volatile flag NVBSEL1. After step S115 is performed, step S120b is performed. In step S120b, the word line of the second non-volatile state register and the second non-volatile flag NVBSEL2 are programmed.

After the end of step S120a or step S120b, step S131 is then performed in the high voltage reset phase to read the non-volatile flag (NVBSEL1 or NVBSEL2). Then, in step S132, it is determined whether the first non-volatile flag and the second non-volatile flag are in the second state ("1"), and the step S132 is the same as the step S111, and is used to select the state register to be heavy. Set the object. When the first non-volatile flag NVBSEL1 = "1", step S133 is performed. When the second non-volatile flag NVBSEL1 = "1", step S134 is performed. In step S133, the word line of the first non-volatile state register is read. In step S134, the word line of the second non-volatile state register is read. Finally, step S140 is performed to reset the temporary storage parameter TO70MS. In other words, it is judged whether or not the first non-volatile flag NVBSEL1 and the second non-volatile flag NVBSEL2 are in the second state in the reset phase (step S132). When the first non-volatile flag NVBSEL1 is in the second state, the first non-volatile state register is reset. When the second non-volatile flag NVBSEL2 is in the second state, the second non-volatile state register is reset.

The non-volatile flag (NVBSEL1 or NVBSEL2) of Figure 4 is represented by a single bit, however in other embodiments, the non-volatile flag may also be represented by a plurality of bit codes. For example, in an embodiment, when the four second non-volatile registers correspond to a first non-volatile register, the non-volatile flag NVBSEL is set to a first state (0000) of four-bit encoding, The first state (0000) corresponds to a first non-volatile state register. When the erasing time of the first non-volatile state register exceeds the upper limit time, the non-volatile flag NVBSEL is set to the second state (0001, 0010, 0100 or 1000), and the second state (0001, 0010, 0100 or 1000) corresponds to (one of the second non-volatile registers). When the erasing time of the first non-volatile state register does not exceed the upper limit time, the non-volatile flag NVBSEL is maintained in the first state (0000). However, the present invention does not limit the encoding and the number of bits of the non-volatile flag. According to the corresponding number of the first non-volatile register and the second non-volatile register, the encoding and the bit of the non-volatile flag The number may not be the same. It should be noted that, in the case of this embodiment, step S111 of FIG. 4 may be replaced by determining that the non-volatile flag NVBSEL is in the first state or the second state, and the first state corresponds to the first non-volatile state. The register, the second state corresponds to the second non-volatile state register. When the non-volatile flag NVBSEL is in the first state, a step of determining whether the erasing time of the first non-volatile state register exceeds the upper limit time is performed (step S113, and corresponding steps S112, S114, S115). When the non-volatile flag NVBSEL is in the second state, the second non-volatile state register is erased (step S116). In addition, in the reset phase, step S132 is replaced with determining that the non-volatile flag NVBSEL is the first state or the second state. When the non-volatile flag NVBSEL is in the first state, the first non-volatile state register is reset (corresponding to step S133 of the reset phase). When the non-volatile flag NVBSEL is in the second state, the second non-volatile state register is reset (corresponding to step S134 of the reset phase).

Then, when the state register is read, the embodiment of the present invention provides the flowchart of FIG. 5 to correspond to the writing process of FIG. 4. In FIG. 5, step S310 is first performed to supply power. Next, in step S320, the non-volatile flag (NVBSEL or NVBSEL1 and NVBSEL2) is read (power supply read phase one). Next, in step S330, it is determined whether the first non-volatile flag and the second non-volatile flag are in the second state ("1"). The step S330 is the same as steps S111 and S132 of FIG. 4 for determining the status register to be read. For example, in the case of setting the first non-volatile flag NVBSEL1 corresponding to the first non-volatile state register and the second non-volatile flag NVBSEL2 corresponding to the second non-volatile state register, and when When the first non-volatile flag NVBSEL1 = "1", step S340 is performed. When the second non-volatile flag NVBSEL2 = "1", step S350 is performed. In step S340, (power supply read phase two) reads the word line of the first non-volatile state register. In step S350, (the power supply reading phase 2) reads the word line of the second non-volatile state register. Finally, read The standby command of step S260 is completed.

[Possible effects of the examples]

In summary, the method for preventing the write time degradation of the non-volatile bit of the long-term cycle provided by the embodiment of the present invention, when the erasing time of the non-volatile state register used exceeds the upper limit time, Switch to an alternative non-volatile state register to extend the life of non-volatile cell arrays. Embodiments of the present invention may utilize non-volatile flags to conveniently determine whether the non-volatile state register used has degraded and thereby select an alternate non-volatile state register.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

S101, S111, S112, S113, S114, S115, S116, S120a, S120b, S131, S132, S133, S134, S140‧‧

NVBSEL1‧‧‧ first non-volatile flag

NVBSEL2‧‧‧ second non-volatile flag

Claims (13)

A method for preventing write time degradation of a non-volatile bit of a long-term cycle, the method comprising: setting a first non-volatile state register and a corresponding at least one second non-volatile state register; Determining whether the erasing time of the first non-volatile state register exceeds an upper limit time in one erasing phase of a write cycle; and when the erasing time of the first non-volatile state register exceeds the upper limit time The second non-volatile state register is accessed in place of the first non-volatile state register in the next strobe cycle; wherein the first non-volatile state register and the second The non-volatile state register is a flash cell. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 1 of the claim, wherein before the step of determining whether the erasing time of the first non-volatile state register exceeds the upper limit time Setting a first non-volatile flag corresponding to the first non-volatile state register and a second non-volatile flag corresponding to the second non-volatile state register to a first state, And when the erasing time of the first non-volatile state register does not exceed the upper limit time, setting the first non-volatile flag to a second state, when the first non-volatile state register is When the erasing time exceeds the upper limit time, the second non-volatile flag is set to the second state. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 1 of the claim, wherein before the step of determining whether the erasing time of the first non-volatile state register exceeds the upper limit time Setting a non-volatile flag to a first state, the first state corresponding to the first non-volatile state register, and when the erasing time of the first non-volatile state register exceeds the upper limit Setting the non-volatile flag to a second state, the second state corresponding to the second non-volatile register, when the erasing time of the first non-volatile state register does not exceed the upper limit At time, the non-volatile flag is maintained in the first state. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 2 of the claim, wherein before the step of determining whether the erasing time of the first non-volatile state register exceeds the upper limit time, The method further includes: determining whether the first non-volatile flag and the second non-volatile flag are the second state; and when the first non-volatile flag is the second state, determining to determine the first non- Whether the erasing time of the volatile state register exceeds the upper limit time; and when the second non-volatile flag is the second state, erasing the second non-volatile state register. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 3 of the claim, wherein before the step of determining whether the erasing time of the first non-volatile state register exceeds the upper limit time, The method further includes: determining whether the non-volatile flag is the first state or the second state; and when the non-volatile flag is the first state, determining whether the erasing time of the first non-volatile state register is a step of exceeding the upper limit time; and when the non-volatile flag is the second state, erasing the second non-volatile state register. The method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 4 of the claim further includes: determining the first non-volatile flag and the second non-volatile flag in the reset phase Whether the flag is the second state; when the first non-volatile flag is the second state, resetting the first non-volatile state register; and when the second non-volatile flag is In the second state, the second non-volatile state register is reset. The method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 5 of the claim further includes: Determining, in the resetting phase, the non-volatile flag is the first state or the second state; when the non-volatile flag is the first state, resetting the first non-volatile state register; And when the non-volatile flag is the second state, resetting the second non-volatile state register. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 6 or Item 7 of the claim, wherein the first non-volatile state register and the second non-volatile state are temporarily stored Each of the devices has a plurality of non-volatile bits that are less than or equal to ten bits. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 8 of the claim, wherein the first non-volatile state register and the second non-volatile state register have six Non-volatile bits and two volatile bits. A method of preventing write time degradation of a long-term non-volatile bit according to claim 1 wherein the strobe cycle includes a pre-program phase, the erase phase, a programming phase, and a reset phase. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to claim 10, wherein the first non-volatile state register is wiped with a plurality of erase pulses during the erase phase except. The method for preventing write time degradation of a non-volatile bit of a long-term cycle according to claim 10, wherein the step of determining whether the erase time of the first non-volatile state register exceeds the upper limit time comprises: Determining whether the number of erasures for erasing the first non-volatile state register by a wipe pulse is greater than or equal to a predetermined number of times, wherein the erase pulse width multiplied by the erase count is equal to the erase time. A method for preventing write time degradation of a non-volatile bit of a long-term cycle according to Item 12 of the claim, wherein the number of erasures of erasing the first non-volatile state register by using an erase pulse is determined Whether it is greater than or equal to the predetermined number of steps After the step, the method further includes: when the erasing frequency is greater than or equal to the predetermined number of times, setting a temporary storage parameter, so that the temporary storage parameter corresponds to the first non-volatile state register, so that the programming phase is The first non-volatile state register is programmed; and when the number of erasures is less than the predetermined number of times, the temporary parameter is set such that the temporary parameter corresponds to the second non-volatile state register, The second non-volatile state register is programmed during the programming phase.