TW201545165A - Apparatus and method for providing configuration data to an integrated circuit - Google Patents

Abstract

An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Description

Apparatus and method for providing configuration data to an integrated circuit

This invention relates to the field of microelectronics, and more particularly to an apparatus and method for providing configuration data to an integrated circuit.

The technology of integrated circuits has achieved exponential progress over the past 40 years. Especially in the field of microprocessors starting with 4-bit single instruction, 10 micron devices, advances in semiconductor fabrication technology have enabled designers to provide increasingly complex devices in terms of architecture and density. In the 1980s and 1990s, so-called pipeline microprocessors and superscalar microprocessors were developed that included millions of transistors on a single die. Now, after 20 years, 64-bit 32-nm equipment is being produced, with billions of transistors on a single die, and it includes multiple microprocessor cores for data processing.

One requirement that has been adhered to since the early days of these early microprocessors was that they were initialized with configuration data when they were powered up or when they were reset. For example, many architectures enable a device to be enabled with one of a number of selectable frequencies and/or voltages. Other architectures require each device to have a sequence number and other information that can be read through the execution of the instruction. The internal registers and control circuitry of the other device require an initial Information. Additional microprocessors, particularly microprocessors with on-board cache memory, use patching data to implement redundant circuitry in these memories to correct manufacturing errors.

Those skilled in the art will appreciate that designers have traditionally employed semiconductor fuse arrays on the die to store and provide initial configuration and repair information. These fuse arrays are typically programmed by blowing selected fuses after the components have been fabricated, and the array contains thousands of bits of information that are read through the corresponding device after power up/reset. Take to initialize and configure the device to operate.

As the complexity of the device has increased over the past few years, the amount of configuration/repair data required for a typical device has also increased proportionally. However, those skilled in the art will appreciate that while the transistor size scales down with the semiconductor fabrication process employed, the semiconductor fuse size is due to the particular need for programming the fuses on the die. increase. This phenomenon in semiconductor fuses and by itself is a problem for designers who are often subject to real estate constraints and power limitations. In other words, there is not enough real resources on a given die to make a bulky fuse array.

Furthermore, the ability to fabricate multiple device cores on a single die has geometrically exacerbated this problem because the configuration requirements for each core result in a number of fuses on the die in a single array or in different arrays. Demand, which is proportional to the number of cores placed on it.

Moreover, those skilled in the art will appreciate that multi-core devices use a complex power saving mode of operation that causes one or more of the cores to be in a so-called power gating event (or "sleep mode") when not in use. Be Power off. Therefore, when the core is powered up after a power gating event, in addition to the more stringent initialization speed requirements, the same requirements for initialization, configuration, and patching continue to exist.

Accordingly, there is a need for an apparatus and method that enables configuration/repair data to be stored and provided to a multi-core device that requires significantly reduced actual resources and power on a single die as compared to devices that have been provided to date.

In addition, there is a need for a fuse array mechanism that is capable of storing and providing significantly more configuration/repair data than current technology while requiring the same or fewer actual resources on a multi-core die.

In addition, techniques are needed to facilitate the initialization, configuration, and patching of multi-core devices after a power gating event.

The present invention provides an apparatus for providing configuration data to an integrated circuit. The device includes a semiconductor fuse array and a plurality of cores. A semiconductor fuse array is placed on the die to which the compressed configuration data is programmed. A plurality of cores are disposed on the die, wherein each of the plurality of cores is coupled to the semiconductor fuse array, and wherein one of the plurality of cores is configured to access the semiconductor fuse after being powered up/reset The array reads and decompresses the compressed configuration data and stores one or more caches in each of the plurality of cores in a storage coupled to each of the plurality of cores A collection of decompressed configuration data for memory memory. Each of the plurality of cores has reset logic and sleep logic. The reset logic is configured to employ a decompressed set of configuration data to initialize one or more cache memories after power up/reset. Sleep logic is configured to determine the power gating event The power is then restored and configured to subsequently access the storage device to retrieve and employ the decompressed set of configuration data to initialize one or more cache memory memories after the power gating event.

In yet another aspect, the invention includes a method for configuring an integrated circuit. The method includes first disposing a semiconductor fuse array on a die, programming a compressed configuration data therein, and secondly arranging a plurality of microprocessor cores on the die, wherein each of the plurality of microprocessor cores One is coupled to the semiconductor fuse array, and wherein one of the plurality of microprocessor cores is configured to access the semiconductor fuse array after power up/reset to read and decompress the compressed configuration data, and Storing a set of decompressed configuration data for one or more cache memories within each of the plurality of cores in a storage device coupled to each of the plurality of cores; Reset logic within each of the instances, using a decompressed set of configuration data to initialize one or more cache memory after power up/reset; and via being disposed in multiple cores Each of the sleep logic determines to recover power after a power gating event, and then accesses the storage device to retrieve and employ the decompressed configuration data set, Initializing the one or more cache memory after power gating event.

With regard to industrial applicability, the present invention is implemented in a microprocessor that can be used in a general purpose or special purpose computing device.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100, 200, 300, 400, 1100‧‧‧ block diagram

101, 420, 1101‧‧ ‧ microprocessor core

102‧‧‧Fuse array

103‧‧‧Reset logic

104‧‧‧Reset circuit

105‧‧‧Reset microcode

107‧‧‧Control circuit

108, 415‧‧‧ microcode register

109, 414‧‧‧ microcode patch components

110, 416‧‧‧ Cache memory correction components

201‧‧‧Fuse Array

202, PFB1~PFBN, RFB1~RFBN‧‧‧Redundant fuse set

203‧‧‧Fuse

210, 211, PR1, RR1‧‧‧ register

212‧‧‧Exclusive logic

FB3‧‧‧ output

310‧‧‧Device Programmer

320‧‧‧Compressor

301‧‧‧Virtual fuse set

302‧‧‧Virtual Fuse

303‧‧‧Virtual Fuse Array

330‧‧‧ grain

332‧‧‧ core

334, 1102, CATCH1~CATCHN‧‧‧ Cache Memory

336, 1110‧‧‧ physical fuse array

RESET‧‧‧Reset

401‧‧‧Physical Fuse Array

403‧‧‧Microcode patch fuse

404‧‧‧Compressed register fuse

405‧‧‧Compressed cache memory correction fuse

406‧‧‧Compressed fuse correction fuse

417‧‧‧Reset controller

421‧‧Decompressor

408‧‧‧ patch fuse components

409‧‧‧Storage fuse element

410‧‧‧Cache memory fuse components

411‧‧‧Fuse correction component

412‧‧‧ busbar

502, 503, 601~603, 701~703, 802, 803, 901~903, 905, 1001~1003‧‧‧ fields

500, 600, 700, 800, 900, 1000‧‧‧ configuration data

604, 704, 804, 904‧‧‧ data blocks

1103‧‧‧Cache memory repair storage device

1104‧‧‧Configuration data storage device

1105‧‧‧Reset logic

1106‧‧‧ Sleep Logic

1120‧‧‧Power Controller

1130‧‧‧Non-core storage devices

SYNC‧‧‧ Sync Bus

1 is a block diagram of a current microprocessor core including a fuse array for providing configuration data to a microprocessor core; and FIG. 2 depicts a first fuse including an array of fuses that can be blown A block diagram of a fuse array in the microprocessor core of FIG. 1 after the group of blown redundant fuse sets; and FIG. 3 is a diagram showing compression and decompression of configuration data for the multi-core device according to the present invention. Block diagram of a system; FIG. 4 is a block diagram showing a fuse decompression mechanism according to the present invention; and FIG. 5 is a block diagram showing an exemplary format of a configuration material for compression according to the present invention; 6 is a block diagram showing an exemplary format of a decompressed microcode patch (PATCH) configuration material in accordance with the present invention; and FIG. 7 depicts a microcode register configuration for decompression in accordance with the present invention. A block diagram of an exemplary format of data; FIG. 8 is a block diagram showing an exemplary format of a cache memory correction data for decompression according to the present invention; FIG. 9 is a diagram for solving a solution according to the present invention. Example of compressed fuse correction data Block diagram of the format; Figure 10 shows a block diagram of an alternative exemplary format for the fuse correction data for decompression in accordance with the present invention; Figure 11 illustrates the provision of a cache for the power gating event A block diagram of a multi-core device in accordance with the present invention for rapid recovery of memory patching data.

Example and illustrative embodiments of the invention are described below. for It is clear that not all features of the actual implementation are described in this specification, as those skilled in the art will appreciate that in the development of any such actual embodiment, various implementation-specific It is decided to achieve specific goals, such as compliance with system-related or business-related restrictions, which may vary depending on the implementation. Moreover, it will be appreciated that these development efforts will be complex and time consuming, however, it should be routine for those of ordinary skill in the art having the benefit of this disclosure. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described herein, but rather in the broad scope of the principles and novel features described herein.

The invention will now be described with reference to the drawings. The various structures, systems, and devices that are schematically depicted in the drawings are for illustrative purposes only, and should not be construed However, the attached drawings are included to describe and explain illustrative examples of the invention. The words and phrases used herein should be understood and interpreted as having the meaning of the words and phrases understood by those skilled in the art. The specific definition of a term or phrase (i.e., a definition different from the ordinary and customary meanings understood by those skilled in the art) is not implied by the consistent use of the term or phrase herein. In order for a term or phrase to be used with a particular meaning (i.e., meaning other than what is understood by a skilled artisan), such a particular definition will be explicitly set forth in a defined manner in the specification. A specific definition for the term or phrase will be provided directly and explicitly.

In view of the above background discussion on device fuse arrays and in use The related art employed in the current integrated circuit that provides configuration data during initial power up will be discussed with reference to Figures 1 and 2 for limitations and disadvantages of these techniques. Hereinafter, a discussion of the present invention will be presented with reference to Figures 3-10. The present invention overcomes the limitations and disadvantages discussed below by providing apparatus and methods for employing a compression configuration in a multi-core die that uses less power and actual resources on the multi-core die to provide for power selection The quick recovery of configuration and patching data after the event is more reliable than the technology that has been provided to date.

definition:

Integrated circuit (IC): A collection of electronic circuits fabricated on small-sized semiconductor materials (typically germanium). An IC can also be referred to as a wafer, a microchip, or a die.

Central Processing Unit (CPU): executes computer programs (also known as "computer applications", "applications", "programs", by performing operations including arithmetic operations, logical operations, and input/output operations on data. Or an "application" of an electronic circuit (ie, "hardware").

Microprocessor: An electronic device used as a CPU on a single integrated circuit. The microprocessor receives the digital data as input, processes the data based on instructions fetched from the memory (on the die or out of the die), and generates the result of the operation specified by the instruction as an output. A general purpose microprocessor can be employed in devices including, but not limited to, desktop computers, mobile computers, or tablets, and can be used for, for example, without limitation, computing, text editing, multimedia display, and the Internet. The task of the tour. The microprocessor can also be arranged in an embedded system to control including electrical appliances, mobile phones, smart phones, And various equipment for industrial control equipment.

Multi-core processors: Also known as multi-core microprocessors, multi-core processors are microprocessors with multiple CPUs (also referred to as "cores") fabricated on a single integrated circuit.

Instruction Set Architecture (ISA) or instruction set: Part of a computer architecture associated with programming, including: data types, instructions, scratchpads, addressing modes, memory architecture, interrupt and execution processing, and input/output. The ISA includes specifications for the set of opcodes (ie, machine language instructions), as well as native commands implemented by a particular CPU.

X86-compatible microprocessor: A microprocessor capable of executing a computer application programmed according to the x86 ISA.

Microcode: A term used to denote multiple microinstructions. Microinstructions (also known as "native instructions") are instructions at the level of execution of the microprocessor subunit. Exemplary subunits include integer units, floating point units, MMX units, and load/store units. For example, microinstructions are executed directly by a Reduced Instruction Set Computer (RISC) microprocessor. For complex instruction set (CISC) microprocessors such as x86 compatible microprocessors, x86 instructions are translated into associated microinstructions, and associated microinstructions pass directly through a subunit within the CISC microprocessor. Or multiple subunits to execute.

Fuse: A conductive structure that is typically arranged as a filament that can be broken at a selected location by applying a voltage across the filament and/or applying a current through the filament. Fuses can be deposited at specified areas across the grain profile using well-known fabrication techniques to produce filaments at all potential programmable areas. After fabrication, the fuse structure is blown (or not blown), so that it is arranged Corresponding devices on the die provide the desired programmability.

Referring to FIG. 1, a block diagram 100 is presented illustrating a current microprocessor core 101 including a fuse array 102 for providing configuration data to a microprocessor core 101. Fuse array 102 includes a plurality of microprocessor fuses (not shown) that are typically arranged in groups called banks. Fuse array 102 is coupled to reset logic 103 that includes both reset circuit 104 and reset microcode 105. The reset logic 103 is coupled to the control circuit 107, the microcode register 108, the microcode patch component 109, and the cache memory correction component 110. An external reset signal RESET is coupled to the microprocessor core 101 and passed to the reset logic 103.

Those skilled in the art will appreciate that fuses (also referred to as "links" or "fuse structures") are employed in a large number of current integrated circuit devices to provide configuration for the device after the device is manufactured. For example, it is contemplated that the microprocessor core 101 of FIG. 1 is fabricated to selectively provide functions such as a desktop device or a mobile device. Thus, after fabrication, the specified fuses within the fuse array 102 can be blown to configure equipment such as mobile devices. Thus, after the reset signal RE SET is enabled, the reset logic 103 reads the state of the specified fuse in the fuse array 102 and resets the circuit 104 (instead of resetting the microcode 105 in this example) A corresponding control circuit 107 is enabled which exclusively disables the elements of the core 101 associated with the operation of the desktop device and exclusively activates the elements of the core 101 associated with the mobile operation. Therefore, after power-on reset, the core 101 is configured as a mobile device. In addition, reset logic 103 reads the status of other fuses in fuse array 102, and reset circuit 104 (rather than reset microcode 105 in this example) enables corresponding cache memory corrections. Element 110 provides a correction mechanism for one or more cache memory (not shown) associated with core 101. Thus, after power-on reset, core 101 is configured as a mobile device and the correction mechanism for its cache memory is ready.

The above examples are just one of many different uses for configuring fuses in an integrated circuit device such as microprocessor core 101 of FIG. Those skilled in the art will appreciate that other uses for configuring fuses include, but are not limited to, configuration of device-specific data (eg, serial number, unique cryptographic key, architecture mandated data that can be accessed by the user). , speed setting, voltage setting), initialization data, and patch data. For example, many current devices execute microcode and often require initialization of the scratchpad 108 that is read by the microcode. Such initialization data may be provided by a microcode register fuse (not shown) within fuse array 102, which may be read after reset and passed through reset logic 103 (using reset circuit 104) Alternatively, the reset microcode 105, or the two components 104-105), is provided to the microcode register 108. For purposes of the present invention, reset circuit 104 includes hardware components that provide certain types of configuration material that cannot be provided via execution of reset microcode 105. The reset microcode 105 includes a plurality of microinstructions arranged within an internal microcode memory (not shown) that are executed after resetting of the core 101 to perform functions corresponding to initialization of the core 101, including The configuration data read by the fuse array 102 is provided to elements such as the microcode register 108 and the microcode patch component 109. The criteria for whether certain types of profiles provided via fuses can be distributed to various elements 107-110 of core 101 via reset microcode 105 are the primary functions of the particular design of core 101. this invention Not only is there a comprehensive teaching of specific configuration techniques that are employed to initialize integrated circuit devices, as those skilled in the art will appreciate that for current microprocessor cores 101, the types of configurable components 107-110 typically fall into the category. To the four categories as illustrated in Figure 1: control circuitry, microcode registers, microcode patching mechanisms, and cache memory correction mechanisms. Moreover, those skilled in the art will appreciate that the particular value of the configuration data varies significantly based on the particular type of material. For example, the 64-bit control circuit 107 can include ASCII data that specifies the sequence number for the core 101. Another 64-bit control register can have 64 different speed settings, only one of which is enabled to specify the operating speed of the core 101. The microcode register 108 can typically be initialized to all zeros (ie, a logic low state) or all ones (ie, a logic high state). The microcode patch element 109 may include a nearly uniform distribution of 1's and 0's to indicate addresses in the microcode ROM (not shown) and alternate microcode values for those addresses. Finally, the cache memory correction (ie, "patches") mechanism can include a very sparse setting of 1 to indicate replacement control signals to replace certain cache memory subgroup elements (ie, rows or columns) with specific ones. Substituting subgroup elements to enable patching of one or more cache memory.

The fuse array 102 provides an excellent means for configuring a device such as the microprocessor core 101 after the device is manufactured. By blowing the selected fuses in the fuse array 102, the core 101 can be configured for operation in its intended environment. However, those skilled in the art will appreciate that the operating environment may vary after the fuse array 102 is programmed. Commercial requirements may command the device 101, originally configured to be configured as a desktop device 101, to be reconfigured as the mobile device 101. Therefore, the designer has provided the following technology: The redundant set of fuses used in the fuse array 102 is provided with "unboiled" to the selected fuse therein, thereby enabling the device 101 to be reconfigured and capable of correcting manufacturing errors and the like. These redundant array techniques will now be discussed with reference to Figure 2.

Referring now to FIG. 2, a block diagram 200 is presented depicting a fuse array 201 within the microprocessor core 101 of FIG. 1 including redundant fuse sets 202 RFB1-RFBN, the redundant fuse set 202 RFB1 The -RFBN will be blown after the first fuse array group 202 PFB1-PFBN in the fuse array 201 is blown. Each of the fuse arrays 202 PFB1-PFBN, RFB1-RFBN includes a prescribed number of individual fuses 203 corresponding to a particular design of the core 101. For example, in a 64-bit microprocessor core 101, the number of fuses 203 in a given fuse set 202 can be 64 fuses 203 to facilitate providing configuration information in a format that is easily implemented in core 101. .

The fuse array 201 is coupled to a register set 210-211, which is typically disposed within the reset logic of the core 101. The main register PR1 is employed to read one of the first fuse sets PFB1-PFBN (for example, PFB3 shown in view 200), and the redundancy register RR1 is employed to read the redundant fuse Corresponding one of the arrays RFB1-RFBN. The registers 210-211 are coupled to mutual exclusion logic 212 that generates an output FB3.

In operation, after manufacturing the core 101, the first fuse set PFB1-PFBN is programmed by known techniques using configuration information for the core 101. The redundant fuse sets RFB1-RFBN are not blown and remain in a logic low state for all of the fuses therein. After power-on/reset of the core 101, the first fuse set PFB1-PFBN and the redundant fuse set RFB1-RFBN are both The settings are read separately for configuration to the primary and redundant registers 210-211. Mutually exclusive OR logic 212 generates an output FB3, which is a logical exclusive or result of the contents of registers 210-211. Since all of the redundant fuse sets are not blown (ie, logic low state), the output FB3 value is programmed into the first fuse set PFB1-PFBN only after being fabricated.

However, it is now considered that some of the information that the design or commercial requirements command is programmed into the first fuse set PFB1-PFBN needs to be changed. Therefore, a programming operation is performed to blow the respective fuses 203 in the redundant fuse sets RFB1-RFBN to change the information read at power-on. By blowing the fuse 203 in the selected redundancy group RFB1-RFBN, the values of the respective fuses 203 in the primary fuse sets PFB1-PFBN are logically complemented.

The mechanism of Figure 2 can be employed to provide "re-blow" of the fuse 203 within the device 101, but those skilled in the art will appreciate that a given fuse 203 can only be re-battered once because only There is a set of redundant fuse sets RFB1-RFBN. In order to provide additional re-blow, a corresponding number of additional fuse sets 202 and registers 210-211 must be added to component 101.

To this end, the fuse array mechanism discussed above with reference to Figures 1-2 has provided sufficient flexibility to configure the microprocessor core and other associated devices while still allowing a limited number of re-blows. This is mainly due to the fact that previous manufacturing techniques, such as the 65 nm and 45 nm processes, allowed sufficient practical resources on the die to achieve sufficient fuses to provide core 101 for placement on the die. Configuration. However, the inventors have observed that current technologies are limited in their advancement due to two important factors. First, a trend in the art is to place multiple device cores 101 in a single On the die to increase processing performance. These so-called multi-core devices may include, for example, 2-16 individual cores 101, each of which must be configured with fuse data after power up/reset. Thus, for a 4-core device, four fuse arrays 201 are required because some of the data associated with the individual cores may vary (eg, cache memory correction data, redundant fuse data, etc.). Secondly, those skilled in the art will appreciate that as the manufacturing process technology shrinks to, for example, 32 nm, as the transistor size shrinks, the fuse size increases, requiring more physical resources of the die to be relative to On the 45 nm grain, a fuse array of the same size was realized on a 32 nm die.

The above two limitations, as well as other limitations, present significant challenges for device designers, and more specifically for multi-core device designers, and the inventors have noted that significant improvements in the configuration mechanism for conventional devices can be achieved in accordance with the present invention. It allows for programming of individual cores in multi-core devices, as well as significantly increased cache memory error correction and fuse reprogramming ("reboil") components. The invention will now be discussed with reference to Figures 3-11.

Referring to Figure 3, the block diagram presented is characterized by a system 300 in accordance with the present invention that provides compression and decompression of configuration/repair data for a multi-core device. The multi-core device includes a plurality of cores 332 that are disposed on the die 330. Although the present invention contemplates various numbers of cores 332 disposed on die 330, four cores 332 are depicted on die 330 for exemplary purposes. In one embodiment, all of the cores 332 share a single cache memory 334 that is also disposed on the die 330. A single programmable physical fuse array 336 is also disposed on the die 330, and each of the cores 332 is configured to access the fuse array 336 for retrieval and decompression during power up/reset as described above Configuration information.

In one embodiment, core 332 includes a microprocessor core configured as a multi-core microprocessor 330. In another embodiment, the multi-core microprocessor 330 is configured as an X86 compatible multi-core microprocessor. In yet another embodiment, cache memory 334 includes level 2 (L2) cache memory 334 associated with microprocessor core 332. In one embodiment, the fuse array 336 includes 8192 (8K) individual fuses (not shown), although other numbers of fuses are also contemplated. In a single core embodiment, only one core 332 is disposed on die 330 and core 332 is coupled to cache memory 334 and physical fuse array 336. The inventors have noted that while the features and functions of the present invention will be discussed below in the context of multi-core device 330, these features and functions can be equally applied to a single core embodiment.

System 300 also includes a device programmer 310 that includes a compressor 320 coupled to a virtual fuse array 303. In one embodiment, device programmer 310 can include a CPU (not shown) configured to process configuration data and to program fuse array 336 after fabrication of die 330 in accordance with well-known programming techniques. design. The CPU can be integrated into a wafer test apparatus that is employed to test the device die 330 after fabrication. In one embodiment, the compressor 320 can include an application executing on the device programmer 310, and the virtual fuse array 303 can include locations within the memory accessed by the compressor 320. The virtual fuse array 303 includes a plurality of virtual fuse sets 301, each of which includes a plurality of virtual fuses 302. In one embodiment, virtual fuse array 303 includes 128 virtual fuse sets 301, each of which includes 64 virtual fuses 302, resulting in a virtual array 303 that is 8 Kb in size.

Operationally, the configuration information of the die 330 is input to the virtual fuse array. Column 303 is included as part of the manufacturing process and is as described above with reference to Figure 1. Therefore, the configuration information includes control circuit configuration data, initialization data for the microcode register, microcode patch data, and cache memory correction data. Furthermore, as described above, the distribution of values associated with each of the material types differs significantly depending on the type. The virtual fuse array 303 is a fuse array including configuration information for each of the microprocessor cores 332 on the die 330, and correction data for each cache memory 334 on the die 330 ( A logical representation of not shown).

After the information is input into the virtual fuse array 303, the compressor 320 reads the state of the virtual fuse 302 in each of the virtual fuse sets 301, and uses a different compression algorithm corresponding to each data type. The information is compressed to render the compressed fuse array data 303. In one embodiment, the system data of the control circuit is not compressed, but is transmitted without compression. To compress the microcode register data, a microcode scratchpad data compression algorithm is employed which is effective for compressing data having a state distribution corresponding to the microcode register data. In order to compress the microcode patch data, a microcode patch data compression algorithm is employed which is effective for compressing data having a state distribution corresponding to the microcode patch material. In order to compress the cache memory correction data, a cache memory correction data compression algorithm is employed which is effective for compressing data having a state distribution corresponding to the cache memory correction data.

Device programmer 310 then programs the uncompressed and compressed fuse array data into physical fuse array 336 on die 330.

After power up/reset, each core 332 can access physical fuse array 336 to retrieve uncompressed and compressed fuse array data and is placed The reset circuit/microcode (not shown) within each core 332 distributes the uncompressed fuse array data and decompresses according to different decompression algorithms corresponding to each of the above recorded data types. The compressed fuse array data is used to represent the value originally input to the virtual fuse array 303. The reset circuit/microcode then inputs configuration information to a control circuit (not shown), a microcode register (not shown), a patch component (not shown), and a cache memory correction component (not shown) )in.

Advantageously, the fuse array compression system 300 in accordance with the present invention enables a device designer to employ a significantly smaller number of fuses in the physical fuse array 336 relative to the techniques that have been provided to date, and to use programming therein. The compression information is used to configure the multi-core device 330 during power up/reset.

Referring now to Figure 4, a block diagram 400 is presented showing a fuse decompression mechanism in accordance with the present invention. The decompression mechanism can be placed in each of the microprocessor cores 332 of FIG. For the purpose of clearly teaching the present invention, only one core 420 is depicted in FIG. 4, and each of the cores 332 disposed on the die includes elements that are substantially equivalent to the core 420 shown. A physical fuse array 401 disposed on the die as described above is coupled to the core 420. The physical fuse array 401 includes a compressed microcode patch fuse 403, a compressed scratchpad fuse 404, a compressed cache memory correction fuse 405, and a compressed fuse correction fuse 406. Physical fuse array 401 may also include uncompressed configuration material such as system configuration data (not shown) and/or block error checking and correction (ECC) code (not shown) as discussed above. The content contained in the ECC feature according to the present invention will be described in more detail below.

Microprocessor core 420 includes a reset controller 417 that receives power-up after core 420 and responds to causing core 420 to initiate a reset sequence step The reset signal RESET is enabled for the event. The reset controller 417 includes a decompressor 421. The decompressor 421 has a patch fuse element 408, a register fuse element 409, and a cache memory fuse element 410. The decompressor 421 also includes a fuse correction component 411 that is coupled via a bus bar 412 to a patch fuse component 408, a scratchpad fuse component 409, and a cache memory fuse component 410. Patch fuse element 408 is coupled to microcode patch element 414 in core 420. Register fuse element 409 is coupled to microcode register 415 in core 420. And the cache memory fuse element 410 is coupled to the cache memory correction component 416 in the core 420. In one embodiment, the cache memory correction component 416 is disposed within an L2 cache memory (not shown) on the die, such as the cache memory 334 of FIG. All cores 420 of the class are shared. Another embodiment contemplates that the cache memory correction component 416 is disposed within an L1 cache (not shown) within the core 420. Another embodiment contemplates that the cache memory correction component 416 is arranged to correct both of the L2 and L1 cache memories described above. Other embodiments contemplate that the cache memory correction component 416 is disposed on multiple cores and not on the core.

In operation, after enabling the reset signal RESET, the reset controller 417 reads the state of the fuses 403-406 in the physical fuse array 410 and the state of the compressed system fuse (not shown). It is distributed to the decompressor 421. After the fuse data has been read and distributed, the fuse correction component 411 of the decompressor 421 decompresses the state of the compressed fuse correction fuse 406 to represent the state indicated in the physical fuse array 401. Data from one or more fuse addresses that have changed from the state of the previous programming. The decompressed data also includes values for each of one or more fuse addresses. One or more The fuse addresses (and optional values) are transmitted via bus 412 to components 408-410 such that the state of the respective fuses processed therein changes prior to decompressing their respective compressed data.

In one embodiment, patch fuse element 408 includes microcode that operates to compress a microcode patch decompression algorithm corresponding to the microcode patch compression algorithm described above with reference to FIG. The state of the microcode patch fuse 403 is decompressed. In one embodiment, the register fuse element 409 includes microcode that operates to decompress the register fuse according to the register fuse compression algorithm as described above with reference to FIG. The algorithm decompresses the state of the compressed scratchpad fuse 404. In one embodiment, the cache memory fuse element 410 includes microcode that operates to operate in accordance with a cache memory corresponding to the cache memory correction fuse compression algorithm described above with reference to FIG. The fuse decompression algorithm is calibrated to decompress the state of the compressed cache memory correction fuse 405. After each of the elements 408-410 changes its address (and optional value) by the state of any fuse provided from the fuse correction element 411 via the bus bar 412, its respective data is calculated according to the corresponding calculation The solution is decompressed. As will be described in more detail below, the present invention contemplates multiple "re-reviews of any fuse address within the physical fuse array prior to initialization of the decompression process performed by any of the components 408-411. Blow out." In one embodiment, bus 412 may include conventional microcode programming mechanisms employed to transfer data between various routines therein. The present invention further contemplates a comprehensive decompressor 421 having the ability to identify and decompress configuration data based on its particular type. Thus, although the elements 408-411 stated in the decompressor 421 are Presented to teach relevant aspects of the art, however, contemplated implementations of the present invention may not necessarily include different elements 408-411, but instead include a comprehensive decompressor 421 that provides each of the elements described above 408-411 corresponding function.

In one embodiment, reset controller 417 initializes execution of microcode within patch fuse element 408 to decompress the state of compressed microcode patch fuse 403. The reset controller 417 also initializes the execution of the microcode within the scratchpad fuse element 409 to decompress the state of the compressed register fuse 404. And reset controller 417 further initiates execution of the microcode within cache memory fuse element 410 to decompress the state of compressed cache memory correction fuse 405. The microcode within decompressor 421 is also operative to change the state of any fuse addressed by the fuse correction data provided by compressed fuse correction fuse 406 prior to decompressing the compressed material.

The reset controller 417, decompressor 421, and elements 408-411 therein are configured to perform the functions and operations discussed above in accordance with the present invention. The reset controller 417, the decompressor 421, and the elements 408-411 therein may include logic, circuitry, devices, or microcode, or a combination of logic, circuitry, devices, or microcode, or employed to perform The equivalents of the functions and operations of the present invention are recorded. Elements that are employed to perform these operations and functions within reset controller 417, decompressor 421, and elements 408-411 therein may be employed to execute at reset controller 417, decompressor 421, Other circuitry, microcode, etc., of other functions and/or operations within elements 408-411 are shared, or shared by other components within core 420.

After the states of fuses 403-406 within physical fuse array 401 have been changed and decompressed, the state of the decompressed "virtual" fuses is then appropriately transferred to microcode patch component 414, microcode register 415. And a cache memory correction component 416. Thus, core 420 is configured for operation after the reset sequence is completed.

The inventors have noted that the decompression functions discussed above do not need to be performed in a particular order during the reset sequence. For example, a microcode patch can be decompressed after decompression of the microcode register initialization data. Likewise, the decompression functions can be performed in parallel or in an order suitable to meet design constraints.

Moreover, the inventors have noted that the implementation of elements 408-411 need not be implemented in microcode relative to hardware circuitry, as typical microprocessor cores 420 can be written relative to direct microcode. The elements of the core 420 are more easily initialized via hardware (eg, a scan chain associated with the cache memory). The details of such an implementation will be left to the designer to judge. However, the inventors have submitted that the prior art teaches that during a reset prior to the initialization of the execution of the microcode, the cache memory correction fuse is conventionally read by the hardware circuit and input to the cache memory correction. In the scan chain, and the invention is characterized in that the cache memory fuse element 410 is implemented in microcode as opposed to the hardware control circuitry, since the core cache memory is typically not turned on until the microcode is run. Executing the memory fuse element 410 by using microcode provides a more flexible and advanced mechanism for logging cache memory correction data into the scan chain and significantly saving hardware.

Referring now to Figure 5, the block diagram presented is illustrated in accordance with the present invention. An exemplary format of a configuration profile 500 for compression. The compressed configuration data 500 is compressed by the compressor 320 of FIG. 3 from the data residing in the virtual fuse array 303 and is programmed (ie, "burned") into the physical fuse array 336 of the multi-core device 330. During the reset sequence as described above, the compressed configuration data 500 is retrieved from the physical fuse array 336 by each of the cores 332 and resolved by elements 408-411 of the decompressor 421 within each core 420. Compression and correction. The decompressed and corrected configuration data is then provided to various elements 414-416 within core 420 to initialize core 420 for operation.

The compressed profile 500 includes one or more compressed data fields (D) 502 for each of the profile types discussed above, and which pass an end-of-type field (ET) ) 503 to demarcate. The programming event (ie, "burn") is delimited by an end-of-blow field (EB) 504. The compressed data field 502 associated with each of the data types is optimized to cause the bits (ie, fuses) required to store a particular bit pattern associated with each of the data types. The number is minimized by a compression algorithm for encoding. The number of fuses in the physical fuse array 336 forming each of the compressed data fields 502 is a function of the compression algorithm employed for a particular data type. For example, consider a core that includes 64 64-bit microcode scratchpads that must be initialized to, for example, all ones or all zeros. An optimized compression algorithm can be employed to generate 64 compressed data fields 502 for the data type, wherein each of the compressed data fields 502 includes initialization data for a particular microcode register, where the compressed data field Bits 502 are specified in the order of the register number (ie, 1-64). Each of the compressed data fields 502 includes a single fuse if the corresponding microcode register is initialized If it is all 1, it is blown, and if the corresponding microcode register is initialized to all 0s, it is not blown.

Elements 408-410 of decompressor 421 in core 420 are configured to use type end field 503 to determine where their respective compressed data is located within physical fuse array 336, and fuse correction element 411 is configured to The burnout end field 504 is used to locate the compressed fuse correction data that has been programmed (ie, blown) after the initial programming event. As will be discussed in more detail below, the present invention features the provision of a large number of spare fuses in the physical fuse array 336 to allow for substantial subsequent programming events.

The exemplary compression type format discussed above is presented to clearly teach aspects of the invention associated with compression and decompression of configuration data. However, the form of compression, demarcation of a particular data type, and the amount and type of material to be compressed within the fuse array 401 are not intended to be limited to the example of FIG. Other digits, types, and formats are contemplated which allow the invention to be adapted to the various devices and architectures that exist in the art.

Referring now to Figure 6, a block diagram is presented illustrating an exemplary format of a microcode patch configuration material 600 for decompression in accordance with the present invention. The compressed microcode patch configuration material is read from the physical fuse array 401 by each core 420 during the reset sequence. The compressed microcode patch configuration data is then corrected based on the fuse correction data provided via bus bar 412. The corrected compressed microcode patch configuration data is then decompressed by patch fuse element 408. The result of the decompression process is the decompressed microcode patch configuration material 600. The data 600 includes a plurality of decompressed data blocks 604 corresponding to the number of microcode patch elements 414 within the core 420 that require initialization data. Each decompression The data block 604 includes a core address field 601, a microcode ROM address field 602, and a microcode patch data field 603. The size of fields 601-603 is a function of the core architecture. As part of the decompression process, patch fuse element 408 generates a complete image of the target material needed to initialize microcode patch component 414. After decompression of the microcode patch configuration material 600, a conventional distribution mechanism can be employed to distribute the data 603 to the corresponding addressed cores in the microcode patch component 414 as well as the microcode ROM replacement circuitry/scratchpad.

Referring now to Figure 7, a block diagram is presented depicting an exemplary format of a microcode register configuration profile 700 for decompression in accordance with the present invention. During the reset sequence, the compressed microcode register configuration data is read by each core 420 from the physical fuse array 401. The compressed microcode register configuration data is then corrected based on the fuse correction data provided via bus bar 412. The corrected compressed microcode register configuration data is then decompressed by the register fuse element 409. The result of the decompression process is the decompressed microcode register configuration data 700. The data 700 includes a plurality of decompressed data blocks 704 corresponding to the number of microcode registers 415 within the core 420 that require initialization data. Each decompressed data block 704 includes a core address field 701, a microcode register address field 702, and a microcode register data field 703. The size of fields 701-703 is a function of the core architecture. As part of the decompression process, the scratchpad fuse element 409 generates a complete image of the target material needed to initialize the microcode register 415. After decompression of the microcode register configuration data 700, a conventional distribution mechanism can be employed to distribute the data 703 to the corresponding addressed core and microcode registers 415.

Referring now to Figure 8, the block diagram presented is characterized by An exemplary format of the cache memory correction material 800 for decompression of the present invention. The compressed cache memory correction data is read from the physical fuse array 401 by each core 420 during the reset sequence. The compressed cache memory correction data is then corrected based on the fuse correction data provided via bus bar 412. The corrected compressed cache memory correction data is then decompressed by the cache memory fuse element 410. The result of the decompression process is the decompressed cache memory correction data 800. Various cache memory mechanisms can be employed in the multi-core processor 330, and the decompressed cache memory correction material 800 is presented in the context of a shared L2 cache memory 334, where all cores 332 can use a common area. A single cache memory 334 is accessed. Therefore, an exemplary format is provided in accordance with the recorded architecture. The data 800 includes a plurality of decompressed data blocks 804 corresponding to the number of cache memory correction elements 416 within the core 420 that require calibration data. Each decompressed data block 804 includes a subunit column address field 802 and an alternate column address field 803. Those skilled in the art will appreciate that redundant memory lines (or columns) are used in the sub-cells of the cache memory to make the memory cache memory to allow for functional redundant lines in a particular sub-unit ( Or column) to replace rows (or columns) that have no function. Thus, the decompressed cache memory correction data 800 allows for the replacement of non-functional rows with functional rows (as shown in Figure 8). Moreover, those skilled in the art will appreciate that the conventional fuse array mechanism associated with cache memory correction includes fuses associated with each sub-cell row being blown when redundant sub-cell rows require replacement. . Therefore, because such a large number of fuses are needed (for addressing all of the subunits and the rows therein), typically only a portion of the subunits are included, and then the cache memory correction fuses will be blown very sparsely. And the inventors have also noticed that the invention is characterized only by the need for replacement Those subunit rows address and compress the subunit row address and the alternate row address, thereby minimizing the number of fuses needed to implement the cache memory correction data. Thus, as limited by the physical fuse array size and the amount of additional configuration material programmed therein, the present invention provides an extension to the cache memory 334 that can be corrected relative to the techniques that have been provided to date. The potential of the number of subunit rows (or columns). In the embodiment shown in FIG. 8, it is noted that the associated core 332 is configured such that only one of the cores 332 of the shared L2 cache 334 will access the correction material 802-803 and provide it to it. A corresponding cache memory correction component 416 is provided. The size of the field 802-803 is a function of the core architecture. As part of the decompression process, the cache memory correction fuse element 410 generates a complete image of the target material needed to initialize the cache memory correction component 416. After decompression of the cache memory correction data 800, the conventional distribution mechanism in the response core 420 can be employed to distribute the data 802-803 to the corresponding addressed cache memory correction component 416.

Referring to Figure 9, the block diagram presented is characterized by an alternative exemplary format for decompressing cache memory correction material 900 in accordance with the present invention. The embodiment of Figure 9 can be employed in a mechanism such as that of Figure 4. Multi-core processor configuration, wherein each core 420 includes one or more cache memories (not shown) on the core, including but not limited to a level one (L1) data cache and an L1 instruction cache. . The compressed cache memory correction data is read from the physical fuse array 401 by each core 420 during the reset sequence. The compressed cache memory correction data is then corrected based on the fuse correction data provided via bus bar 412. The corrected compressed cache memory correction data is then decompressed by the cache memory fuse element 410. The result of the decompression process is the decompressed cache Memory correction data 900. The data 900 includes a plurality of decompressed data blocks 904 corresponding to the number of cache memory correction elements 416 within the core 420 that require calibration data. Each decompressed data block 904 has a core address field 901, a cache memory address (CAD) field 905, a sub-cell row address field 902, and an alternate row address field 903. Thus, the decompressed cache memory correction data 900 allows for the replacement of functional rows (or columns) within the core 420 specified by the core address field 901 within the cache specified by the CAD field 905. A line (or column) that has no function. The predefined core address values in the core address field 901 may specify a shared cache memory, such as an L2 cache memory that is not on the core. The size of fields 901-903, 905 is a function of the core architecture. As part of the decompression process, the cache memory correction fuse element 410 generates a complete image of the target material needed to initialize the cache memory correction component 416. After decompression of the cache memory correction data 900, the conventional distribution mechanism in the response core 420 can be employed to distribute the data 901-903, 905 to the corresponding addressed cache memory correction component 416.

Referring now to Figure 10, a block diagram is presented showing an exemplary format of fuse correction material 1000 for decompression in accordance with the present invention. As discussed above, during reset, the fuse correction component 411 accesses the compressed fuse correction data 406 within the physical fuse array 401, decompresses the compressed fuse correction data, and produces a resolved solution. The compressed fuse correction data 1000 is provided to other components 408-410 within core 420. The decompressed fuse correction data includes one or more burnout end fields (EB) 1001 that indicate the end of the successfully programmed event in the physical fuse array 401. If a subsequent programming event has occurred, the re-burnout field (R) 1002 is programmed to indicate the following Situation: Subsequent one or more fuse correction fields (FC) 1003 indicate fuses within the physical fuse array 401 that are to be re-blowed. Each of the fuse correction fields includes the address of a particular fuse within the physical fuse array 401 that is to be re-blowed and the state of the particular fuse (ie, blown or not blown). Only those fuses that will be re-blowed are provided in the fuse correction field 1003, and each set of fields 1003 within a given re-blow event is delimited by the burnout end field 1001. If the appropriately encoded re-burnout field 1002 is present after a given burn-out field 1001, the subsequent one or more fuses may be configured to be re-directed as indicated by the corresponding fuse correction field. Boiled. Thus, the present invention provides the ability to re-blow a sufficient number of identical fuses as defined by the array size or other materials provided therein.

The inventors have also observed that the actual resources and power gain associated with the utilization of the shared physical fuse array in which the compressed configuration data is stored present an opportunity for additional features to be placed on the multi-core die. Moreover, the inventors have also noted that those skilled in the art will appreciate that today's semiconductor fuse structures are often subject to several disadvantages, one of which is referred to as "growback." Inverse growth is the inverse of the programming process, which causes the fuse to reconnect after it has been blown for a period of time, ie, it is changed from being programmed (ie, blown) back to unprogrammed ( That is, the state is not burned.

On the other hand, as indirectly mentioned above, the inventors have noted that when power gating techniques are employed to minimize power consumption on, for example, the multi-core die of die 330 of Figure 3, there are many challenge. Such techniques outside the scope of this application are employed to detect one or more cores 332 It is not utilized and powers down one or more cores 332 (also known as power gating events) in a variety of ways. When the power gated core 322 is required to execute, the power is restored to the core 332 and it begins execution. Of particular interest to the inventors is the case where the core 332 includes one or more cache memories on the core, as discussed with reference to Figure 9, where power is taken from these cache memories during power gating events. Removed from the body. Those skilled in the art will appreciate that in order to power up one or more cache memories after a power gating event, one or more cache memories must first be configured using the fuse correction data as described above. However, those skilled in the art will also appreciate that over-reading of the fuse array reduces the life of the fuse therein. Another problem associated with power gating is that each core may require excessive time to read the cache memory correction fuse to decompress the compressed fuse repair data and configure it for its corresponding core. Cache the correction of each of the memories. Accordingly, another embodiment of the present invention is provided to: 1) reduce the amount of time required for all cores to decompress and configure the cache memory on their respective cores after a power gating event; and 2) pass The number of core accesses is reduced under power gating conditions to increase the overall life of the fuse array.

Referring now to Figure 11, the block diagram presented therein details the mechanism according to the present invention for quickly loading cache memory correction data into the multi-core device 1100 initially and after a power gating event. Apparatus 1100 includes a plurality of cores 1101 that are substantially configured as described above with reference to Figures 3-10. In addition, each core 1101 includes one or more core cache memories CACHE1-CACHEN 1102, a cache memory repair storage device 1103, a configuration data storage device 1104, a reset logic 1105, and Sleep logic 1106. Each of the cores 1101 is coupled to a physical fuse array 1110 configured as described above with reference to Figures 3-10, and coupled to a storage device disposed on the same die as the core 1101 (eg, randomly stored) Memory (RAM) 1130 is taken, but it is not disposed in any of the cores 1101. Therefore, the storage device 1130 is hereinafter referred to as a "non-core (UNCORE)" storage device 1130. The non-core storage device 1130 includes designated sub-storage devices 1131-1134, each of which corresponds to each of the cores 1101. Multi-core device 1100 further includes a power controller 1120 coupled to each core 1101. A synchronous bus SYNC is coupled to each core 1101 to provide synchronous communication therebetween during power up, reset, and power gating events.

For purposes of example, only four cores 1101, a single physical fuse array 1110, and a single non-core storage device 1130 are shown, however, the inventors have noted that the novel and inventive content in accordance with the present invention can be Expanded to multiple cores 1101, fuse array 1110, and any number of non-core storage devices 1130. In one embodiment, the non-core storage device 1130 includes random access memory (RAM) that maintains power during a power gating event. In one embodiment, the non-core storage device 1130 includes 4 KB of RAM, but other sizes are also contemplated.

In operation, power controller 1120 is configured to perform power gating to restore power to one or more cores 1101 or to remove power therefrom. During power up/reset, the reset logic 1105 on each core 1101 is configured to perform the configuration for core 1101 as described above, among other operations. In addition, reset logic 1105 is configured to read configuration data register 1104 to determine if core 1101 is a primary core or a secondary core. If the configuration data refers to The core 1101 is a slave core, and as part of the reset process, waiting from the core until a flash memory repair data indicating decompression for each core 1101 appears on the sync bus SYNC has been taken from the fuse array 1110. The medium core signals in the corresponding sub-storage devices 1131-1134 in the non-core storage device 1130 are read and have been written. After the corresponding sub-storage devices 1131-1134 on SYNC have been written, each slave core reads its corresponding decompressed patch material from the corresponding sub-storage device 1131-1134 and proceeds as described above. Configure the cache on its corresponding core. If the configuration data indicates that the core 1101 is the main core, the main core reads the cache memory correction data of all the cores 1101 from the fuse array 1110 as part of the power-on/reset, and corrects the compression of all the cores 1101. The data is decompressed, and the decompressed cache memory patch data is written to the sub-storage devices 1131-1134 corresponding to each core 1101. The main core then signals the completion of the write of the decompressed cache memory to other cores 1101 on SYNC.

During a power gating event, power control 1120 removes power from one or more cores 1101 such that power is also removed from cache memory 1102 on the core of the core. However, the power source is not removed from the non-core storage device 1130, so that the compressed patch material is known for each core 1101. The sleep logic 1106 is configured to determine when the power is restored to the corresponding core 1101 after the power gating event to directly read the cache memory for the cache memory on its core from its respective child storage device 1131-1134 The material is patched and its corresponding patched data storage device 1103 is configured for correction of the cache memory 1102 on its core, thereby greatly reducing the time required to return to operation after the power gating event At the same time, the life of the fuse array 1110 is obviously increased. Life.

Portions of the present invention and corresponding detailed description are presented in terms of algorithms and symbolic representations of the software in the computer memory, or operations on the data bits. Those skilled in the art will be able to effectively convey the substance of their work to those skilled in the art. Algorithms, as the term is used herein, and as it is commonly used, are considered to be a self-consistent sequence of steps leading to a desired result. The steps are steps that require physical manipulation of physical quantities. Generally, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, digits, and so forth.

However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are only applied to the convenient labels of these quantities. Unless specifically stated otherwise or apparent from the discussion, terms such as "processing" or "calculating" or "determining" or "displaying" refer to a computer system, microprocessor, central processing unit, or similar electronic computing device. Actions and procedures, the device will be represented as physical and electronic data manipulation and conversion in the scratchpad and memory of the computer system to be similarly represented as computer system memory or scratchpad, or other such information Other materials that store, transmit, or display physical quantities within the device.

It should also be noted that in the software implementation of the present invention, it is typically encoded on some form of program storage medium or on some type of transmission medium. Program storage media can be electronic (eg, read-only memory, Flash read-only memory, electrically programmable read-only memory, random access memory), magnetic (for example, floppy or hard), or optical (for example, CD-ROM, or "CD ROM") And it can be read only or randomly accessed. Similarly, the transmission medium can be a metal trace, a twisted pair, a coaxial cable, an optical fiber, or some other suitable transmission medium known in the art. The invention is not limited to these aspects of any given implementation.

The specific embodiments disclosed above are merely exemplary, and those skilled in the art will understand that the present invention can be Various changes, substitutions, and alterations of the invention are possible in the present invention without departing from the scope of the invention as set forth in the appended claims.

310‧‧‧Device Programmer

320‧‧‧Compressor

301‧‧‧Virtual fuse set

302‧‧‧Virtual Fuse

303‧‧‧Virtual Fuse Array

330‧‧‧ grain

332‧‧‧ core

334‧‧‧Cache memory

336‧‧‧Physical fuse array

Claims (15)

An apparatus for providing configuration data to an integrated circuit, the apparatus comprising: a semiconductor fuse array disposed on a die, programming compressed configuration data therein; and a plurality of cores disposed on the die Wherein each of the plurality of cores is coupled to the semiconductor fuse array, and wherein one of the plurality of cores is configured to access the semiconductor fuse after power up/reset The array reads and decompresses the compressed configuration data and stores one or more for each of the plurality of cores in a storage device coupled to each of the plurality of cores a set of decompressed configuration data of the cache memory, each of the plurality of cores including: reset logic configured to employ the decompressed configuration data set to power up/reset Initializing the one or more cache memory memories; and sleep logic configured to determine to restore power after the power gating event and configured to subsequently access the storage Position, and to retrieve said decompressed using the configuration data set, or a plurality of initializing the cache memory after the power gating event. The apparatus for providing configuration data to an integrated circuit according to claim 1, wherein the cache memory fuse element in the one of the plurality of cores is powered on/reset The microcode is executed to decompress the compressed configuration data. The apparatus for providing configuration data to an integrated circuit according to claim 1, wherein each of the decompressed configuration data sets includes a first plurality of semiconductor fuses, the indication being in the one Or one or more subunit locations within the one of the plurality of cache memories, the one or more cache memories not being employed during normal operation. The apparatus for providing configuration data to an integrated circuit as described in claim 3, wherein each of the decompressed configuration data sets further includes a second plurality of semiconductor fuses indicating the one Or one or more substitute subunit locations within one of the plurality of cache memory, the one or more cache memories replacing the one or more subunit locations during normal operation The location will be taken. The apparatus for providing configuration data to an integrated circuit according to claim 4, wherein the subunit position and location in the one of the one or more cache memories The alternate subunit locations include columns and redundant columns, respectively. The apparatus for providing configuration data to an integrated circuit according to claim 4, wherein the subunit position and location in the one of the one or more cache memories The alternate subunit locations include rows and redundant rows, respectively. The apparatus for providing configuration data to an integrated circuit as described in claim 1, wherein the apparatus comprises a multi-core microprocessor. The apparatus for providing configuration data to an integrated circuit according to claim 1, wherein the storage device is configured to store and access a solution. A collection of compressed profiles. A method for configuring an integrated circuit, the method comprising: arranging a semiconductor fuse array on a die, programming a compressed configuration data therein; and arranging a plurality of microprocessor cores on the die, wherein Each of the plurality of microprocessor cores is coupled to the semiconductor fuse array, and wherein one of the plurality of microprocessor cores is configured to access the semiconductor fuse array after power up/reset to compress The configuration data is read and decompressed and stored in a storage device coupled to each of the plurality of cores for decompression of one or more cache memories within each of the plurality of cores Configuring a data set; employing a set of decompressed configuration data via reset logic disposed within each of the plurality of cores to initialize one or more cache memory after power up/reset; And determining, via a sleep logic disposed within each of the plurality of cores, restoring power after the power gating event, and subsequently accessing the storage device to retrieve and retrieve Decompression of configuration data set to initialize one or more cache memory after power gating event. A method for configuring an integrated circuit as described in claim 9, wherein the cache memory fuse element in one of the plurality of cores performs microcode during power up/reset To decompress the compressed configuration data. The method for configuring an integrated circuit according to claim 9, wherein each of the decompressed configuration data sets includes a first plurality of a conductor fuse indicating one or more sub-unit locations within one of the one or more cache memory, the one or more cache memories not being employed during normal operation . The method for configuring an integrated circuit according to claim 11, wherein each of the decompressed configuration data sets further includes a second plurality of semiconductor fuses indicating the one or more Cache one or more substitute subunit locations within one of the memory banks, the one or more cache memory locations replacing the corresponding locations of the one or more subunit locations during normal operation will be use. The method for configuring an integrated circuit according to claim 12, wherein, in one of the one or more cache memories, the subunit position and the substitute subunit position respectively comprise a column And redundant columns. The method for configuring an integrated circuit according to claim 12, wherein, in one of the one or more cache memories, the subunit position and the substitute subunit position respectively comprise a line And redundant lines. The method for configuring an integrated circuit according to claim 12, further comprising: arranging the storage device on a die configured to store and access the decompressed configuration data set.