TWI552068B - Processing device and method for configuration data - Google Patents

Description

Configuration data processing device and method

The present invention relates to a processing apparatus, and more particularly to a processing apparatus and method for providing configuration information to a microprocessor.

The technology of integrated circuits has grown exponentially over the past 40 years. Especially in the field of microprocessors, starting with 4-bit single-instruction, 10 micron devices, the growth of semiconductor manufacturing technology has allowed designers to increase the component density inside composite devices. In pipeline microprocessors and ultra-pure microprocessors in the 1980s and 1990s, millions of transistors were placed in a single die. Over the next 20 years, a 64-bit 32 nm device emerged that placed billions of transistors in a single die with a multi-microprocessor core for processing data.

These early devices need to be initialized by the configuration data when starting or resetting the device. For example, many architectures utilize at least one selectable frequency and/or voltage to enable the device. Other architectures require each device to have a serial number and other information that can be read by executing the instructions. The internal registers and control circuits of other devices require initialization data. When the aforementioned circuit is in error at the time of manufacture or is not in a critical limit, other devices perform additional circuits using the configuration data.

It is well known in the art that designers can store and provide initial configuration data using conventional semiconductor fuse arrays integrated on the die. Partial insurance When the array of dangerous wires has been manufactured, these fuse arrays can be programmed by blowing the selected fuses, and the fuse array has thousands of bits of information. When the device is activated/reset, the fuse can be read. An array for initializing and setting the operation of the corresponding device.

As the complexity of the device increases, so does the amount of configuration data. However, it is well known in the art that although the size of the transistor is reduced with the semiconductor process, the size of the semiconductor fuse integrated on the die is increased. This phenomenon affects the usable space and power loss, and thus becomes a designer's problem. Therefore, if a large fuse array is to be fabricated on a die, the die may not provide sufficient usable space.

In addition, since a certain number of fuses are required for each core, the above problems are aggravated if a large number of cores are to be fabricated on a single die.

Therefore, there is a need for a device and method that allows configuration data to be stored and provided in a multi-core device, and in a single die, does not take up too much space and consumes too much power.

In addition, a fuse array mechanism is needed to store and provide more configuration data than conventional techniques in the same or smaller space.

The present invention utilizes a compressed configuration of a fuse array in a multi-core device to provide a preferred technique for solving the above problems and meeting other problems and disadvantages as well as the limitations of the prior art. In a possible embodiment, the present invention provides a processing device for providing configuration data to a microprocessor and including a fuse array, a cache memory, and at least one core. The fuse array is placed on a die and programmed according to the configuration data. Fuse array includes plural The first semiconductor fuse is configured to store a compressed cache correction data. The cache memory is placed on the die. The core is placed on the die. The core couples the fuse array and the cache memory, and accesses the fuse array under the start/reset operation to decompress the compressed cache correction data and issue a decompressed cache correction data for initialization Cache memory.

The invention further provides a processing device for providing configuration data to a microprocessor and including an array of fuses. The fuse array is disposed on a die and is programmed according to the compression configuration data and includes a plurality of first semiconductor fuses and a plurality of second semiconductor fuses. The first semiconductor fuse is used to store configuration data according to a code compression format. The second semiconductor fuse is used to store a first fuse correction data. The first fuse correction data is used to indicate an address and a value corresponding to at least one first fuse of the first semiconductor fuse that needs to be changed.

The present invention further provides a processing method for providing configuration data to a microprocessor, and including setting a fuse array on a die, the fuse array including a plurality of first semiconductor fuses, and storing a compressed cache correction data In the first semiconductor fuse; at least one core is disposed on the die, wherein the core is coupled to the fuse array and the cache memory; and in the start/reset operation, the core is accessed through the fuse array, and the compressed cache is decompressed Correct the data and issue a decompressed cache correction data to initialize the cache memory.

The present invention further provides a processing method for providing configuration data to a microprocessor, and including setting a fuse array on a die, wherein the setting step includes: storing configuration data in the plurality of first semiconductor fuses, wherein The configuration data is stored in a code compression format; and the first fuse is stored The positive data is in a plurality of second semiconductor fuses, wherein the first fuse correction data is used to indicate an address and a value corresponding to at least one first fuse of the first semiconductor fuse that needs to be changed.

For industrial applications, the invention is applicable to microprocessors that are used in general or special purpose computer devices.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100, 200‧‧‧ squares

101‧‧‧Microprocessor core

102, 201, 336 ‧ ‧ fuse array

103‧‧‧Reset logic

104‧‧‧Reset circuit

105‧‧‧Reset microcode

107‧‧‧Control circuit

108‧‧‧Microcode register

109‧‧‧Microcode Insertion Components

110‧‧‧Cache correction component

RESET‧‧‧Reset signal

202, PFB1~PFBN, RFB1~RFBN‧‧‧Fuse Group

203‧‧‧Fuse

210~211‧‧‧ register

PR1‧‧‧main register

RR1‧‧‧Redundant Register

212‧‧‧Exclusive or logic gate

FB3‧‧‧ output

310‧‧‧ device programmer

320‧‧‧Compressor

301‧‧‧Virtual fuse set

302‧‧‧virtual fuse

330‧‧‧ grain

332, 1002, 1102‧‧ core

334‧‧‧Cache memory

401, 1001, 1101, 1201‧‧‧ physical fuse array

403‧‧‧Compressed microcode insertion fuse

404‧‧‧Compressed register fuse

405‧‧‧Compressed cache correction fuse

406‧‧‧Compressed fuse correction fuse

408‧‧‧Insert fuse element

409‧‧‧Storage fuse element

410‧‧‧Quick Fuse Components

411‧‧‧Fuse correction component

412‧‧‧ busbar

414‧‧‧Microcode Insertion Component

415‧‧‧microcode register

416‧‧‧Cache correction component

417‧‧‧Reset controller

420‧‧‧Microprocessor core

421‧‧Decompressor

500‧‧‧Compressed configuration data

502‧‧‧Compressed data field

503‧‧‧End type field

504‧‧‧End of the melting field

600‧‧‧Uncompressed microcode insertion configuration data

601‧‧‧ core address field

602‧‧‧Microcode ROM address field

603‧‧‧Microcode insertion data field

604‧‧Decompressed data block

700‧‧‧Uncompressed Microcode Register Configuration Data

701‧‧‧Core address field

702‧‧‧Microcode register address field

703‧‧‧Microcode register data field

704‧‧‧Uncompressed data block

800‧‧‧Uncompressed cache correction data

802‧‧‧unit cell address field

803‧‧‧Replacement of the address field

804‧‧‧Uncompressed data box

900‧‧·Uncompressed fuse correction data

901‧‧‧End of the melting field

902‧‧‧ remelting field

903‧‧‧Fuse correction field

1000‧‧‧Multi-core devices

1003, 1103‧‧‧ array control

1004‧‧‧Configuration Data Register

1100‧‧‧ device

1104‧‧‧Load data register

1105‧‧‧Non-core RAM

1200‧‧‧Error confirmation correction mechanism

1202‧‧‧ECC code block

1203‧‧‧Compressed configuration data block

1224‧‧‧ECC components

1226‧‧ decompressor

1220‧‧‧Microprocessor core

1222‧‧‧Reset controller

CDATA‧‧‧ busbar

ADDR‧‧‧ address bus

CODE‧‧‧ code bus

DATA‧‧‧ data bus

300‧‧‧Fuse Array Compression System

303‧‧‧Virtual Fuse Array

400‧‧‧Fuse decompression mechanism

Figure 1 is a schematic illustration of a conventional microprocessor core having a fuse array.

Figure 2 is a schematic diagram of the microprocessor core with redundant fuse sets of Figure 1.

Figure 3 is a schematic illustration of the provision of compression and decompression configuration data to a multi-core device in accordance with the present invention.

Figure 4 is a possible embodiment of a fuse decompression mechanism in accordance with the present invention.

Figure 5 is a schematic diagram of a possible format of the compressed configuration data of the present invention.

Figure 6 is a schematic diagram of a possible format of the decompressed microcode insertion configuration data of the present invention.

Figure 7 is a schematic diagram of a possible format of the decompressed microcode register configuration data of the present invention.

Figure 8 is a schematic diagram of a possible format of the decompressed cache correction data of the present invention.

Figure 9 is a schematic diagram of a possible format of the decompressed fuse correction data of the present invention.

Figure 10 is a possible embodiment of a multi-core device with a configurable redundant fuse array of the present invention.

Figure 11 is a schematic diagram of the mechanism for quickly loading configuration data into a multi-core device of the present invention.

Figure 12 is a possible embodiment of the error confirmation correction mechanism of the present invention.

Integrated circuit (IC) refers to a collection of electronic circuits formed on a small size semiconductor material, such as germanium. An integrated circuit can also be referred to as a wafer, a microchip or a die.

A central processing unit (CPU) is an electronic circuit (ie, a hardware) that executes a data program to execute a computer program (ie, a computer application or an application). The operation of the data includes arithmetic operations and logic. Operation and input/output operations.

Microprocessor refers to an electronic device as a central processing unit on a single integrated circuit. A microprocessor receives the digital data as input, processes the data according to a memory instruction, and produces an operation result required by the output instruction, wherein the memory is set or not disposed on the die. A general purpose microprocessor can be used in desktop, portable or tablet circuits and can be used for computing, word processing, multimedia display and web browsing. A microprocessor may be placed in an embedded system to control a number of devices, including devices, mobile phones, smart phones, and industrial controls.

Multi-core processors are also known as multi-core microprocessors, multi-core The processor is a microprocessor having a plurality of central units (cores) formed on the same integrated circuit.

An instruction set architecture (ISA) or instruction set is a part of a computer architecture that is used to be programmed, including data types, instructions, registers, address patterns, memory architecture, interrupts, exception handling, and input/output. . An ISA includes the characteristics of the set of opcodes (ie, machine language instructions) and local commands used by a particular CPU.

An x86-compatible microprocessor is a microprocessor with a computer-implemented application that can be used to program a computer application based on the x86 ISA.

Microcode refers to a complex microinstruction. A microinstruction (also referred to as a local instruction) is an instruction that can be executed by a microprocessor sub-operational unit. In a possible embodiment, the secondary unit includes an integer arithmetic unit, a floating point arithmetic unit, an MMX arithmetic unit, and a load/store arithmetic unit. For example, microinstructions are directly executed by a reduced instruction set (RISC). For a Complex Instruction Set (CISC) microprocessor (such as an x86 compatible microprocessor), the x86 instructions are translated into combined microinstructions and the combined microinstructions are executed directly by the CISC's microprocessor.

The fuse is a conductor structure, typically a thin wire, which can be blown by applying a voltage to the thin wire and/or causing a current to flow through the thin wire. Using conventional manufacturing techniques, a fuse is deposited at a specific location on a grain topology to create a programmable thin line. After fabrication is complete, the fuse is blown (or not blown) to provide a stylization of a corresponding device on the die.

Please refer to FIG. 1, which is a schematic diagram of the current microprocessor core 101. The microprocessor core 101 has a fuse array 102 for providing configuration information to the microprocessor core 101. Fuse array 102 has multiple semiconductor guarantees Dangerous wire (not shown). Semiconductor fuses are typically arranged in columns. The fuse array 102 is coupled to the reset logic 103. The reset logic 103 includes a reset circuit 104 and a reset microcode 105. The reset logic 103 is coupled to the control circuit 107, the microcode register 108, the microcode insertion component 109, and the cache correction component 110. An external reset signal RESET is coupled to the microprocessor core 101. The reset logic 103 receives the external reset signal RESET.

It is well known to those skilled in the art that after the integrated circuit device is manufactured, a large number of integrated circuit devices use fuses (also referred to as connection or fuse structures) to provide configuration of the integrated circuit. For example, the microprocessor core 101 of FIG. 1 provides a function selection for selection in a desktop device or a portable device. Thus, at the time of manufacture, the fuses in the fuse array 102 may be blown to select a device, such as a portable device. Thus, when the reset signal RESET is enabled, the reset logic 103 reads the state of the specified fuse in the fuse array 102, and the reset circuit 104 (in this example, not resetting the microcode 105) enables the phase Corresponding control circuit 107. The control circuit 107 disables the components of the microprocessor core 101 that are associated with the desktop function and enables the components of the microprocessor core 101 that are associated with the portable function. Thus, the microprocessor core 101 is activated and reset to a portable device. Additionally, the reset logic 103 reads the state of the other fuses in the fuse array 102, and the reset circuit 104 (in this example, not resetting the microcode 105) enables the corresponding cache correction component 110 for At least one cache memory (not shown) of microprocessor core 101 provides a correction mechanism. Therefore, the microprocessor core 101 is activated and reset to a portable device, and the correction mechanism of the cache memory of the microprocessor core 101 is also set.

The above examples are only for the microprocessor core that describes Figure 1. Many different uses of the fuse in 101. Those skilled in the art are well aware of other uses of the fuse and are not limited to the configuration of the device specific data (such as serial number, unique encryption code, authorized data of the internal structure of the computer, which can be accessed by the user, speed setting, Voltage setting), initialization data and insert data. For example, many current devices execute microcode to initialize the microcode register 108. A microcode register fuse (not shown) in fuse array 102 may provide information for initialization by reset logic 103 (reset circuit 104 or reset microcode 105, or reset) during reset operation The circuit 104 and the reset microcode 105) read the initialized data and provide the read initialization data to the microcode register 108. In order to achieve the above object, the reset circuit 104 includes hardware components that provide a specific type of configuration data, and the reset microcode 105 system cannot provide configuration data for these specific types. The reset microcode 105 includes a plurality of microinstructions that are placed in an internal microcode memory (not shown). When the microprocessor core 101 is reset, an internal microcode memory is executed to perform the initialization function of the microprocessor core 101. These functions include reading the configuration data in the fuse array 102 and providing the read result. The plurality of components, such as the microcode register 108 and the microcode insertion mechanism 109. A special setting of the microprocessor core 101 is to determine whether the configuration data of the fuse array is provided to the different components 107-110 of the microprocessor core 101 via the reset microcode 105. The purpose of the present invention is not to initialize the integrated circuit device individually. It is well known to those skilled in the art that the types of configuration elements 107-110 of the current microprocessor core 101 generally fall into four types, as shown in Figure 1. For example, it is a control circuit, a microcode register, a microcode insertion mechanism, and a cache correction mechanism. In addition, those skilled in the art will appreciate that the value of the configuration data is obviously changed depending on the type of the data. For example, a 64-bit control circuit 107 may include ASCII The data, ASCII data is used to specify the serial number of the microprocessor core 101. Other 64-bit control registers may have 64 different speed settings, and only one speed setting will be enabled at a time to control the operating speed of the microprocessor core 101. In general, the microcode register 108 may be initialized to all zeros (ie, low logic states) or all ones (eg, high logic states). The microcode insertion mechanism 109 may include uniformly distributed 1's and 0's to represent the addresses of the microcode values in a microcode ROM (not shown) that need to be replaced, the microcode values of which will be replaced. Finally, the cache correction mechanism may contain very few setpoints 1 to indicate that a certain cache sub-bank component (ie, a column or row) needs to be replaced with a particular replacement sub-group component.

Fuse array 102 provides an excellent function for setting microprocessor core 101 after fabrication of a device, such as microprocessor core 101. By blowing some of the fuses in the fuse array 102, the microprocessor core 101 can be operated in a corresponding environment. However, those skilled in the art are well aware that by programming the fuse array 102, the operating environment of the microprocessor core 101 can be changed. The microprocessor core 101 may be initialized for business needs, such as being initialized by a desktop device into a portable device. Therefore, the designer can set the redundant fuse in the fuse array 102 as a non-blown fuse, so that the configuration of the microprocessor core 101 can be initialized, the manufacturing error can be corrected, and the like. A fuse array with redundant fuses will be described in Figure 2.

Referring to FIG. 2, block 200 shows a fuse array 201 in the microprocessor core 101 having a fuse bank 202 (redundant fuse sets RFB1~RFBN and first fuses PFB1~PFBN). The first fuse sets PFB1~PFBN in the fuse array 201 are blown first, and then the redundant fuses are blown. Group RFB1~RFBN. The redundant fuse sets RFB1~RFBN and PFB1~PFBN include a predetermined number of fuses 203, and the fuses 203 are independent of each other. The number of fuses 203 is related to the specific design of the microprocessor core 101. For example, in a 64-bit microprocessor core 101, the number of fuses 203 of the fuse bank 202 may be 64, in order to facilitate the use of configuration data by the microprocessor core 101.

The fuse array 201 is coupled to the registers 210-211. In general, the registers 210-211 are disposed in the reset logic of the microprocessor core 101. The main register PR1 is used to read one of the first fuse groups PFB1 to PFBN (assumed to be the fuse group PFB3 in the block diagram 200). The redundancy register RR1 is used to read one of the redundant fuse sets RFB1~RFBN. Each of the registers 210 and 211 is coupled to a mutually exclusive or logic gate 212. Mutually exclusive or logic gate 212 provides an output FB3.

In operation, after the microprocessor core 101 is fabricated, the first fuse sets PFB1~PFBN can be programmed by conventional techniques to be configuration data that can be used by the microprocessor core 101. The redundant fuse sets RFB1~RFBN are not blown and are maintained in a low logic state. When the microprocessor core 101 is started/reset, the main register 210 and the redundancy register 211 read the states of the first fuse groups PFB1 to PFBN and the redundant fuse groups RFB1 to RFBN, respectively. The exclusive or logic gate 212 mutually exclusive ORs the data stored in the registers 210 and 211 to generate an output FB3. Since all of the redundant fuse sets are not blown (ie, both are in a low logic state), the value of the output FB3 is simple, that is, the result of the first fuse set PFB1~PFBN being programmed after manufacture.

Currently, information required to be written to the first fuse group PFB1~PFBN can be changed due to design or business requirements. Therefore, in order to change the information read after startup, a programmable operation must be performed to blow the redundant fuse set. Corresponding redundant fuse 203 in RFB1~RFBN. When a fuse 203 in the selected redundant fuse group RFB1~RFBN is blown, a corresponding fuse 203 in the first fuse group PFB1~PFBN is logically matched thereto.

The mechanism of Figure 2 may provide a remelted fuse 203 in the microprocessor core 101, but it is well known in the art that since there is only one set of redundant fuse sets RFB1~RFBN, the redundant fuse sets RFB1~RFBN Each fuse 203 in the fuse can only be re-melted once. In order to provide multiple re-melting, multiple sets of additional fuse sets 202 and registers 210-211 can be added to the microprocessor core 101.

To date, the fuse array mechanism of Figures 1 and 2 provides sufficient flexibility to the microprocessor core and other associated devices to allow for a limited number of remelting. Manufacturing techniques (such as 65 and 45 nm processes) can form enough fuses on the die to set up a microprocessor core 101 on the die. However, current technology is still limited to two distinct factors. The first factor is that the trend in the art is to form multiple microprocessor cores 101 in the same die to increase processing performance. These may be referred to as multi-core devices with 2-16 independent cores 101. To enable/reset core 101, each core is configured with fuse data. Therefore, for a 4-core device, the four fuse arrays 201 will be used in separate cores, and the data for each core may be different (such as cache correction data, redundant fuse data, etc.). Secondly, people in the field are well aware that the manufacturing technology is reduced (such as 32 nm), so the size of the transistor is also reduced, so the size of the fuse is increased, so it is necessary to achieve 45 nanometers on the 32 nm die. The fuse array of meters.

In accordance with the above limitations and other challenges of the device designer, particularly the designer of the multi-core device, the present invention provides significant improvements over conventional ones. The device configuration mechanism, the present invention programs a separate core in a multi-core device and increases the number of cache corrections and fuse reprogramming (remelting). The invention will be described later through Figures 3-12.

Figure 3 is a schematic illustration of a fuse array compression system 300 of the present invention for compressing and decompressing configuration data for a multi-core device. The multi-core device has multiple cores 332. The core 332 is disposed on a die 330. For convenience of explanation, Figure 3 only shows the core CORE1~CORE4. The cores CORE1~CORE4 are disposed on the die 330. In other embodiments, die 330 may have other numbers of cores 332. In this embodiment, all cores 332 share a single cache memory 334. The cache memory 334 is also disposed over the die 330. A single programmable fuse array 336 is also disposed on the die 330, and under start/reset operation, each core 332 is used to access the fuse array 336 for capturing and decompressing configuration data.

In one embodiment, core 332 includes a microprocessor core to form a multi-core microprocessor (die) 330. In other embodiments, multi-core microprocessor 330 acts as an x86 compatible multi-core microprocessor. In other embodiments, the cache memory 334 includes a level 2 cache memory coupled to the microprocessor core 332. In one possible embodiment, fuse array 336 has 8192 (8K) separate fuses (not shown), although other numbers of fuses can be used. In a single core embodiment, only one core 332 is disposed over the die 330, and the core 332 is coupled to the cache memory 334 and the fuse array 336. Although the features and functions of the multi-core device (die) 330 will be described later, the features of the multi-core device are the same as those of the single core.

The fuse array compression system 300 also includes a device programmer 310. The device programmer 310 includes a compressor 320. The compressor 320 is coupled to the virtual fuse Array 303. In one possible embodiment, the device programmer 310 may include a central processing unit (not shown) for processing the configuration data and, after the fabrication of the die 330 is completed, the programmed fuse array is programmed using conventional programming techniques. 336. The central processor may be integrated into a wafer test facility to test the fabricated device die 330. In a possible embodiment, the compressor 320 may have an application program that can be executed on the device programmer 310, and the virtual fuse array 303 may include an address of a memory that is stored by the compressor 320. take. The virtual fuse array 303 has a number of virtual fuse sets 301. Each virtual fuse set 301 has a plurality of virtual fuses 302. In one possible embodiment, virtual fuse array 303 has 128 virtual fuse sets 301, each virtual fuse set 301 having 64 virtual fuses 302, and thus fuse array 303 is 8Kb in size.

Operationally, as shown in FIG. 1, the configuration information of the device 330 is input to the virtual fuse array 330 during the manufacturing phase. Therefore, the configuration information includes the configuration data of the control circuit, the initialization data of the microcode register, the microcode insertion data, and the cache correction data. In addition, as described above, the values of the configuration data of different types are different. The virtual fuse array 303 is a logical representation of a fuse array (not shown) having configuration information for each microprocessor core 332 on the die 330 and each cache memory 334 on the die 330. Correct the data.

After the information is stored in the virtual fuse array 303, the compressor 320 reads the state of the virtual fuse 302 of each virtual fuse group 301, and compresses using the distinct compression algorithms corresponding to each data type. Used to generate compressed fuse array data. In a possible embodiment, the system data of the control circuit is not compressed, but will not be Converted in case of compression. To compress the microcode register data, a microcode register data compression algorithm can be used to compress the data having a state distribution that is relative to the microcode register data. To compress the microcode insertion data, a microcode insertion data compression algorithm can be used to effectively compress the data having a state distribution corresponding to the microcode insertion data. To compress the cache correction data, a cache correction data compression algorithm can be used to effectively compress the data having a state distribution corresponding to the cache correction data.

Next, device programmer 310 programs the uncompressed and compressed fuse array data to physical level fuse array 336 on die 330.

At the start/reset operation, each core 332 may access the physical level fuse array 336 for extracting uncompressed and compressed fuse array data and reset circuitry/microcode within each core 332 ( Not shown) uncompressed fuse array data is released, and the compressed fuse array data is decompressed according to the separate decompression algorithm for each data type to provide the original value originally in the virtual fuse array 303. The reset circuit/microcode then provides configuration information to a control circuit (not shown), a microcode register (not shown), an interposer (not shown), and a cache correction component (not shown).

With the fuse array compression system 300 of the present invention, the device designer can be enabled to reduce the number of fuses in the physical level fuse array 336, and to set up a multi-core device 330 using a compressed information program during the start/reset operation. .

Referring to Figure 4, block 400 shows the fuse decompression mechanism of the present invention. The decompression mechanism may be provided in each of the microprocessor cores 332 of FIG. in. For clarity of the present invention, FIG. 4 shows only a single core 420, but each core 332 on the die of FIG. 3 has elements of core 420 of FIG. The physical level fuse array 401 is disposed on the die and coupled to the core 420. The physical grade fuse array 401 has a compressed microcode insertion fuse 403, a compressed register fuse 404, a compressed cache correction fuse 405, and a compressed fuse correction fuse 406. The physical grade fuse array 401 may also have uncompressed configuration data (not shown), such as the system configuration data described above and/or the Error Checking and Correction (ECC) code (not shown). The ECC feature according to the present invention will be described later.

Microprocessor core 420 includes a reset controller 417. The reset controller 417 receives a reset signal REST, which is used to initialize the core 420, causing the core 420 to perform a reset step. The reset controller 417 has a decompressor 421. The decompressor 421 has an insertion fuse element 408, a register fuse element 409, and a cache fuse element 410. The decompressor 421 also includes a fuse correction component 411 coupled through the bus bar 412 to the fuse element 408, the register fuse element 409, and the cache fuse element 410. The insertion fuse element 408 is coupled to the microcode insertion element 414 within the core 420. The register fuse element 409 is coupled to the microcode register 415 in the core 420. The cache fuse element 410 is coupled to the cache correction component 416 within the core 420. In one possible embodiment, the cache correction component 416 is disposed on a die having a secondary (L2) cache (not shown). All cores 420 share a cache correction component 416, such as cache memory 334 of FIG. In another embodiment, the cache correction component 416 is disposed on a die having a level one (L1) cache (not shown). In other embodiments, the cache correction component 416 is provided with one level (L1) and two level (L2) cache memories (not shown) Show) on the die.

In operation, when the reset signal RESET is enabled, the reset controller 417 reads the states of the fuses 403-406 in the physical-stage fuse array 401 and provides a state of the compressed system fuse (not shown). Compressor 421. After reading and providing, the fuse correction component 411 in the decompressor 421 decompresses the state of the compressed fuse correction fuse 406 for providing information indicative of at least one fuse address of the physical level fuse array 401, This state that has been previously programmed will be changed. The decompressed data may contain values for at least one fuse address. The at least one fuse address (and random value) is transmitted through bus bar 412 to components 408-410 such that the state of the corresponding fuse is changed before being decompressed.

In a possible embodiment, the inserted fuse element 408 includes microcode for decompressing the state of the compressed microcode inserted into the fuse 403 according to a microcode insertion decompression algorithm, and the microcode insertion decompression algorithm corresponds to The microcode insertion compression algorithm described in FIG. 3 is inserted. In a possible embodiment, the register fuse element 409 includes microcode for decompressing the compressed register fuse 404 according to a register fuse decompression algorithm, and the register fuse decompression algorithm corresponds to The register fuse compression algorithm described in Figure 3. In a possible embodiment, the cache fuse element 410 includes microcode for decompressing the compressed cache correction fuse 405 according to a cache correction fuse decompression algorithm, and the cache correction fuse decompression algorithm corresponds to The cache correction compression algorithm described in Figure 3. The fuse correction component 411 provides the address of the fuse through the bus bar 412. Each of the components 408-410 changes the state of the corresponding fuse according to the addresses, and then decompresses the respective fuses according to the corresponding algorithm. data. The multiple remelting fuse of the present invention will be described in detail later, and the remelting step is earlier than the initialization of the decompression action of the components 408-411. In a possible embodiment, bus 412 may include a conventional microcode programming mechanism for transmitting data. The invention further has a comprehensive decompressor 421 which can distinguish and decompress the configuration data according to the type of the configuration data. Thus, for purposes of illustrating the present invention, decompressor 421 has only elements 408-411, however, as long as condensation decompressor 421 can provide the functionality of elements 408-411, elements 408-411 may not be required by the present invention.

In a possible embodiment, the reset controller 417 initializes the microcode inserted into the fuse element 408 for decompressing the compressed microcode insert fuse 403. The reset controller 417 also initializes the microcode of the scratchpad fuse element 409 for decompressing the state of the compressed scratchpad fuse 404. Moreover, the reset controller 417 further initializes the microcode of the cache fuse element 410 for decompressing the compressed cache correction fuse 405. Prior to decompression, the microcode of decompressor 421 first changes the state of certain fuses, which are the fuses specified by the fuse correction data for the compressed fuse correction fuse 406.

The reset controller 417, the decompressor 421, and the components 408-411 are used to perform the functions described above. Reset controller 417, decompressor 421, and components 408-411 may include logic, circuitry, devices, or microcode, or a combination of logic, circuitry, devices, or microcode, or equivalent components that perform the functions and operations described above. . The components for implementing the reset controller 417, the decompressor 421, and the components 408-411 may be shared by other circuits, microcodes, etc., which may execute the reset controller 417, the decompressor 421, and the component 408~ Other functions and/or operations of 411 or other components in core 420.

After changing and decompressing the states of the fuses 403-406 in the physical-grade fuse array 401, the state of the decompressed virtual fuse is provided to the microcode insertion component 414, the microcode register 415, and the cache correction component 416. . Therefore, the core 420 performs the next reset operation.

In other embodiments, the decompression functions described above are not required to be performed in a particular order when performing a reset operation. For example, the decompression action of the microcode insertion data may be after the decompression action of the microcode register initialization data. As such, in other embodiments, the decompression function may be performed simultaneously to meet design requirements.

In addition, the implementation of the elements 408-411 of the present invention does not necessarily require the use of microcode corresponding to the hardware circuit. Since in the general microprocessor core 420, it has some components that can be more easily penetrated through the hardware. Initialization (such as a scan chain associated with a cache), rather than direct write microcode. The implementation details of these are at the discretion of the designer. However, in the reset operation prior to initializing the microcode, the prior art utilizes a hardware circuit that causes the cache correction fuse to be read by convention and into a cache correction scan chain. Unless the microcode begins to operate, the core cache memory is not turned on. Therefore, the feature of the present invention utilizes the microcode corresponding to the hardware control circuitry to execute the cache fuse decompressor 410. By executing the cache fuse element 410 with microcode, the cache correction data can be written into a scan chain, and the hardware components are significantly saved, thereby increasing design flexibility and beneficial mechanisms.

Please refer to FIG. 5, which shows the format of the compressed configuration data 500 of the present invention. The compressor 320 of FIG. 3 compresses the data of the virtual fuse array 330 and programs (ie, blows) the compressed configuration data 500 to the physical level of the multi-core device 330. In the fuse array 336. In the reset result described above, the compressed configuration data 500 is retrieved from the physical level fuse array 336 by each core 332 and decompressed and decompressed by the components of the decompressor 421 of each core 420. Corrected by 408~411. The decompressed and corrected configuration data is then provided to the multi-element 414-416 of core 420 for initializing core 420.

The compressed configuration data 500 has at least one compressed data field (D) 502, and each of the configuration data types described above is separated by an End Type Field (ET) 503. Stylized events (ie, blown) are separated by an end blow field (EB) 504. According to a compression algorithm, a compressed data field 502 associated with each data type is encoded to minimize the number of bits (ie, fuses) used to store the feature bits associated with each data type. Meta pattern. The number of fuses of the physical level fuse array 336 that make up each compressed data field 502 is characteristic of the compression algorithm used by a particular data type. For example, considering that a core has a 64-bit microcode scratchpad, it must all be initialized to 0 or 1. An optimal compression algorithm may provide 64 compressed data fields 502 according to the data type. Each compressed data field 502 has initialization data of a specific microcode register, and the compressed data field 502 is designated. The number of registers is in the order (ie 1-64). And each compressed data field 502 has a single fuse. If a corresponding microcode register needs to be initialized to 1, the single fuse is blown, if the corresponding microcode register needs to be initialized to 0. When the single fuse is not blown.

After the initial stylization event, elements 408-410 of decompressor 421 in core 420 use end type field 503 to determine if their respective compressed data has been placed in physical level fuse array 336, and fuse correction is decompressed. The device 411 uses the end fuse fuse 504 to find the compression fuse correction data. The compression fuse correction data has been programmed (ie, blown) after an initialization program event. The present invention provides a large number of spare fuses in the physical level fuse array 336 for subsequent multi-program events, as will be described in more detail below.

The above compression type format is used to illustrate the compression and decompression of the configuration data of the present invention. However, the compression, separation, and compression of the particular type of data shown in FIG. 5 into the fuse array 401 are not intended to limit the invention. In other embodiments, the invention may be modified in other quantities, types, and formats to yield different devices and algorithms.

Please refer to FIG. 6, which shows a possible format of the decompressed microcode insertion configuration material 600 in accordance with the present invention. Under the reset operation, each core 420 reads the compressed microcode insertion configuration data in the physical level fuse array 401. Then, according to the fuse correction data provided by the bus bar 412, the compressed microcode insertion configuration data is corrected. The corrected compressed microcode insertion configuration data is then decompressed by inserting the fuse decompressor 408. The result of the decompression program is the decompressed microcode insertion configuration data 600. The data 600 includes a complex decompressed data block 604. The number of decompressed data blocks 604 corresponds to the number of microcode insertion elements 414 in the core 420 that need to be initialized. Each decompressed data block 604 includes a core address field 601, a microcode memory (ROM) address field 602, and a microcode insertion data field 603. The length of the fields 601~603 is a feature of the core algorithm. When a partial decompression procedure is performed, a complete image of the target material provided by fuse element 408 is inserted for initializing microcode insertion component 414. In the subsequent decompression of the microcode insertion configuration data 600, it is possible to use a conventional distribution mechanism for distributing the data 603 to the respective address core and the microcode ROM replacement circuit/scratch in the microcode insertion component 414. Device.

Please refer to FIG. 7. FIG. 7 shows the format of the decompressed microcode register configuration data 700 in accordance with the present invention. In the reset operation, the compressed microcode register configuration data in the physical level fuse array 401 is read by each core 420. The compressed microcode register configuration data is then corrected based on the fuse correction data provided by the bus bar 412. The register fuse element 409 then decompresses the corrected compressed microcode register configuration data. The result of the decompressor is the decompressed microcode register configuration data 700. The data 700 includes a complex decompression data block 704, the number of decompressed data blocks 704 corresponding to the number of microcode registers 415 in the core 420 that require initial data. Each decompressed data block 704 has a core address field 701, a microcode register address field 702, and a microcode register data field 703. The length of the fields 701~703 is a feature of the core algorithm. The buffer fuse element provides a complete image of the target data for initializing the microcode register 415 during a partial decompression process. In the subsequent decompression of the microcode register configuration data 700, a conventional publishing mechanism may be used to publish the data 703 to the respective address cores and the microcode registers 415.

Please refer to FIG. 8. FIG. 8 shows a possible format of the decompressed cache correction data 800 in accordance with the present invention. In the reset operation, the compressed cache correction data of the physical stage fuse array 401 is read by each core 420. Then, the compression cache correction data is corrected based on the fuse correction data provided by the bus bar 412. Next, the compression fuse correction data is decompressed by the cache fuse element 410. The result of the decompression program is the decompressed cache correction data 800. The fuse array compression system 300 uses different cache mechanisms, and the decompressed cache correction data 800 is present in the shared secondary cache memory 334. All cores 332 may access the same cache memory 334 to use the same storage space. Therefore, Figure 8 The format shown is based on the algorithm described above. The data 800 includes a complex decompressed data block 804, the number of decompressed data blocks 804 corresponding to the number of cache correction elements 416 in the core 420 that require correction data. Each decompressed data block 804 has a primary row address field 802 and a replacement row address field 803. It is well known in the art that when manufacturing a cache memory, redundant rows (or columns) are formed in the secondary unit of the cache memory to utilize a non-functional row (or column). Replaces functional redundant rows (or columns) in a particular subunit. Thus, decompressing the cache correction data 800 allows non-functional lines to replace the functional lines (as shown in Figure 8). In addition, it is well known to those skilled in the art that when it is desired to replace with a redundant sub-cell row, it is conventional that the fuse of each cell row having the fuse array mechanism of the cache correction is blown. Therefore, since a large number of fuses are required (to access all of the sub-units and rows), only a part of the sub-units can be included, so that the conventional cache correction fuse is rarely blown. The invention is characterized by accessing and compressing the address of the secondary unit row and replacing the row address for the secondary unit row that needs to be replaced. Therefore, the number of fuses applied to the cache correction data is minimized. Therefore, the present invention extends the number of sub-cell rows (or columns) of the cache memory 334 under the constraints of the size of the physical-level fuse array and the amount of additional programmed data, and the cache memory 334 can be corrected. . In the embodiment illustrated in FIG. 8, associated core 332 shares secondary cache memory 334 for accessing and providing correction data 802-803 to respective cache correction elements 416. The length of the fields 801~803 is a feature of the core algorithm. In the portion of the decompression procedure, the cache correction fuse element 410 provides a complete image of the target data, and the target data is used to initialize the cache correction component 416. After decompressing the cache correction data 800, the conventional release mechanism in the responsible core 420 may issue the data 802~803 to the accessed cache. Correction element 416.

Please refer to FIG. 9. FIG. 9 shows a possible format of the decompressed fuse correction data 900 of the present invention. As described above, upon reset, the fuse correction component 411 accesses the compression fuse correction data 406 in the physical stage fuse array 401, decompresses the compression fuse correction data, and provides decompressed fuse correction data 900 to the core 420. Element 408~410. The decompressed fuse correction data has at least one End Fuse Field (EB) 901 indicating that the stylized event in the physical level fuse array 401 has successfully completed. If a stylized event occurs, a reflow field (R) 902 is stylized to indicate the subsequent at least one fuse correction field (FC) 903, which indicates that the fuse in the physical class fuse array 401 will again It is blown. Each fuse correction field has the address of a particular fuse in the physical level fuse array 401, and the particular fuse is again set to a state (ie, blown or not blown). Only the fuses in the fuse correction block field 903 will be set again, and each field 903 of the reset event will be separated by an end fuse field 901. If the remelting field 902 is successfully encoded after a particular end fuse field 901, the field is corrected according to the corresponding fuse, and then at least the fuse may be blown again. Thus, the present invention can be used to set the same fuse multiple times in a defined fuse array size and data that can be provided by the array.

For additional features on a multi-core die, the present invention shares a physical-level fuse array with compressed configuration data to provide actual characteristics and power gain. Additionally, those skilled in the art are well aware that current semiconductor fuse structures often have some drawbacks, one of which is "growback." Long back is the reversal of the stylized program, such as a fuse is blown After a period of time, the connection is resumed, that is, from a program state (ie, blown) back to an unprogrammed state (ie, not blown).

In order to control long return and other challenges, the present invention has many advantages, one of which is to provide a redundant, unconfigured physical level fuse array. Thus, Figure 11 provides a configurable redundant fuse bank mechanism.

Please refer to FIG. 10, which shows a possible embodiment of a physical level fuse array 1001 of a multi-core device 1000 in accordance with the present invention. Multi-core device 1000 includes a plurality of cores 1002, the features of which are disclosed in Figures 3-10 and related description. Additionally, each core 1002 includes an array control 1003 that is programmed according to configuration data in the configuration data register 1004. Each array control 1003 is coupled to a redundant fuse array 1001.

For the purpose of illustrating the invention, FIG. 10 shows only four cores 1002 and two physical level fuse arrays 1001, but is not intended to limit the invention. In other embodiments, other numbers of cores may be used in accordance with the disclosure of the present invention. 1002 and physical class fuse array 1001.

In operation, each physical stage fuse array 1001 receives configuration data from the configuration data register 1004, which represents a particular configuration of the physical level fuse array 1001. In one embodiment, the physical level fuse array 1001 acts as an aggregate physical level fuse array based on the value of the configuration data. The size of the aggregated physical-level fuse array is equal to the size of the respective physical-grade fuse array 1001, and the aggregated physical-level fuse array may be used to store the next multiple configuration data, which stores more data than a single physical-grade fuse. The amount of data stored in array 1001. Thus, array control 1003 controls the corresponding core 1002 for reading physical level fuse array 1001, such as an aggregate physical level fuse array. In other embodiments, to control the long return, the physical level fuse array 1001 acts as a redundant fuse array based on the value of the configuration data, which is programmed with the same configuration data, and array control in each core 1002 The 1003 has a number of components for OR logic of the contents of the two (or more) arrays, so that if at least one of the fuses of the array 1001 is prolonged, at least one other corresponding fuse in the array 1001 remains fused. status. In a fail-safe embodiment, at least one physical-level fuse array 1001 is selectively disabled based on the value of the configuration data, and the remaining array 1001 is enabled for use as an aggregate configuration or an OR logical group state. Thus, the array control 1003 in each core 1002 does not access the contents of the disabled array 1001, but accesses the enabled redundant array, based on a particular configuration data in the configuration data register 1004.

The configuration data register 1004 can be programmed by any conventional device having a programmable fuse, an external pin setting, a JTAG program, or the like.

In another embodiment, the present invention finds that when at least one physical level fuse array is placed on a single die having multiple cores, problems can occur when the core accesses the array. Specifically, under the start/reset operation, each core in the multi-core processor must read the physical-level fuse array according to a serial direction. First, the first core reads the array, then the second core reads the array, then the third core reads the array, and so on. It is well known to those skilled in the art that the reading of the fuse array is the most time consuming compared to other operations performed by the core, so when many cores have to read the same array, the time required is roughly a core The read time is multiplied by the number of cores on the die. It is well known in the art that in order to obtain reliable results, it is necessary to read these fuses, but According to the manufacturing process, the number of semiconductor fuses read and the impact of life will affect the quality of semiconductor fuses. Thus, in other embodiments, the present invention reduces the time it takes for the core of the towel to read the physical-level fuse array and increases the number of accesses to the core of the multi-core processor during startup and reset operations to increase the retention The life of the array.

Please refer to FIG. 11, which shows a schematic diagram of the mechanism for quickly loading configuration data into the multi-core device 1100 in accordance with the present invention. Apparatus 1100 has a plurality of cores 1102, the characteristics of which are described in the related description of Figures 3-10. In addition, each core 1102 has an array control 1103 that is programmed by a load data loaded into the data register 1104. Each core 1102 is coupled to a physical stage fuse 1101, which is characterized by the associated description of Figures 3-10. Each core 1102 is coupled to a random access memory (RAM) 1105 that is disposed on the same die as the core 1102 but cannot be disposed in the core 1102. Therefore, the RAM 1105 is referred to as a non-core RAM 1105.

For convenience of explanation, FIG. 11 shows only the quad core 1102 and a physical fuse array 1101, but is not intended to limit the present invention. In other embodiments, it may be extended to any number of cores 1101 and a plurality of physical level fuse arrays 1101.

In operation, each core receives the load data loaded into the data register 1104, which represents a particular load profile relative to the physical level fuse array 1101. The content value of the load data register 1104 specifies a core 1102 as the primary core 1102, while the other remaining cores are referred to as the secondary core 1102, which has a load order. Thus, under the start/reset operation, array control 1103 causes main core 1102 to read the contents of physical level fuse array 1101 and then write the contents of physical level fuse array 1101 to non-core RAM 1105. If multiple physical level fuse arrays 1101 are set On the die, the capacity of the non-core RAM 1105 must be capable of storing data for all physical level fuse arrays 1101. After the main core 1102 stores the contents of the physical-level fuse array 1101 in the non-core RAM 1105, the array control 1103 causes the corresponding secondary core 1102 to read the specific content loaded into the data register 1104 in the non-core RAM 1105.

Conventional programmable fuses, external pin settings, JTAG programs, or other related devices can be programmed into the data register 1104. The embodiment shown in Fig. 11 can also be integrated in the redundant fuse array mechanism described in Fig. 10.

Please refer to Fig. 12, which shows a possible embodiment of an error confirmation correction (ECC) mechanism in accordance with the present invention. The error confirmation correction mechanism 1200 can be integrated in the embodiment of Figures 3-11 and enhances the compression and decompression of the configuration data. Figure 12 depicts a microprocessor core 1220 disposed over a die and coupled to a physical stage fuse array 1201. The physical level fuse array 1201 includes a compressed configuration data block 1203. The compressed configuration data block is as described above. To compress configuration data block 1203, physical level fuse array 1201 has an ECC code block 1202. Each ECC code block 1202 is associated with a corresponding data block 1203. In one possible embodiment, data block 1203 has 64 bits (ie, 64 fuses) and ECC code block 1202 has 8 bits (ie, 8 fuses). The core 1220 has a reset controller 1222 that receives a reset signal RESET. The reset controller 1222 has an ECC element 1224 coupled to a decompressor 1226 via a bus bar CDATA. The ECC component 1224 is coupled to the fuse array 1201 through an address bus ADDR, a data bus DATA, and a code bus CODE.

In operation, as described in Figures 3-11, the fuse array 1201 It will be programmed by the configuration data of data block 1203. A specific data block 1203 or a configuration data spanning a specific data type (such as microcode insertion data, microcode register data) corresponding to multiple data blocks 1203 is not programmed. In addition, configuration data relative to more than two data types may be programmed into the same data block 1203. Additionally, the ECC code in block ECC code 1202 is programmed to array 1201. According to the conventional ECC mechanism, the ECC code is programmed to a corresponding data block 1203, but is not intended to limit the invention. In other embodiments, changes in the SECDED Hamming code, Chipkill ECC, or Pre-Error Correction (FEC) code may also be used. In a possible embodiment, the address associated with data block 1203 and its corresponding ECC code block 1202 are well known. Therefore, the corresponding ECC code block 1202 of the adjacent data block 1203 in Figure 12 is not required.

The structure and function of the decompressor 1226 are substantially the same as those of the decompressor 421 shown in Fig. 4, and have been slightly described in Figs. 5-11. Upon resetting the core 1220, the ECC component in the reset controller 1222 accesses the fuse array to retrieve its contents prior to performing the decompression function described above. Through the bus ADDR, it is possible to obtain the address of the data block 1203 and the ECC code block 1202. The configuration data in the compressed data block 1203 can be obtained through the bus DATA. The ECC code in each ECC code block 1202 is obtained through the bus CODE. After obtaining the data, the address and the code, the ECC component 1224 generates an ECC confirmation for the data retrieved by each data block 1202 according to the ECC mechanism, and the ECC mechanism is used to generate the ECC code, and the ECC code is stored in the corresponding ECC code block 1202. The ECC component 1224 also compares the ECC confirmation with the corresponding ECC code of the array 1201 for generating an ECC syndrome. The ECC component 1224 further decodes the ECC syndrome to determine if there is no An error occurred, a correctable error occurred, or an uncorrectable error occurred. The ECC component 1224 is also used to correct for correctable errors. The uncorrected and corrected data is provided to the decompressor 1226 by bus bar CDATA for performing the decompression operation described above. Uncorrectable errors are provided to decompressor 1226 by bus CDATA. If the critical portion of the operation of the configuration data is judged to be uncorrectable, the decompressor 1226 may cause the core 1220 to be turned off or otherwise flagged.

In a possible embodiment, the ECC component 124 includes at least one microcode program for performing the ECC functions described above.

The software or algorithms and symbols provided by the present invention and corresponding descriptions represent the operation of data bits in a computer memory. These and the illustrations will enable those skilled in the art to effectively express the relevant content to those skilled in the art. The algorithm described above is used to express a self-consistent order. These steps require physical level operations of physical quantities. Generally, these physical quantities may be optical, electrical or magnetic numbers that can be stored, converted, integrated, compared, and otherwise manipulated. For convenience, these signals are referred to as bits, values, components, symbols, characteristics, items, quantities, or other related content.

However, it should be noted that these similar terms are related to physical quantities and are merely used to facilitate the description of these physical quantities. Unless otherwise stated, the above terms (such as processing, estimating, calculating, judging, displaying, or other related terms) refer to the actions of a computer system, a microprocessor, a central processing unit, or a similar electronic computer device. And processing, which operates and converts data, which represents physicality, the number of registers of the computer system, and the amount of memory used to obtain memory, scratchpads, or other similar information storage devices, or displays of other similar computer systems. Information on the physical quantity of the device.

It should be noted that the method of implementing the software of the present invention encodes on a program storage medium or other similar type of transmission medium. The program storage medium may be electronic (such as read-only memory, flash-read only memory, electronic erased read-only memory), random access memory magnetic device (such as a floppy disk or a hard disk) or optical (such as CD-ROM memory CD ROM), and other read-only or random access components. Likewise, the transmission medium may be a metal wire, a twisted pair cable, a coaxial cable, an optical fiber, or other conventionally similar transmission medium. The invention is not limited to these embodiments.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1000‧‧‧Multi-core devices

1001‧‧‧Physical Grade Fuse Array

1002‧‧‧ core

1003‧‧‧Array control

1004‧‧‧Configuration Data Register

Claims (44)

A processing device for providing configuration data to a microprocessor, the processing device comprising: an array of fuses disposed on a die and programmed according to the configuration data, the fuse array comprising: a plurality of a semiconductor fuse for storing a compressed cache correction data; and a plurality of second semiconductor fuses for storing a compressed fuse correction data indicating the corresponding requirements of the first semiconductor fuses Changing the address and value of at least one fuse of the state; a cache memory disposed on the die; and at least one core disposed on the die, wherein the at least one core is coupled to the fuse array and the fast Taking the memory, and in the start/reset operation, accessing the fuse array to decompress the compressed cache correction data, and releasing a decompressed cache correction data for initializing the cache memory The at least one core further includes: a cache fuse decompressor, changing a state of the at least one fuse according to the address and the value, for solving The compressed cache correction data is compressed, and the decompressed cache correction data is released for initializing the cache memory. The processing device of claim 1, wherein the at least one core decompresses the compressed cache correction data by performing microcode during a start/reset operation. The processing device of claim 1, wherein the fuse array further comprises a plurality of second semiconductor fuses, the second semiconductor fuses indicating The address of at least one unit of the cache memory, the normal unit is not used at least once. The processing device of claim 3, wherein the fuse array further comprises a plurality of third semiconductor fuses, the third semiconductor fuses indicating addresses of at least one replacement sub-unit in the cache, in normal operation Next, the replacement subunit does not replace the at least one unit. The processing device of claim 4, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of lines of the cache memory and a plurality of redundant lines. The processing device of claim 4, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of columns and a plurality of redundant columns of the cache. The processing device of claim 1, wherein the microprocessor comprises an x86 compatible single or multi-core microprocessor. The processing device of claim 1, wherein the cache fuse decompressor decompresses the compressed cache correction data by performing microcode during a start/reset operation. A processing device for providing configuration data to a microprocessor, the processing device comprising: an array of fuses disposed on a die and programmed according to the configuration data, the fuse array including a plurality of first a semiconductor fuse for storing a compressed cache correction data; a cache memory disposed on the die; and at least one core disposed on the die, wherein the at least one core is coupled to the security a fuse array and the cache memory, and in the start/reset operation, accessing the fuse array to decompress the compressed cache correction data and issue a decompressed cache correction data for Initializing the cache memory, wherein the fuse array further includes a plurality of second semiconductor fuses, the second semiconductor fuses indicating an address of at least one unit in the cache memory, and the normal unit does not used. The processing device of claim 9, wherein the fuse array further comprises a plurality of third semiconductor fuses, the third semiconductor fuses indicating an address of at least one replacement sub-unit in the cache, in normal operation Next, the replacement subunit does not replace the at least one unit. The processing device of claim 10, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of lines of the cache memory and a plurality of redundant lines. The processing device of claim 10, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of columns and a plurality of redundant columns of the cache memory. A processing method for providing configuration information to a microprocessor includes: providing a fuse array on a die, the fuse array including a plurality of first semiconductor fuses, and storing a compressed cache correction data at the a first semiconductor fuse; a cache memory is disposed on the die; at least one core is disposed on the die, wherein the at least one core is coupled to the fuse array and the cache memory; during startup/reset Operating, accessing the fuse array through the at least one core, Decompressing the compressed cache correction data and issuing a decompressed cache correction data for initializing the cache memory; storing a fuse correction data in a plurality of second semiconductor fuses of the fuse array, wherein the fuse Correcting data indicating address and value of at least one fuse corresponding to the state change in the first semiconductor fuse; and a cache fuse decompressor passing through the at least one core, and changing according to the address and the value The state of the at least one fuse is used to decompress the compressed cache correction data, and the decompressed cache correction data is issued to initialize the cache memory. The processing method of claim 13, wherein the at least one core decompresses the compressed cache correction data by performing microcode under a start/reset operation. The processing method of claim 13, wherein the fuse array further comprises a plurality of second semiconductor fuses, the second semiconductor fuses indicating an address of at least one unit in the cache memory, under normal operation, The at least one unit will not be used. The processing method of claim 15, wherein the fuse array further comprises a plurality of third semiconductor fuses, the third semiconductor fuses indicating addresses of at least one replacement sub-unit in the cache, in normal operation Next, the at least one replacement sub-unit does not replace the at least one unit. The processing method of claim 16, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of lines and a plurality of redundant lines of the cache memory. The processing method of claim 16, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a complex column and a complex redundancy column of the cache memory. The processing method of claim 13, wherein the microprocessor comprises an x86 compatible single core or multi-core microprocessor. The processing method of claim 13, wherein the cache fuse decompressor decompresses the compressed cache correction data by performing microcode during a start/reset operation. A processing method for providing configuration information to a microprocessor includes: providing a fuse array on a die, the fuse array including a plurality of first semiconductor fuses, and storing a compressed cache correction data at the a first semiconductor fuse; a cache memory is disposed on the die; at least one core is disposed on the die, wherein the at least one core is coupled to the fuse array and the cache memory; and at startup/heavy And operating the fuse array through the at least one core, decompressing the compressed cache correction data, and releasing a decompressed cache correction data for initializing the cache memory, wherein the fuse array is further A plurality of second semiconductor fuses are included, the second semiconductor fuses indicating an address of at least one unit in the cache memory, and the normal unit is not used at least once in normal operation. The processing method of claim 21, wherein the fuse array further comprises a plurality of third semiconductor fuses, the third semiconductor fuses indicating addresses of at least one replacement sub-unit in the cache, in normal operation In this case, the at least one replacement subunit does not replace the at least one unit. The processing method of claim 22, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a plurality of lines and a plurality of redundant lines of the cache memory. The processing method of claim 22, wherein the address of the at least one unit and the address of the at least one replacement unit respectively comprise a complex column and a complex redundancy column of the cache memory. A processing device for providing configuration data to a microprocessor, the processing device comprising: an array of fuses disposed on a die and programmed according to a compressed configuration data, the fuse array comprising: a plurality of first semiconductor fuses for storing the configuration data according to a code compression format; a plurality of second semiconductor fuses for storing a first fuse correction data, the first fuse correction data for indicating corresponding to the first An address and a value of at least one first fuse in a semiconductor fuse that needs to be changed; and at least one core disposed on the die, wherein the at least one core is coupled to the fuse array and is in a start/reset operation Accessing the compressed configuration data and the first fuse correction data, and changing a state of the configuration data corresponding to the at least one first fuse, and initializing the plurality of components in the at least one core, wherein the at least one The core includes a fuse correction decompressor for decompressing the first fuse correction data and issuing the decompressed first protection Risk correction data to other decompressors for decompressing the group Before the state information, the state of the at least one first fuse is changed. The processing device of claim 25, wherein the at least one core sets a state of the configuration data corresponding to the address of the at least one first fuse according to the value of the at least one first fuse, To change the state of the configuration data. The processing device of claim 25, wherein the other decompressors set a state corresponding to the address of the at least one first fuse according to the value of the at least one first fuse, to change the at least The state of a first fuse. The processing device of claim 25, wherein the first semiconductor fuses comprise a plurality of second fuses, the second fuses being programmed to separate the end of the configuration data. The processing device of claim 25, wherein the second semiconductor fuse comprises a plurality of second fuses and a plurality of third fuses, the second fuses being programmed to separate the first fuse correction data Initially, the third fuses are programmed to separate the end of the first fuse correction data. A processing device for providing configuration data to a microprocessor, the processing device comprising: an array of fuses disposed on a die and programmed according to a compressed configuration data, the fuse array comprising: a plurality of first semiconductor fuses for storing the configuration data according to a code compression format; and a plurality of second semiconductor fuses for storing a first fuse correction data The first fuse correction data is used to indicate an address and a value corresponding to at least one first fuse in the first semiconductor fuse that needs to be changed, wherein the first semiconductor fuse includes a plurality of second fuses, and the second The fuse is programmed to separate the end of the configuration data. A processing device for providing configuration data to a microprocessor, the processing device comprising: an array of fuses disposed on a die and programmed according to a compressed configuration data, the fuse array comprising: a plurality of first semiconductor fuses for storing the configuration data according to a code compression format; and a plurality of second semiconductor fuses for storing a first fuse correction data, the first fuse correction data for indicating corresponding to the The first semiconductor fuse needs to change the address and the value of the at least one first fuse, wherein the fuse array further includes: a plurality of third semiconductor fuses for storing a second fuse correction data, the second fuse correction data To indicate an address and a value corresponding to at least one second fuse of the first and second semiconductor fuses that need to be changed. The processing device of claim 31, further comprising: at least one core disposed on the die, the at least one core coupled to the fuse array, and accessing the compressed under the start/reset operation The configuration data, the first and second fuse correction data, and changing the state of the configuration data corresponding to the at least one first fuse and the at least one second fuse, and initializing the at least one core plurality of components. The processing device of claim 32, wherein the at least one core sets a state of the configuration data corresponding to the address of the at least one first fuse according to the value of the at least one first fuse, And changing the state of the configuration data; and setting a state of the configuration data corresponding to the address of the at least one second fuse according to the value of the at least one second fuse, for changing the state of the configuration data . The processing device of claim 31, wherein the third semiconductor fuse further comprises a plurality of third fuses and a plurality of fourth fuses, the third fuses being programmed to separate the second fuse correction data At the beginning, the fourth fuses are programmed to separate the end of the second fuse correction data. The processing device of claim 31, further comprising: a fuse correction decompressor for decompressing the first and second fuse correction data, and releasing a decompressed first and the first The second fuse correction data is supplied to the other decompressors for changing the state of the at least one first and second fuses before the other decompressors decompress the configuration data. The processing device of claim 35, wherein the other decompressors respectively set the at least one first fuse and the at least one according to the value of the at least one first fuse and the at least one second fuse a state of the address of a second fuse for changing the state of the at least one first and second fuses. A processing method for providing configuration data to a microprocessor, comprising: setting a fuse array on a die, wherein the setting step comprises: storing a compressed configuration data in the plurality of first semiconductor fuses, wherein The configuration data is stored in a code compression format; the first fuse correction data is stored in the plurality of second semiconductor fuses, wherein the first fuse correction data is used to indicate at least a state of the first semiconductor fuse that needs to be changed. Address and value of a first fuse; and storing second fuse correction data in a plurality of third semiconductor fuses, the second fuse correction data indicating that a change in state of the first and second semiconductor fuses is required The address and value of at least one second fuse. The processing method of claim 37, further comprising: disposing at least one core on the die, wherein the at least one core is coupled to the fuse array, and accessing the compressed under the start/reset operation The configuration data and the first fuse correction data, and changing the state of the configuration data corresponding to the at least one first fuse, and initializing the plurality of components in the at least one core. The processing method of claim 38, wherein the at least one core sets a state of the configuration data corresponding to the address of the at least one first fuse according to the value of the at least one first fuse, To change the state of the configuration data. The processing method of claim 37, wherein the first semiconductor fuses comprise a plurality of second fuses, the second fuses being programmed to separate the end of the configuration data. The processing method of claim 37, wherein the second semiconductor fuse comprises a plurality of second fuses and a plurality of third fuses, The second fuse is programmed to separate the beginning of the first fuse correction data, and the third fuse is programmed to separate the end of the first fuse correction data. A processing method for providing configuration data to a microprocessor, comprising: setting a fuse array on a die, wherein the setting step comprises: storing a compressed configuration data in the plurality of first semiconductor fuses, wherein The configuration data is stored in a code compression format; the first fuse correction data is stored in the plurality of second semiconductor fuses, wherein the first fuse correction data is used to indicate at least a state of the first semiconductor fuse that needs to be changed. Address and value of a first fuse; and decompressing the first fuse correction data through a fuse correction decompressor, and releasing a decompressed first fuse correction data to other decompressors for The state of the at least one first fuse is changed before the other decompressor decompresses the configuration data. The processing method of claim 42, wherein the other decompressors respectively set a state corresponding to an address of the at least one first fuse according to the value of the at least one first fuse, to change the at least The state of a first fuse. The processing method of claim 42, wherein the fuse array further comprises: storing the second fuse correction data in the plurality of third semiconductor fuses, the second fuse correction data for indicating corresponding to the first The address of at least one second fuse that needs to change state in the second semiconductor fuse and value.