TW201544220A - A plural resistance-capacitances (PRC) electrical discharge machining system - Google Patents

A plural resistance-capacitances (PRC) electrical discharge machining system Download PDF

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TW201544220A
TW201544220A TW103118922A TW103118922A TW201544220A TW 201544220 A TW201544220 A TW 201544220A TW 103118922 A TW103118922 A TW 103118922A TW 103118922 A TW103118922 A TW 103118922A TW 201544220 A TW201544220 A TW 201544220A
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circuit
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discharge machining
capacitor
electrical discharge
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TWI560013B (en
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Shun-Tong Chen
Chi-Hung Chen
Po-Yuan Shih
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Univ Nat Taiwan Normal
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Abstract

The present invention provides a plural resistance-capacitances (PRC) electrical discharge machining system comprising a control module, a digital electronic module, a driving module, and a discharge module. The control module allows the user to input a command then output a control signal accordingly. The digital electronic module processes the control signal and outputs a sequence signal to the driving circuit. The driving module amplifies the sequence signal, and then outputs a driving signal to the discharge module. The discharge module controls and drives a plurality of transistors of it to open circuit and break circuit according to the driving signal for controlling the charging and the discharging of a plurality of capacitors of the discharge module in electrical discharge machining. The present creation can increase the amounts of the discharging in a machining process, and improve the efficiency thereof.

Description

多重電阻電容放電加工系統 Multiple resistance capacitor discharge machining system

本發明是關於一種微細放電加工系統,特別是有關於一種具有複數個電晶體控制複數個電容進行充電放電的放電加工系統。 The present invention relates to a micro-discharge machining system, and more particularly to an electric discharge machining system having a plurality of transistors for controlling a plurality of capacitors for charging and discharging.

近年來,隨著半導體、電子與機械等相關技術的進步,使產品朝向微小與精緻化方向發展,放電加工為主要加工方法之其中之一者,而其中的放電電源的改善則為各廠商的技術發展的方向。 In recent years, with the advancement of related technologies such as semiconductors, electronics and machinery, the products have been developed in the direction of micro and refinement. EDM is one of the main processing methods, and the improvement of the discharge power supply is for each manufacturer. The direction of technological development.

故許多廠商皆為自行開發的電源申請諸多專利,如Charmilles Co.Ltd在美國提出的專利(US 6727455B1),其電路利用0.1~10MHz超高頻交流電壓讓陰離子與陽離子在放電間隙中相互震盪、撞擊產生引弧的效果但不觸碰到工件所以不會產生電解效應,並在引弧後,立即切換為負極性放電,增加金屬切削率。Mitsubishi Co.Ltd.也發表了一篇專利(US 6727455B1),其中提出放電後存在於放電間隙的殘留能量會影響下次放電時的間隙狀況,同時也直接影響了工件加工後的表面精度。因此該公司利用交流放電時,以相反極性的放電迴路作為移除多餘的放電間隙殘餘能量,進而提升放電頻率,以增加其放電的效率。另一間公司Sodick Co.Ltd在美國發表了一篇專利(US 6130395A),其利用兩組直流電壓配合兩組電晶體,先進行粗加工後,再進行精修,成功製作出表面粗糙度Rmax小於1μm。財團 法人工業技術研究院也提出一篇專利(I 413559),利用兩組電源進行放電,高壓引弧電源主要為誘發放電現象;而低壓放電電源模組主要為加工所用,此迴路高壓引弧後,會進行電壓偵測,並對低壓電源進行調整以精確控制單發的放電加工能量,達高效節能功效。顏木田等學者也提出關於放電加工電源的專利(I 357840),此迴路運用橋式轉換器使直流電源產生出正負兩極的轉換,此法可使放電加工時具有穩定的電源供應,也可避免直流電源放電時產生的電解現象,使工件的變質層減少。同時也加入了一組卸除多餘電壓的機制迴路,使正極放電時避免上一發的負極電源干擾,同時比避免負正極放電時上一發的正負極電源干擾,以減少快速放電時的放電損失,以提升效率。 Therefore, many manufacturers apply for many patents for self-developed power supplies, such as the patent proposed by Charmilles Co. Ltd in the United States (US 6727455B1), the circuit uses 0.1~10MHz ultra-high frequency AC voltage to make the anions and cations oscillate in the discharge gap. The impact produces an arc-inducing effect but does not touch the workpiece, so there is no electrolytic effect, and immediately after the arc-triggering, it switches to a negative discharge, increasing the metal cutting rate. Mitsubishi Co. Ltd. also published a patent (US 6727455B1), in which it is proposed that the residual energy existing in the discharge gap after the discharge affects the gap condition at the next discharge, and also directly affects the surface precision after the workpiece is processed. Therefore, when the company uses AC discharge, the discharge circuit of opposite polarity is used as the residual energy of the excess discharge gap, thereby increasing the discharge frequency to increase the discharge efficiency. Another company, Sodick Co. Ltd, published a patent in the United States (US 6130395A), which uses two sets of DC voltages to match two sets of transistors, which are first roughed and then refined to produce a surface roughness Rmax. Less than 1 μm. Consortium The Institute of Industrial Technology also proposed a patent (I 413559), which uses two sets of power sources for discharge. The high-voltage arc-igniting power supply is mainly for induced discharge. The low-voltage discharge power module is mainly used for processing. Voltage detection will be performed, and the low-voltage power supply will be adjusted to accurately control the single-shot EDM energy to achieve high efficiency and energy saving. Yan Mutian and other scholars also proposed a patent on the electric discharge machining power supply (I 357840). This circuit uses a bridge converter to convert the positive and negative poles of the DC power supply. This method can provide a stable power supply during EDM and can also avoid The electrolysis phenomenon generated when the DC power source is discharged reduces the deterioration layer of the workpiece. At the same time, a set of mechanism circuit for removing excess voltage is added to avoid the interference of the negative power supply of the previous one when discharging the positive electrode, and to avoid the interference of the positive and negative power sources of the previous one when the negative positive discharge is avoided, so as to reduce the discharge during rapid discharge. Loss to improve efficiency.

而就現有技術來說,放電加工(EDM)分成電晶體放電和單電 阻電容放電兩種迴路,電晶體放電迴路,它一次所釋放能量太多,移除材料相對也較多,使加工速度較快,但加工精度並不高,不符合微加工所要求。有鑑於此,在微細加工開發上,常採用電阻電容放電迴路,此法主要以電容的充放電原理,瞬間產生高電流,使電子在刀具與工具間進行跳躍,產生近萬度高溫,進而移除材料。雖產生的溫度高,但時間短暫,單發能量並不高,移除材料的範圍較少,故能維持良好表面粗糙度。但因電阻電容放電迴路在放電時需同時滿足兩電極處在一定小的距離與電容充滿電荷的條件,方可放電。習知的電阻電容放電迴路以單顆電容進行放電,使固定時間下放電次數少,進而加工效率無法提升。 In the prior art, electrical discharge machining (EDM) is divided into transistor discharge and single electricity. The two circuits of the resistance capacitor discharge, the transistor discharge circuit, it releases too much energy at one time, and the material is relatively removed, so that the processing speed is fast, but the processing precision is not high, and does not meet the requirements of micro-machining. In view of this, in the development of microfabrication, resistor-capacitor discharge loops are often used. This method mainly uses the charge and discharge principle of capacitors to generate high currents instantaneously, causing electrons to jump between the tool and the tool, generating nearly 10,000 degrees of high temperature, and then shifting. In addition to materials. Although the temperature generated is high, the time is short, the single-energy energy is not high, and the range of material removal is small, so that good surface roughness can be maintained. However, because the resistor-capacitor discharge circuit needs to satisfy the condition that the two electrodes are at a certain small distance and the capacitor is full of charge, the discharge can be discharged. The conventional resistor-capacitor discharge circuit discharges with a single capacitor, so that the number of discharges is small at a fixed time, and the processing efficiency cannot be improved.

因應上述問題,本發明係提供一種多重電阻電容放電加工系 統,可藉由複數個電晶體與複數個電容所組成的充電放電單元,充電放電單元依照一時序分別放電,以增加固定時間內的放電次數,改善放電加工製程。多重電阻電容放電加工系統包含:一控制模組、一數位電路模組、一驅動電路模組以及一放電電路模組。 In response to the above problems, the present invention provides a multiple resistor-capacitor electrical discharge machining system. The charging and discharging unit is composed of a plurality of transistors and a plurality of capacitors, and the charging and discharging units are respectively discharged according to a timing to increase the number of discharges in a fixed time and improve the electrical discharge machining process. The multiple resistance capacitor electrical discharge machining system comprises: a control module, a digital circuit module, a driving circuit module and a discharging circuit module.

其中控制模組得為一電腦,控制模組提供使用者輸入一指 令,適於控制放電加工系統;數位電路模組得為一可程式邏輯裝置,適於處理控制程式並輸出一時序訊號;驅動電路模組適於放大時序訊號並輸出一驅動訊號至放電電路模組;放電電路模組包含複數個電晶體以及複數個電容,放電電路模組根據驅動訊號控制並驅動複數個電晶體進行高頻率的開路(斷路)與閉路(通路)之動作,藉以控制複數個電容進行多次充電放電,以進行放電加工製程,而前述高頻率的範圍介於0.1至10MHz之間。 The control module is a computer, and the control module provides a user input finger The method is suitable for controlling an electrical discharge machining system; the digital circuit module is a programmable logic device adapted to process the control program and output a timing signal; the driving circuit module is adapted to amplify the timing signal and output a driving signal to the discharging circuit module The discharge circuit module includes a plurality of transistors and a plurality of capacitors, and the discharge circuit module controls and drives a plurality of transistors according to the driving signals to perform high frequency open (open) and closed (channel) operations, thereby controlling a plurality of The capacitor is charged and discharged multiple times to perform an electrical discharge machining process, and the aforementioned high frequency range is between 0.1 and 10 MHz.

其中可先利用式1求得各電容所需的充電時間,並在各電容的充電時間中加入其他電容,使各電容放電,以增加放電電路加工效率。本發明所採用方式為先使所有電容充滿電荷達到飽和狀態,並從電容C1開始放電,當電容C1結束放電後,由電容C2接續放電,此時電容C1進入充電狀態,等電容C2放電結束後,依序如此。 Firstly, the charging time required for each capacitor can be obtained by using Equation 1, and other capacitors are added in the charging time of each capacitor to discharge the capacitors to increase the processing efficiency of the discharge circuit. The method adopted by the invention is that all capacitors are filled with electric charge to reach a saturated state, and discharge is started from the capacitor C1. When the capacitor C1 is discharged, the capacitor C2 is continuously discharged. At this time, the capacitor C1 enters a charging state, and after the capacitor C2 is discharged, the capacitor C2 is discharged. , in order.

相較於習知技術,本發明所提供之多重電阻電容放電加工系統,可提高固定時間內放電加工製程的放電次數,改善單電阻電容放電電路加工效率。且因為單次放電時間相較於習知技術短,放電能量相較於習知技術低,故能使加工後工件具有良好表面粗糙度。經實驗證實,本發明所提供之多重電阻電容放電加工系統比習知技術的單電阻電容放電電路放 電進給率可提升60%以上。 Compared with the prior art, the multiple resistance capacitor electric discharge machining system provided by the invention can improve the number of discharges of the electric discharge machining process in a fixed time and improve the processing efficiency of the single resistance capacitor discharge circuit. Moreover, since the single discharge time is shorter than the conventional technique, the discharge energy is lower than that of the prior art, so that the workpiece after processing has a good surface roughness. It has been experimentally confirmed that the multiple resistance-capacitor electrical discharge machining system provided by the present invention is placed in a single-resistance capacitor discharge circuit of the prior art. The electric feed rate can be increased by more than 60%.

1‧‧‧多重電阻電容放電加工系統 1‧‧‧Multiple Resistor Capacitor Electrical Discharge Machining System

10‧‧‧控制模組 10‧‧‧Control Module

11‧‧‧電源 11‧‧‧Power supply

12‧‧‧數位電路模組 12‧‧‧Digital Circuit Module

122‧‧‧第一子電路 122‧‧‧First subcircuit

124‧‧‧第二子電路 124‧‧‧Second subcircuit

126‧‧‧第三子電路 126‧‧‧ third subcircuit

128‧‧‧波形產生裝置 128‧‧‧ Waveform generating device

121‧‧‧計時器 121‧‧‧Timer

123‧‧‧第四子電路 123‧‧‧ fourth subcircuit

13‧‧‧直流電源 13‧‧‧DC power supply

14‧‧‧驅動電路模組 14‧‧‧Drive Circuit Module

142‧‧‧光電耦合元件 142‧‧‧Photoelectric coupling elements

144‧‧‧放大器電路 144‧‧‧Amplifier circuit

16‧‧‧放電電路模組 16‧‧‧Discharge circuit module

162‧‧‧充電放電單元 162‧‧‧Charging and discharge unit

18‧‧‧放電加工裝置 18‧‧‧Electrical discharge processing equipment

19‧‧‧待加工工件 19‧‧‧Workpieces to be machined

C1、C2、C3、...、C2n‧‧‧電容 C 1 , C 2 , C 3 , ..., C 2n ‧‧‧ capacitor

Q1、Q2、Q3、...、Q2n‧‧‧電晶體 Q 1 , Q 2 , Q 3 , ..., Q 2n ‧‧‧O crystal

R1、R2、R3、...、R2n‧‧‧電阻 R 1 , R 2 , R 3 ,..., R 2n ‧‧‧resistance

S1‧‧‧時序訊號 S1‧‧‧ timing signal

S2‧‧‧驅動訊號 S2‧‧‧ drive signal

圖一繪製了根據本發明之一具體實施例的功能方塊圖。 Figure 1 depicts a functional block diagram in accordance with an embodiment of the present invention.

圖二繪製了根據本發明之一具體實施例的數位電路模組之細部系統的功能方塊圖。 2 is a functional block diagram of a detail system of a digital circuit module in accordance with an embodiment of the present invention.

圖三繪製了根據本發明之一具體實施例之驅動電路模組的細部系統的功能方塊圖。 3 is a functional block diagram of a detailed system of a drive circuit module in accordance with an embodiment of the present invention.

圖四繪製了根據本發明之一具體實施例之放電電路模組回路圖。 Figure 4 is a circuit diagram of a discharge circuit module in accordance with an embodiment of the present invention.

圖五繪製了根據本發明之一具體實施例之放電電路模組內複數個電晶體的開關動作波形圖。 Figure 5 is a diagram showing the switching operation waveforms of a plurality of transistors in a discharge circuit module according to an embodiment of the present invention.

圖六繪製了根據本發明之另一具體實施例之電容C1放電時之電路回路圖。 FIG six plotted circuit diagram of the circuit the capacitor C discharges, according to another embodiment of a particular embodiment of the present invention.

圖七繪製了根據圖六之電容C1放電時電晶體Q1以及Q2的開關動作波形圖。 Figure 7 is a diagram showing the switching operation waveforms of the transistors Q 1 and Q 2 according to the discharge of the capacitor C 1 of Figure 6.

圖八繪製了根據本發明之另一具體實施例之電容C2放電時之電路回路圖。 Figure 8 is a circuit diagram showing the discharge of capacitor C 2 in accordance with another embodiment of the present invention.

圖九繪製了根據圖八之電容C2放電時電晶體Q3以及Q4的開關動作波形圖。 Figure 9 is a diagram showing the switching operation waveforms of the transistors Q 3 and Q 4 when the capacitor C 2 is discharged according to Figure 8.

圖十繪製了根據本發明之另一具體實施例之電容C3放電時之電路回路圖。 FIG ten plotted circuit diagram of the circuit capacitance C of Example 3 of the discharge in accordance with another specific embodiment of the present invention.

圖十一繪製了根據圖十之電容C3放電時電晶體Q5以及Q6的 開關動作波形圖。 Figure 11 is a diagram showing the switching operation waveforms of the transistors Q 5 and Q 6 according to the capacitance C 3 of Figure 10.

以下將詳述本發明之較佳具體實施例,藉以充分說明本發明之特徵、精神及優點。 The preferred embodiments of the present invention will be described in detail in the following description.

請一併參閱圖一至圖三,圖一繪製了根據本發明之一具體實施例的功能方塊圖;圖二繪製了根據本發明之一具體實施例的數位電路模組之細部系統的功能方塊圖;圖三繪製了根據本發明之一具體實施例之驅動電路模組的細部系統的功能方塊圖。 Referring to FIG. 1 to FIG. 3 together, FIG. 1 is a functional block diagram according to an embodiment of the present invention; FIG. 2 is a functional block diagram of a detailed system of a digital circuit module according to an embodiment of the present invention. FIG. 3 is a functional block diagram of a detailed system of a drive circuit module in accordance with an embodiment of the present invention.

如圖一所示,本發明多重電阻電容放電加工系統1係包含有一控制模組10、一數位電路模組12、一驅動電路模組14、一放電電路模組16以及一放電加工裝置18。 As shown in FIG. 1 , the multiple resistance capacitor electrical discharge machining system 1 of the present invention comprises a control module 10 , a digital circuit module 12 , a drive circuit module 14 , a discharge circuit module 16 , and an electrical discharge machining device 18 .

其中控制模組10得為一電腦,適於提供使用者輸入指令以控制多重電阻電容放電加工系統1;數位電路模組12得為一可程式邏輯裝置(Programmable Logic Device,PLD),適於處理經由控制模組10輸入的指令並輸出一相對應之控制訊號;然而本發明的控制模組10以及數位電路模組12並不以前述的電腦以及可程式邏輯裝置為限,需要時,使用者亦可使用任何足以達成本發明效能的其他裝置代替;驅動電路模組包含一放大器電路144,適於對控制訊號進行增益放大,放大器電路144得為一電壓放大器電路,但本發明並不以此為限,放大器電路144亦可為一電流放大器電路或其他足以達成本發明效能的其他裝置;放電電路模組16包含複數個電容與複數個電晶體,複數個電晶體控制複數個電容的充電放電動作;放電加工裝置18直接對待加工物件進行放電加工。 The control module 10 is a computer, and is adapted to provide a user input command to control the multiple resistance-capacitor electrical discharge machining system 1; the digital circuit module 12 is a programmable logic device (PLD) suitable for processing The command input by the control module 10 outputs a corresponding control signal; however, the control module 10 and the digital circuit module 12 of the present invention are not limited to the aforementioned computer and the programmable logic device, and when needed, the user Any other device sufficient to achieve the performance of the present invention may be used instead; the driver circuit module includes an amplifier circuit 144 adapted to gain amplify the control signal, and the amplifier circuit 144 is a voltage amplifier circuit, but the present invention does not The amplifier circuit 144 can also be a current amplifier circuit or other device sufficient to achieve the performance of the present invention. The discharge circuit module 16 includes a plurality of capacitors and a plurality of transistors, and the plurality of transistors control the charging and discharging of the plurality of capacitors. The electric discharge machining device 18 directly performs electric discharge machining on the workpiece.

控制模組10與數位電路模組12電性連接,數位電路模組12 亦與驅動電路模組14電性連接,驅動電路模組14與放電電路模組16電性連接,最後放電電路模組16與放電加工裝置18電性連接,形成本發明多重電阻電容放電加工系統1。 The control module 10 is electrically connected to the digital circuit module 12, and the digital circuit module 12 The circuit module 14 is electrically connected to the driving circuit module 14 , and the driving circuit module 14 is electrically connected to the discharging circuit module 16 . Finally, the discharging circuit module 16 is electrically connected to the electrical discharge processing device 18 to form the multiple resistance capacitor electrical discharge machining system of the present invention. 1.

請一併參閱圖二至圖四,圖二、圖三及圖四分別繪述了根據 本發明之一具體實施例的數位電路模組之細部系統的功能方塊圖;根據本發明之一具體實施例之驅動電路模組的細部系統的功能方塊圖;以及繪製了根據本發明之一具體實施例之放電電路回路圖。 Please refer to Figure 2 to Figure 4 together. Figure 2, Figure 3 and Figure 4 respectively illustrate the basis. Functional block diagram of a detail system of a digital circuit module in accordance with an embodiment of the present invention; a functional block diagram of a detail system of a driver circuit module in accordance with an embodiment of the present invention; and A discharge circuit circuit diagram of an embodiment.

由圖可見,使用者經由控制模組10輸入指令後,控制模組10 輸出一相對應前述指令的控制訊號至數位電路模組12,數位電路模組12對控制訊號進行處理以形成一時序訊號S1,接著時序訊號S1被數位電路模組12輸入至驅動電路模組14內,驅動電路模組14內的放大器電路144放大時序訊號S1,使被放大的時序訊號S1形成一驅動訊號S2,驅動電路模組14再將驅動訊號S2輸入至放電電路模組16內,藉由驅動訊號S2驅動並控制放電電路模組16內複數個電晶體在開路(斷路)與閉路(通路)之間進行高頻率的切換,藉以控制複數個電容的充電與放電時序,再將前述電容所放出的電導入放電加工裝置18內,以進行放電加工製程,而前述高頻率的範圍介於0.1至10MHz之間。 As can be seen from the figure, after the user inputs an instruction via the control module 10, the control module 10 A control signal corresponding to the command is outputted to the digital circuit module 12, and the digital circuit module 12 processes the control signal to form a timing signal S1, and then the timing signal S1 is input to the driving circuit module 14 by the digital circuit module 12. The amplifier circuit 144 in the driving circuit module 14 amplifies the timing signal S1, so that the amplified timing signal S1 forms a driving signal S2, and the driving circuit module 14 inputs the driving signal S2 into the discharging circuit module 16, Driven by the driving signal S2 and controlled by the plurality of transistors in the discharge circuit module 16 to switch between open circuit (open circuit) and closed circuit (channel), thereby controlling the charging and discharging timing of the plurality of capacitors, and then the capacitor The discharged electric current is introduced into the electric discharge machining apparatus 18 to perform an electric discharge machining process, and the high frequency range is between 0.1 and 10 MHz.

由於控制模組10與數位電路模組12之間電性連結,使用者在 多重電阻電容放電加工系統1進行放電加工製程中,能及時更改修正放電加工作業所需的參數,以提高放電加工效能與其作業順暢性。由於電阻電容放電電路能提供短脈衝及高峰值的放電電流,故待加工工件的材料移除量 較習知技術小,能改善加工表面粗糙度。 Since the control module 10 and the digital circuit module 12 are electrically connected, the user is In the multi-resistance electric discharge machining system 1 during the electric discharge machining process, the parameters required for correcting the electric discharge machining operation can be changed in time to improve the electric discharge machining efficiency and the smoothness of the operation. Since the resistor-capacitor discharge circuit can provide a short pulse and a high peak discharge current, the material removal amount of the workpiece to be processed It is smaller than the conventional technology and can improve the surface roughness of the machined surface.

再請參閱圖二,由圖可見,於本例中,數位電路模組12進一 步包含一第一子電路122、一第二子電路124、一第三子電路126、一波形產生裝置128、一計時器121以及一第四子電路123。 Referring again to FIG. 2, it can be seen from the figure that in this example, the digital circuit module 12 is further advanced. The step includes a first sub-circuit 122, a second sub-circuit 124, a third sub-circuit 126, a waveform generating device 128, a timer 121, and a fourth sub-circuit 123.

其中第二子電路124得為一可程式邏輯電路區塊 (Configurable Logic Block,CLB);第三子電路126得為一可程式交連電路區塊(Programmable Interconnects Block,PIB);一波形產生裝置128得為一振盪器(Oscillator)或一函數產生器(Function generator)。 The second sub-circuit 124 is a programmable logic circuit block. (Configurable Logic Block, CLB); the third sub-circuit 126 is a Programmable Interconnects Block (PIB); a waveform generating device 128 is an oscillator (Oscillator) or a function generator (Function Generator).

首先,啟動與數位電路模組12連接之一電源11,再將由控制 模組10所輸入的控制訊號,輸入至第一子電路122,第一子電路122將控制程式輸入至第二子電路124及第三子電路126內。其中,第二子電路124能自我組織出所需之加法器、減法器,反向器等邏輯閘,並透過第三子電路126,將加法器、減法器,反向器等邏輯閘連結,以產生一邏輯程式。另外,透過波形產生裝置128以及計時器121,產生一高頻率計時訊號,此計時訊號被傳至第二子電路124中與邏輯程式進行整合,產生時序訊號S1。再藉由第四子電路123輸出時序訊號S1至驅動電路模組14,而前述高頻率的範圍介於0.1至10MHz之間。 First, a power supply 11 connected to the digital circuit module 12 is activated, and then controlled by The control signal input by the module 10 is input to the first sub-circuit 122, and the first sub-circuit 122 inputs the control program into the second sub-circuit 124 and the third sub-circuit 126. The second sub-circuit 124 can self-organize the required logic gates such as adders, subtractors, and inverters, and through the third sub-circuit 126, the logic gates such as adders, subtractors, and inverters are connected. To generate a logic program. In addition, a high frequency timing signal is generated through the waveform generating device 128 and the timer 121. The timing signal is transmitted to the second sub-circuit 124 and integrated with the logic program to generate the timing signal S1. The fourth sub-circuit 123 outputs the timing signal S1 to the driving circuit module 14, and the high frequency range is between 0.1 and 10 MHz.

請參閱圖三,圖三繪製了根據本發明之一具體實施例之驅動 電路模組的細部系統的功能方塊圖。其中驅動電路模組14進一步包含一光電耦合元件142,適於保護時序訊號S1免於受到放電加工製程中產生的雜訊影響。經由第四子電路123輸出的時序訊號S1,被輸入至光電耦合元件142中,以便隔絕放電加工製程中所產生的雜訊,並保護前端的數位電路模組 12不受放電加工的影響。而時序訊號S1經放大器電路144放大後,形成驅動訊號S2,並輸入至放電電路模組16內,並驅動放電電路模組16中的複數個電晶體在開路(斷路)與閉路(通路)之間進行高頻率的切換,藉以控制複數個電容的充電與放電時序,以進行放電加工製程,而前述高頻率的範圍介於0.1至10MHz之間。 Referring to FIG. 3, FIG. 3 depicts a driving according to an embodiment of the present invention. Functional block diagram of the detailed system of the circuit module. The driving circuit module 14 further includes a photoelectric coupling component 142 adapted to protect the timing signal S1 from the noise generated in the electrical discharge machining process. The timing signal S1 outputted through the fourth sub-circuit 123 is input to the optocoupler element 142 to isolate the noise generated in the EDM process and protect the digital circuit module at the front end. 12 is not affected by electrical discharge machining. The timing signal S1 is amplified by the amplifier circuit 144 to form a driving signal S2, and is input into the discharge circuit module 16, and drives a plurality of transistors in the discharge circuit module 16 to be in an open circuit (open circuit) and a closed circuit (channel). High frequency switching is performed to control the charging and discharging timing of a plurality of capacitors for performing an electrical discharge machining process, and the aforementioned high frequency range is between 0.1 and 10 MHz.

接著請參閱圖四,圖四繪繪製了根據本發明之一具體實施例 之放電電路回路圖。如圖四所示,放電電路模組16的一端與一直流電源13電性連接,另一端與放電加工裝置18連接,在放電加工裝置18的下方則設置有一待加工工件19。 Referring to FIG. 4, FIG. 4 depicts a specific embodiment according to the present invention. The circuit diagram of the discharge circuit. As shown in FIG. 4, one end of the discharge circuit module 16 is electrically connected to the DC power source 13 and the other end is connected to the EDM device 18. Below the EDM device 18, a workpiece 19 to be processed is disposed.

其中放電電路模組16內包含複數個充電放電單元162,於本 實施例中,充電放電單元162以每二個電晶體間有一個電容及一個電阻的方式電性串聯連接而組成,而各個充電放電單元162則以並聯的方式電性連接並分別地與驅動電路模組14電性連接。 The discharge circuit module 16 includes a plurality of charge and discharge units 162, In the embodiment, the charging and discharging unit 162 is electrically connected in series by a capacitor and a resistor between each of the two transistors, and each of the charging and discharging units 162 is electrically connected in parallel and separately connected to the driving circuit. The module 14 is electrically connected.

其中電晶體Q1及電晶體Q2負責控制電容C1的充放電時序; 電晶體Q3及電晶體Q4負責控制電容C2的充放電時序;電晶體Q5及電晶體Q6負責控制電容C3的充放電時序;以此類推,電晶體Q2n-1及電晶體Q2n負責控制電容Cn的充放電時序,n為非0的正整數。電容Cn所需之充電時間可由下段的式1算得,其中τN為充電時間,C為電容,R為電阻,Ed為放電電壓,E0為直流電源13電壓。求得各電容所需的充電時間後,並在各電容的充電時間中加入其他電容,使各電容放電,以增加多重電阻電容放電加工系統1的加工效率。 The transistor Q 1 and the transistor Q 2 are responsible for controlling the charge and discharge timing of the capacitor C 1 ; the transistor Q 3 and the transistor Q 4 are responsible for controlling the charge and discharge timing of the capacitor C 2 ; the transistor Q 5 and the transistor Q 6 are responsible for controlling The charge and discharge timing of the capacitor C 3 ; and so on, the transistor Q 2n-1 and the transistor Q 2n are responsible for controlling the charge and discharge timing of the capacitor C n , and n is a positive integer other than zero. The charging time required for the capacitor C n can be calculated from Equation 1 in the following paragraph, where τ N is the charging time, C is the capacitance, R is the resistance, E d is the discharging voltage, and E 0 is the voltage of the DC power source 13 . After the charging time required for each capacitor is obtained, other capacitors are added in the charging time of each capacitor to discharge the capacitors to increase the processing efficiency of the multiple resistor-capacitor electrical discharge machining system 1.

接著請參閱圖五,圖五繪製了根據本發明之一具體實施例之 放電電路模組內複數個電晶體的開關動作波形圖。首先請看圖五上方,電晶體Q1的方波波谷代表電晶體Q1的開路(斷路),而電晶體Q2的方波波峰代表電晶體Q2的閉路(通路)。將電晶體Q1與電晶體Q2的方波波形重疊後,可得到電容C1的一次放電週期,如圖五下方間隔訊號所示。 Referring to FIG. 5, FIG. 5 is a diagram showing switching waveforms of a plurality of transistors in a discharge circuit module according to an embodiment of the present invention. First, look at the top of Figure V, the transistor Q 1 square wave valleys representative of transistor Q 1 is open (open circuit), the transistor Q square wave peak represents the transistor Q 2 2 is closed (passage). After superposing the square wave waveform of the transistor Q 1 and the transistor Q 2 , a single discharge period of the capacitor C 1 can be obtained, as shown by the interval signal in FIG.

請繼續參閱圖五,放電電路模組之波形設計,係在單一充電 放電單元162的一次充電放電週期中,再加入多組充電放電單元162的放電週期,並使各電容C1~C2n依循數位電路模組12的規劃,依序放電,如圖五下方間隔訊號所示。亦即,電容C1放電後,接續電容C2放電,電容C3放電,以此類推至電容Cn放電,完成後,再依序循環。藉此,本發明利用多組充電放電單元162的依序放電,得以有效提高單位時間內放電加工裝置18對待加工工件19的放電加工次數。 Referring to FIG. 5, the waveform design of the discharge circuit module is performed in a single charge discharge cycle of the single charge discharge unit 162, and then the discharge cycle of the plurality of charge and discharge cells 162 is added, and the capacitors C 1 to C 2n are followed. The planning of the digital circuit module 12 is sequentially discharged, as shown in the lower interval signal of FIG. That is, the capacitor C 1 discharging, connecting the capacitor C 2 discharges, discharges the capacitor C 3, and so on to discharge the capacitor C n, completed, and then sequentially and repeatedly. Thereby, the present invention utilizes the sequential discharge of the plurality of sets of charging and discharging units 162, thereby effectively improving the number of times of electric discharge machining of the workpiece 19 to be processed by the electric discharge machining apparatus 18 per unit time.

接著請同時參閱圖六與圖七,圖六繪製了根據本發明之另一 具體實施例之電容C1放電時之電路回路圖;圖七繪製了根據圖六之電容C1放電時電晶體Q1以及Q2的開關動作波形圖。 Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 6 is a circuit diagram of the capacitor C 1 when discharging according to another embodiment of the present invention; FIG. 7 is a diagram showing the capacitor Q according to the capacitor C 1 of FIG. 1 and Q 2 switching action waveforms.

於本實施例中,以三組充電放電單元162為代表,即n等於3時,放電電路模組16中,電晶體Q1以及Q2控制電容C1進行放電的示意圖組,其中以電路開關圖示代表電晶體的開路(斷路)與閉路(通路)。如圖六所示,此時電晶體Q1為開,而電晶體Q2為關,代表電容C1已充電完成且正在進行放電,如圖七方框所標記的區域所示,當電容C1先行放電時,電晶體Q2為關,而電晶體Q4及Q6為開,以免電容C1的電荷被回充至電容C2及C3。同時間,電晶體Q1為開,以免電容C1放電時,使用到電容C2與C3中的電荷, 而電晶體Q3及Q5為關,以使電容C2與C3進行充電,等待下次的放電。 In the present embodiment, three sets of charging and discharging units 162 are representative, that is, when n is equal to 3, in the discharge circuit module 16, the transistors Q 1 and Q 2 control the capacitor C 1 to perform a schematic diagram of discharging, wherein the circuit switch The illustration represents the open (open) and closed (via) of the transistor. As shown in Figure 6, at this time, the transistor Q 1 is on, and the transistor Q 2 is off, indicating that the capacitor C 1 has been charged and is discharging, as shown in the area marked by the box in Figure 7, when the capacitor C When the first discharge is performed, the transistor Q 2 is turned off, and the transistors Q 4 and Q 6 are turned on, so that the charge of the capacitor C 1 is not charged back to the capacitors C 2 and C 3 . At the same time, the transistor Q 1 is on to avoid the charge in the capacitors C 2 and C 3 when the capacitor C 1 is discharged, and the transistors Q 3 and Q 5 are off to charge the capacitors C 2 and C 3 . Wait for the next discharge.

接著請同時參閱圖八與圖九,圖八繪製了根據本發明之另一 具體實施例之電容C2放電時之電路回路圖;圖九繪製了根據圖八之電容C2放電時電晶體Q3以及Q4的開關動作波形圖。 Referring to FIG. 8 and FIG. 9 at the same time, FIG. 8 is a circuit diagram of capacitor C 2 discharge according to another embodiment of the present invention; FIG. 9 is a diagram showing capacitor C 2 discharge according to FIG. 3 and Q 4 switching action waveforms.

於本實施例中,電容C1放電完畢後,電晶體Q3以及Q4控制 電容C2接續電容C1進行放電,其中以電路開關圖示代表電晶體的開路(斷路)與閉路(通路)。如圖八所示,此時電晶體Q3為開,而電晶體Q4為關,代表電容C2已充電完成且正在進行放電,如圖九方框所標記的區域所示,當電容C2進行放電時,電晶體Q4為關,而電晶體Q2及Q6為開,以免電容C2的電荷被回充至電容C1及C3。同時間,電晶體Q3為開,以免電容C2放電時,使用到電容C1與C3中的電荷,而電晶體Q1及Q5為關,以使電容C1與C3進行充電,等待下次的放電。 In the present embodiment, the capacitor C 1 is discharged, the transistor Q 3 and Q 4 successive control capacitor C 2 discharges the capacitor C 1, which illustrates the representative circuit switching transistor is open (open) and closed (passage) . As shown in Figure 8, at this time, the transistor Q 3 is on, and the transistor Q 4 is off, indicating that the capacitor C 2 has been charged and is discharging, as shown in the area marked by the box of Figure 9, when the capacitor C 2 When discharging, the transistor Q 4 is off, and the transistors Q 2 and Q 6 are on, so that the charge of the capacitor C 2 is not charged back to the capacitors C 1 and C 3 . At the same time, the transistor Q 3 is on to avoid the charge in the capacitors C 1 and C 3 when the capacitor C 2 is discharged, and the transistors Q 1 and Q 5 are off to charge the capacitors C 1 and C 3 . Wait for the next discharge.

接著請同時參閱圖十與圖十一,圖十繪製了根據本發明之另 一具體實施例之電容C3放電時之電路回路圖;圖十一繪製了根據圖十之電容C3放電時電晶體Q5以及Q6的開關動作波形圖。 Next, please refer to FIG. 10 and FIG. 11 at the same time. FIG. 10 is a circuit circuit diagram of capacitor C 3 discharging according to another embodiment of the present invention; FIG. 11 is a diagram showing the capacitor C 3 discharging current according to FIG. Switching waveform diagram of crystal Q 5 and Q 6 .

於本實施例中,電容C1以及C2放電完畢後,電晶體Q5以及 Q6控制電容C3接續電容C1以及C2進行放電,其中以電路開關圖示代表電晶體的開路(斷路)與閉路(通路)。如圖十所示,此時電晶體Q5為開,而電晶體Q6為關,代表電容C3已充電完成且正在進行放電,如圖十一方框所標記的區域所示,當電容C3進行放電時,電晶體Q6為關,而電晶體Q2及Q4為開,以免電容C3的電荷被回充至電容C1及C2。同時間,電晶體Q5為開,以免電容C3放電時,使用到電容C1與C2中的電荷,而電晶體Q1及Q3為關,以 使電容C1與C2進行充電,等待下次的放電。綜合圖六至圖十一的各電容放電步驟,形成一放電循環供多重電組電容放電加工系統進行放電加工。 In this embodiment, after the capacitors C 1 and C 2 are discharged, the transistors Q 5 and Q 6 control the capacitor C 3 to discharge the capacitors C 1 and C 2 , wherein the circuit switch diagram represents the open circuit of the transistor (open circuit) ) with closed circuit (channel). As shown in Figure 10, at this time, the transistor Q 5 is on, and the transistor Q 6 is off, indicating that the capacitor C 3 has been charged and is discharging, as shown in the area marked by the box in Figure 11, when the capacitor When C 3 is discharged, transistor Q 6 is off, and transistors Q 2 and Q 4 are on, so that the charge of capacitor C 3 is not recharged to capacitors C 1 and C 2 . At the same time, the transistor Q 5 is on to avoid the charge in the capacitors C 1 and C 2 when the capacitor C 3 is discharged, and the transistors Q 1 and Q 3 are off to charge the capacitors C 1 and C 2 . Wait for the next discharge. Combining the capacitor discharge steps of FIG. 6 to FIG. 11 to form a discharge cycle for the electric multi-group capacitor discharge machining system for electrical discharge machining.

綜上所述,本發明提供了一種多重電阻電容放電加工系統, 利用控制模組輸入指令並輸出相對應前述指令之控制訊號,控制訊號經由數位電路模組進行處理並輸出時序訊號,再經由驅動電路模組放大並輸出驅動訊號至放電電路模組中,驅動訊號控制並驅動複數個電晶體在開路(斷路)與閉路(通路)之間進行高頻率的切換,藉以控制複數個電容進行多次充電放電,進行放電加工製程,而前述高頻率的範圍介於0.1至10MHz之間。 In summary, the present invention provides a multiple resistance capacitor electrical discharge machining system, The control module inputs a command and outputs a control signal corresponding to the foregoing command, and the control signal is processed by the digital circuit module to output a timing signal, and then the drive circuit module amplifies and outputs the driving signal to the discharge circuit module to drive the signal. Controlling and driving a plurality of transistors to switch between open circuit (open circuit) and closed circuit (channel) at a high frequency, thereby controlling a plurality of capacitors to perform multiple discharge discharges, and performing an electrical discharge machining process, wherein the high frequency range is 0.1 Between 10MHz.

相較於習知技術,本發明所提供之多重電阻電容放電加工系 統,利用複數個電晶體高頻率的控制複數個電容進行多次充電放電,並依照一時序對放電加工裝置放電,可提高固定時間內放電加工製程的放電次數,改善放電加工效率。且因為單次放電時間相較於習知技術短,放電能量相較於習知技術低,故能使加工後工件具有良好的表面粗糙度。 Compared with the prior art, the multiple resistance capacitor electrical discharge machining system provided by the present invention The system uses a plurality of transistors to control a plurality of capacitors to perform multiple charging and discharging, and discharges the electric discharge machining device according to a timing, thereby improving the number of discharges of the electric discharge machining process in a fixed time period and improving the efficiency of electric discharge machining. Moreover, since the single discharge time is shorter than the conventional technique, the discharge energy is lower than that of the conventional technique, so that the workpiece after processing can have a good surface roughness.

藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本 發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。因此,本發明所申請之專利範圍的範疇應根據上述的說明作最寬廣的解釋,以致使其涵蓋所有可能的改變以及具相等性的安排。 With the above detailed description of the preferred embodiments, it is desirable to describe this more clearly. The invention is not limited by the specific embodiments disclosed herein. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. Therefore, the scope of the patented scope of the invention should be construed in the broadest

1‧‧‧多重電阻電容放電加工系統 1‧‧‧Multiple Resistor Capacitor Electrical Discharge Machining System

10‧‧‧控制模組 10‧‧‧Control Module

12‧‧‧數位電路模組 12‧‧‧Digital Circuit Module

14‧‧‧驅動電路模組 14‧‧‧Drive Circuit Module

16‧‧‧放電電路模組 16‧‧‧Discharge circuit module

18‧‧‧放電加工裝置 18‧‧‧Electrical discharge processing equipment

Claims (10)

一種多重電阻電容放電加工系統,其包含有:一控制模組,自一使用者取得一輸入指令並輸出有一相對應的控制訊號;一數位電路模組,與該控制模組電性連接,該數位電路模組處理該控制訊號以輸出一相對應的時序訊號;一驅動電路模組,與該數位電路模組電性連接,包含有一放大器電路,該放大器電路適於放大該時序訊號以輸出一相對應的驅動訊號;以及一放電電路模組,與該驅動電路模組電性連接,該放電電路包含複數個電晶體與複數個電容,該放電電路模組根據該驅動訊號來將該複數個電晶體自開路與閉路之間進行切換,藉以控制該複數個電容的充電與放電時序以對一工件進行放電加工。 A multiple resistance-capacitor electrical discharge machining system, comprising: a control module, an input command is obtained from a user and a corresponding control signal is outputted; and a digital circuit module is electrically connected to the control module, The digital circuit module processes the control signal to output a corresponding timing signal; a driving circuit module is electrically connected to the digital circuit module, and includes an amplifier circuit, wherein the amplifier circuit is adapted to amplify the timing signal to output a a corresponding driving signal; and a discharging circuit module electrically connected to the driving circuit module, the discharging circuit comprising a plurality of transistors and a plurality of capacitors, the discharging circuit module is configured to use the plurality of capacitors according to the driving signal The transistor switches between an open circuit and a closed circuit to control the charging and discharging timing of the plurality of capacitors to perform electrical discharge machining on a workpiece. 如申請專利範圍第1項所述之多重電阻電容放電加工系統,其中該數位電路模組包含一可程式邏輯裝置(Programmable Logic Device,PLD)。 The multiple resistance-capacitor electrical discharge machining system of claim 1, wherein the digital circuit module comprises a Programmable Logic Device (PLD). 如申請專利範圍第1項所述之多重電阻電容放電加工系統,其中該數位電路模組進一步包含:一第一子電路,用以接收該控制訊號;一第二子電路,與該第一子電路電性連接,用以根據該控制訊號自我組織出複數個邏輯閘;一第三子電路,與該第一子電路及該第二子電路電性連接,用以根據該控制訊號整合該複數個邏輯閘,以形成一邏輯程式;以及一波形產生裝置,與該第二子電路電性連接,用以產生一計時訊號;其中,該控制訊號經由該第一子電路輸入至該第二子電路以及該第三 子電路內,該第二子電路根據該控制訊號產生複數個邏輯閘,並輸入至該第三子電路,該第三子電路根據該控制訊號連結該複數個邏輯閘,並輸出該邏輯程式至該第二子電路,該邏輯程式再與該波形產生裝置所輸出之一計時訊號整合成該時序訊號。 The multiple resistance-capacitor electrical discharge machining system of claim 1, wherein the digital circuit module further comprises: a first sub-circuit for receiving the control signal; a second sub-circuit, and the first sub-circuit The circuit is electrically connected to self-organize a plurality of logic gates according to the control signal; a third sub-circuit is electrically connected to the first sub-circuit and the second sub-circuit for integrating the complex number according to the control signal a logic gate to form a logic program; and a waveform generating device electrically coupled to the second sub-circuit for generating a timing signal; wherein the control signal is input to the second sub-circuit via the first sub-circuit Circuit and the third In the sub-circuit, the second sub-circuit generates a plurality of logic gates according to the control signal, and inputs to the third sub-circuit, the third sub-circuit connects the plurality of logic gates according to the control signal, and outputs the logic program to The second sub-circuit is further integrated with the timing signal output by the waveform generating device into the timing signal. 如申請專利範圍第3項所述之多重電阻電容放電加工系統,其中該波形產生裝置包含振盪器(Oscillator)或函數產生器(Function generator)。 The multiple resistance-capacitor electrical discharge machining system of claim 3, wherein the waveform generating device comprises an oscillator or a function generator. 如申請專利範圍第3項所述之多重電阻電容放電加工系統,其中該第二子電路包含一可程式邏輯區塊(Configurable Logic Block,CLB);該第三子電路包含一可程式交連區塊(Programmable Interconnects Block, PIB)。 The multiple resistance-capacitor electrical discharge machining system of claim 3, wherein the second sub-circuit comprises a Configurable Logic Block (CLB); the third sub-circuit comprises a programmable cross-connect block (Programmable Interconnects Block, PIB). 如申請專利範圍第1項所述之多重電阻電容放電加工系統,其中該放大器電路包含電壓放大器電路或電流放大器電路。 The multiple resistance-capacitor electrical discharge machining system of claim 1, wherein the amplifier circuit comprises a voltage amplifier circuit or a current amplifier circuit. 如申請專利範圍第1項所述之多重電阻電容放電加工系統,其中該驅動電路模組進一步包含一光電耦合元件,適於保護該時序訊號免於受到放電加工過程中產生的雜訊影響。 The multi-resistance electrical discharge machining system of claim 1, wherein the driving circuit module further comprises an optocoupler element adapted to protect the timing signal from noise generated during the electrical discharge machining process. 如申請專利範圍第1項所述之多重電阻電容放電加工系統,其中該放電電路模組包含複數個充電放電單元,該複數個充電放電單元分別包含有以至少二個之該電晶體以及至少一個之該電容,該電容係設置於該二電晶體之間並與該二電晶體串聯,該複數個充電放電單元係以並聯的方式電性連接。 The multiple resistance-capacitor electrical discharge machining system of claim 1, wherein the discharge circuit module comprises a plurality of charge and discharge units, the plurality of charge and discharge units respectively comprising at least two of the transistors and at least one The capacitor is disposed between the two transistors and connected in series with the two transistors, and the plurality of charge and discharge units are electrically connected in parallel. 如申請專利範圍第8項所述之多重電阻電容放電加工系統,其中該複數個充電放電單元內包含複數個電阻,設置於該複數個電晶體與該複數個電容之間,並與該複數個電晶體以及該複數個電容串聯。 The multiple resistance-capacitor electrical discharge machining system of claim 8, wherein the plurality of charge and discharge cells comprise a plurality of resistors disposed between the plurality of transistors and the plurality of capacitors, and the plurality of capacitors The transistor and the plurality of capacitors are connected in series. 如申請專利範圍第9項所述之多重電阻電容放電加工系統,其中該多重電阻電容放電加工系統進一步包含一直流電源與一放電加工裝置,該直 流電源與該放電電路模組電性連接,用以提供該複數個電容充電所需之電源;該放電加工裝置與該放電電路模組電性連接,用以接收該複數個充電放電單元所放出的電,以對該工件進行放電加工。 The multiple resistance-capacitor electrical discharge machining system according to claim 9, wherein the multiple resistance-capacitor electrical discharge machining system further comprises a DC power supply and an electric discharge machining device, the straight The power supply is electrically connected to the discharge circuit module for providing a power supply for charging the plurality of capacitors; the electrical discharge processing device is electrically connected to the discharge circuit module for receiving the plurality of charge and discharge units The electric power is used to perform electrical discharge machining on the workpiece.
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