TW201541732A - Interfaces with built-in transient voltage suppression - Google Patents

Abstract

An interface for protecting electronic devices from external Electric Over-Stress (EOS), Electromagnetic Interference (EMI) and Electrostatic Discharge (ESD) is disclosed. The interface is coupled to a PCB having electronic circuits. The interface device comprises a plurality of conducting lines for establishing electrical communication with the circuits on the PCB, wherein each conducting line has a distinct potential; and protection components connected to the conducting lines in the interface to shunt the EOS/EMI/ESD energy therethrough in the event of EOS occurring on the conducting lines.

Description

Interface with built-in transient voltage suppression

The present invention relates to preventing over-current stress (EOS), electromagnetic interference (EMI), and electrostatic discharge (ESD) in peripheral devices or connectors.

Failure of an electronic device can be caused by various causes such as high temperatures, high currents and/or voltages, mechanical shocks, pressure or collisions, and the like. When electronic equipment and circuits are exposed to transient voltages or currents, various harmful conditions can occur, such as electrical stress (EOS), electromagnetic interference (EMI), and electrostatic discharge (ESD), surges, and spikes during electrical communication. In general, electronic equipment has limited protection and EOS/EMI/ESD processing capabilities, so equipment is susceptible to damage in the event of these harmful conditions. When the above-mentioned harmful conditions occur, a high current and/or voltage is generated at the input of the electronic device. Rapid changes in current and/or voltage at the input can cause electronic equipment to malfunction.

An electronic device typically includes at least one circuit designed to meet the functional requirements of the electronic device. Conventional processes for manufacturing electronic devices begin with specifications that specify electrical requirements, such as input/output signals, power requirements, etc., to achieve the functional requirements of the electronic device. The specification also includes physical parameters that must be met by the electronic device, such as size, weight, moisture resistance, temperature range, heat output, vibration tolerance, and the like. The circuit is designed on a specification basis, in which individual circuit elements are selected to perform each function in the circuit, and the interconnection of the parts that realize the overall function is determined and schematically represented. Thereafter, the physical layout is typically formed in the form of a printed circuit board (PCB) layout of the design circuit and a PCB is prepared.

The selected circuit components typically include operational components that perform each function of the circuit, as well as protective components used around the operational components that are not affected by the aforementioned EOS/EMI/ESD and other deleterious conditions. The operating elements usually include active components such as semiconductors, transistors, and diodes, as well as passive components such as resistors and capacitors. The protection element typically includes a transient voltage suppression (TVS) diode, a Zener diode, a Schottky diode, a varactor, a clamp, and the like. In addition, a semiconductor package having a plurality of such diodes can also be used.

The PCB must accommodate both the operating and protective components. However, electronic devices with size limitations have certain constraints on the PCB size, so the PCB area of the circuit components is reduced. This results in thinner conductive vias and improperly arranged circuit components, which increases parasitic impedance and makes routing of conductive vias very difficult, and the design and layout of the circuitry is extremely time consuming. In the event of EOS, the parasitic impedance causes an erroneous function of the operating and protective components on the PCB, causing the electronic device to malfunction.

In addition, the requirements of the protective element are also related to the number of conductive channels. Therefore, as the number of conductive paths increases, the number of protective components required on the PCB also increases, so a larger PCB must be used. The increased number of protection components on the PCB and the protection components must use larger PCBs, resulting in higher PCB manufacturing costs and higher total cost of electronic equipment.

Therefore, in order to protect electronic devices and circuits, it is necessary to solve the above disadvantages associated with the use of protective elements.

An electrical connection is formed between the plurality of electronic devices and circuitry using the interface. The interface typically includes a connector to the PCB that is mounted on the PCB. The interface is usually divided into a "public" interface and a "mother" interface, which are connected to enable communication between electronic devices. During communication, electronic devices have been affected by transient voltages or currents that can occur in a variety of hazardous conditions, including EOS, EMI, ESD, surges, and spikes. EOS/EMI/ESD often occurs when an electronic device loads excessive voltage or current. EOS/EMI/ESD may be caused by various reasons, such as when the PCB is powered up, the wrong connection interface, causing a short circuit between two or more pins in the interface, an incorrect power supply or direction, etc., causing voltage/current surges. Excessive voltage at the turn causes the electronic device to malfunction. In order to protect electronic devices from these harmful conditions, protective components such as TVS diodes, Zener diodes, varactors, and clamps are used in the circuits of these devices, consuming excessive transient voltage/current. Generated EOS/EMI/ESD energy. In addition, a semiconductor package containing a plurality of such diodes can also be used.

Referring to Figure 1, a conventional interface configuration for connecting a PCB is shown, with the protection components mounted on the PCB. According to the embodiment shown in FIG. 1, the conventional interface includes a first interface as a common interface 11, a second interface as a mother interface 12, and a mother interface 12 connected to the PCB 14. The interface 11 is directly connected to another PCB or connected to another PCB through a connecting wire. Alternatively, the interface 11 is included in the data line.

The mother interface 12 typically includes a plurality of conductive traces/channels that are also connected to corresponding conductive traces/channels in the PCB 14 when the mother interface 12 is connected to the PCB 14. The conductive vias are also connected to the operating elements of the circuitry 16 on the PCB 14. Similarly, the interface 11 typically includes a plurality of conductive traces/channels connected to corresponding conductive traces/channels in the PCB, the PCB being connected to the interface 11 . In addition, when the peripheral devices 11 and 12 are connected to form an electrical connection between the circuits on the separate PCB, the conductive lines of the mother interface 12 are electrically connected to the corresponding conductive lines of the interface 11 . The conductive traces in the interface typically include data, power, and ground.

According to the embodiment shown in FIG. 1, the interface 12 includes a first conductive line 20 and a second conductive line 22, wherein when the interface 12 is connected to the PCB 14, the first conductive line 20 is connected to the corresponding first conductive path 24, The second conductive trace 22 is connected to a corresponding second conductive via 26 on the PCB 14. Interface 12 includes additional conductive traces 21a-21n that include respective conductive vias 25a-25n. Conductive channels 24, 25a-25n and 26 transfer data and power to the operating elements of circuit 16 on PCB 14.

According to the embodiment shown in FIG. 1, the first conductive path 24 has a higher potential than the second conductive path 26, wherein the first conductive path 24 is a power supply channel and the second conductive path 26 is a ground path. Typically, each conductive channel has a different potential. A protective element 18 is used between the first conductive channel/power channel 24 and the second conductive channel/ground channel 26 of the PCB 14. Similar protective elements 19a-19n are used between the conductive vias 25a-25n and the second conductive via 26, respectively. Protection elements 18 and 19a-19n are disconnected between their respective lines and ground path 26. In addition, more complex protection components/devices are required depending on the EOS/EMI/ESD specifications of each electronic device. Moreover, the EOS/EMI/ESD protection specifications of each conductive channel of the PCB may also be different, and each channel requires a different protection component.

See Figure 2 for EOS/EMI/ESD in the line/channel on the PCB shown in Figure 1. In the event of EOS/EMI/ESD, destructive EOS/EMI/ESD energy 30 enters the PCB through interface 12. The current Ip flowing through the first conductive line is suddenly increased. The transient spike current flows into the first conductive path 24 connected to the first conductive line, resulting in a destructive induced voltage, an unacceptable current density, and overheating of the operating elements of the circuit 16 connected to the first conductive path 24. This spike current can also cause thermal damage to the electronic device.

The protective element 18 coupled between the first conductive path 24 and the second conductive path 26 directs excess current on the first conductive path 24 to the ground by providing a path through itself to the second conductive path 26. The path defined by node 1-2-3-4-5-6 indicates the direction of current flow when EOS/EMI/ESD occurs.

However, the configurations shown in Figures 1 and 2 also have a number of deficiencies. The main disadvantage is that the structure places parasitic impedances Z1 and Z2 on the conductive paths on the PCB 14, weakening the performance of the protection element. The determination of the parasitic impedances Z1 and Z2 depends on the length, width, thickness and material of the conductive vias 24 and 26 on the PCB 14. Impedance Z1 passes through the path defined by node 2-3, and impedance Z2 passes through the path defined by node 3-4-5. Typically, although the parasitic impedance of the metal channel is established by resistance, inductance, and capacitance, the resistance and inductance have a large effect on the operation of the protection elements 18 and 19a-19n.

See Figure 3 for a graphical representation of the adverse effects of parasitic impedance on the operation of the protection elements on the PCB shown in Figure 1. Figure 3 shows the rise in current and voltage values with current and voltage waveforms when EOS/EMI/ESD occurs. When EOS/EMI/ESD occurs and the destructive EOS/EMI/ESD energy enters the first conductive path 24, the parasitic impedances Z1 and Z2 will circulate on the current divided by nodes 1-2-3-4-5-6. An unnecessary voltage drop is formed, resulting in an increase in the clamp voltage TVS_Clamp of the protection element 18. The voltage of the first conductive path 24 is represented by VIN, and the current flowing through the circuit at EOS/EMI/ESD is represented by Ip. Typically, the protection element 18 protects the operational elements of the circuit by maintaining the voltage level TVS_Clamp below the breakdown voltage level IC_BV of the operational element of the circuit 16. The protection element 18 prevents the voltage amplitude from exceeding their clamp voltage level TVS_Clamp, which must be lower than the breakdown voltage of the operating element.

However, the parasitic impedances Z1 and Z2 overshoot the clamp voltage TVS_Clamp. The rise of the voltage level Vp is calculated according to the following equation: Vp ≈ Ip × (Z1 + Z2).

Ideally, under normal operating conditions, the overshoot VIN must be limited by the protection element 18 below the clamp voltage TVS_Clamp. However, an increase in the parasitic impedances Z1 and Z2 causes the voltage VIN to exceed the breakdown voltage IC_BV of the electronic device, resulting in an irreparable failure of the operating elements of the circuit 16.

It is an object of the present invention to improve one or more of the following prior art techniques, or at least to propose an effective alternative:

It is an object of the present invention to provide enhanced protection against harmful conditions such as EOS/EMI/ESD.

It is an object of the present invention to provide an interface that facilitates the use of a compact PCB.

It is an object of the present invention to provide a cost effective interface.

It is an object of the present invention to provide an interface that facilitates reducing the maintenance cost of electronic equipment.

In accordance with the present invention, an interface is provided that includes at least a portion of an EOS/EMI/ESD protection device that is adapted to be removably attached to an electronic device to be protected.

Typically, the interface includes at least one first connector for connecting a second connector associated with the electronic device.

In general, the connector is a male/female connector.

In general, the interface is freely selectable from the following groups: Universal Serial Bus (USB) interface, High Definition Multimedia Interface (HDMI) interface, Display (DP) interface, IEEE1394 interface, Video Image Array (VGA) interface, and Digital Video Interface (DVI) interface, etc.

Typically, the USB interface is freely available from the following groups, including: Micro USB interface, mini USB interface, and standard USB interface.

Typically, ESO/EMI/ESD protection devices contain at least one component selected from the group consisting of: TVS diodes, Zener diodes, varactors, avalanche diodes, and clamps. .

In addition, the ESO/EMI/ESD protection device contains at least one component selected from the group consisting of a TVS diode, a Zener diode, a varactor diode, an avalanche diode, and a clamp.

Typically, the interface includes a plurality of conductive vias, and the EOS/EMI/ESD protection device is electrically coupled to at least two of the conductive vias.

Other objects and advantages of the present invention will become more apparent from the following description and appended claims.

11‧‧‧Member

12‧‧‧ mother interface

14‧‧‧PCB

16‧‧‧ Circuitry

18‧‧‧Protection components

19a-19n‧‧‧protective components

20‧‧‧First conductive line

21a-21n‧‧‧Electrical circuit

22‧‧‧Second conductive line

24‧‧‧First conductive path

25a-25n‧‧‧ conductive channel

26‧‧‧Second conductive channel

30‧‧‧Energy

100‧‧‧ first interface

102‧‧‧Second interface

104‧‧‧First conductive line

105a-105n‧‧‧Electrical circuit

106‧‧‧Second conductive line

108‧‧‧Protection components

109a-109n‧‧‧protective components

110‧‧‧PCB

112‧‧‧ Circuitry

114‧‧‧First conductive path

115a-115n‧‧‧ conductive channel

116‧‧‧Second conductive channel

120‧‧‧Transient voltage

2-3‧‧‧ nodes

3-4-5‧‧‧ nodes

Z1, Z2‧‧‧ parasitic impedance

7-8-9-10‧‧‧ nodes

7‧‧‧ nodes

1-2-3-4-5-6‧‧‧ nodes

102‧‧‧Import

1 is a conventional interface configuration in the prior art in combination with a PCB on which a protection element is mounted;

Figure 2 is a diagram showing the occurrence of EOS/EMI/ESD in the line/channel on the PCB shown in Figure 1;

Figure 3 graphically illustrates the adverse effects of parasitic impedance on the operation of the protection element on the PCB shown in Figure 1;

Figure 4 is an embodiment of the present invention, which includes an interface of an EOS/EMI/ESD protection device;

Figure 5 shows the interface shown in Figure 4 connected to the PCB;

Figure 6 is a diagram showing the case where EOS/EMI/ESD occurs in the line/channel in the EOS/EMI/ESD protection device shown in Fig. 4;

Figure 7 graphically shows the current and voltage at which EOS/EMI/ESD conditions occur, and the clamps for the interface shown in Figure 4 when EOS/EMI/ESD conditions occur.

The present invention will be further described below in detail with reference to the accompanying drawings.

The terminology used herein is for the purpose of illustration and description and embodiments The singular forms "a," "," The terms "comprising," "comprising," and "having," are inclusive, and are intended to s , ingredients, parts and/or components. The method steps, procedures, and operations described herein are not required for the performance requirements unless specifically stated as a performance requirement. It should also be apparent that the invention may also employ additional or alternative processes.

When an element or layer is referred to as being "on," "connected to," "connected to," or "coupled to" another element or layer, it is meant to be directly connected, mounted, connected, or coupled. On other components or layers, or there are intermediate components or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly connected" or "directly coupled" to another element or layer, there are no other intermediate elements or layers. Other words describing the relationship between elements should be interpreted in a similar manner (eg, "between" and "next", "near" and "adjacent", etc.). The term "and/or" used herein includes any and all combinations of one or more of the associated.

The words first, second, third, etc. are used to denote the various elements, parts, regions, layers and/or parts, and are not limited to these words. The words used are only used to distinguish such elements, parts, regions, layers and/ Unless specifically stated otherwise, the words "first", "second", and other words used herein are not intended to mean a sequence or order. Accordingly, a first element, component, region, layer or portion may be hereinafter referred to as a second element, component, region, layer or portion, without departing from the scope of the embodiments.

The expression "at least" or "at least one" as used herein refers to the use of one or more elements or elements, as used in the embodiments of the invention, to achieve one or more desired objectives or results.

"Over-current stress (EOS), electromagnetic interference (EMI), and electrostatic discharge (ESD)" as used in the present invention refers to a situation in which an electronic device and/or circuit is subjected to voltages and/or currents exceeding a normal command specification. This definition is not only used in the art.

Referring to Figures 4 and 5, in accordance with one embodiment of the present invention, an interface having an EOS/EMI/ESD protection device and an interface to the PCB are shown, respectively. According to the embodiment shown in FIGS. 4 and 5, the interface includes a first interface 100 as a male interface and a second interface 102 as a mother interface. However, since the interfaces 100 and 102 can be respectively connected in the interchangeable mating structure, the mating structures of the interfaces 100 and 102 are not limited to the above structure. The mother interface 102 is also coupled to the PCB 110. The interface 100 is coupled to another PCB either directly or through a connection line. Alternatively, the interface 100 is included in the data line. The interfaces 100 and 102 are typically soldered to their respective PCBs. The interfaces 100 and 102 include, but are not limited to, a USB interface, an HDMI interface, a DP interface, an IEEE 1394 interface (a serial standard developed by Apple, and a Chinese translation called a FireWire interface). In addition, the USB interface includes a micro USB interface, a mini USB interface, and a standard USB interface; the DP interface includes all interfaces specified by the Video Electronics Standards Association (VESA). Interfaces 100 and 102 are typically connectors.

The mother interface 102 typically includes a plurality of conductive traces/channels that are coupled to corresponding conductive traces/channels in the PCB 110 when the mother interface 102 is coupled to the PCB 110. The conductive path is also connected to the operating element of circuit 112 on PCB 110. Similarly, the male peripheral device 100 typically includes a plurality of conductive traces/channels connected to corresponding conductive traces/channels in the PCB, the PCB being coupled to the male peripheral device 100. In addition, when the peripheral devices 100 and 102 are connected to form an electrical connection between the circuits on the separate PCBs, the conductive lines of the mother interface 102 are electrically connected to the corresponding conductive lines of the interface 100. The conductive traces in the interface typically include data, power, and ground.

In accordance with the embodiment illustrated in Figures 4 and 5, the interface 102 of the present invention includes a first conductive trace 104 and a second conductive trace 106 and additional conductive traces 105a-105n. When interface 102 is coupled to PCB 110, first conductive trace 104 is coupled to a corresponding first conductive via 114 on PCB 110, and second conductive trace 106 is coupled to a respective second conductive via 116. The PCB includes respective additional conductive vias 115a-115n. Conductive channels 114, 115a-115n and 116 transfer data and power to the operational elements of circuit 112 on PCB 110.

Additionally, the interface 102 of the present invention includes an EOS/EMI/ESD protection device in which a protection element 108 (typically a TVS device) is coupled between the first conductive line 104 and the second conductive line 106. Similarly, protection elements 109a-109n are coupled between additional conductive lines 105a-105n and second conductive line 106, respectively. Protection elements 108 and 109a-109n include, but are not limited to, TVS diodes, Zener diodes, Schottky diodes, varactors, avalanche diodes, and clamps. The protection elements 108 and 109a-109n constituting the EOS/EMI/ESD protection device are built-in, so that the interface 102 eliminates the need to mount the protection element on the PCB as in the prior art.

According to the embodiment shown in FIGS. 4 and 5, the first conductive line 104 has a higher potential than the second conductive line 106, wherein the first conductive line 104 is a power line and the second conductive line 106 is a ground line. Thus, the protection element 108 is electrically coupled between the first conductive line/power line 104 and the second conductive line/ground line 106. Typically, each conductive line has a different potential.

In the case where EOS/EMI/ESD occurs, when the potentials of the first conductive line 104 and the second conductive line 106 exceed a predetermined value, the protection element 108 provides a low impedance path for the transient current, thereby protecting the circuit on the PCB 110. The operating element of 112. The connection of the protection element 108 in the interface 102 allows for a compact, smaller size PCB 110 to be used in comparison to the prior art, thereby facilitating easy and efficient switching of the operational elements of the circuit 112 on the PCB 110.

See Figure 6 for the EOS/EMI/ESD situation in the line/channel of the EOS/EMI/ESD protection device shown in Figure 4. When EOS/EMI/ESD occurs, a transient voltage 120 is present at node 7 on the first conductive line 104 such that the current Ip flowing through the first conductive line 104 increases significantly. The protective element 108 coupled between the first conductive line 104 and the second conductive line 106 transfers excess current from the first conductive line 104 to the ground through a path through itself to the second conductive line 106. Excess current is not allowed to flow to the PCB 110. The path defined by nodes 7-8-9-10 represents the current flowing through protection element 108 when EOS/EMI/ESD occurs. Excess current flows back from the inlet 102 itself through the protective element 108, thereby preventing excess current from flowing to the PCB 110. In addition, in the case of EOS/EMI/ESD, the parasitic impedance has the least effect on the protection element 108 when conducting excess current. The parasitic impedance associated with the conductive pathways of PCB 110, if any, does not affect the functionality of protection element 108.

See Figure 7 for a graphical representation of the current and voltage at which the EOS/EMI/ESD condition occurs, and the clamps formed by the interface shown in Figure 6 for EOS/EMI/ESD conditions. Ip indicates the inrush current generated when EOS/EMI/ESD occurs. The clamp voltage TVS_Clamp is less than the breakdown voltage IC_BV of the operating element of the circuit 112. Protection elements 108 and 109a-109n are selected in accordance with system requirements, i.e., current and voltage specifications of the operating elements of circuit 112. Due to the minimization of the parasitic impedance, there is no overshoot voltage, so the voltage on the operating element of circuit 112 is lower than the clamp voltage of protection element 108.

Therefore, when the interface containing the protection element of the present invention is coupled to the PCB, the excess voltage/current is transferred out of the interface itself through the protection element, preventing excessive current from flowing to the PCB, thereby effectively protecting the components mounted on the PCB. In addition, the position of the protection component in the interface can effectively reduce the size of the PCB, reducing the cost of developing the PCB, thereby further reducing the overall cost of the electronic device. In addition, in any protection component, any breakdown caused by EOS/EMI/ESD requires only replacing the interface and maintaining the same PCB, thereby reducing the maintenance cost of the electronic device.

The advancement of the process achieved by the interface of the present invention includes: providing greater protection against EOS/EMI/ESD harmful conditions; facilitating the use of protective components in peripheral devices; in the event of EOS/EMI/ESD Electronic equipment provides protection; easy to use compact PCB; and provides a cost-effective interface.

The above description of the exemplary embodiments fully demonstrates the generality of the embodiments, which, with the prior knowledge, can be easily changed and/or applied to different applications without departing from the general concepts, and therefore such adaptations and modifications should be considered and intended It is understood that they fall within the meaning and range equivalent to the above embodiments. It will be understood that the phraseology or terminology used herein is for the purpose of explanation and Therefore, while the invention has been described in terms of the preferred embodiments, the embodiments of the invention are intended to be

Domestic registration information [please note according to the registration authority, date, number order]

no

Foreign deposit information [please note according to the country, organization, date, number order]

no

no

110‧‧‧PCB

112‧‧‧ Circuitry

120‧‧‧Transient voltage

106‧‧‧Second conductive line

102‧‧‧Second interface

104‧‧‧First conductive line

108‧‧‧Protection components

109n‧‧‧protective components

109a‧‧‧Protection components

7‧‧‧ nodes

8‧‧‧ nodes

9‧‧‧ nodes

10‧‧‧ nodes

Claims (8)

An interface comprising at least a portion of an overcurrent stress/electromagnetic interference/electrostatic discharge protection device, wherein the interface is adapted to be detachably coupled to an electronic device for protection. The interface of claim 1, wherein the interface comprises at least one first connector for assembling a second connector, the second connector being coupled to the electronic device. The interface of claim 2, wherein the connector is a male/female connector. The interface described in claim 1, wherein the interface is freely selected from the group consisting of: a universal serial bus interface, a high definition multimedia interface, a display interface, an IEEE 1394 interface, a video image array interface, and a digital video interface. And all kinds of connectors for data interface, battery charging, mobile functions, docking applications in mobile phones or handheld electronic devices. The interface of claim 4, wherein the universal serial bus interface comprises a micro universal serial bus interface, a mini universal serial bus interface, and a standard universal serial bus interface; the display interface includes a video electronic standards association All interfaces specified. The interface of claim 1, wherein the protection device for the electrical stress/the electromagnetic interference/the electrostatic discharge comprises at least one component freely selected from the group consisting of a transient voltage suppression diode, Zener diodes, varactors, avalanche diodes, and clamps. The interface of claim 1, wherein the protection device for the electrical stress/the electromagnetic interference/the electrostatic discharge comprises at least a portion of the components freely selected from the group consisting of transient voltage suppression diodes, Zener diodes, varactors, avalanche diodes, and clamps. The interface of claim 1, wherein the interface comprises a plurality of electrically conductive channels, and the electrical stress/the electromagnetic interference/the electrostatic discharge of the protection device is electrically coupled to the at least two electrically conductive channels.