TW201537718A - Chip structure with coaxial multi-core TSV amd method for manufacturing the same - Google Patents

Abstract

Disclosed is a chip structure with coaxial multi-core TSV. Disposed on an active surface of a semiconductor base are a plurality of surface conductor layers. And, disposed on an back surface of the semiconductor base are a plurality of backside conductor layers. An axial post and a coaxial hollow pipe are disposed in a through hole penetrating through the semiconductor base. Both are insulated by specific insulation layers and the coaxial hollow pipe is fully covered. Each of the two extruded ends of the axial post is respectively connected with a connecting pad. The length of the coaxial hollow pipe is smaller than the one of the axial post, so that the upper and lower connecting pads are insulated from the coaxial hollow pipe and its connected circuit patterns. Accordingly, multiple signals can be used through a same TSV without the issue of current leakage so as to reduce TSV disposition amount.

Description

Coaxial multi-core perforated wafer structure and manufacturing method thereof

The present invention relates to a vertical interconnect access (VIA) for a semiconductor wafer, and more particularly to a coaxial multi-core perforated wafer structure and method of fabricating the same.

Through Silicon Via (TSV) is a vertical interconnect via through a wafer or wafer.矽Perforation is widely used in stereo (3D) wafer-to-wafer stacking. Compared to traditional wire-bonding, chip-on-package (Package-On-Package, POP) can shorten the signal transmission distance to achieve high-speed interconnect transmission. However, as the size of the wafer is reduced or the transfer pin is increased, the number of turns of the turn is also required to increase, and the problem of die cracking is likely to occur.

U.S. Patent No. US 2011/0095435 A1 teaches a coaxial type of perforated wafer structure. As shown in FIGS. 1 and 2, the conventional perforated wafer structure 200 includes a semiconductor substrate 210 and a through hole 220 penetrating the semiconductor substrate 210. A surface insulating layer 231 and a back insulating layer 261 are formed on the upper surface of the semiconductor substrate 210. A dielectric liner 232 is formed on the surface insulating layer 231 and the inner hole wall of the through hole 220. The center of 220 is a semiconductor axial column 221, thereby forming an annular hole to facilitate the electroplating formation of a plurality of coaxial hollow tubes 241, 242, 243 in the through hole 220, the coaxial spaces A hole insulating layer 233 is interposed between the heart tubes 241, 242, and 243. Finally, a BSG insulating layer is formed on the surface of the semiconductor substrate 210 and the semiconductor substrate 210 is etched to form a coaxial via. However, the conventional perforated wafer structure 200 does not specifically disclose the connection manner of the coaxial hollow tubes 241, 242, and 243. The gap between the coaxial hollow tubes 241, 242, and 243 is too small, and the connection with the same plane is likely to cause leakage. The problem of current, and the semiconductor shaft 221 also occupies an effective plating space for the through hole 220.

In order to solve the above problems, the main object of the present invention is to provide a coaxial multi-core perforated wafer structure and a manufacturing method thereof, so that multiple signals can share the same perforation and no risk of leakage, thereby reducing the perforation of the crucible. The number is set to reduce the die crack caused by the increased number of perforations.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a coaxial multi-core perforated wafer structure, which comprises a semiconductor substrate, a through hole penetrating the semiconductor substrate, a first surface insulating layer, a first surface conductive layer, a second surface insulating layer, and a a second surface conductive layer, a first crystalline back insulating layer, a first crystalline back conductive layer, a second crystalline back insulating layer, and a second crystalline back conductive layer. The semiconductor substrate has an active surface and a back surface. The first surface insulating layer is formed on the active surface of the semiconductor substrate and in the through hole. The first surface conductive layer is formed on the active surface and the through hole, and the first surface conductive layer comprises a coaxial hollow tube in the through hole, and the first surface is electrically conductive on the active surface The layer is patterned into a first line pattern connecting the coaxial hollow tubes. The second surface insulating layer is formed on the first surface insulating layer and in the through hole, and the second surface insulating layer covers the first line pattern, and the through hole has a The second surface insulating layer fills the axial hole. The second surface conductive layer is formed on the second surface insulating layer and in the axial hole of the through hole, such that the second surface conductive layer comprises a hole in the axial hole and is coaxial with the coaxial hollow tube The electrically insulating shaft column, the second surface conductive layer on the second surface insulating layer is patterned into an upper pad connected to the shaft post and a connection to the upper pad Two line patterns. The first back insulating layer is formed on the back surface, and an end surface of the coaxial hollow tube and an end surface of the shaft post are exposed on the back surface. The first back conductive layer is formed on the first back insulating layer, and the first back conductive layer comprises a third line pattern connecting the end faces of the coaxial hollow tube. The second back insulating layer is formed on the first back insulating layer, and the second back insulating layer covers the third line pattern without covering the end surface of the shaft post. The second back conductive layer is formed on the second back insulating layer, and the second back conductive layer is patterned into an underlying pad under the axial column, wherein the coaxial hollow tube The second surface insulating layer is completely covered by the second surface insulating layer, and the length of the coaxial hollow tube is less than the length of the shaft column, so that the upper pad and the lower pad are electrically Insulating the coaxial hollow tube and the first line pattern and the third line pattern connected thereto. The present invention further discloses a method of fabricating the above wafer structure.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In a preferred embodiment of the foregoing wafer structure, the first surface conductive layer further includes a separate line pattern on the active surface, the independent line pattern electrically insulating the first line pattern and the The coaxial hollow tube is electrically connected to the independent circuit pattern, so that the second circuit pattern is electrically insulated from the first circuit pattern to be electrically connected to the semiconductor substrate.

In a preferred embodiment of the foregoing wafer structure, it may be packaged separately And comprising at least one first external terminal and at least one second external terminal, wherein the first external terminal is bonded to the lower pad, and the second back conductive layer further comprises a reconfigurable pad bonded to the third line pattern The second external terminal is coupled to the re-arrangement pad, so that the two signals passing through the same crucible are individually longitudinally turned by different external terminals.

In a preferred embodiment of the foregoing wafer structure, the lower pad and the re-stack pad may be bumped, and the first external terminal and the second external terminal are solder.

In a preferred embodiment of the foregoing wafer structure, the first crystalline back conductive layer may further comprise a growth block bonded to an end surface of the axial column for increasing the length of the axial column.

In a preferred embodiment of the foregoing wafer structure, the upper pads can be in a plurality of configurations and have different shapes for use as identification bonding pads.

100‧‧‧ coaxial multi-core perforated wafer structure

110‧‧‧Semiconductor substrate

111‧‧‧Active surface

112‧‧‧Back

112A‧‧‧The front side is not thinned

113‧‧‧First pad

114‧‧‧Second pad

120‧‧‧through holes

120A‧‧ hole

121‧‧‧Axis hole

131‧‧‧First surface insulation

132‧‧‧Second surface insulation

140‧‧‧First surface conductive layer

141‧‧‧Coaxial hollow tube

142‧‧‧First line pattern

143‧‧‧Independent line pattern

150‧‧‧Second surface conductive layer

151‧‧‧ Axis column

152‧‧‧second line pattern

153‧‧‧Upper pad

161‧‧‧First Crystal Back Insulation

162‧‧‧Second crystal back insulation

170‧‧‧First crystalline back conductive layer

171‧‧‧ Third line pattern

172‧‧‧ growth block

180‧‧‧Second crystal back conductive layer

181‧‧‧下 pads

182‧‧‧Relocation mat

191‧‧‧First external terminal

192‧‧‧Second external terminal

200‧‧‧矽punched wafer structure

210‧‧‧Semiconductor substrate

220‧‧‧through holes

221‧‧‧Semiconductor shaft column

231‧‧‧Surface insulation

232‧‧‧ dielectric lining

233‧‧‧ hole insulation

241‧‧‧Coaxial hollow tube

242‧‧‧Coaxial hollow tube

243‧‧‧Coaxial hollow tube

261‧‧‧ Crystal back insulation

Figure 1: Schematic cross-sectional view of a conventional 矽 perforated wafer structure.

2A and 2B are schematic partial top views of a conventional perforated wafer structure.

Figure 3 is a partial cross-sectional view showing the structure of a coaxial multi-core perforated wafer in accordance with an embodiment of the present invention.

Fig. 4 is a partial top plan view showing the structure of the crucible perforation according to an embodiment of the invention.

5A to 5Q: According to an embodiment of the present invention, a partial cross-sectional view of the crucible structure in the manufacturing process is illustrated.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a coaxial multi-core perforated wafer structure is illustrated in a partial cross-sectional view of FIG. 3, a partial top view of FIG. 4, and 5A to 5Q are illustrated in various steps of the process. A partial cross-sectional view of the main components. The coaxial multi-core perforated wafer structure 100 includes a semiconductor substrate 110, a uniform via 120, a first surface insulating layer 131, a first surface conductive layer 140, a second surface insulating layer 132, and a second surface conductive layer. 150. A first back insulating layer 161, a first back conductive layer 170, a second back insulating layer 162, and a second back conductive layer 180.

The semiconductor substrate 110 has an active surface 111 and a back surface 112. The substrate of the semiconductor substrate 110 is made of a semiconductor material such as germanium (Si). The active surface 111 is provided with integrated circuit components and a suitable conducting interconnect, and a first pad 113 and a second A solder pad 114 can be disposed on the active surface 111 for signal transmission of the integrated circuit. The through hole 120 penetrates through the semiconductor substrate 110. The number of the through holes 120 is not limited to one, and the total number thereof should be divided by a certain multiple (2 or more) of the pad of the wafer, and then the appropriate amount is increased or decreased. The through hole 120 should not be aligned with the first pad 113 and the second pad 114.

The first surface insulating layer 131 is formed on the active surface 111 of the semiconductor substrate 110 and in the through hole 120 for isolating the first surface conductive layer 140 from the semiconductor substrate 110. The first surface conductive layer 140 is formed on the active surface 111 and in the through hole 120, and the The first surface conductive layer 140 includes a coaxial hollow tube 141 in the through hole 120. The first surface conductive layer 140 on the active surface 111 is patterned into a first line connecting the coaxial hollow tube 141. The pattern 142 is electrically connected to the first pad 113 of the semiconductor substrate 110. Preferably, the first surface conductive layer 140 further includes a separate line pattern 143 on the active surface 111. The independent line pattern 143 is electrically insulated from the first line pattern 142 and the coaxial hollow tube 141. .

The second surface insulating layer 132 is formed on the first surface insulating layer 131 and the through hole 120. The second surface insulating layer 132 covers the first line pattern 142 for isolating the first surface conductive layer. 140 and the second surface conductive layer 150. The through hole 120 has a shaft hole 121 not filled by the second surface insulating layer 132. The second surface conductive layer 150 is formed on the second surface insulating layer 132 and the axial hole 121 of the through hole 120 such that the second surface conductive layer 150 includes a hole in the axial hole 121 and The shaft column 151 is electrically insulated from the coaxial hollow tube 141. The second surface conductive layer 150 on the second surface insulating layer 132 is patterned into an upper pad 153 aligned on the axis column 151 and a second line pattern connecting the upper pads 153. 152. Typically, the upper pads 153 can be in a plurality of configurations and have different shapes, such as a combination of a circular pad and a square pad (as shown in FIG. 4) as a bonding pad for identification. Preferably, the second line pattern 152 is electrically connected to the independent line pattern 143, so the second line pattern 152 is electrically insulated from the first line pattern 142 to be electrically connected to the semiconductor. The second pad 114 of the substrate 110.

The first back insulating layer 161 is formed on the back surface 112 to isolate the first back conductive layer 170 from the semiconductor substrate 110. An end surface of the coaxial hollow tube 141 and an end surface of the shaft post 151 are exposed on the back surface 112. The first crystalline back conductive layer 170 is formed on the first crystal back The insulating layer 161, and the first back conductive layer 170 includes a third line pattern 171 which is connected to the end surface of the coaxial hollow tube 141.

The second back insulating layer 162 is formed on the first back insulating layer 161 for isolating the second back conductive layer 180 from the first back conductive layer 170. The second back insulating layer 162 covers the third line pattern 171 without covering the end surface of the shaft pillar 151. The second back conductive layer 180 is formed on the second back insulating layer 162. The second back conductive layer 180 is patterned into a pad 181 which is aligned under the axis 151.

The coaxial hollow tube 141 is completely covered by the second surface insulating layer 132 and the second crystalline back insulating layer 162, and the length of the coaxial hollow tube 141 is smaller than the length of the shaft post 151, so that the upper portion The pad 153 and the lower pad 181 are electrically insulated from the coaxial hollow tube 141 and the first line pattern 142 and the third line pattern 171 connected thereto. In addition, the first back conductive layer 170 may further include a growth block 172 bonded to an end surface of the shaft pillar 151 for increasing the length of the shaft pillar 151.

More specifically, the coaxial multi-core perforated wafer structure 100 can further include at least one first external terminal 191 and at least one second external terminal 192, and the first external terminal 191 is coupled to the lower pad 181, and the The second back conductive layer 180 further includes a re-arrangement pad 182 bonded to the third line pattern 171. The second external terminal 192 is bonded to the re-arrangement pad 182, so that the two signals passing through the same crucible are Different external terminals are used for individual longitudinal conduction. Preferably, the lower pad 181 and the re-arrangement pad 182 can be bumped, for example, a copper stud bump. The first external terminal 191 and the second external terminal 192 are soldered, for example, lead-free solder. To bond to pads 153 on adjacent wafer structures.

The steps in the fabrication of the coaxial multi-core perforated wafer structure 100 can be seen in Figures 5A through 5Q. First, as shown in Figure 5A, A wafer type semiconductor substrate 110 is provided having an active surface 111 and a back surface, which is the unthinned front surface 112A in FIG. 5A. The active surface 111 is a forming surface of the integrated circuit and may be provided with at least one first pad 113. Thereafter, as shown in FIG. 5B, a cavity 120A is formed by the active surface 111. The depth of the hole 120A is smaller than the unthickened thickness of the semiconductor substrate 110 and larger than the thinned thickness of the semiconductor substrate 110. The method of forming the holes 120A may be a lithography imaging and etching method, particularly reactive ion etching (RIE). The shape of the aperture 120A can be circular, rectangular or triangular. Thereafter, as shown in FIG. 5C, a first surface insulating layer 131 is formed on the active surface 111 and in the cavity 120A. The first surface insulating layer 131 may be a tetraethoxy decane (TEOS) or a HARP insulating layer, which may be formed by a sub-atmospheric CVD (SACVD) process at a low temperature or a thermal oxidation. The process is formed at a high temperature.

Thereafter, as shown in FIG. 5D, a first surface conductive layer 140 is formed on the active surface 111 and in the cavity 120A, and the first surface conductive layer 140 includes a coaxial hollow tube 141 in the cavity 120A. . The first surface conductive layer 140 can be formed by sputtering titanium (Ti), electroplated copper (Cu), or low pressure chemical vapor deposition (LPCVD) process of polycrystalline silicon (poly-Si). ). Next, as shown in FIG. 5E, the first surface conductive layer 140 on the active surface 111 is patterned into a first line pattern connecting the coaxial hollow tubes 141 by lithography and pattern etching. 142. In addition, the first surface conductive layer 140 further includes a separate line pattern 143 on the active surface 111. The independent line pattern 143 is electrically insulated from the first line pattern 142 and the coaxial hollow tube 141.

Then, as shown in FIG. 5F, a second surface insulating layer 132 is formed on the first surface insulating layer 131 and in the hole 120A. The second surface insulating layer 132 covers the first line pattern 142. The 120A has a shaft hole 121 not filled by the second surface insulating layer 132. Tetraethoxysilane forming surface of the second insulating layer 132 may be by a chemical vapor deposition (CVD) process to form the silicon dioxide (SiO _2), or a sub-atmospheric chemical vapor deposition (Sub-Atmospheric CVD, SACVD) process A terpene (TEOS) or HARP insulating layer. Thereafter, as shown in FIG. 5G, openings of the second surface insulating layer 132 are formed, such as laser cutting or patterned dry etching, to expose the contacts of the independent line patterns 143.

Then, as shown in FIG. 5H, a second surface conductive layer 150 is formed on the second surface insulating layer 132 and the axial hole 121 of the hole 120A, so that the second surface conductive layer 150 includes The shaft post 151 is electrically insulated from the coaxial hollow tube 141 in the shaft hole 121. The method of forming the second surface conductive layer 150 can be the same as the method of forming the first surface conductive layer 140 described above. Then, as shown in FIG. 5I, the second surface conductive layer 150 on the second surface insulating layer 132 is patterned into an alignment connection on the axis column by lithography imaging and pattern etching. The upper pad 153 and the second line pattern 152 connecting the upper pad 153. Preferably, the second line pattern 152 is electrically connected to the independent line pattern 143 through the opening of the second surface insulating layer 132.

Thereafter, as shown in FIG. 5J, the semiconductor substrate 110 is thinned by the back surface 112 such that the hole 120A is formed as a through hole 120 penetrating the semiconductor substrate 110. The step of thinning the semiconductor substrate 110 from the back surface 112 may further include chemical etching in addition to the crystal back polishing, and the axis pillar 151 and the coaxial hollow tube 141 protrude from the thinned back surface 112. Thereafter, as shown in FIG. 5K, a first crystalline back insulating layer 161 is formed on the thinned back surface 112.

Thereafter, as shown in FIG. 5L, the coaxial hollow tube 141 is exposed. The end surface and the end surface of the shaft post 151 are on the thinned back surface 112. The step of exposing the end surface of the coaxial hollow tube 141 and the end surface of the shaft post 151 on the thinned back surface 112 includes chemical mechanical polishing of the wafer back surface. Thereafter, as shown in FIG. 5M, a first back surface conductive layer 170 is formed on the first crystal back insulating layer 161. Moreover, as shown in FIG. 5N, the lithography and pattern etching techniques can be utilized to make the first back surface conductive layer 170 include a third line pattern 171 that is connected to the end surface of the coaxial hollow tube 141. The first rear back conductive layer 170 can further include a growth block 172 bonded to an end surface of the shaft post 151 for increasing the length of the shaft post 151. The growth block 172 is not connected to the third line pattern 171.

Thereafter, as shown in FIG. 5O, a second back insulating layer 162 is formed on the first back insulating layer 161, and the second back insulating layer 162 covers the third line pattern 171. Then, as shown in FIG. 5P, the second back insulating layer 162 is patterned and etched to expose the pads of the third line pattern 171 and the direct or indirect end faces of the shaft pillars 151 to make the second The crystal back insulating layer 162 does not cover the end surface of the shaft post 151.

Thereafter, as shown in FIG. 5Q, a second back conductive layer 180 is formed on the second back insulating layer 162, and the second back conductive layer 180 is patterned to be aligned on the axis. a lower 151 under the 151, wherein the coaxial hollow tube 141 is completely covered by the second surface insulating layer 132 and the second crystalline back insulating layer 162, and the length of the coaxial hollow tube 141 is smaller than the axial column The length of the 151 is such that the upper pad 153 and the lower pad 181 are electrically insulated from the coaxial hollow tube 141 and the first line pattern 142 and the third line pattern 171 connected thereto. In addition, at least one first external terminal 191 and at least one second external terminal 192 may be disposed. The first external terminal 191 is coupled to the lower pad 181, and the second back conductive layer 180 further includes a bonding The re-arrangement pad 182 of the third line pattern 171 is bonded to the re-arrangement pad 182.

Therefore, with the coaxial multi-core perforated wafer structure and the manufacturing method thereof provided by the present invention, the multi-signal can share the same perforation and no risk of leakage, thereby reducing the number of perforated perforations and reducing the number of defects. A die crack caused by the perforation.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧ coaxial multi-core perforated wafer structure

110‧‧‧Semiconductor substrate

111‧‧‧Active surface

112‧‧‧Back

113‧‧‧First pad

114‧‧‧Second pad

120‧‧‧through holes

121‧‧‧Axis hole

131‧‧‧First surface insulation

132‧‧‧Second surface insulation

140‧‧‧First surface conductive layer

141‧‧‧Coaxial hollow tube

142‧‧‧First line pattern

143‧‧‧Independent line pattern

150‧‧‧Second surface conductive layer

151‧‧‧ Axis column

152‧‧‧second line pattern

153‧‧‧Upper pad

161‧‧‧First Crystal Back Insulation

162‧‧‧Second crystal back insulation

170‧‧‧First crystalline back conductive layer

171‧‧‧ Third line pattern

172‧‧‧ growth block

180‧‧‧Second crystal back conductive layer

181‧‧‧下 pads

182‧‧‧Relocation mat

191‧‧‧First external terminal

192‧‧‧Second external terminal

Claims (10)

A coaxial multi-core perforated wafer structure comprising: a semiconductor substrate having an active surface and a back surface; a through hole extending through the semiconductor substrate; a first surface insulating layer formed on the active surface and the through surface a first surface conductive layer formed on the active surface and the through hole, and the first surface conductive layer includes a coaxial hollow tube in the through hole, where the active surface The first surface conductive layer is patterned into a first line pattern connecting the coaxial hollow tubes; a second surface insulating layer is formed on the first surface insulating layer and in the through hole, the second surface insulating layer Covering the first circuit pattern, the through hole has a shaft hole not filled by the second surface insulating layer; a second surface conductive layer is formed on the second surface insulating layer and the through hole The axis of the hole is such that the second surface conductive layer includes a shaft post in the shaft hole and electrically insulated from the coaxial hollow tube, and the second surface insulating layer Two surface conduction The pattern is formed by an upper pad connected on the axis column and a second line pattern connecting the upper pads; a first back insulating layer is formed on the back surface, the coaxial hollow tube The end surface of the shaft and the end of the shaft are exposed on the back surface; a first back conductive layer is formed on the first back insulating layer, and the first back conductive layer comprises a third line pattern Connected to the end surface of the coaxial hollow tube; a second crystalline back insulating layer is formed on the first crystalline back insulating layer, and the second crystalline back insulating layer covers the third line pattern without overlying Covering an end face of the shaft post; and a second back conductive layer formed on the second back insulating layer, the second back conductive layer being patterned to be aligned under the axis a lower pad, wherein the coaxial hollow tube is completely covered by the second surface insulating layer and the second back insulating layer, and the length of the coaxial hollow tube is smaller than a length of the shaft column to make the upper The pad and the lower pad are electrically insulated from the coaxial hollow tube and the first line pattern and the third line pattern connected thereto. The coaxial multi-core perforated wafer structure according to claim 1, wherein the first surface conductive layer further comprises an independent circuit pattern on the active surface, the independent circuit pattern being electrically insulated from the first a line pattern and the coaxial hollow tube, the second line pattern is electrically connected to the independent line pattern. The coaxial multi-core perforated wafer structure according to claim 1, further comprising at least one first external terminal and at least one second external terminal, wherein the first external terminal is coupled to the lower pad, the second The crystalline back conductive layer further includes a relocation pad bonded to the third line pattern, the second external terminal being bonded to the relocation pad. The coaxial multi-core perforated wafer structure according to claim 3, wherein the lower pad and the re-arrangement pad are bumped, and the first external terminal and the second external terminal are solder. The coaxial multi-core perforated wafer structure according to claim 1, wherein the first back-conducting layer further comprises a growth block bonded to an end surface of the shaft post for increasing the axis The length of the column. The coaxial multi-core perforated wafer structure according to claim 1, wherein the upper pads are in a plurality of configurations and have different shapes for use as identification bonding pads. Method for manufacturing coaxial multi-core perforated wafer structure, including steps Providing a semiconductor substrate having an active surface and a back surface; forming a hole from the active surface; forming a first surface insulating layer on the active surface and the hole; forming a first surface conductive layer thereon An active surface and the cavity, and the first surface conductive layer includes a coaxial hollow tube in the hole, and the first surface conductive layer on the active surface is patterned to connect the coaxial hollow tube a first line pattern; forming a second surface insulating layer on the first surface insulating layer and the hole, the second surface insulating layer covering the first line pattern, the hole having a second portion a surface insulating layer filled with the axial hole; forming a second surface conductive layer on the second surface insulating layer and the axial hole of the hole, so that the second surface conductive layer comprises a hole in the axial hole a shaft post electrically insulated from the coaxial hollow tube, the second surface conductive layer on the second surface insulating layer being patterned as an aligning pad on the shaft post and Connected to the upper pad a second line pattern; the semiconductor substrate is thinned by the back surface such that the hole is formed as a through hole penetrating the semiconductor substrate; a first back insulating layer is formed on the thinned back surface; and an end surface of the coaxial hollow tube is exposed An end surface of the shaft pillar is on the thinned back surface; a first back surface conductive layer is formed on the first crystal back insulating layer, and the first crystal back conductive layer comprises a third line pattern, which is connected An end surface of the coaxial hollow tube; forming a second back insulating layer on the first back insulating layer, the second back insulating layer covering the third line pattern without covering the An end surface of the axial column; and a second crystalline back conductive layer formed on the second crystalline back insulating layer, the second crystalline back conductive layer is patterned into an alignment pad under the axial column The coaxial hollow tube is completely covered by the second surface insulating layer and the second crystal back insulating layer, and the length of the coaxial hollow tube is smaller than the length of the shaft column, so that the upper pad and the upper pad The lower pad is electrically insulated from the coaxial hollow tube and the first line pattern and the third line pattern connected thereto. The method for manufacturing a coaxial multi-core perforated wafer structure according to claim 7, wherein the first surface conductive layer further comprises an independent circuit pattern on the active surface, the independent circuit pattern being electrically insulated. The second line pattern is electrically connected to the independent line pattern in the first line pattern and the coaxial hollow tube. The method for manufacturing a coaxial multi-core perforated wafer structure according to claim 7 , further comprising: providing at least one first external terminal and at least one second external terminal, wherein the first external terminal is coupled to the lower connection The pad, the second back conductive layer further includes a relocation pad bonded to the third line pattern, and the second external terminal is bonded to the relocation pad. The method for manufacturing a coaxial multi-core perforated wafer structure according to claim 7, wherein the step of thinning the semiconductor substrate from the back surface comprises chemical etching, and the axis column and the coaxial hollow tube are protruded The step of thinning the back surface; and the step of exposing the end surface of the coaxial hollow tube and the end surface of the shaft post on the thinned back surface comprises chemical mechanical polishing.