TW201532306A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- TW201532306A TW201532306A TW104114223A TW104114223A TW201532306A TW 201532306 A TW201532306 A TW 201532306A TW 104114223 A TW104114223 A TW 104114223A TW 104114223 A TW104114223 A TW 104114223A TW 201532306 A TW201532306 A TW 201532306A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- graded
- aluminum nitride
- nitride layer
- layers
- Prior art date
Links
Abstract
Description
本發明是有關於一種半導體結構，且特別是有關於一種具有漸變式應力緩衝層的半導體結構。 This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a graded stress buffer layer.
隨著半導體科技的進步，現今的發光二極體已具備了高亮度的輸出，加上發光二極體具有省電、體積小、低電壓驅動以及不含汞等優點，因此發光二極體已廣泛地應用在顯示器與照明等領域。一般而言，發光二極體晶片採用寬能隙半導體材料，如氮化鎵(GaN)等材料，來進行製作。然而，除了熱膨脹係數以及化學性質的不同外，氮化鎵與異質基板的晶格常數(lattice constant)亦具有無法忽視的差異。所以，於異質基板上成長之氮化鎵會因為晶格不匹配(lattice mismatch)而產生晶格差排(dislocation)的現象，且晶格差排又會沿著氮化鎵層之厚度方向而延伸。再者，亦由於氮化鎵與異質基板的晶格不匹配的原因，氮化鎵材料相對於異質基板會產生極大的結構應力，其中隨著成長厚度越厚時，所累積的應力就越大，當超過某一臨界值，材料層就無法承受此應力，而必須以其他形式來釋放應力。如此一來，晶格差排除了會造成磊晶上的缺陷而使得發光二極體的發光效率降低，並且導致使用壽命縮短之外，亦無法成長很厚的氮化鎵。 With the advancement of semiconductor technology, today's light-emitting diodes have high-intensity output, and the light-emitting diodes have the advantages of power saving, small size, low voltage driving, and no mercury, so the light-emitting diode has Widely used in the fields of display and lighting. In general, a light-emitting diode wafer is fabricated using a wide bandgap semiconductor material such as gallium nitride (GaN). However, in addition to the difference in thermal expansion coefficient and chemical properties, the lattice constant of gallium nitride and a heterogeneous substrate also has a negligible difference. Therefore, gallium nitride grown on a heterogeneous substrate may have a lattice dislocation due to a lattice mismatch, and the lattice difference row will extend along the thickness direction of the gallium nitride layer. Furthermore, due to the lattice mismatch between gallium nitride and the heterogeneous substrate, the gallium nitride material generates great structural stress with respect to the heterogeneous substrate, and the thicker the thickness, the greater the accumulated stress. When a certain critical value is exceeded, the material layer cannot withstand this stress, and the stress must be released in other forms. As a result, the lattice difference eliminates defects that cause epitaxy, which causes the luminous efficiency of the light-emitting diode to decrease, and leads to a shortened service life, and it is also impossible to grow a very thick gallium nitride.
本發明提供一種半導體結構，其能夠釋放習知晶格不匹配所造成的應力問題且能減少晶格差排在厚度方向上的延伸現象。 The present invention provides a semiconductor structure capable of releasing stress problems caused by conventional lattice mismatch and reducing the elongation of the lattice difference in the thickness direction.
本發明提出一種半導體結構，其包括一氮化鋁層以及多組漸變式應力緩衝層。漸變式應力緩衝層配置於氮化鋁層上。每一組漸變式應力緩衝層包括依序堆疊的一漸變層及一過渡層。這些漸變層的化學通式為Al1-xGaxN，其中x值從鄰近氮化鋁層之一側往遠離氮化鋁層之方向逐漸遞增，且0≦x≦1。每一過渡層與同組中的漸變層中最遠離氮化鋁層之一側表面具有相同的化學通式，且最遠離氮化鋁層的這組漸變式應力緩衝層中的過渡層的化學通式為GaN。此外，漸變式應力緩衝層之漸變層的厚度由鄰近氮化鋁層之一側往遠離氮化鋁層之方向遞增。 The present invention provides a semiconductor structure comprising an aluminum nitride layer and a plurality of sets of graded stress buffer layers. The graded stress buffer layer is disposed on the aluminum nitride layer. Each set of graded stress buffer layers includes a graded layer and a transition layer stacked in sequence. These graded layers have a chemical formula of Al 1-x Ga x N, wherein the value of x gradually increases from the side adjacent to the aluminum nitride layer toward the direction away from the aluminum nitride layer, and 0 ≦ x ≦ 1. Each transition layer has the same chemical formula as the side surface of the graded layer in the same group farthest from the aluminum nitride layer, and the transition layer in the set of graded stress buffer layers farthest from the aluminum nitride layer The general formula is GaN. In addition, the thickness of the graded layer of the graded stress buffer layer is increased from the side adjacent to the aluminum nitride layer toward the direction away from the aluminum nitride layer.
在本發明之一實施例中，上述每一漸變層的厚度介於50奈米到700奈米之間。 In an embodiment of the invention, each of the graded layers has a thickness of between 50 nanometers and 700 nanometers.
在本發明之一實施例中，上述之這些組漸變式應力緩衝層之這些過渡層的厚度由鄰近氮化鋁層之一側往遠離氮化鋁層之方向遞增。 In an embodiment of the invention, the thickness of the transition layers of the set of progressive stress buffer layers is increased from a side adjacent to the aluminum nitride layer toward a direction away from the aluminum nitride layer.
在本發明之一實施例中，上述之每一過渡層的厚度介於50奈米到700奈米之間。 In an embodiment of the invention, each of the transition layers has a thickness between 50 nanometers and 700 nanometers.
在本發明之一實施例中，上述之過渡層之化學通式中的x值以等差級數逐漸遞增。 In one embodiment of the invention, the value of x in the chemical formula of the transition layer described above is gradually increased by an order of difference.
在本發明之一實施例中，上述之漸變式應力緩衝層包括2組 至10組的漸變式應力緩衝層。 In an embodiment of the invention, the gradual stress buffer layer comprises two groups Up to 10 sets of graded stress buffer layers.
在本發明之一實施例中，上述之半導體結構更包括一超晶格結構層，配置於氮化鋁層與這些組漸變式應力緩衝層之間。超晶格結構層包括多組氮化鋁鎵銦結構層，每一組氮化鋁鎵銦結構層包括相互堆疊的一第一氮化鋁鎵銦層以及一第二氮化鋁鎵銦層。這些第一氮化鋁鎵銦層的化學通式為AlsGatIn(1-s-t)N，其中0<s<1，0<t<1，且0<s+t≦1。這些第二氮化鋁鎵銦層的化學通式為AlmGanIn(1-m-n)N，其中0<m<1，0<n<1，且0<m+n≦1，當m=s時，n≠t；當n=t時，m≠s。 In an embodiment of the invention, the semiconductor structure further includes a superlattice structure layer disposed between the aluminum nitride layer and the set of graded stress buffer layers. The superlattice structure layer comprises a plurality of sets of aluminum gallium indium nitride structural layers, and each set of aluminum gallium indium nitride structural layers comprises a first aluminum gallium indium layer and a second aluminum gallium indium layer stacked on each other. The first aluminum gallium indium nitride layer has a chemical formula of Al s Ga t In (1-st) N, where 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of these second aluminum gallium indium layers is Al m Ga n In (1-mn) N, where 0<m<1, 0<n<1, and 0<m+n≦1, when m When =s, n≠t; when n=t, m≠s.
在本發明之一實施例中，上述之每一組氮化鋁鎵銦結構層的厚度介於5奈米至500奈米之間。 In an embodiment of the invention, each of the sets of aluminum gallium indium nitride structural layers has a thickness of between 5 nm and 500 nm.
在本發明之一實施例中，上述之超晶格結構層的厚度介於20奈米至5000奈米之間。 In an embodiment of the invention, the superlattice structure layer has a thickness of between 20 nm and 5000 nm.
在本發明之一實施例中，上述之超晶格結構層包括5組以上的氮化鋁鎵銦結構層。 In an embodiment of the invention, the superlattice structure layer comprises five or more sets of aluminum gallium indium nitride structural layers.
在本發明之一實施例中，上述之半導體結構更包括一超晶格結構層，配置於這些組漸變式應力緩衝層之間。超晶格結構層包括多組氮化鋁鎵銦結構層，每一組氮化鋁鎵銦結構層包括相互堆疊的一第一氮化鋁鎵銦層以及一第二氮化鋁鎵銦層。這些第一氮化鋁鎵銦層的化學通式為AlsGatIn(1-s-t)N，其中0<s<1，0<t<1，且0<s+t≦1。這些第二氮化鋁鎵銦層的化學通式為AlmGanIn(1-m-n)N，其中0<m<1，0<n<1，且0<m+n≦1，當m=s時，n≠t；當n=t時，m≠s。 In an embodiment of the invention, the semiconductor structure further includes a superlattice structure layer disposed between the set of graded stress buffer layers. The superlattice structure layer comprises a plurality of sets of aluminum gallium indium nitride structural layers, and each set of aluminum gallium indium nitride structural layers comprises a first aluminum gallium indium layer and a second aluminum gallium indium layer stacked on each other. The first aluminum gallium indium nitride layer has a chemical formula of Al s Ga t In (1-st) N, where 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of these second aluminum gallium indium layers is Al m Ga n In (1-mn) N, where 0<m<1, 0<n<1, and 0<m+n≦1, when m When =s, n≠t; when n=t, m≠s.
在本發明之一實施例中，上述之每一組氮化鋁鎵銦結構層的 厚度介於5奈米至500奈米之間。 In an embodiment of the invention, each of the above groups of aluminum gallium indium nitride structural layers The thickness is between 5 nm and 500 nm.
在本發明之一實施例中，上述之超晶格結構層的厚度介於20奈米至5000奈米之間。 In an embodiment of the invention, the superlattice structure layer has a thickness of between 20 nm and 5000 nm.
在本發明之一實施例中，上述之超晶格結構層包括5組以上的氮化鋁鎵銦結構層。 In an embodiment of the invention, the superlattice structure layer comprises five or more sets of aluminum gallium indium nitride structural layers.
在本發明之一實施例中，上述之半導體結構可進一步包括一基板，其中氮化鋁層配置於基板上。 In an embodiment of the invention, the semiconductor structure may further include a substrate, wherein the aluminum nitride layer is disposed on the substrate.
本發明另提出一種半導體結構，其包括一氮化鋁層以及多組漸變式應力緩衝層。漸變式應力緩衝層配置於氮化鋁層上。每一組漸變式應力緩衝層包括依序堆疊的一漸變層及一過渡層。這些漸變層的化學通式為Al1-xGaxN，其中x值從鄰近氮化鋁層之一側往遠離氮化鋁層之方向逐漸遞增，且0≦x≦1。每一過渡層與同組中的漸變層中最遠離氮化鋁層之一側表面具有相同的化學通式，且最遠離氮化鋁層的這組漸變式應力緩衝層中的過渡層的化學通式為GaN。此外，漸變式應力緩衝層之過渡層的厚度由鄰近氮化鋁層之一側往遠離氮化鋁層之方向遞增。 The invention further provides a semiconductor structure comprising an aluminum nitride layer and a plurality of sets of graded stress buffer layers. The graded stress buffer layer is disposed on the aluminum nitride layer. Each set of graded stress buffer layers includes a graded layer and a transition layer stacked in sequence. These graded layers have a chemical formula of Al 1-x Ga x N, wherein the value of x gradually increases from the side adjacent to the aluminum nitride layer toward the direction away from the aluminum nitride layer, and 0 ≦ x ≦ 1. Each transition layer has the same chemical formula as the side surface of the graded layer in the same group farthest from the aluminum nitride layer, and the transition layer in the set of graded stress buffer layers farthest from the aluminum nitride layer The general formula is GaN. In addition, the thickness of the transition layer of the graded stress buffer layer is increased from the side adjacent to the aluminum nitride layer toward the direction away from the aluminum nitride layer.
本發明另提出一種半導體結構，其包括一氮化鋁層以及多組漸變式應力緩衝層。漸變式應力緩衝層配置於氮化鋁層上。每一組漸變式應力緩衝層包括依序堆疊的一漸變層及一過渡層。這些漸變層的化學通式為Al1-xGaxN，其中x值從鄰近氮化鋁層之一側往遠離氮化鋁層之方向逐漸遞增，且0≦x≦1。每一過渡層與同組中的漸變層中最遠離氮化鋁層之一側表面具有相同的化學通式，且最遠離氮化鋁層的 這組漸變式應力緩衝層中的過渡層的化學通式為GaN，其中各該漸變層的厚度介於50奈米到700奈米之間。 The invention further provides a semiconductor structure comprising an aluminum nitride layer and a plurality of sets of graded stress buffer layers. The graded stress buffer layer is disposed on the aluminum nitride layer. Each set of graded stress buffer layers includes a graded layer and a transition layer stacked in sequence. These graded layers have a chemical formula of Al 1-x Ga x N, wherein the value of x gradually increases from the side adjacent to the aluminum nitride layer toward the direction away from the aluminum nitride layer, and 0 ≦ x ≦ 1. Each transition layer has the same chemical formula as the side surface of the graded layer in the same group farthest from the aluminum nitride layer, and the transition layer in the set of graded stress buffer layers farthest from the aluminum nitride layer The general formula is GaN, wherein each of the graded layers has a thickness of between 50 nm and 700 nm.
基於上述，由於本發明之氮化鋁層上配置有多組漸變式應力緩衝層，藉此逐漸提高鎵的含量，最終獲得一氮化鎵層。如此一來，可有效降低晶格差排在厚度方向上的延伸現象，進而提升整體半導體結構的品質。 Based on the above, since the aluminum nitride layer of the present invention is provided with a plurality of sets of graded stress buffer layers, thereby gradually increasing the content of gallium, a gallium nitride layer is finally obtained. In this way, the extension of the lattice difference in the thickness direction can be effectively reduced, thereby improving the quality of the overall semiconductor structure.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100a、100b、100c‧‧‧半導體結構 100a, 100b, 100c‧‧‧ semiconductor structure
110‧‧‧矽基板 110‧‧‧矽 substrate
112、1422a、1422b、1422c、1422d‧‧‧表面 112, 1422a, 1422b, 1422c, 1422d‧‧‧ surface
120‧‧‧氮化鋁層 120‧‧‧Aluminum nitride layer
140a、140b、140c、140d‧‧‧漸變式應力緩衝層 140a, 140b, 140c, 140d‧‧‧graded stress buffer layer
142a、142b、142c、142d‧‧‧漸變層 142a, 142b, 142c, 142d‧‧‧grading layer
144a、144b、144c、144d‧‧‧過渡層 144a, 144b, 144c, 144d‧‧‧ transition layer
150a、150b‧‧‧超晶格結構層 150a, 150b‧‧‧ superlattice structural layer
151a1、151a2、151b1、151b2‧‧‧第一氮化鋁鎵銦層 151a1, 151a2, 151b1, 151b2‧‧‧ first aluminum gallium indium nitride layer
153a1、153a2、153b1、153b2‧‧‧第二氮化鋁鎵銦層 153a1, 153a2, 153b1, 153b2‧‧‧ second aluminum gallium indium nitride layer
152a1、152a2、152b1、152b2‧‧‧氮化鋁鎵銦結構層 152a1, 152a2, 152b1, 152b2‧‧‧ aluminum nitride indium structure layer
h1、h1’、h2、h2’、h3、h3’、h4、h4’、t、t1、t2、t’、t1’、t2’‧‧‧厚度 H1, h1', h2, h2', h3, h3', h4, h4', t, t1, t2, t', t1', t2'‧‧‧ thickness
圖1繪示為本發明之一實施例之一種半導體結構的剖面示意圖。 1 is a cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention.
圖2繪示為本發明之另一實施例之一種半導體結構的剖面示意圖。 2 is a cross-sectional view showing a semiconductor structure in accordance with another embodiment of the present invention.
圖3繪示為本發明之又一實施例之一種半導體結構的剖面示意圖。 3 is a cross-sectional view showing a semiconductor structure according to still another embodiment of the present invention.
首先，在以下實施例的描述中，應當理解當指出一層(或膜)或一結構配置在另一個基板、另一層(或膜)、或另一結構“上”或“下”時，其可“直接”位於其他基板、層(或膜)、或另一結構，亦或者兩者間具有一個以上的中間層以“間接”方式配置，審查委員可參照附圖說明每一層所在位置。 First, in the following description of the embodiments, it should be understood that when a layer (or film) or a structure is disposed on another substrate, another layer (or film), or another structure "on" or "down", "Directly" is located in another substrate, layer (or film), or another structure, or has more than one intermediate layer disposed therebetween in an "indirect" manner. The review panel may describe the location of each layer with reference to the drawings.
圖1繪示為本發明之一實施例之一種半導體結構的剖面示意圖。請參考圖1，在本實施例中，半導體結構100a包括一矽基板110、一氮化鋁層120以及多組漸變式應力緩衝層140a、140b、140c、140d(圖1中僅示意地繪示四組)。矽基板110具有一上表面112。氮化鋁層120配置於矽基板110的上表面112上。這些組漸變式應力緩衝層140a、140b、140c、140d配置於氮化鋁層120上。每一組漸變式應力緩衝層140a(或140b、140c、140d)包括依序堆疊的一漸變層142a(或142b、142c、142d)及一過渡層144a(或144b、144c、144d)。漸變層142a、142b、142c、142d的化學通式為Al1-xGaxN，特別是，x值從鄰近矽基板110之上表面112往遠離矽基板110之上表面112逐漸遞增，且x值為0≦x≦1。每一過渡層144a(或144b、144c、144d)與同組中的漸變層142a(或142b、142c、142d)中最遠離矽基板之一側表面1422a(或1422b、1422c、1422d)具有相同的元素組成。 1 is a cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention. Referring to FIG. 1, in the embodiment, the semiconductor structure 100a includes a germanium substrate 110, an aluminum nitride layer 120, and a plurality of sets of tapered stress buffer layers 140a, 140b, 140c, 140d (only schematically shown in FIG. 1). Four groups). The germanium substrate 110 has an upper surface 112. The aluminum nitride layer 120 is disposed on the upper surface 112 of the tantalum substrate 110. The set of graded stress buffer layers 140a, 140b, 140c, 140d are disposed on the aluminum nitride layer 120. Each set of graded stress buffer layers 140a (or 140b, 140c, 140d) includes a graded layer 142a (or 142b, 142c, 142d) and a transition layer 144a (or 144b, 144c, 144d) stacked in sequence. The chemical formula of the graded layers 142a, 142b, 142c, 142d is Al 1-x Ga x N, in particular, the value of x gradually increases from the upper surface 112 of the adjacent germanium substrate 110 to the upper surface 112 away from the germanium substrate 110, and x The value is 0≦x≦1. Each of the transition layers 144a (or 144b, 144c, 144d) has the same as the one of the graded layers 142a (or 142b, 142c, 142d) in the same group farthest from the 矽 substrate side surface 1422a (or 1422b, 1422c, 1422d). Elemental composition.
舉例來說，本實施例之漸變式應力緩衝層140a之漸變層142a的化學通式中的x值例如是介於0至0.25，也就是說，漸變層142a之Al含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之一側逐漸遞減，即Al含量由1逐漸遞減至0.75；而Ga含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之方向逐漸遞增，即Ga含量由0逐漸遞增至0.25；且過渡層144a和漸變層142a中最遠離矽基板之一側表面1422a具有相同的元素組成，即過渡層144a的化學通式為Al0.75Ga0.25N。 For example, the value of x in the chemical formula of the graded layer 142a of the graded stress buffer layer 140a of the present embodiment is, for example, 0 to 0.25, that is, the Al content of the graded layer 142a is adjacent to the aluminum nitride layer. One side of 120 is gradually decreased toward one side away from the aluminum nitride layer 120, that is, the Al content is gradually decreased from 1 to 0.75; and the Ga content is gradually changed from the side adjacent to the aluminum nitride layer 120 toward the direction away from the aluminum nitride layer 120. Increasingly, that is, the Ga content is gradually increased from 0 to 0.25; and the transition layer 144a and the gradient layer 142a have the same elemental composition farthest from the side surface 1422a of the germanium substrate, that is, the chemical formula of the transition layer 144a is Al 0.75 Ga 0.25 N .
同理，本實施例之漸變式應力緩衝層140b之漸變層142b的化學通式中的x值例如是介於0.25至0.5，也就是說，漸變層142b之 Al含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之一側逐漸遞減，即Al含量由0.75逐漸遞減至0.5；而Ga含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之方向逐漸遞增，即Ga含量由0.25逐漸遞增至0.5；且過渡層144b和漸變層142b最遠離矽基板之一側表面1422b具有相同的元素組成，即過渡層144b的化學通式為Al0.5Ga0.5N。 Similarly, the value of x in the chemical formula of the graded layer 142b of the graded stress buffer layer 140b of the present embodiment is, for example, 0.25 to 0.5, that is, the Al content of the graded layer 142b is adjacent to the aluminum nitride layer 120. One side gradually decreases away from one side of the aluminum nitride layer 120, that is, the Al content gradually decreases from 0.75 to 0.5; and the Ga content gradually increases from the side adjacent to the aluminum nitride layer 120 toward the direction away from the aluminum nitride layer 120. That is, the Ga content is gradually increased from 0.25 to 0.5; and the transition layer 144b and the graded layer 142b have the same elemental composition farthest from the side surface 1422b of the tantalum substrate, that is, the chemical formula of the transition layer 144b is Al 0.5 Ga 0.5 N.
漸變式應力緩衝層140c之漸變層142c的化學通式中的x值例如是介於0.5至0.75，也就是說，漸變層142c之Al含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之一側逐漸遞減，即Al含量由0.5逐漸遞減至0.25；而Ga含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之方向逐漸遞增，即Ga含量由0.5逐漸遞增至0.75；且過渡層144c和漸變層142c中最遠離矽基板之一側表面1422c具有相同的元素組成，即過渡層144c的化學通式為Al0.25Ga0.75N。 The value of x in the chemical formula of the graded layer 142c of the graded stress buffer layer 140c is, for example, between 0.5 and 0.75, that is, the Al content of the graded layer 142c is from the side adjacent to the aluminum nitride layer 120 to away from the nitride. One side of the aluminum layer 120 is gradually decreased, that is, the Al content is gradually decreased from 0.5 to 0.25; and the Ga content is gradually increased from the side adjacent to the aluminum nitride layer 120 toward the direction away from the aluminum nitride layer 120, that is, the Ga content is gradually increased from 0.5. Increasing to 0.75; and the transition layer 144c and the graded layer 142c have the same elemental composition farthest from the tantalum substrate side surface 1422c, that is, the transition layer 144c has a chemical formula of Al 0.25 Ga 0.75 N.
漸變式應力緩衝層140d之漸變層142d的化學通式中的x值例如是介於0.75至1，也就是說，漸變層142d之Al含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之一側逐漸遞減，即Al含量由0.25逐漸遞減至0；而Ga含量由鄰近氮化鋁層120之一側往遠離氮化鋁層120之方向逐漸遞增，即Ga含量由0.75逐漸遞增至1。特別是，最遠離矽基板110的漸變式應力緩衝層140d中的過渡層144和漸變層142d中最遠離矽基板之一側表面1422d具有相同的元素組成，即最後一個過渡層144d的化學通式為GaN。 The value of x in the chemical formula of the graded layer 142d of the graded stress buffer layer 140d is, for example, between 0.75 and 1, that is, the Al content of the graded layer 142d is from the side adjacent to the aluminum nitride layer 120 to away from the nitride. One side of the aluminum layer 120 gradually decreases, that is, the Al content gradually decreases from 0.25 to 0; and the Ga content gradually increases from the side adjacent to the aluminum nitride layer 120 toward the direction away from the aluminum nitride layer 120, that is, the Ga content gradually increases from 0.75. Increase to 1. In particular, the transition layer 144 in the tapered stress buffer layer 140d farthest from the ruthenium substrate 110 and the one side surface 1422d of the gradation layer 142d farthest from the ruthenium substrate have the same elemental composition, that is, the chemical formula of the last transition layer 144d. It is GaN.
也就是說，這些組漸變式應力緩衝層140a、140b、140c、140d之過渡層144a、144b、144c、144d之化學通式中的x值(即鎵含量) 是以等差級數逐漸遞增，意即鋁含量呈等差級數逐漸減少。當然，於其他實施例中，這些過渡層144a、144b、144c、144d之化學通式中的x值亦可以是呈非等差級數而逐漸遞增，於此並不加以限制。 That is, the x value (ie, the gallium content) in the chemical formula of the transition layers 144a, 144b, 144c, 144d of the set of graded stress buffer layers 140a, 140b, 140c, 140d The increase in the number of steps is gradually increasing, which means that the aluminum content is gradually reduced in the order of the difference. Of course, in other embodiments, the value of x in the chemical formula of the transition layers 144a, 144b, 144c, and 144d may also be gradually increased in a non-equal order, and is not limited herein.
再者，這些組漸變式應力緩衝層140a、140b、140c、140d之這些漸變層142a、142b、142c、142d的厚度h1、h2、h3、h4由鄰近矽基板110之上表面112往遠離矽基板110之上表面112逐漸遞增。也就是說，漸變層142a的厚度h1小於漸變層142b的厚度h2，漸變層142b的厚度h2小於漸變層142c的厚度h3，而漸變層142c的厚度h3小於漸變層142d的厚度h4。此處，較佳地，每一漸變層142a(或142b、142c、142d)的厚度h1(或h2、h3、h4)之厚度介於50奈米到700奈米之間，其中，需說明的是，厚度介於此範圍內的漸變層其磊晶品質較穩定且不易產生缺陷。 Moreover, the thicknesses h1, h2, h3, h4 of the graded layers 142a, 142b, 142c, 142d of the set of progressive stress buffer layers 140a, 140b, 140c, 140d are adjacent to the upper surface 112 of the germanium substrate 110 away from the germanium substrate. The surface 112 above 110 gradually increases. That is, the thickness h1 of the gradation layer 142a is smaller than the thickness h2 of the gradation layer 142b, the thickness h2 of the gradation layer 142b is smaller than the thickness h3 of the gradation layer 142c, and the thickness h3 of the gradation layer 142c is smaller than the thickness h4 of the gradation layer 142d. Here, preferably, the thickness h1 (or h2, h3, h4) of each of the graded layers 142a (or 142b, 142c, 142d) is between 50 nm and 700 nm, wherein Yes, the graded layer having a thickness within this range has a stable epitaxial quality and is less prone to defects.
此外，這些組漸變式應力緩衝層140a、140b、140c、140d之這些過渡層144a、144b、144c、144d的厚度由鄰近矽基板110之上表面112往遠離矽基板110之上表面112逐漸遞增。也就是說，過渡層144a的厚度h1’小於過渡層144b的厚度h2’，過渡層144b的厚度h2’小於過渡層144c的厚度h3’，而過渡層144c的厚度h3’小於過渡層144d的厚度h4’。此處，較佳地，每一過渡層144a(或144b、144c、144d)的厚度h1’(或h2’、h3’、h4’)介於50奈米到700奈米之間，其中，需說明的是，厚度介於此範圍內的漸變層其磊晶品質較穩定且不易產生缺陷。 Moreover, the thickness of the transition layers 144a, 144b, 144c, 144d of the set of graded stress buffer layers 140a, 140b, 140c, 140d is gradually increased from the upper surface 112 of the substrate 110 away from the upper surface 112 of the substrate 110. That is, the thickness h1' of the transition layer 144a is smaller than the thickness h2' of the transition layer 144b, the thickness h2' of the transition layer 144b is smaller than the thickness h3' of the transition layer 144c, and the thickness h3' of the transition layer 144c is smaller than the thickness of the transition layer 144d. H4'. Here, preferably, the thickness h1' (or h2', h3', h4') of each of the transition layers 144a (or 144b, 144c, 144d) is between 50 nm and 700 nm, wherein It is noted that the graded layer having a thickness within this range has a stable epitaxial quality and is less prone to defects.
在本實施例之半導體結構100a中，漸變式應力緩衝層140a、 140b、140c、140d配置於氮化鋁層120上，其中這些過渡層144a、144b、144c、144d中的鋁含量是以等差級數逐漸遞減，而鎵含量是以等差級數逐漸遞增，且過渡層144a、144b、144c、144d則與同組中的漸變層142a、142b、142c、142d中最遠離矽基板110的一側表面1422a(或1422b、1422c、1422d)具有相同鋁含量及鎵含量。如此一來，最終可獲得一氮化鎵層(即過渡層144d)，並可藉由漸變式應力緩衝層140a、140b、140c、140d來降低氮化鎵層(即過渡層144d)與矽基板110之間因膨脹係數及晶格的差異所造成應力，意即漸變式應力緩衝層140a、140b、140c、140d具有釋放應力之功效之外，亦可有效降低習知晶格差排在厚度方向上的延伸現象，進而提升整體半導體結構100a的品質。 In the semiconductor structure 100a of the present embodiment, the graded stress buffer layer 140a, 140b, 140c, 140d are disposed on the aluminum nitride layer 120, wherein the aluminum content in the transition layers 144a, 144b, 144c, 144d is gradually decreased by an order of difference, and the gallium content is gradually increased by an order of difference. And the transition layers 144a, 144b, 144c, 144d have the same aluminum content and gallium as the one side surface 1422a (or 1422b, 1422c, 1422d) farthest from the germanium substrate 110 among the graded layers 142a, 142b, 142c, 142d in the same group. content. In this way, a gallium nitride layer (ie, the transition layer 144d) is finally obtained, and the gallium nitride layer (ie, the transition layer 144d) and the germanium substrate can be reduced by the graded stress buffer layers 140a, 140b, 140c, and 140d. The stress caused by the difference in expansion coefficient and lattice between 110, that is, the gradient stress buffer layers 140a, 140b, 140c, 140d have the effect of releasing stress, and can also effectively reduce the extension of the conventional lattice difference in the thickness direction. The phenomenon further enhances the quality of the overall semiconductor structure 100a.
當然，圖1中所繪示的這些組漸變式應力緩衝層140a、140b、140c、140d的組數僅是作為舉例說明之用，本領域的技術人員當可依據實際狀況調整鋁含量及鎵含量而增加組數，意即若x值(即鎵含量)是以0.1的差距呈等差級數逐漸遞增，則漸變式應力緩衝層的組數為10組，以符合減緩矽基板110與氮化鎵層(即過渡層144d)之間因膨脹係數及晶格的差異所造成應力，此處不再逐一贅述。 Of course, the number of sets of the group of progressive stress buffer layers 140a, 140b, 140c, and 140d illustrated in FIG. 1 is for illustrative purposes only, and those skilled in the art can adjust the aluminum content and the gallium content according to actual conditions. Increasing the number of groups means that if the x value (ie, the gallium content) is gradually increased by the difference of 0.1, the number of groups of the gradual stress buffer layer is 10 groups to conform to the slowing of the ruthenium substrate 110 and nitridation. The stress caused by the difference in expansion coefficient and lattice between the gallium layer (ie, the transition layer 144d) will not be described one by one.
在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。 It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.
圖2繪示為本發明之另一實施例之一種半導體結構的剖面示 意圖。請參考圖2，本實施例之半導體結構100b與圖1之半導體結構100a相似，其不同之處在於：本實施例之半導體結構100b更包括一超晶格結構層150a，其中超晶格結構層150a配置於氮化鋁層120與這些組漸變式應力緩衝層140a、140b、140c、140d之間。 2 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention. intention. Referring to FIG. 2, the semiconductor structure 100b of the present embodiment is similar to the semiconductor structure 100a of FIG. 1 except that the semiconductor structure 100b of the present embodiment further includes a superlattice structure layer 150a, wherein the superlattice structure layer 150a is disposed between the aluminum nitride layer 120 and the set of graded stress buffer layers 140a, 140b, 140c, 140d.
更具體來說，超晶格結構層150a配置於氮化鋁層120與漸變式應力緩衝層140a之間，且超晶格結構層150a包括多組氮化鋁鎵銦結構層152a1、152a2(圖2中僅示意地繪示兩組)。每一組氮化鋁鎵銦結構層152a1(或152a2)包括相互堆疊的一第一氮化鋁鎵銦層151a1(或151a2)以及一第二氮化鋁鎵銦層153a1(或153a2)。這些第一氮化鋁鎵銦層151a1、151a2的化學通式為AlsGatIn(1-s-t)N，其中s值為0<s<1，t值為0<t<1，且0<s+t≦1。這些第二氮化鋁鎵銦層153a1、153a2的化學通式為AlmGanIn(1-m-n)N，其中0<m<1，0<n<1，且0<m+n≦1，當m=s時，n≠t；當n=t時，m≠s。也就是說，第一氮化鋁鎵銦層151a1(或151a2)及第二氮化鋁鎵銦層153a1(或153a2)之元素組成比例不能完全相同。 More specifically, the superlattice structure layer 150a is disposed between the aluminum nitride layer 120 and the graded stress buffer layer 140a, and the superlattice structure layer 150a includes a plurality of sets of aluminum gallium indium nitride structural layers 152a1, 152a2 (Fig. Only two groups are shown schematically in 2). Each set of aluminum gallium indium nitride structural layer 152a1 (or 152a2) includes a first aluminum gallium indium layer 151a1 (or 151a2) and a second aluminum gallium indium layer 153a1 (or 153a2) stacked on each other. The first aluminum gallium indium nitride layers 151a1, 151a2 have a chemical formula of Al s Ga t In (1-st) N, wherein the s value is 0 < s < 1, and the t value is 0 < t < 1, and 0 <s+t≦1. The chemical formula of these second aluminum gallium indium layers 153a1, 153a2 is Al m Ga n In (1-mn) N, where 0 < m < 1, 0 < n < 1, and 0 < m + n ≦ 1 When m=s, n≠t; when n=t, m≠s. That is, the elemental composition ratios of the first aluminum gallium indium nitride layer 151a1 (or 151a2) and the second aluminum gallium indium nitride layer 153a1 (or 153a2) may not be identical.
舉例來說，本實施例之氮化鋁鎵銦結構層152a1之第一氮化鋁鎵銦層151a1的化學通式可為Al0.3Ga0.2In0.5N，而第二氮化鋁鎵銦層153a1的化學通式可為Al0.3Ga0.4In0.3N。此外，本實施例之每一組氮化鋁鎵銦結構層152a1(或152a2)的厚度t1、t2例如是介於5奈米至500奈米之間。超晶格結構層150a的厚度t例如是介於20奈米至5000奈米之間，較佳地，這些組氮化鋁鎵銦結構層152a1、152a2的組數至少為五組。由於氮化鋁層120與漸變式應力緩衝層140a之間配置有超晶 格結構層150a，因此可輔助減緩漸變式應力緩衝層140a與矽基板110之間因膨脹係數及晶格的差異所造成應力，也可阻擋在超晶格結構層150a成長前已形成之差排，使差排無法繼續向上成長，進而提升整體半導體結構100b的品質。 For example, the first aluminum gallium indium layer 151a1 of the aluminum gallium indium structure layer 152a1 of the present embodiment may have a chemical formula of Al 0.3 Ga 0.2 In 0.5 N, and the second aluminum gallium indium layer 153a1 The chemical formula can be Al 0.3 Ga 0.4 In 0.3 N. In addition, the thicknesses t1 and t2 of each set of the aluminum gallium indium nitride structural layer 152a1 (or 152a2) of the present embodiment are, for example, between 5 nm and 500 nm. The thickness t of the superlattice structure layer 150a is, for example, between 20 nm and 5000 nm. Preferably, the number of sets of the aluminum nitride indium structure layers 152a1, 152a2 is at least five. Since the superlattice structure layer 150a is disposed between the aluminum nitride layer 120 and the graded stress buffer layer 140a, it can assist in slowing down the difference between the gradient stress buffer layer 140a and the germanium substrate 110 due to the difference in expansion coefficient and lattice. The stress can also block the difference formed before the growth of the superlattice structure layer 150a, so that the difference row cannot continue to grow upward, thereby improving the quality of the overall semiconductor structure 100b.
圖3繪示為本發明之再一實施例之一種半導體結構的剖面示意圖。請參考圖3，本實施例之半導體結構100c與圖1之半導體結構100a相似，其不同之處在於：本實施例之半導體結構100c更包括一超晶格結構層150b，其中超晶格結構層150b配置於漸變式應力緩衝層140a與漸變式應力緩衝層140b之間。超晶格結構層150b包括多組氮化鋁鎵銦結構層152b1、152b2，每一組氮化鋁鎵銦結構層152b1(或152b2)包括相互堆疊的一第一氮化鋁鎵銦層151b1(或151b2)以及一第二氮化鋁鎵銦層153b1(或153b2)。這些第一氮化鋁鎵銦層151b1、151b2)的化學通式為AlsGatIn(1-s-t)N，其中s值為0<s<1，t值為0<t<1，且0<s+t≦1。這些第二氮化鋁鎵銦層153b1、153b2的化學通式為AlmGanIn(1-m-n)N，其中m值為0<m<1，n值為0<n<1，且0<m+n≦1，當m=s時，n≠t；當n=t時，m≠s。也就是說，第一氮化鋁鎵銦層151b1(或151b2)及第二氮化鋁鎵銦層153b1(或153b2)之元素組成比例不能完全相同。 3 is a cross-sectional view showing a semiconductor structure in accordance with still another embodiment of the present invention. Referring to FIG. 3, the semiconductor structure 100c of the present embodiment is similar to the semiconductor structure 100a of FIG. 1, except that the semiconductor structure 100c of the present embodiment further includes a superlattice structure layer 150b, wherein the superlattice structure layer 150b is disposed between the graded stress buffer layer 140a and the graded stress buffer layer 140b. The superlattice structure layer 150b includes a plurality of sets of aluminum gallium indium nitride structural layers 152b1, 152b2, and each set of aluminum gallium indium structure layers 152b1 (or 152b2) includes a first aluminum gallium indium nitride layer 151b1 stacked on each other ( Or 151b2) and a second aluminum gallium indium nitride layer 153b1 (or 153b2). The first aluminum gallium indium nitride layers 151b1, 151b2) have a chemical formula of Al s Ga t In (1-st) N, wherein the s value is 0 < s < 1, and the t value is 0 < t < 1, and 0<s+t≦1. The second aluminum gallium indium nitride layers 153b1, 153b2 have a chemical formula of Al m Ga n In (1-mn) N, wherein the m value is 0 < m < 1, and the n value is 0 < n < 1, and 0 <m+n≦1, when m=s, n≠t; when n=t, m≠s. That is, the elemental composition ratios of the first aluminum gallium indium nitride layer 151b1 (or 151b2) and the second aluminum gallium indium nitride layer 153b1 (or 153b2) may not be identical.
舉例來說，本實施例之氮化鋁鎵銦結構層152b1之第一氮化鋁鎵銦層151b1的化學通式可為Al0.3Ga0.2In0.5N，而第二氮化鋁鎵銦層153b1的化學通式可為Al0.3Ga0.4In0.3N。此外，本實施例之每一組氮化鋁鎵銦結構層152b1、152b2的厚度t1’、t2’例如是介於5奈米至500 奈米之間。超晶格結構層150b的厚度t’例如是介於20奈米至5000奈米之間，較佳地，這些組氮化鋁鎵銦結構層152b1、152b2的組數至少為五組。由於相鄰的這些漸變式應力緩衝層140a、140b之間配置有超晶格結構層150b，因此可輔助減緩漸變式應力緩衝層140a、140b之間因膨脹係數及晶格的差異所造成應力，也可阻擋在超晶格結構層150b成長前已形成之差排，使差排無法繼續向上成長，進而提升整體半導體結構100c的品質。 For example, the first aluminum gallium indium layer 151b1 of the aluminum gallium indium structural layer 152b1 of the present embodiment may have a chemical formula of Al 0.3 Ga 0.2 In 0.5 N and a second aluminum gallium indium layer 153 b1. The chemical formula can be Al 0.3 Ga 0.4 In 0.3 N. In addition, the thicknesses t1', t2' of each set of the aluminum gallium indium structure layers 152b1, 152b2 of the present embodiment are, for example, between 5 nm and 500 nm. The thickness t' of the superlattice structure layer 150b is, for example, between 20 nm and 5000 nm. Preferably, the number of sets of the aluminum nitride indium structure layers 152b1, 152b2 is at least five. Since the superlattice structure layer 150b is disposed between the adjacent gradual stress buffer layers 140a and 140b, the stress caused by the difference in expansion coefficient and lattice difference between the gradual stress buffer layers 140a and 140b can be assisted. It is also possible to block the difference formed before the growth of the superlattice structure layer 150b, so that the difference row cannot continue to grow upward, thereby improving the quality of the overall semiconductor structure 100c.
值得一提的是，本發明並不限定這些超晶格結構150a、150b的位置與型態，雖然此處所提及的超晶格結構150a、150b具體化為位於氮化鋁層120與漸變式應力緩衝層140a之間，或者是，位於漸變式應力緩衝層140a與漸變式應力緩衝層140b之間。但於其他未繪示的實施例中，超晶格結構亦可配置於這些組漸變式應力緩衝層140a、140b、140c、140d中任2相鄰層之間，如漸變層142a和過渡層144a之間，或是漸變層142c和過渡層144c之間；或者是，超晶格結構層亦可同時配置於氮化鋁層120與漸變式應力緩衝層140a之間以及這些組漸變式應力緩衝層140a、140b、140c、140d中任兩相鄰組之間。本領域的技術人員當可依據實際狀況調整或增加超晶格結構的設置，以符合減緩差排的現象，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。 It is worth mentioning that the present invention does not limit the position and configuration of these superlattice structures 150a, 150b, although the superlattice structures 150a, 150b referred to herein are embodied as being located in the aluminum nitride layer 120 and the gradient. Between the stress buffer layers 140a, or between the graded stress buffer layer 140a and the graded stress buffer layer 140b. However, in other embodiments not shown, the superlattice structure may also be disposed between any two adjacent layers of the set of graded stress buffer layers 140a, 140b, 140c, 140d, such as a graded layer 142a and a transition layer 144a. Between the gradient layer 142c and the transition layer 144c; or, the superlattice structure layer may be simultaneously disposed between the aluminum nitride layer 120 and the graded stress buffer layer 140a and the set of gradient stress buffer layers Between two adjacent groups of 140a, 140b, 140c, 140d. Those skilled in the art can adjust or increase the setting of the superlattice structure according to the actual situation to conform to the phenomenon of mitigating the difference, and still belong to the technical solution that can be adopted by the present invention without departing from the scope of the present invention.
綜上所述，由於本發明之氮化鋁層上配置有多組漸變式應力緩衝層，藉此逐漸提高鎵的含量，最終獲得一氮化鎵層，如此可有效降低氮化鎵層與矽基的晶格差異所產生的應力，以及可有效降低晶格 差排在厚度方向上的延伸現象，進而提升整體半導體結構的品質。 In summary, since the aluminum nitride layer of the present invention is provided with a plurality of sets of gradual stress buffer layers, thereby gradually increasing the content of gallium, and finally obtaining a gallium nitride layer, thereby effectively reducing the gallium nitride layer and the germanium layer. The stress generated by the lattice difference of the base, and the lattice can be effectively reduced The extension of the difference in the thickness direction enhances the quality of the overall semiconductor structure.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100a‧‧‧半導體結構 100a‧‧‧Semiconductor structure
110‧‧‧矽基板 110‧‧‧矽 substrate
112、1422a、1422b、1422c、1422d‧‧‧表面 112, 1422a, 1422b, 1422c, 1422d‧‧‧ surface
120‧‧‧氮化鋁層 120‧‧‧Aluminum nitride layer
140a、140b、140c、140d‧‧‧漸變式應力緩衝層 140a, 140b, 140c, 140d‧‧‧graded stress buffer layer
142a、142b、142c、142d‧‧‧漸變層 142a, 142b, 142c, 142d‧‧‧grading layer
144a、144b、144c、144d‧‧‧過渡層 144a, 144b, 144c, 144d‧‧‧ transition layer
h1、h1’、h2、h2’、h3、h3’、h4、h4’‧‧‧厚度 H1, h1', h2, h2', h3, h3', h4, h4'‧‧‧ thickness
Claims (21)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104114223A TWI562402B (en) | 2012-12-06 | 2012-12-06 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104114223A TWI562402B (en) | 2012-12-06 | 2012-12-06 | Semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201532306A true TW201532306A (en) | 2015-08-16 |
| TWI562402B TWI562402B (en) | 2016-12-11 |
Family
ID=54343202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104114223A TWI562402B (en) | 2012-12-06 | 2012-12-06 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI562402B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI602248B (en) * | 2016-08-31 | 2017-10-11 | 聯鈞光電股份有限公司 | Nitride semiconductor structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2650744B2 (en) * | 1988-12-28 | 1997-09-03 | シャープ株式会社 | Light emitting diode |
| US6649287B2 (en) * | 2000-12-14 | 2003-11-18 | Nitronex Corporation | Gallium nitride materials and methods |
| KR100756841B1 (en) * | 2006-03-13 | 2007-09-07 | 서울옵토디바이스주식회사 | Light emitting diode having graded buffer layer and fabrication method thereof |
| JP2009026865A (en) * | 2007-07-18 | 2009-02-05 | Toyoda Gosei Co Ltd | Manufacturing method of group iii nitride-based compound semiconductor light emitting element |
| TWI466314B (en) * | 2008-03-05 | 2014-12-21 | Advanced Optoelectronic Tech | Light emitting device of iii-nitride based semiconductor |
| WO2011055774A1 (en) * | 2009-11-06 | 2011-05-12 | 日本碍子株式会社 | Epitaxial substrate for semiconductor element, semiconductor element, and method for producing epitaxial substrate for semiconductor element |
| JP2013514662A (en) * | 2009-12-16 | 2013-04-25 | ナショナル セミコンダクター コーポレーション | Low ohmic contacts with germanium for gallium nitride or other nitride based power devices |
-
2012
- 2012-12-06 TW TW104114223A patent/TWI562402B/en active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI602248B (en) * | 2016-08-31 | 2017-10-11 | 聯鈞光電股份有限公司 | Nitride semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI562402B (en) | 2016-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI495154B (en) | Semiconductor structure | |
| US8664638B2 (en) | Light-emitting diode having an interlayer with high voltage density and method for manufacturing the same | |
| JP5462377B1 (en) | Group III nitride epitaxial substrate and manufacturing method thereof | |
| JP5113120B2 (en) | Semiconductor device manufacturing method and structure thereof | |
| WO2015143902A1 (en) | Multi-quantum well structure and light-emitting diode using same | |
| TWI683372B (en) | Semiconductor device and method of forming the same | |
| US20180138367A1 (en) | Nitride Light Emitting Diode and Growth Method | |
| JP2014053611A (en) | Semiconductor buffer structure and semiconductor element including the same, and manufacturing method of the same | |
| CN103972344A (en) | Semiconductor structure | |
| JP2017092442A (en) | Ultraviolet light emitting diode | |
| TWI528582B (en) | Light emitting structure and semiconductor light emitting element having the same | |
| KR20150023533A (en) | Semiconductor laminate structure and semiconductor element | |
| US9660137B2 (en) | Method for producing a nitride compound semiconductor device | |
| TWI570911B (en) | Semiconductor structure | |
| TW201532306A (en) | Semiconductor structure | |
| CN101483212B (en) | Group III nitride compound semiconductor LED and method for manufacturing the same | |
| KR20080088221A (en) | Light emitting diode having well layer of superlattice structure | |
| CN109560174A (en) | A kind of LED epitaxial structure and preparation method thereof | |
| CN113838954B (en) | LED (light-emitting diode) epitaxy and manufacturing method thereof | |
| US9472624B2 (en) | Semiconductor buffer structure, semiconductor device including the same, and manufacturing method thereof | |
| TWI445055B (en) | Fabrication method of nitride forming on silicon substrate | |
| TWI398908B (en) | Method for forming semiconductor layer | |
| US20150380605A1 (en) | Semiconductor structure | |
| TWI475726B (en) | Light-emitting diode and a method of manufacturing the same | |
| CN113725327A (en) | GaN-based green light LED epitaxial structure and preparation method and application thereof |