TW201527957A - Driving circuit - Google Patents

Abstract

The present disclosure relates to a driving circuit including a controlling circuit, a PCH, and a slot. An output port of the PCH is electrically connected to the slot. The slot is configured to insert a function card. The controlling circuit includes a first output resistance, a second output resistance, an electronic switch, and a jumper. The jumper includes a first pin, a second pin, and a third pin. The first pin is electrically connected to a power source. The third pin is electrically connected to the ground. The electronic switch includes a controlling port, a first switch port, and a second switch port. The controlling port is electrically connected to the second pin. The first switch port is electrically connected to the ground through the first output resistance and the second output resistance. A node formed between the first output resistance and the second output resistance is electrically connected to a bias adjusting pin of the PCH.

Description

Drive circuit

The invention relates to a drive circuit.

As is known, the motherboard usually contains a group of crystal cells, and the cell group provides a common platform for the motherboard to be connected to different devices to control communication between different devices. The die set also provides support for different expansion slots, such as PCIe (Peripheral Component Interconnection Express) slots. The wafer group usually consists of a north bridge and a south bridge. The PCH (Platform Controller Hub) is an integrated south bridge developed by Intel Corporation. In addition, the motherboard usually has a BIOS (Basic Input Output System) stored in an EEPROM (Electrically Erasable Programmable Read Only Memory) chip for initializing the motherboard. During the startup process, the memory and peripheral devices on the motherboard are tested and initialized. This process is called Power On Self Test (POST). With the advancement of technology, PCIe has been upgraded from the 2.0 standard to the 3.0 standard. Because the 2.0 standard PCIe and the 3.0 standard PCIe test specifications are inconsistent, when the PCIe slot design is performed, it is impossible to predict whether the PCI 2.0 card or the 3.0 standard PCIe card inserted in the PCIe slot is inserted, so the PCIe slot The design is difficult. The current design is to meet the two PCIe slots of the PCIe card of the 2.0 standard and the 3.0 standard, respectively, so that the traces on the printed circuit board are wasteful.

In view of this, it is necessary to provide a drive circuit that avoids wasted wiring on the printed circuit board.

A driving circuit includes a control circuit, a platform controller and a slot. An output of the platform controller is coupled to the slot. The slot is for inserting a function card. The control circuit includes a first output resistor, a second output resistor, an electronic switch, and a jump cap. The jump cap includes a first stitch, a second stitch, and a third stitch. The first pin is connected to a power source, and the third pin is grounded. The electronic switch includes a control end, a first switch end and a second switch end. The control end is configured to control opening and closing between the first switch end and the second switch end. The control end is connected to the second pin of the jump cap, and the first switch end is grounded by the first output resistor and the second output resistor in sequence, and the second switch end is grounded. A node between the first output resistor and the second output resistor is coupled to an offset adjustment pin of the platform controller. The jump cap is used to control the cutoff and conduction of the electronic switch. When the second stitch of the jump cap is in communication with the third pin, the electronic switch is turned off, and the bias adjustment pin is only connected to the second output resistor. When the first pin of the jump cap is in communication with the second pin, the electronic switch is turned on, the bias adjustment pin is simultaneously connected to the first output resistor and the second output resistor, and the first output resistor is The second output resistors are connected in parallel.

Compared with the prior art, the driving circuit of the present invention is applied to a platform controller, including a first output resistor, a second output resistor, an electronic switch, and a jump cap, through the communication between different stitches of the jump cap And changing the resistance value of the equivalent resistance of the offset adjustment pin connection of the platform controller, so that the driving circuit can drive a plurality of different types of function cards.

1 is a schematic diagram of a driving circuit provided by the present invention.

The technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.

Referring to FIG. 1 to FIG. 2 together, the cleaning fixture 10 provided by the present invention is provided.

Referring to FIG. 1 , the driving circuit 100 provided by the present invention includes a control circuit 10 , a platform controller (PCH) 20 , and a slot 30 . The control circuit 10, the platform controller 20, and the slot 30 are all disposed on a main board (not shown).

The control circuit 10 includes an input resistor R1, a first output resistor R2, a second output resistor R3, a jump cap 50, and an electronic switch.

The jumper cap 50 includes a first stitch 51, a second stitch 52, and a third stitch 53. The first pin 51 is connected to a power source P3V3 by the input resistor R1, and the third pin 53 is grounded.

The electronic switch includes a control end, a first switch end and a second switch end. The control end is configured to control opening and closing between the first switch end and the second switch end. In this embodiment, the electronic switch is an N-channel field effect transistor Q1. The gate G of the FET Q1 is the control terminal, the drain D of the FET Q1 is the first switch terminal, and the source S of the FET Q1 is the second switch. end. The gate G of the field effect transistor Q1 is connected to the second pin 52 of the jump cap 50. The source S of the field effect transistor Q1 is grounded. The drain D of the FET Q1 is grounded by the first output resistor R2 and the second output resistor R3 in sequence. Specifically, the drain D of the FET Q1 is connected to one end of the first output resistor R2, and the other end of the first output resistor R2 is connected to one end of the second output resistor R3. The other end of the two output resistors R3 is grounded. A node O is formed between the first output resistor R2 and the second output resistor R3.

The platform controller 20 includes an offset adjustment pin PEG0_RBIASP and an output terminal 21. The bias adjustment pin PEG0_RBIASP is connected to the node O. The output 21 is connected to the slot 30. The slot 30 is for inserting a function card 40. In this embodiment, the slot 30 is a PCIe (Peripheral Component Interconnection Express) slot, and the function card 40 is a 2.0 standard PCIe card or a 3.0 standard PCIe card.

In use, one of the function cards 40 is inserted into the slot 30 and then turned on. When the inserted function card 40 is 3.0 standard, the second pin 52 of the jump cap 50 is connected to the third pin 53 , the gate G of the field effect transistor Q1 is grounded, and the field effect transistor Q1 is turned off. The bias adjustment pin PEG0_RBIASP is only connected to the second output resistor R3, and the output signal is outputted to the slot 30 by the output terminal 21 to drive the 3.0 standard function card 40.

When the inserted function card 40 is 2.0 standard, the first pin 51 of the jump cap 50 is connected to the second pin 52, and the gate G of the field effect transistor Q1 is connected to the power source P3V3, the field The effect transistor Q1 is turned on. At this time, the first output resistor R2 is connected in parallel with the second output resistor R3, and the resistance value of the equivalent resistance of the bias adjustment pin PEG0_RBIASP is lowered, and the bias adjustment pin is The input current of PEG0_RBIASP becomes larger, thereby increasing the output intensity of the driving signal and increasing the driving capability of the driving signal, thereby driving the 2.0 standard function card.

The driving circuit 100 provided by the present invention is applied to a platform controller 20, including a first output resistor R2, a second output resistor R3, a field effect transistor Q1, and a jump cap 50, with different pins between the jump caps 50. The connection changes the resistance value of the equivalent resistance of the bias adjustment pin PEG0_RBIASP of the platform controller 20, so that the driving circuit 100 can drive a plurality of different types of function cards 40.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ drive circuit

10‧‧‧Control circuit

20‧‧‧ platform controller

21‧‧‧ Output

30‧‧‧Slots

40‧‧‧ function card

50‧‧‧ Jumping cap

51‧‧‧First stitch

52‧‧‧second stitch

53‧‧‧third stitch

Q1‧‧‧ FET

R1‧‧‧ input resistance

R2‧‧‧ first output resistance

R3‧‧‧second output resistor

no

100‧‧‧ drive circuit

10‧‧‧Control circuit

20‧‧‧ platform controller

21‧‧‧ Output

30‧‧‧Slots

40‧‧‧ function card

50‧‧‧ Jumping cap

51‧‧‧First stitch

52‧‧‧second stitch

53‧‧‧third stitch

Q1‧‧‧ FET

R1‧‧‧ input resistance

R2‧‧‧ first output resistance

R3‧‧‧second output resistor

Claims (4)

A driving circuit includes a control circuit, a platform controller and a slot, wherein the output of the platform controller is connected to the slot, and the slot is used for inserting a function card. The control circuit includes a first output resistor, a second output resistor, an electronic switch, and a jump cap. The jump cap includes a first pin, a second pin, and a third pin. The first pin is connected. The third pin is grounded at a power source, the electronic switch includes a control end, a first switch end and a second switch end, and the control end is configured to control the first switch end and the second end Opening and closing between the switch ends, the control end is connected to the second pin of the jump cap, and the first switch end is grounded by the first output resistor and the second output resistor in sequence, the first The second switch end is grounded, a node between the first output resistor and the second output resistor is connected to an offset adjustment pin of the platform controller, and the jump cap is used to control the cutoff of the electronic switch Turn on, the second of the jump cap When the foot is in communication with the third pin, the electronic switch is turned off, the bias adjustment pin is only connected to the second output resistor, and the electronic switch is turned on when the first pin of the jump cap is in communication with the second pin The bias adjustment pin simultaneously connects the first output resistor and the second output resistor, and the first output resistor is connected in parallel with the second output resistor. The driving circuit of claim 1, wherein the electronic switch is an N-channel FET, and the gate, the drain and the source of the N-channel FET respectively correspond to the control end of the electronic switch, and the first Switch end and second switch end. The driving circuit of claim 2, wherein the slot is a PCIe slot, and the function card is a 2.0 standard PCIe card or a 3.0 standard PCIe card. The driving circuit of claim 1, wherein the control circuit further comprises an input resistor, the first pin being connected to the power source by the input resistor.