TW201525976A - Liquid crystal display device and driving method - Google Patents
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本發明是有關於一種顯示裝置及驅動方法,特別是指一種液晶顯示裝置及驅動方法。 The present invention relates to a display device and a driving method, and more particularly to a liquid crystal display device and a driving method.
參閱圖1,是一種習知的液晶顯示裝置,包含八條平行設置的掃描線11、四條與該等掃描線11垂直設置的資料線12、一掃描驅動電路13、一資料驅動電路14、一共同端信號產生電路15,及四個對偶畫素電路16。 Referring to FIG. 1 , a conventional liquid crystal display device includes eight scanning lines 11 arranged in parallel, four data lines 12 disposed perpendicularly to the scanning lines 11 , a scan driving circuit 13 , a data driving circuit 14 , and a The common terminal signal generating circuit 15 and the four dual pixel circuits 16 are provided.
該掃描驅動電路13用來產生八個掃描電壓S1~S8,並將每一掃描電壓S1~S8輸出至該等掃描線11中的一對應者。 The scan driving circuit 13 is configured to generate eight scan voltages S 1 to S 8 and output each of the scan voltages S 1 to S 8 to a corresponding one of the scan lines 11 .
該資料驅動電路14用來產生四個資料電壓D1~D4,並將每一資料電壓D1~D4輸出至該等資料線12中的一對應者。 The data driving circuit 14 is configured to generate four data voltages D 1 to D 4 and output each of the data voltages D 1 to D 4 to a corresponding one of the data lines 12 .
該共同端信號產生電路15用來產生一直流共同電壓DC_vcom及一交流共同電壓AC_vcom二者其中之一。 The common-end signal generating circuit 15 is configured to generate one of a DC common voltage DC_vcom and an AC common voltage AC_vcom.
該等對偶畫素電路16中的每一者包括四個第一及第二畫素單元161、162,每一第一及第二畫素單元161、162具有一薄膜電晶體163及一儲存電容164。該薄膜電 晶體163具有一接收對應的資料電壓的源極、一汲極,及一接收對應的掃描電壓並決定該源極與該汲極是否導通的閘極。該儲存電容164電連接對應的該薄膜電晶體163之汲極與該共同端信號產生電路15之間,以接收來自該共同端信號產生電路15之該直流共同電壓DC_vcom或該交流共同電壓AC_vcom。 Each of the dual pixel circuits 16 includes four first and second pixel units 161, 162, each of the first and second pixel units 161, 162 having a thin film transistor 163 and a storage capacitor. 164. The film electricity The crystal 163 has a source receiving a corresponding data voltage, a drain, and a gate that receives the corresponding scan voltage and determines whether the source and the drain are turned on. The storage capacitor 164 is electrically connected between the drain of the corresponding thin film transistor 163 and the common terminal signal generating circuit 15 to receive the DC common voltage DC_vcom or the AC common voltage AC_vcom from the common terminal signal generating circuit 15.
參閱圖1與圖2,顯示該液晶顯示裝置在一畫面週期內,當該共同端信號產生電路15產生該直流共同電壓DC_vcom,且該等掃描電壓S1~S8中的每一者依序使該等薄膜電晶體163中的對應者導通時,每一資料電壓D1~D4需改變其準位,以避免該等對偶畫素電路16產生極化現象,當該等薄膜電晶體163中的一者所接收到的資料電壓的準位大於該直流共同電壓DC_vcom的準位時,對應該等薄膜電晶體163中的一者的該儲存電容164根據對應的該資料電壓進行充電,當該等薄膜電晶體163中的一者所接收到的資料電壓的準位小於該直流共同電壓DC_vcom的準位時,對應該等薄膜電晶體163中的一者的該儲存電容164進行放電,且進行充電的該儲存電容164以符號正號表示,進行放電的該儲存電容164以符號負號表示。 Referring to FIG. 1 and FIG. 2, the liquid crystal display device generates the DC common voltage DC_vcom when the common-end signal generating circuit 15 generates the scanning voltages S 1 -S 8 in a frame period. When the corresponding ones of the thin film transistors 163 are turned on, each of the data voltages D 1 -D 4 needs to change its level to avoid polarization of the dual pixel circuits 16 when the thin film transistors 163 When the level of the data voltage received by one of the ones is greater than the level of the DC common voltage DC_vcom, the storage capacitor 164 corresponding to one of the thin film transistors 163 is charged according to the corresponding data voltage. When the level of the data voltage received by one of the thin film transistors 163 is less than the level of the DC common voltage DC_vcom, the storage capacitor 164 corresponding to one of the thin film transistors 163 is discharged, and The storage capacitor 164 that is charged is indicated by a sign with a positive sign, and the storage capacitor 164 that performs the discharge is indicated by a negative sign.
參閱圖2與圖3,參數T表示該畫面週期,參數VDDA表示一偏壓電壓。在操作時,當該等掃描電壓S1~S8中的每一者依序使該等薄膜電晶體163中的對應者導通時,該等資料電壓D1、D2的準位於該等掃描電壓S2、S4、S6、S8中的每一者使該等薄膜電晶體163中的對應者導 通時改變,且此時每一資料電壓D1、D2的準位變化量等於該偏壓電壓VDDA。該等資料電壓D3、D4的準位變化(圖未示)分別與該等資料電壓D1、D2相似。 Referring to Figures 2 and 3, the parameter T represents the picture period, and the parameter VDDA represents a bias voltage. In operation, when each of the scan voltages S 1 -S 8 sequentially turns on the corresponding ones of the thin film transistors 163, the data voltages D 1 , D 2 are located in the scans. Each of the voltages S 2 , S 4 , S 6 , and S 8 changes when the corresponding one of the thin film transistors 163 is turned on, and at this time, the level change of each of the data voltages D 1 and D 2 is equal to The bias voltage is VDDA. The level changes (not shown) of the data voltages D 3 and D 4 are similar to the data voltages D 1 and D 2 , respectively.
參閱圖4,顯示該液晶顯示裝置在該畫面週期T內,當該共同端信號產生電路15產生該交流共同電壓AC_vcom,且該等掃描電壓S1~S8中的每一者依序使該等薄膜電晶體163中的對應者導通時,該交流共同電壓AC_vcom需改變其準位,以避免該等對偶畫素電路16產生極化現象,當該交流共同電壓AC_vcom的準位小於該等薄膜電晶體163中的一者所接收到的資料電壓的準位時,對應該等薄膜電晶體163中的一者的該儲存電容164根據對應的該資料電壓進行充電,當該交流共同電壓AC_vcom的準位大於該等薄膜電晶體163中的一者所接收到的資料電壓的準位時,對應該等薄膜電晶體163中的一者的該儲存電容164進行放電。 Referring to FIG. 4, the liquid crystal display device is shown in the picture period T, when the common-side signal generating circuit 15 generates the alternating current common voltage AC_vcom, and each of the scan voltages S 1 -S 8 sequentially When the corresponding one of the thin film transistors 163 is turned on, the alternating common voltage AC_vcom needs to change its level to avoid polarization of the dual pixel circuits 16, when the level of the alternating common voltage AC_vcom is smaller than the films. When the data voltage received by one of the transistors 163 is at the level of the data voltage, the storage capacitor 164 corresponding to one of the thin film transistors 163 is charged according to the corresponding data voltage, when the AC common voltage AC_vcom When the level is greater than the level of the data voltage received by one of the thin film transistors 163, the storage capacitor 164 corresponding to one of the thin film transistors 163 is discharged.
參閱圖4與圖5,在操作時,當該等掃描電壓S1~S8中的每一者依序使該等薄膜電晶體163中的對應者導通時,該交流共同電壓AC_vcom及該等資料電壓D1、D2的準位於該等掃描電壓S2、S4、S6、S8中的每一者使該等薄膜電晶體163中的對應者導通時改變,且此時該交流共同電壓AC_vcom的準位變化量等於該偏壓電壓VDDA的一半。該等資料電壓D3、D4的準位變化(圖未示)分別與該等資料電壓D1、D2相似。 Referring to FIG. 4 and FIG. 5, in operation, when each of the scan voltages S 1 -S 8 sequentially turns on the corresponding ones of the thin film transistors 163, the AC common voltage AC_vcom and the like The data voltages D 1 and D 2 are located at each of the scan voltages S 2 , S 4 , S 6 , and S 8 so that the corresponding ones of the thin film transistors 163 are turned on, and the current is exchanged. The level change of the common voltage AC_vcom is equal to half of the bias voltage VDDA. The level changes (not shown) of the data voltages D 3 and D 4 are similar to the data voltages D 1 and D 2 , respectively.
習知液晶顯示裝置具有以下缺點: Conventional liquid crystal display devices have the following disadvantages:
1.當操作於該共同端信號產生電路15用於產生該直流共同電壓DC_vcom時,於該畫面週期T內,每一資料電壓D1~D4準位變化的次數較多(次數為四),且每一資料電壓D1~D4的準位變化量較大(等於該偏壓電壓VDDA),導致該液晶顯示裝置的功率損耗較高。 1. When the common-side signal generating circuit 15 is configured to generate the DC common-voltage DC_vcom, the number of times each of the data voltages D 1 -D 4 changes in the picture period T (the number of times is four) And the amount of change of the level of each of the data voltages D 1 to D 4 is large (equal to the bias voltage VDDA), resulting in high power loss of the liquid crystal display device.
2.當操作於該共同端信號產生電路15用於產生該交流共同電壓AC_vcom時,於該畫面週期T內,由於該交流共同電壓AC_vcom及每一資料電壓D1~D4準位變化的次數較多(皆四次),導致該液晶顯示裝置的功率損耗較大。 2. When the common-side signal generating circuit 15 is configured to generate the alternating common voltage AC_vcom, the number of times the alternating common voltage AC_vcom and each of the data voltages D 1 to D 4 change in the frame period T More (all four times), resulting in a large power loss of the liquid crystal display device.
因此,本發明之第一目的,即在提供一種可降低功率損耗的液晶顯示裝置。 Accordingly, a first object of the present invention is to provide a liquid crystal display device which can reduce power loss.
於是本發明液晶顯示裝置,包含M條平行設置的掃描線、N條與該等掃描線垂直設置的資料線、一掃描驅動電路、一資料驅動電路、一共同端信號產生電路及K個對偶畫素電路。 Therefore, the liquid crystal display device of the present invention comprises M parallel scan lines, N data lines vertically arranged with the scan lines, a scan driving circuit, a data driving circuit, a common terminal signal generating circuit and K dual paintings. Prime circuit.
該掃描驅動電路電連接到該等掃描線,並產生M個掃描電壓,並將每一掃描電壓輸出至該等掃描線中的一對應者,M為偶數。 The scan driving circuit is electrically connected to the scan lines, and generates M scan voltages, and outputs each scan voltage to a corresponding one of the scan lines, and M is an even number.
該資料驅動電路電連接到該等資料線,並產生N個資料電壓,並將每一資料電壓輸出至該等資料線中的一對應者,N為正整數。 The data driving circuit is electrically connected to the data lines, and generates N data voltages, and outputs each data voltage to a corresponding one of the data lines, where N is a positive integer.
該共同端信號產生電路用來產生一直流共同電 壓。 The common-end signal generating circuit is used to generate a common current Pressure.
該等對偶畫素電路中的每一對偶畫素電路包括N個第一及第二畫素單元,每一第一及第二畫素單元電連接該共同端信號產生電路以接收該直流共同電壓,於第i個對偶畫素電路中,每一第一畫素單元電連接第(2i-1)條掃描線以接收來自該第(2i-1)條掃描線的掃描電壓,每一第二畫素單元電連接第2i條掃描線以接收來自該第2i條掃描線的掃描電壓,且第j個第一及第二畫素單元電連接第j條資料線以接收來自該第j條資料線的資料電壓,其中,K=M/2,K≧3,1≦i≦K,1≦j≦N,且i、j為整數。 Each pair of pixel circuits in the dual pixel circuits includes N first and second pixel units, and each of the first and second pixel units is electrically connected to the common terminal signal generating circuit to receive the DC common voltage. In the i-th dual pixel circuit, each first pixel unit is electrically connected to the (2i-1)th scan line to receive a scan voltage from the (2i-1)th scan line, each second The pixel unit electrically connects the 2ith scan line to receive the scan voltage from the 2ith scan line, and the jth first and second pixel units are electrically connected to the jth data line to receive the data from the jth The data voltage of the line, where K = M / 2, K ≧ 3, 1 ≦ i ≦ K, 1 ≦ j ≦ N, and i, j are integers.
當K為偶數時,該掃描驅動電路先依序致能第p個對偶畫素電路中的每一第一畫素單元及第(p+1)個對偶畫素電路中的每一第二畫素單元,p為奇數,(p+1)≦K,接著再依序致能該第p個對偶畫素電路中的每一第二畫素單元及該第(p+1)個對偶畫素電路中的每一第一畫素單元。 When K is an even number, the scan driving circuit first sequentially enables each of the first pixel unit and the second pixel of the (p+1)th dual pixel circuit in the p-th dual pixel circuit. a prime unit, p is an odd number, (p+1) ≦K, and then sequentially enabling each second pixel unit in the p-th dual pixel circuit and the (p+1)th dual pixel Each first pixel unit in the circuit.
當K為奇數時,該掃描驅動電路先依序致能第一個對偶畫素電路中的每一第一畫素單元、第q個對偶畫素電路中的每一第二畫素單元、第(q+1)個對偶畫素電路中的每一第一畫素單元,q為偶數,(q+1)≦K,接著再依序致能該第一個對偶畫素電路中的每一第二畫素單元、該第q個對偶畫素電路中的每一第一畫素單元、該第(q+1)個對偶畫素電路中的每一第二畫素單元。 When K is an odd number, the scan driving circuit first sequentially enables each of the first pixel units in the first dual pixel circuit, each second pixel unit in the qth dual pixel circuit, (q+1) each of the first pixel units in the dual pixel circuit, q is an even number, (q+1) ≦K, and then sequentially enabling each of the first dual pixel circuits a second pixel unit, each first pixel unit in the qth dual pixel circuit, and each second pixel unit in the (q+1)th dual pixel circuit.
當K為偶數及奇數二者其中之一,且該掃描驅動電路致能第二個對偶畫素電路中的每一第二畫素單元時 ,此時每一資料電壓的準位改變,以致每一資料電壓具有一第一準位變化量。 When K is one of an even number and an odd number, and the scan driving circuit enables each second pixel unit in the second dual pixel circuit At this time, the level of each data voltage is changed, so that each data voltage has a first level change amount.
當K為偶數及奇數二者其中之一,且該掃描驅動電路致能該第一個對偶畫素電路中的每一第二畫素單元時,此時每一資料電壓的準位改變,以致每一資料電壓具有一第二準位變化量。 When K is one of an even number and an odd number, and the scan driving circuit enables each second pixel unit in the first dual pixel circuit, the level of each data voltage changes at this time, So that each data voltage has a second level change.
當K為偶數且該掃描驅動電路致能該第K個對偶畫素電路中的每一第一畫素單元時,此時每一資料電壓的準位改變,以致每一資料電壓具有一第三準位變化量。 When K is an even number and the scan driving circuit enables each of the first pixel units in the Kth dual pixel circuit, the level of each data voltage changes at this time, so that each data voltage has a third The amount of change in the level.
當K為奇數且該掃描驅動電路致能該第K個對偶畫素電路中的每一第二畫素單元時,此時每一資料電壓的準位改變,以致每一資料電壓具有一第三準位變化量。 When K is an odd number and the scan driving circuit enables each second pixel unit in the Kth dual pixel circuit, the level of each data voltage changes at this time, so that each data voltage has a third The amount of change in the level.
本發明之第二目的,即在提供另一種可降低功率損耗的液晶顯示裝置。 A second object of the present invention is to provide another liquid crystal display device which can reduce power loss.
該液晶顯示裝置包含M條平行設置的掃描線、N條與該等掃描線垂直設置的資料線、一掃描驅動電路、一資料驅動電路、一共同端信號產生電路及K個對偶畫素電路。 The liquid crystal display device comprises M scanning lines arranged in parallel, N data lines arranged perpendicularly to the scanning lines, a scanning driving circuit, a data driving circuit, a common terminal signal generating circuit and K dual pixel circuits.
該掃描驅動電路電連接到該等掃描線,並產生M個掃描電壓,並將每一掃描電壓輸出至該等掃描線中的一對應者,M為偶數。 The scan driving circuit is electrically connected to the scan lines, and generates M scan voltages, and outputs each scan voltage to a corresponding one of the scan lines, and M is an even number.
該資料驅動電路電連接到該等資料線,並產生N個資料電壓,並將每一資料電壓輸出至該等資料線中的一對應者,N為正整數。 The data driving circuit is electrically connected to the data lines, and generates N data voltages, and outputs each data voltage to a corresponding one of the data lines, where N is a positive integer.
該共同端信號產生電路用來產生一交流共同電壓。 The common-end signal generating circuit is configured to generate an alternating current voltage.
該等對偶畫素電路中的每一對偶畫素電路包括N個第一及第二畫素單元,每一第一及第二畫素單元電連接該共同端信號產生電路以接收該交流共同電壓,於第i個對偶畫素電路中,每一第一畫素單元電連接第(2i-1)條掃描線以接收來自該第(2i-1)條掃描線的掃描電壓,每一第二畫素單元電連接第2i條掃描線以接收來自該第2i條掃描線的掃描電壓,且第j個第一及第二畫素單元電連接第j條資料線以接收來自該第j條資料線的資料電壓,其中,K=M/2,K≧3,1≦i≦K,1≦j≦N,且i、j為整數。 Each pair of pixel circuits in the dual pixel circuits includes N first and second pixel units, and each of the first and second pixel units is electrically connected to the common terminal signal generating circuit to receive the alternating common voltage. In the i-th dual pixel circuit, each first pixel unit is electrically connected to the (2i-1)th scan line to receive a scan voltage from the (2i-1)th scan line, each second The pixel unit electrically connects the 2ith scan line to receive the scan voltage from the 2ith scan line, and the jth first and second pixel units are electrically connected to the jth data line to receive the data from the jth The data voltage of the line, where K = M / 2, K ≧ 3, 1 ≦ i ≦ K, 1 ≦ j ≦ N, and i, j are integers.
當K為偶數時,該掃描驅動電路先依序致能第p個對偶畫素電路中的每一第一畫素單元及第(p+1)個對偶畫素電路中的每一第二畫素單元,p為奇數,(p+1)≦K,接著再依序致能該第p個對偶畫素電路中的每一第二畫素單元及該第(p+1)個對偶畫素電路中的每一第一畫素單元。 When K is an even number, the scan driving circuit first sequentially enables each of the first pixel unit and the second pixel of the (p+1)th dual pixel circuit in the p-th dual pixel circuit. a prime unit, p is an odd number, (p+1) ≦K, and then sequentially enabling each second pixel unit in the p-th dual pixel circuit and the (p+1)th dual pixel Each first pixel unit in the circuit.
當K為奇數時,該掃描驅動電路先依序致能第一個對偶畫素電路中的每一第一畫素單元、第q個對偶畫素電路中的每一第二畫素單元、第(q+1)個對偶畫素電路中的每一第一畫素單元,q為偶數,(q+1)≦K,接著再依序致能該第一個對偶畫素電路中的每一第二畫素單元、該第q個對偶畫素電路中的每一第一畫素單元、該第(q+1)個對偶畫素電路中的每一第二畫素單元。 When K is an odd number, the scan driving circuit first sequentially enables each of the first pixel units in the first dual pixel circuit, each second pixel unit in the qth dual pixel circuit, (q+1) each of the first pixel units in the dual pixel circuit, q is an even number, (q+1) ≦K, and then sequentially enabling each of the first dual pixel circuits a second pixel unit, each first pixel unit in the qth dual pixel circuit, and each second pixel unit in the (q+1)th dual pixel circuit.
當K為偶數及奇數二者其中之一,且該掃描驅 動電路致能該第一個對偶畫素電路中的每一第二畫素單元時,此時該交流共同電壓的準位改變,以致該交流共同電壓具有一準位變化量。 When K is one of an even number and an odd number, and the scan drive When the dynamic circuit enables each of the second pixel units in the first dual pixel circuit, the level of the alternating common voltage changes at this time, so that the alternating common voltage has a level change amount.
本發明之第三目的,即在提供一種可降低功率損耗的液晶顯示裝置之驅動方法。 A third object of the present invention is to provide a driving method of a liquid crystal display device which can reduce power loss.
該液晶顯示裝置之驅動方法適用於一包含M條平行設置的掃描線、N條與該等掃描線垂直設置的資料線,及K個分別包括N個第一及第二畫素單元之對偶畫素電路的液晶顯示裝置,每一第一畫素單元電連接第(2i-1)條掃描線,每一第二畫素單元電連接第2i條掃描線,且第j個第一及第二畫素單元電連接第j條資料線,1≦i≦K,1≦j≦N,且i、j為整數,M為偶數,N為正整數,K=M/2,K≧3,該液晶顯示裝置之驅動方法包含以下步驟:(A)產生一直流共同電壓至每一第一及第二畫素單元;(B)於一畫面週期內,產生複數個掃描電壓依序致能第p個對偶畫素電路中的每一第一畫素單元及第(p+1)個對偶畫素電路中的每一第二畫素單元,p為奇數,(p+1)≦K,K為偶數,並產生複數個資料電壓並分別輸出至相對應的該等第一及第二畫素單元,且於第二個對偶畫素電路中的每一第二畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有一第一準位變化量;(C)產生複數個掃描電壓依序致能該第p個對偶畫素電路中的每一第二畫素單元及該第(p+1)個對偶畫素電 路中的每一第一畫素單元,p為奇數,(p+1)≦K,K為偶數,且於第一個對偶畫素電路中的每一第二畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有一第二準位變化量,且於第K個對偶畫素電路中的每一第一畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有一第三準位變化量;(D)於一畫面週期內,產生複數個掃描電壓依序致能該第一個對偶畫素電路中的每一第一畫素單元、第q個對偶畫素電路中的每一第二畫素單元、第(q+1)個對偶畫素電路中的每一第一畫素單元,q為偶數,(q+1)≦K,K為奇數,且於該第二個對偶畫素電路中的每一第二畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有該第一準位變化量;及(E)產生複數個掃描電壓依序致能該第一個對偶畫素電路中的每一第二畫素單元、該第q個對偶畫素電路中的每一第一畫素單元、該第(q+1)個對偶畫素電路中的每一第二畫素單元,q為偶數,(q+1)≦K,K為奇數,且於該第一個對偶畫素電路中的每一第二畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有該第二準位變化量,且於該第K個對偶畫素電路中的每一第二畫素單元被致能時,改變每一資料電壓的準位,以致每一資料電壓具有該第三準位變化量。 The driving method of the liquid crystal display device is applicable to a scanning line including M parallel arranged lines, N data lines vertically disposed with the scanning lines, and K dual images including N first and second pixel units respectively The liquid crystal display device of the prime circuit, each first pixel unit is electrically connected to the (2i-1)th scan line, each second pixel unit is electrically connected to the 2ith scan line, and the jth first and second The pixel unit is electrically connected to the jth data line, 1≦i≦K,1≦j≦N, and i and j are integers, M is an even number, N is a positive integer, K=M/2, K≧3, The driving method of the liquid crystal display device comprises the steps of: (A) generating a constant current common voltage to each of the first and second pixel units; (B) generating a plurality of scanning voltages sequentially in a picture period to sequentially enable the p Each of the first pixel units in the dual pixel circuits and each of the second pixel units in the (p+1)th dual pixel circuit, p is an odd number, (p+1) ≦K, K is Evenly, and generating a plurality of data voltages and respectively outputting to the corresponding first and second pixel units, and each second pixel in the second dual pixel circuit When enabled, changing the level of each data voltage such that each data voltage has a first level change; (C) generating a plurality of scan voltages sequentially enabling the p-th dual pixel circuit Each second pixel unit and the (p+1)th dual pixel Each first pixel unit in the path, p is an odd number, (p+1) ≦ K, K is an even number, and when each second pixel unit in the first dual pixel circuit is enabled, Changing the level of each data voltage such that each data voltage has a second level change amount, and each data element is changed when each of the first pixel units in the Kth dual pixel circuit is enabled The voltage level is such that each data voltage has a third level change amount; (D) generating a plurality of scan voltages in a picture period to sequentially enable each of the first dual pixel circuits a pixel unit, each second pixel unit in the qth dual pixel circuit, and each first pixel unit in the (q+1)th dual pixel circuit, q is an even number, (q+ 1) ≦K, K is an odd number, and when each second pixel unit in the second dual pixel circuit is enabled, the level of each data voltage is changed, so that each data voltage has the first a level change amount; and (E) generating a plurality of scan voltages to sequentially enable each of the second pixel units in the first dual pixel circuit, the qth pair Each first pixel unit in the prime circuit, each second pixel unit in the (q+1)th dual pixel circuit, q is an even number, (q+1)≦K, K is an odd number, And when each second pixel unit in the first dual pixel circuit is enabled, changing the level of each data voltage, so that each data voltage has the second level change amount, and When each of the second pixel units in the Kth dual pixel circuit is enabled, the level of each data voltage is changed so that each data voltage has the third level change amount.
本發明之第四目的,即在提供另一種可降低功率損耗的液晶顯示裝置之驅動方法。 A fourth object of the present invention is to provide another driving method of a liquid crystal display device which can reduce power loss.
該液晶顯示裝置之驅動方法適用於一包含M條平行設置的掃描線、N條與該等掃描線垂直設置的資料線,及K個分別包括N個第一及第二畫素單元之對偶畫素電路的液晶顯示裝置,每一第一畫素單元電連接第(2i-1)條掃描線,每一第二畫素單元電連接第2i條掃描線,且第j個第一及第二畫素單元電連接第j條資料線,1≦i≦K,1≦j≦N,且i、j為整數,M為偶數,N為正整數,K=M/2,K≧3,該液晶顯示裝置之驅動方法包含以下步驟:(A)產生一交流共同電壓至每一第一及第二畫素單元;(B)於一畫面週期內,產生複數個掃描電壓依序致能第p個對偶畫素電路中的每一第一畫素單元及第(p+1)個對偶畫素電路中的每一第二畫素單元,p為奇數,(p+1)≦K,K為偶數;(C)產生複數個掃描電壓依序致能該第p個對偶畫素電路中的每一第二畫素單元及該第(p+1)個對偶畫素電路中的每一第一畫素單元,p為奇數,(p+1)≦K,K為偶數,且於第一個對偶畫素電路中的每一第二畫素單元被致能時,改變該交流共同電壓的準位,以致該交流共同電壓具有一準位變化量;(D)於一畫面週期內,產生複數個掃描電壓依序致能該第一個對偶畫素電路中的每一第一畫素單元、第q個對偶畫素電路中的每一第二畫素單元、第(q+1)個對偶畫素電路中的每一第一畫素單元,q為偶數,(q+1)≦K,K為 奇數;及(E)產生複數個掃描電壓依序致能該第一個對偶畫素電路中的每一第二畫素單元、該第q個對偶畫素電路中的每一第一畫素單元、該第(q+1)個對偶畫素電路中的每一第二畫素單元,q為偶數,(q+1)≦K,K為奇數,且於該第一個對偶畫素電路中的每一第二畫素單元被致能時,改變該交流共同電壓的準位,以致該交流共同電壓具有該準位變化量。 The driving method of the liquid crystal display device is applicable to a scanning line including M parallel arranged lines, N data lines vertically disposed with the scanning lines, and K dual images including N first and second pixel units respectively The liquid crystal display device of the prime circuit, each first pixel unit is electrically connected to the (2i-1)th scan line, each second pixel unit is electrically connected to the 2ith scan line, and the jth first and second The pixel unit is electrically connected to the jth data line, 1≦i≦K,1≦j≦N, and i and j are integers, M is an even number, N is a positive integer, K=M/2, K≧3, The driving method of the liquid crystal display device comprises the steps of: (A) generating an alternating current common voltage to each of the first and second pixel units; and (B) generating a plurality of scanning voltages in a picture period to sequentially enable the p Each of the first pixel units in the dual pixel circuits and each of the second pixel units in the (p+1)th dual pixel circuit, p is an odd number, (p+1) ≦K, K is And (C) generating a plurality of scan voltages to sequentially enable each of the second pixel elements in the p-th dual pixel circuit and each of the first (p+1) dual pixel circuits painting a unit, p is an odd number, (p+1) ≦ K, K is an even number, and when each second pixel unit in the first dual pixel circuit is enabled, the level of the alternating common voltage is changed, Therefore, the AC common voltage has a level change amount; (D) generating a plurality of scan voltages in a picture period to sequentially enable each of the first pixel units in the first dual pixel circuit, the qth Each second pixel unit in the dual pixel circuit, each first pixel unit in the (q+1)th dual pixel circuit, q is an even number, (q+1)≦K, K is An odd number; and (E) generating a plurality of scan voltages to sequentially enable each of the first pixel units in the first dual pixel circuit, each of the first pixel elements in the qth dual pixel circuit Each second pixel unit in the (q+1)th dual pixel circuit, q is an even number, (q+1) ≦K, K is an odd number, and is in the first dual pixel circuit When each of the second pixel units is enabled, the level of the alternating common voltage is changed, so that the alternating common voltage has the level change amount.
2‧‧‧掃描線 2‧‧‧ scan line
711‧‧‧薄膜電晶體 711‧‧‧film transistor
3‧‧‧資料線 3‧‧‧Information line
712‧‧‧儲存電容 712‧‧‧ Storage Capacitor
4‧‧‧掃描驅動電路 4‧‧‧Scan drive circuit
VDDA‧‧‧偏壓電壓 VDDA‧‧‧ bias voltage
s1~s8‧‧‧掃描電壓 s 1 ~s 8 ‧‧‧ scan voltage
V1‧‧‧第一準位變化量 V1‧‧‧ first level change
5‧‧‧資料驅動電路 5‧‧‧Data Drive Circuit
V2‧‧‧第二準位變化量 V2‧‧‧ second level change
d1~d4‧‧‧資料電壓 d 1 ~d 4 ‧‧‧data voltage
V3‧‧‧第三準位變化量 V3‧‧‧ third level change
6‧‧‧共同端信號產生電路 6‧‧‧Common signal generation circuit
8‧‧‧共同端信號產生電路 8‧‧‧Common signal generation circuit
dc_vcom‧‧‧直流共同電壓 Dc_vcom‧‧‧DC common voltage
ac_vcom‧‧‧交流共同電壓 Ac_vcom‧‧‧Common voltage
7‧‧‧對偶畫素電路 7‧‧‧Dual pixel circuit
V4‧‧‧準位變化量 V4‧‧‧ level change
71‧‧‧第一畫素單元 71‧‧‧ first pixel unit
T1、T2‧‧‧畫面週期 T1, T2‧‧‧ picture cycle
72‧‧‧第二畫素單元 72‧‧‧Second pixel unit
本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中:圖1是一種習知液晶顯示裝置的電路圖;圖2是該液晶顯示裝置之每一儲存電容進行充放電的電路示意圖;圖3是該液晶顯示裝置的時序圖;圖4是該液晶顯示裝置之每一儲存電容進行充放電的另一電路示意圖;圖5是對應該另一電路示意圖之該液晶顯示裝置的時序圖;圖6是本發明液晶顯示裝置之第一較佳實施例的電路圖;圖7是該第一較佳實施例之每一儲存電容進行充放電的電路示意圖;圖8是該第一較佳實施例的時序圖; 圖9是本發明液晶顯示裝置之第二較佳實施例與每一儲存電容進行充放電的電路示意圖;圖10是該第二較佳實施例的時序圖;圖11是本發明液晶顯示裝置之第三較佳實施例的電路圖;圖12是該第三較佳實施例之每一儲存電容進行充放電的電路示意圖;圖13是該第三較佳實施例的時序圖;圖14是本發明液晶顯示裝置之第四較佳實施例與每一儲存電容進行充放電的電路示意圖;及圖15是該第四較佳實施例的時序圖。 Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a circuit diagram of a conventional liquid crystal display device; FIG. 2 is a charging of each storage capacitor of the liquid crystal display device. FIG. 3 is a timing diagram of the liquid crystal display device; FIG. 4 is another circuit diagram of charging and discharging each storage capacitor of the liquid crystal display device; FIG. 5 is a schematic view of the liquid crystal display corresponding to another circuit diagram FIG. 6 is a circuit diagram of a first preferred embodiment of the liquid crystal display device of the present invention; FIG. 7 is a circuit diagram of charging and discharging each storage capacitor of the first preferred embodiment; FIG. a timing diagram of a preferred embodiment; 9 is a circuit diagram showing a second preferred embodiment of the liquid crystal display device of the present invention and charging and discharging each storage capacitor; FIG. 10 is a timing chart of the second preferred embodiment; FIG. 11 is a liquid crystal display device of the present invention. FIG. 12 is a circuit diagram showing charging and discharging of each storage capacitor of the third preferred embodiment; FIG. 13 is a timing chart of the third preferred embodiment; FIG. 14 is a timing chart of the third preferred embodiment; A fourth preferred embodiment of a liquid crystal display device and a circuit diagram for charging and discharging each storage capacitor; and FIG. 15 is a timing chart of the fourth preferred embodiment.
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖6,本發明液晶顯示裝置之第一較佳實施例包含M條平行設置的掃描線2、N條與該等掃描線2垂直設置的資料線3、一掃描驅動電路4、一資料驅動電路5、一共同端信號產生電路6,及K個對偶畫素電路7,M為偶數,N為正整數,K=M/2,K≧3。在此實施例中,M=8,N=4,K=4,但不限於此。 Referring to FIG. 6, a first preferred embodiment of the liquid crystal display device of the present invention comprises M parallel scan lines 2, N data lines 3 disposed perpendicularly to the scan lines 2, a scan driving circuit 4, and a data drive. The circuit 5, a common-end signal generating circuit 6, and K dual-pixel circuits 7, M is an even number, N is a positive integer, K = M/2, K ≧ 3. In this embodiment, M = 8, N = 4, and K = 4, but is not limited thereto.
該掃描驅動電路4電連接到該等掃描線2,並產生八(即,M=8)個掃描電壓s1~s8,並將每一掃描電壓s1~s8輸出至該等掃描線2中的一對應者。 The scan driving circuit 4 is electrically connected to the scan lines 2, and generates eight (ie, M=8) scan voltages s 1 to s 8 , and outputs each scan voltage s 1 s 8 to the scan lines. A counterpart in 2.
該資料驅動電路5電連接到該等資料線3,並產生四(即,N=4)個資料電壓d1~d4,並將每一資料電壓d1~d4輸出至該等資料線3中的一對應者。 The data driving circuit 5 is electrically connected to the data lines 3, and generates four (ie, N=4) data voltages d 1 to d 4 , and outputs each data voltage d 1 to d 4 to the data lines. A corresponding one of 3.
該共同端信號產生電路6用來產生一直流共同電壓dc_vcom。 The common-end signal generating circuit 6 is used to generate a DC-common voltage dc_vcom.
該等對偶畫素電路7中的每一者包括四個第一及第二畫素單元71、72,每一第一及第二畫素單元71、72具有一薄膜電晶體711及一儲存電容712。該薄膜電晶體711具有一源極、一汲極,及一決定該源極與該汲極是否導通的閘極。 Each of the dual pixel circuits 7 includes four first and second pixel units 71, 72, each of the first and second pixel units 71, 72 having a thin film transistor 711 and a storage capacitor. 712. The thin film transistor 711 has a source, a drain, and a gate that determines whether the source and the drain are turned on.
於該等對偶畫素電路7中的第i個對偶畫素電路7中,每一第一畫素單元71之薄膜電晶體711的閘極電連接第(2i-1)條掃描線2以接收來自該第(2i-1)條掃描線2的掃描電壓s(2i-1),每一第二畫素單元72之薄膜電晶體711的閘極電連接第2i條掃描線2以接收來自該第2i條掃描線2的掃描電壓s(2i),且第j個第一及第二畫素單元71、72之薄膜電晶體711的源極電連接第j條資料線3以接收來自該第j條資料線3的資料電壓d(j),其中,1≦i≦K,1≦j≦N,在此實施例中,K=4,N=4,且i、j為整數。每一第一及第二畫素單元71、72之該儲存電容712電連接對應的該薄膜電晶體711之汲極與該共同端信號產生電路6之間,以接收來自該共同端信號產生電路6之該直流共同電壓dc_vcom。 In the i-th dual pixel circuit 7 of the dual pixel circuits 7, the gate of the thin film transistor 711 of each first pixel unit 71 is electrically connected to the (2i-1)th scan line 2 for reception. The scan voltage s (2i-1) from the (2i-1)th scan line 2, the gate of the thin film transistor 711 of each second pixel unit 72 is electrically connected to the 2ith scan line 2 to receive from The scanning voltage s (2i) of the 2i scanning line 2, and the source of the thin film transistor 711 of the jth first and second pixel units 71, 72 is electrically connected to the jth data line 3 to receive from the first The data voltage d (j) of j data lines 3, where 1 ≦ i ≦ K, 1 ≦ j ≦ N, in this embodiment, K = 4, N = 4, and i, j are integers. The storage capacitor 712 of each of the first and second pixel units 71, 72 is electrically connected between the drain of the corresponding thin film transistor 711 and the common terminal signal generating circuit 6 to receive the signal generating circuit from the common terminal The DC common voltage dc_vcom of 6.
參閱圖7,顯示該液晶顯示裝置在一畫面週期內 ,每一資料電壓d1~d4需改變其準位,以避免該等對偶畫素電路7產生極化現象,且當該等薄膜電晶體711中的一者所接收到的資料電壓的準位大於該直流共同電壓dc_vcom的準位時,對應該等薄膜電晶體711中的一者的該儲存電容712根據對應的該資料電壓進行充電,當該等薄膜電晶體711中的一者所接收到的資料電壓的準位小於該直流共同電壓dc_vcom的準位時,對應該等薄膜電晶體711中的一者的該儲存電容712進行放電,且進行充電的該儲存電容712以符號正號表示,進行放電的該儲存電容712以符號負號表示。 Referring to FIG. 7, it is shown that the liquid crystal display device needs to change its level for each data voltage d 1 ~d 4 in a picture period to avoid polarization of the dual pixel circuits 7, and when the thin films are electrically When the level of the data voltage received by one of the crystals 711 is greater than the level of the DC common voltage dc_vcom, the storage capacitor 712 corresponding to one of the thin film transistors 711 is charged according to the corresponding data voltage. When the level of the data voltage received by one of the thin film transistors 711 is less than the level of the DC common voltage dc_vcom, the storage capacitor 712 corresponding to one of the thin film transistors 711 is discharged. The storage capacitor 712 that is charged and denoted by a positive sign, the storage capacitor 712 that performs the discharge is indicated by a negative sign.
以下說明在此第一較佳實施例中該掃描驅動電路4如何執行一驅動方法以致能該等對偶畫素電路7。 The following describes how the scan driving circuit 4 performs a driving method in the first preferred embodiment to enable the dual pixel circuits 7.
參閱圖7與圖8,參數T1表示該畫面週期,參數VDDA表示一偏壓電壓,且該直流共同電壓dc_vcom的準位等於該偏壓電壓VDDA的一半,每一資料電壓d1、d2的最高準位等於該偏壓電壓VDDA,但不限於此。 Referring to FIG. 7 and FIG. 8, the parameter T1 represents the picture period, the parameter VDDA represents a bias voltage, and the level of the DC common voltage dc_vcom is equal to half of the bias voltage VDDA, and each of the data voltages d 1 and d 2 The highest level is equal to the bias voltage VDDA, but is not limited thereto.
當操作於該畫面週期T1內時,該掃描驅動電路4先依序致能第p個對偶畫素電路7中的每一第一畫素單元71及第(p+1)個對偶畫素電路7中的每一第二畫素單元72,p為奇數,(p+1)≦K,在此實施例中,K=4,接著再依序致能該第p個對偶畫素電路7中的每一第二畫素單元72及該第(p+1)個對偶畫素電路7中的每一第一畫素單元71。 When operating in the picture period T1, the scan driving circuit 4 sequentially enables each of the first pixel units 71 and the (p+1)th pixel circuits of the p-th dual pixel circuit 7 in sequence. Each of the second pixel units 72 in 7, p is an odd number, (p+1) ≦ K, in this embodiment, K = 4, and then sequentially enables the p-th dual pixel circuit 7 Each of the second pixel units 72 and each of the first (p+1) dual pixel circuits 7 are in the first pixel unit 71.
詳細來說,該掃描驅動電路4所輸出的該等掃描電壓s1、s4、s5、s8中的每一者先依序使該等薄膜電晶體 711中的對應者導通,以依序致能第一個對偶畫素電路7中的每一第一畫素單元71、第二個對偶畫素電路7中的每一第二畫素單元72、第三個對偶畫素電路7中的每一第一畫素單元71及第四個對偶畫素電路7中的每一第二畫素單元72,接著該等掃描電壓s2、s3、s6、s7中的每一者再依序使該等薄膜電晶體711中的對應者導通,以依序致能該第一個對偶畫素電路7中的每一第二畫素單元72、該第二個對偶畫素電路7中的每一第一畫素單元71、該第三個對偶畫素電路7中的每一第二畫素單元72及該第四個對偶畫素電路7中的每一第一畫素單元71。 In detail, each of the scan voltages s 1 , s 4 , s 5 , and s 8 output by the scan driving circuit 4 sequentially turns on the corresponding ones of the thin film transistors 711 to Each of the first pixel units 71 in the first dual pixel circuit 7, the second pixel unit 72 in the second dual pixel circuit 7, and the third dual pixel circuit 7 are Each of the first pixel unit 71 and each of the second pixel units 72 of the fourth dual pixel circuit 7 is followed by each of the scan voltages s 2 , s 3 , s 6 , s 7 The corresponding ones of the thin film transistors 711 are sequentially turned on to sequentially enable each of the second pixel units 72 and the second dual pixel circuits 7 of the first dual pixel circuit 7. Each of the first pixel units 71, each of the second pixel units 72 of the third dual pixel circuit 7, and each of the first pixel units 71 of the fourth dual pixel circuit 7 .
此時,每一資料電壓d1、d2的準位於該掃描電壓s4致能該第二個對偶畫素電路7中的每一第二畫素單元72時、於該掃描電壓s2致能該第一個對偶畫素電路7中的每一第二畫素單元72時,及於該掃描電壓s7致能該第四個對偶畫素電路7中的每一第一畫素單元71時改變,以致每一資料電壓d1、d2具有一第一至第三準位變化量V1~V3。該等資料電壓d3、d4的準位變化(圖未示)分別與該等資料電壓d1、d2相似,故不重述。 At this time, each of the data voltages d 1 and d 2 is located when the scan voltage s 4 is enabled in each of the second pixel units 72 of the second dual pixel circuit 7 at the scan voltage s 2 When each of the second pixel units 72 of the first dual pixel circuit 7 is enabled, and the scanning voltage s 7 enables each of the first pixel units 71 of the fourth dual pixel circuit 7 The time changes so that each of the data voltages d 1 and d 2 has a first to third level change amounts V1 to V3. The level changes (not shown) of the data voltages d 3 and d 4 are similar to the data voltages d 1 and d 2 , respectively, and therefore are not repeated.
應注意的是,在此實施例中,於該畫面週期T1內,每一資料電壓d1~d4的準位變化三次,且每一資料電壓d1~d4的該第一及第三準位變化量V1、V3小於該偏壓電壓VDDA的一半,該第二準位變化量V2大於該偏壓電壓VDDA的一半且小於該偏壓電壓VDDA。 It should be noted that, in this embodiment, in the picture period T1, the level of each data voltage d 1 ~ d 4 changes three times, and the first and third of each data voltage d 1 ~ d 4 The level change amounts V1, V3 are less than half of the bias voltage VDDA, and the second level change amount V2 is greater than half of the bias voltage VDDA and smaller than the bias voltage VDDA.
參閱圖9,本發明液晶顯示裝置之第二較佳實施例與該第一較佳實施例相似,二者不同之處在於:此實施例省略於圖7之該第一較佳實施例中的第七及第八條掃描線2,及該第四個對偶畫素電路7,亦即此實施例僅包含六(M=6)條掃描線2,及三(K=3)個對偶畫素電路7,但不限於此。 Referring to FIG. 9, a second preferred embodiment of the liquid crystal display device of the present invention is similar to the first preferred embodiment, except that the embodiment is omitted from the first preferred embodiment of FIG. The seventh and eighth scan lines 2, and the fourth dual pixel circuit 7, that is, this embodiment includes only six (M=6) scan lines 2, and three (K=3) dual pixels. Circuit 7, but is not limited thereto.
參閱圖9與圖10,本實施例所執行的該驅動方法為:當操作於一畫面週期T2內時,該掃描驅動電路4先依序致能該第一個對偶畫素電路7中的每一第一畫素單元71、第q個對偶畫素電路7中的每一第二畫素單元72、第(q+1)個對偶畫素電路7中的每一第一畫素單元71,q為偶數,(q+1)≦K,在此實施例中,K=3,接著再依序致能該第一個對偶畫素電路7中的每一第二畫素單元72、該第q個對偶畫素電路7中的每一第一畫素單元71、該第(q+1)個對偶畫素電路中7的每一第二畫素單元72。 Referring to FIG. 9 and FIG. 10, the driving method performed in this embodiment is: when operating in a picture period T2, the scan driving circuit 4 sequentially enables each of the first dual pixel circuits 7 in sequence. a first pixel unit 71, each of the second pixel units 72 of the qth dual pixel circuit 7, and each of the first pixel units 71 of the (q+1)th dual pixel circuit 7, q is an even number, (q+1) ≦K, in this embodiment, K=3, and then sequentially enabling each second pixel unit 72 in the first dual pixel circuit 7, the first Each of the first pixel units 71 of the q dual pixel circuits 7 and each of the second pixel units 72 of the 7th (q+1)th dual pixel circuits.
應注意的是,在此實施例中,於該畫面週期T2內,每一資料電壓d1、d2的準位於該掃描電壓s4致能該第二個對偶畫素電路7中的每一第二畫素單元72時、於該掃描電壓s2致能該第一個對偶畫素電路7中的每一第二畫素單元72時,及於該掃描電壓s6致能該第三個對偶畫素電路7中的每一第二畫素單元72時改變,以致每一資料電壓d1、d2具有該第一至第三準位變化量V1~V3。該等資料電壓d3、d4的準位變化(圖未示)分別與該等資料電壓d1、d2相似,且該第一至第三準位變化量V1~V3的範圍與該第一較佳 實施例相似,故不重述。 It should be noted that, in this embodiment, in the picture period T2, each of the data voltages d 1 , d 2 is located at the scan voltage s 4 to enable each of the second dual pixel circuits 7 . When the second pixel unit 72 enables the second pixel unit 72 of the first dual pixel circuit 7 when the scan voltage s 2 is enabled, and the third voltage is enabled for the scan voltage s 6 Each of the second pixel units 72 in the dual pixel circuit 7 is changed so that each of the data voltages d 1 and d 2 has the first to third level variations V1 to V3. The level changes (not shown) of the data voltages d 3 and d 4 are similar to the data voltages d 1 and d 2 , respectively, and the ranges of the first to third level changes V1 to V3 are the same as the first A preferred embodiment is similar and will not be repeated.
參閱圖11,本發明液晶顯示裝置之第三較佳實施例與該第一較佳實施例相似,二者不同之處在於:此實施例以一共同端信號產生電路8取代該第一較佳實施例中的該共同端信號產生電路6(見圖6)。該共同端信號產生電路8用來產生一交流共同電壓ac_vcom,且該共同端信號產生電路8的連接方式與該共同端信號產生電路6相似,故不重述。 Referring to FIG. 11, a third preferred embodiment of the liquid crystal display device of the present invention is similar to the first preferred embodiment. The difference is that this embodiment replaces the first preferred one with a common terminal signal generating circuit 8. The common-end signal generating circuit 6 (see Fig. 6) in the embodiment. The common-end signal generating circuit 8 is configured to generate an AC common voltage ac_vcom, and the connection mode of the common-end signal generating circuit 8 is similar to that of the common-end signal generating circuit 6, and therefore will not be described again.
參閱圖12,顯示此實施例中的該液晶顯示裝置在該畫面週期T1內,該交流共同電壓ac_vcom需改變其準位,以避免該等對偶畫素電路7產生極化現象,且當該交流共同電壓ac_vcom的準位小於該等薄膜電晶體711中的一者所接收到的資料電壓的準位時,對應該等薄膜電晶體711中的一者的該儲存電容712根據對應的該資料電壓進行充電(圖12中以正號表示),當該交流共同電壓ac_vcom的準位大於該等薄膜電晶體711中的一者所接收到的資料電壓的準位時,對應該等薄膜電晶體711中的一者的該儲存電容712進行放電(圖12中以負號表示)。 Referring to FIG. 12, the liquid crystal display device in this embodiment is shown in the picture period T1, the alternating common voltage ac_vcom needs to change its level to avoid polarization of the dual pixel circuits 7, and when the alternating current When the level of the common voltage ac_vcom is less than the level of the data voltage received by one of the thin film transistors 711, the storage capacitor 712 corresponding to one of the thin film transistors 711 is corresponding to the corresponding data voltage. Charging (indicated by a positive sign in FIG. 12), when the level of the alternating common voltage ac_vcom is greater than the level of the data voltage received by one of the thin film transistors 711, the corresponding thin film transistor 711 The storage capacitor 712 of one of them is discharged (shown by a minus sign in FIG. 12).
參閱圖12與圖13,本實施例所執行的該驅動方法為:該交流共同電壓ac_vcom的最高準位等於該偏壓電壓VDDA的一半,每一資料電壓d1、d2的最高準位略小於該偏壓電壓VDDA的一半,每一資料電壓d1、d2的最低準位略大於零,但不限於此。 Referring to FIG. 12 and FIG. 13 , the driving method performed in this embodiment is: the highest level of the alternating common voltage ac_vcom is equal to half of the bias voltage VDDA, and the highest level of each data voltage d 1 , d 2 is slightly Less than half of the bias voltage VDDA, the lowest level of each data voltage d 1 , d 2 is slightly larger than zero, but is not limited thereto.
當操作於該畫面週期T1內時,此實施例中的該掃描驅動電路4致能該等對偶畫素電路7的操作程序與該第一較佳實施例相似,故不重述。 When the operation is performed in the picture period T1, the operation procedure of the scan driving circuit 4 in this embodiment to enable the dual pixel circuits 7 is similar to the first preferred embodiment, and therefore will not be described again.
此時,該資料電壓d1的準位於該掃描電壓s4致能該第二個對偶畫素電路7中的每一第二畫素單元72時由最高準位轉為最低準位、於該掃描電壓s2致能該第一個對偶畫素電路7中的每一第二畫素單元72時由最低準位轉為最高準位、於該掃描電壓s3致能該第二個對偶畫素電路7中的每一第一畫素單元71時由最高準位轉為最低準位,而該資料電壓d2的準位變化則互補於該資料電壓d1。該等資料電壓d3、d4的準位變化(圖未示)分別與該等資料電壓d1、d2相似,故不重述。 At this time, the data voltage d 1 is located at the lowest level from the highest level to the lowest level when the scanning voltage s 4 enables each of the second pixel units 72 of the second dual pixel circuit 7 . The scan voltage s 2 enables each second pixel unit 72 in the first dual pixel circuit 7 to be rotated from the lowest level to the highest level, and the second dual picture is enabled at the scan voltage s 3 Each of the first pixel units 71 in the prime circuit 7 is switched from the highest level to the lowest level, and the level change of the data voltage d 2 is complementary to the data voltage d 1 . The level changes (not shown) of the data voltages d 3 and d 4 are similar to the data voltages d 1 and d 2 , respectively, and therefore are not repeated.
應注意的是,在此實施例中,於該畫面週期T1內,每一資料電壓d1~d4的準位變化三次,且當該掃描驅動電路4致能該第一個對偶畫素電路7中的每一第二畫素單元72時(即,該掃描電壓s2使該等薄膜電晶體711中的對應者導通時),此時該交流共同電壓ac_vcom的準位改變,以致該交流共同電壓ac_vcom具有一準位變化量V4,且該準位變化量V4等於該偏壓電壓VDDA的一半。 It should be noted that, in this embodiment, in the picture period T1, the level of each data voltage d 1 ~ d 4 changes three times, and when the scan driving circuit 4 enables the first dual pixel circuit Each of the second pixel units 72 of 7 (ie, when the scanning voltage s 2 turns on the corresponding one of the thin film transistors 711), the level of the alternating common voltage ac_vcom changes at this time, so that the alternating current The common voltage ac_vcom has a level change amount V4, and the level change amount V4 is equal to half of the bias voltage VDDA.
參閱圖14,本發明液晶顯示裝置之第四較佳實施例與該第三較佳實施例相似,二者不同之處在於:此實施例省略於圖12之該第三較佳實施例中的第七及第八條掃描線2,及該第四個對偶畫素電路7,亦即此實施例僅包含 六(M=6)條掃描線2,及三(K=3)個對偶畫素電路7,但不限於此。 Referring to FIG. 14, a fourth preferred embodiment of the liquid crystal display device of the present invention is similar to the third preferred embodiment, except that the embodiment is omitted from the third preferred embodiment of FIG. The seventh and eighth scan lines 2, and the fourth dual pixel circuit 7, that is, this embodiment only includes Six (M=6) scanning lines 2, and three (K=3) dual pixel circuits 7, but are not limited thereto.
參閱圖14與圖15,本實施例所執行的該驅動方法為:當操作於該畫面週期T2內時,該掃描驅動電路4致能該等對偶畫素電路7的操作程序與該第二較佳實施例相似,且每一資料電壓d1~d4及該交流共同電壓ac_vcom的準位變化情形與該第三較佳實施例相似,故不重述。 Referring to FIG. 14 and FIG. 15, the driving method performed in this embodiment is: when operating in the picture period T2, the scan driving circuit 4 enables the operation procedure of the dual pixel circuits 7 and the second comparison. The preferred embodiment is similar, and the level change of each of the data voltages d1 to d4 and the alternating common voltage ac_vcom is similar to that of the third preferred embodiment, and therefore will not be repeated.
綜上所述,上述實施例具有以下優點: In summary, the above embodiment has the following advantages:
1.當該共同端信號產生電路6用於產生該直流共同電壓dc_vcom時,於該畫面週期T1內,每一資料電壓d1~d4準位變化的次數較少(準位變化三次),且每一資料電壓d1~d4的準位變化量較小(該第一至第三準位變化量V1~V3皆小於該偏壓電壓VDDA),相較於習知每一資料電壓D1~D4具有四次準位變化,且每一準位變化量等於該偏壓電壓VDDA,具有較低功率損耗。 1. When the common-side signal generating circuit 6 is configured to generate the DC common voltage dc_vcom, the number of times each of the data voltages d 1 to d 4 changes in the frame period T1 is less (the level changes three times). And the amount of change of the level of each data voltage d 1 ~ d 4 is small (the first to third level change amounts V1 ~ V3 are smaller than the bias voltage VDDA), compared to the conventional data voltage D 1 ~ D 4 have four level changes, and each level change is equal to the bias voltage VDDA, with lower power loss.
2.當該共同端信號產生電路8用於產生該交流共同電壓ac_vcom時,於該畫面週期T1內,由於該交流共同電壓ac_vcom及每一資料電壓d1~d4準位變化的次數較少(分別是一次、三次),相較於習知的該交流共同電壓AC_vcom及每一資料電壓D1~D4皆是四次準位變化,具有較低功率損耗。 2. When the common-side signal generating circuit 8 is configured to generate the alternating common voltage ac_vcom, the number of times the alternating common voltage ac_vcom and each of the data voltages d 1 to d 4 change is less in the picture period T1. (One time, three times respectively), compared with the conventional AC common voltage AC_vcom and each data voltage D 1 ~ D 4 are four-level change with lower power loss.
惟以上所述者,僅為本發明之較佳實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修 飾,皆仍屬本發明專利涵蓋之範圍內。 However, the above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the simple equivalent change and repair according to the scope of the patent application and the patent specification of the present invention. Decorations are still within the scope of the invention patent.
2‧‧‧掃描線 2‧‧‧ scan line
3‧‧‧資料線 3‧‧‧Information line
4‧‧‧掃描驅動電路 4‧‧‧Scan drive circuit
s1~s8‧‧‧掃描電壓 s 1 ~s 8 ‧‧‧ scan voltage
5‧‧‧資料驅動電路 5‧‧‧Data Drive Circuit
d1~d4‧‧‧資料電壓 d 1 ~d 4 ‧‧‧data voltage
6‧‧‧共同端信號產生電路 6‧‧‧Common signal generation circuit
dc_vcom‧‧‧直流共同電壓 Dc_vcom‧‧‧DC common voltage
7‧‧‧對偶畫素電路 7‧‧‧Dual pixel circuit
71‧‧‧第一畫素單元 71‧‧‧ first pixel unit
72‧‧‧第二畫素單元 72‧‧‧Second pixel unit
711‧‧‧薄膜電晶體 711‧‧‧film transistor
712‧‧‧儲存電容 712‧‧‧ Storage Capacitor
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