TW201519576A - Digital logic circuit and digital logic element - Google Patents

Abstract

A digital logic circuit is applied the concept of Schmitt trigger and operating in sub-threshold region and near-threshold region of transistor. The second terminal of a first transistor and a second transistor of the digital logic circuit are directly connected with a operating voltage respectively. The first terminal of a third transistor is directly connected with the first terminal of the first transistor. Its second terminal is directly connected with the third terminal of the first transistor and the first terminal of the second transistor respectively. Its third terminal is electrically connected with the third terminal of the second transistor. The first terminal of a forth transistor is directly connected with the first terminal of the third transistor. Its second terminal is directly connected with the third terminal of the second transistor and electrically connected with the third terminal of the third transistor. Its third terminal is electrically connected with a ground terminal. The invention also disclosed a digital logic element.

Description

Digital logic circuit and digital logic component

The present invention relates to a digital logic circuit and a digital logic element, and more particularly to a digital logic circuit and a digital logic element operable in a sub-threshold voltage region or a near-critical voltage region of a transistor.

As electronic products continue to evolve, applications such as portable mobile devices, biomedical electronic systems, and wireless sensors require low power designs to extend product life. Generally speaking, when the voltage difference between the gate and the source of the transistor is greater than or equal to its threshold voltage, the transistor will be turned on, but the power loss is also high. In order to reduce the loss of the transistor, a newer technology is used. Ultra low voltage is used to operate the transistor. Therefore, ultra low voltage design is one of the emerging and effective methods for applications where low power consumption is the first priority.

Ultra-low voltage design means that the circuit operates in the sub-threshold region or the near-threshold region of the transistor, and operating in this voltage region can make the circuit have less energy consumption and Very low leakage current power consumption. However, it is quite challenging to operate the circuit near this voltage. As the overdrive voltage of the transistor is reduced, the on-current of the transistor is close to the static leakage current, so the functionality of the circuit will be affected, especially This effect will be deepened by the process variation of the transistor, and the most influential one is the correctness of the circuit function. Since the operating voltage approaches the threshold voltage, the on-state current when the transistor is turned on is quite close to the leakage current when the transistor is in a static state (ie, when it is not turned on), so that the logic circuit does not necessarily be correctly charged to logic 1 or Discharging to a logic 0 causes an error in the logic decision that prevents the logic circuit from functioning properly when operating near the threshold voltage.

In order to enable complementary logic (Complementary Logic) circuits to be positive Indeed operating in the sub-threshold voltage region or the near-threshold voltage region, increasing the ratio of the transistor on-current to the static leakage current is a primary goal. Technically, increasing the ratio of the transistor conduction current to the static leakage current can be increased by conduction. Current is achieved and or static leakage current is reduced.

It is an object of the present invention to provide a digital logic circuit and digital logic elements that operate correctly in a sub-threshold voltage region or a near-critical voltage region of a transistor to reduce power consumption.

To achieve the above object, a digital logic circuit according to the present invention applies the concept of a Schmitt trigger, and the digital logic circuit operates in a sub-critical voltage region or a near-critical voltage region of the transistor, and includes a first transistor, a a second transistor, a third transistor, and a fourth transistor. The second end of the first transistor is directly connected to an operating voltage. The second end of the second transistor is directly connected to the operating voltage. The first end of the third transistor is directly connected to the first end of the first transistor, and the second end thereof is directly connected to the third end of the first transistor and the first end of the second transistor, respectively, and the third end thereof The third end of the second transistor is electrically connected. The first end of the fourth transistor is directly connected to the first end of the third transistor, the second end of the fourth transistor is directly connected to the third end of the second transistor, and is electrically connected to the third end of the third transistor. The third end is electrically connected to a ground.

To achieve the above object, a digital logic circuit according to the present invention applies the concept of a Schmitt trigger and can operate in a sub-critical voltage region or a near-critical voltage region of a transistor, the digital logic circuit including a first transistor, a second transistor, a third transistor, and a fourth transistor. The second end of the first transistor is directly connected to an operating voltage. The second end of the second transistor is directly connected to the operating voltage. The first end of the third transistor is directly connected to the first end of the first transistor, the second end of the third transistor is directly connected to the first end of the second transistor, and is electrically connected to the third end of the first transistor. The third end is directly connected to the third end of the second transistor. The first end of the fourth transistor is directly connected to the first end of the third transistor, and the second end thereof is directly connected to the third end of the second transistor and the third end of the third transistor, respectively, and the third end thereof Connect directly to a ground terminal.

In one embodiment, the third end of the third transistor is directly connected to the third end of the second transistor and the second end of the fourth transistor, and the third end of the fourth transistor is directly connected to the ground.

In one embodiment, the leakage current of the third transistor is reduced by controlling the second transistor.

In one embodiment, the leakage current of the third transistor and the sixth transistor is reduced by controlling the second transistor.

In an embodiment, the digital logic circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor. The second end of the fifth transistor is directly connected to the working voltage, and the third end is directly connected to the third end of the first transistor and the second end of the third transistor, respectively. The first end of the sixth transistor is electrically connected to the first end of the fifth transistor, the second end thereof is directly connected to the third end of the third transistor, and the third end thereof is respectively connected with the third end of the second transistor The terminal and the second end of the fourth transistor are directly connected. The first end of the seventh transistor is directly connected to the first end of the sixth transistor, the second end of the seventh transistor is directly connected to the third end of the fourth transistor, and the third end is directly connected to the ground.

In an embodiment, the digital logic circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor. The second end of the fifth transistor is directly connected to the third end of the first transistor, and the third end is directly connected to the first end of the second transistor and the second end of the third transistor, respectively. The first end of the sixth transistor is directly connected to the first end of the fifth transistor, and the second end thereof is respectively connected to the first end of the second transistor, the second end of the third transistor, and the fifth transistor The three ends are directly connected, and the third end thereof is directly connected to the third end of the second transistor and the third end of the third transistor. The first end of the seventh transistor is directly connected to the first end of the fifth transistor and the first end of the sixth transistor, and the second end thereof is respectively connected to the third end of the second transistor and the third transistor The third end and the third end of the sixth transistor are directly connected, and the third end is directly connected to the ground.

In one embodiment, the operating voltage is close to the threshold voltage of the transistors.

To achieve the above object, a digital logic element in accordance with the present invention includes at least the above-described digital logic circuit.

In one embodiment, the digital logic element includes a gate, a gate, a mutex or gate, an adder, a subtractor, a multiplier, a divider, a central processing unit, a microcontroller or A digital signal processor.

As described above, in the digital logic circuit and the digital logic element of the present invention, the concept of a Schmitt trigger is applied and can be operated in a sub-critical voltage region or a near-critical voltage region of the transistor. Among them, the digital logic circuit and the digital logic component are made by the connection relationship of the transistors. The output affects (cuts off) the path of its static leakage current conduction, minimizing the static leakage current, thereby increasing the ratio of the transistor conduction current to the static leakage current, so that the digital logic circuit can be correctly and robustly charged to logic 1. Therefore, the digital logic circuit and the digital logic element of the present invention have the capability of ultra-low voltage operation and self-tolerance process variation, and have minimal energy consumption and extremely low leakage current power consumption.

1, 2, 3‧‧‧ digital logic circuits

A, B‧‧‧ input

I _OFF , I _OFF1 , I _OFF2 ‧‧‧Leakage current

I _ON1 , I _ON2 , I _ON3 ‧‧‧ conduction current

T1~T7‧‧‧O crystal

T11~T71‧‧‧ first end

T12~T72‧‧‧ second end

T13~T73‧‧‧ third end

V _DD ‧‧‧ working voltage

V _O ‧‧‧ output

1 is a circuit diagram of a digital logic circuit in accordance with a preferred embodiment of the present invention.

2 is a circuit diagram of a digital logic circuit according to another preferred embodiment of the present invention.

3 is a circuit diagram of a digital logic circuit according to still another preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a digital logic circuit and a digital logic element in accordance with a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.

The digital logic circuit and the digital logic component of the present invention apply the Schmitt-Trigger concept and include a circuit composed of a plurality of transistors. Wherein, the digital logic circuit and the digital logic element can robustly operate in a Sub-threshold region or a Near-threshold region to reduce power consumption of the overall circuit or component, and Enables logic circuits or components to have ultra-low voltage operation and self-tolerance process variation. Here, the operation of the transistor in the sub-threshold voltage region or the near-critical voltage region indicates that the operating voltage (and input voltage) supplied to the transistor is "close" to the threshold voltage (Vth) of the transistor. Wherein, close proximity means that the operating voltage can be equal to the threshold voltage, or greater than a little, or less than a little, and the relevant art can be fully understood by those skilled in the art.

Please refer to FIG. 1, which is a circuit diagram of a digital logic circuit 1 in accordance with a preferred embodiment of the present invention.

The digital logic circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Here, the digital logic circuit 1 takes an example of a NOT Gate. The first transistor T1 to the fourth transistor T4 are applied with complementary gold It is manufactured by the Complementary Metal-Oxide-Semiconductor (CMOS) process. The first transistor T1 is a PMOS (P-channel MOSFET), and the second transistor T2, the third transistor T3, and the fourth transistor T4 are respectively exemplified by an NMOS (N-channel MOSFET). In addition, the first point is that the following "direct connection" and "electrical connection" are not exactly the same, and the direct connection must be electrically connected, but the electrical connection is not necessarily a direct connection. Wherein, the direct connection means that only the conductive material (for example, a metal layer) is connected between the two, and there is no other element between the two. The electrical connection includes a direct connection, indicating that the two can be connected through other components.

As shown in FIG. 1, the first end T11 of the first transistor T1, the first end T31 of the third transistor T3, and the first end T41 of the fourth transistor T4 are directly connected and connected to the digital logic circuit 1. An input A. In addition, the second terminal T12 of the first transistor T1 is directly connected to an operating voltage V _DD , and the second terminal T22 of the second transistor T2 is also directly connected to the operating voltage V _DD . Here, the operating voltage V _DD is a constant voltage (not equal to 0V), and is the operating voltage of the transistor, and the second end T12 of the first transistor T1 and the second end T22 of the second transistor T2 are not Directly connected to the operating voltage V _DD via other components. Here, a practical example will be given to explain the operating voltage V _DD and the threshold voltage. Taking a typical 90 nm process as an example, the threshold voltage of the NMOS or PMOS is, for example, 0.45 to 0.46 volts, and the operating voltage is, for example, 0.4 volts (below the threshold voltage).

In addition, the second end T32 of the third transistor T3 is directly connected to the third end T13 of the first transistor T1 and the first end T21 of the second transistor T2, respectively, and the third end T33 of the third transistor T3 is The third end T23 of the second transistor T2 is electrically connected. The second end T42 of the fourth transistor T4 is directly connected to the third end T23 of the second transistor T2, and is electrically connected to the third end T33 of the third transistor T3, and the third end of the fourth transistor T4. The T43 is electrically connected to a ground.

In this embodiment, as shown in FIG. 1, the third end T33 of the third transistor T3 is directly connected to the third end T23 of the second transistor T2 and the second end T42 of the fourth transistor T4, respectively. The third end T43 of the fourth transistor T4 is directly connected to the ground. Wherein, in the case of PMOS, the first end is a gate, the second end is a source, and the third end is a drain; in the case of an NMOS, the first end is a gate and the second end is a gate. The pole is the source at the third end.

Therefore, when the input terminal A of the digital logic circuit 1 is logic 0 (0 V), the supply current of the first transistor T1 (PMOS) operation (ie, the on current I _ON1 ) will flow from the operating voltage V _DD to the first transistor T1. The second terminal T12 and its third terminal T13 (one output terminal V _O of the digital logic circuit 1) cause the potential of the output terminal V _O to gradually rise to a logic 1 (ie, rise to V _DD ). When the output terminal V _O is logic 1, the supply current (ie, the on current I _ON2 ) of the second transistor T2 (NMOS) operation will flow from the operating voltage V _DD to the second terminal T22 and the third end of the second transistor T2. T23, finally, the potential of the third terminal T23 of the second transistor T2, the third terminal T33 of the third transistor T3, and the second terminal T42 of the fourth transistor T4 is made close to the operating voltage V _DD . Therefore, the voltage difference between the second terminal T32 of the third transistor T3 and its third terminal T33 will approach zero (ideally zero), and the first terminal T31 of the third transistor T3 and its third terminal T33 The voltage difference is negative. Since the third transistor T3 is not turned on (NMOS), and the voltage difference between the second terminal T32 of the third transistor T3 and the third terminal T33 thereof approaches zero, the leakage current I _{OFF of the} third transistor T3 is minimized. . Therefore, the digital logic circuit 1 reduces the leakage current of the third transistor T3 by controlling the second transistor T2. In other words, the digital logic circuit 1 causes the output terminal V _{O to} influence (truncate) the path through which the static leakage current (ie, the leakage current) conducts, thereby minimizing the static leakage current, thereby increasing the ratio of the transistor conduction current to the static leakage current, The digital logic circuit 1 can be correctly and robustly charged to logic 1. On the contrary, when the input terminal A of the digital logic circuit 1 is logic 1 (V _DD ), the third transistor T3 and the fourth transistor T4 will be turned on, and the potential of the output terminal V _O can pass through the third transistor T3 and the third The quad transistor T4 is correctly discharged to a logic zero. Therefore, the digital logic circuit 1 has the capability of ultra-low voltage operation and self-tolerance process variation, and has minimal energy consumption and extremely low leakage current power consumption.

Furthermore, the conventional NOT gate circuit uses two stacked PMOSs (series) in comparison with other conventional NOT gate circuits that use the Schmitt trigger concept and operate at a sub-threshold voltage or a near-threshold voltage. Since the carrier mobility of the NMOS is larger than that of the PMOS, the current of the PMOS transistor is smaller than that of the NMOS transistor under the same size, so the stacked PMOS will make the on-current smaller, resulting in the output terminal V _O . The charging speed becomes slower (the circuit delay time becomes longer). However, the digital logic circuit 1 of the embodiment uses only one PMOS, so that the overall layout area can be reduced and the circuit can be reduced as compared with the conventional circuit. Delay time and power loss.

In addition, please refer to FIG. 2, which is a circuit diagram of the digital logic circuit 2 according to another preferred embodiment of the present invention. Here, the digital logic circuit 2 is exemplified by a NAND gate.

The digital logic circuit 2 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. In addition, the digital logic circuit 2 further includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first to seventh transistors T1 to T7 of the present embodiment are still applied to a transistor fabricated by a complementary metal oxide semiconductor process. The first transistor T1 and the fifth transistor T5 are respectively PMOS, and the second to fourth transistors T2 to T4, the sixth transistor T6 and the seventh transistor T7 are respectively exemplified by NMOS.

The first end T11 of the first transistor T1, the first end T31 of the third transistor T3, and the first end T41 of the fourth transistor T4 are directly connected and connected to one input terminal A of the digital logic circuit 2, and The first end T51 of the fifth transistor T5, the first end T61 of the sixth transistor T6, and the first end T71 of the seventh transistor T7 are directly connected and connected to one input terminal B of the digital logic circuit 1. In addition, the second end T12 of the first transistor T1 is directly connected to the operating voltage V _DD , and the second end T22 of the second transistor T2 is also directly connected to the operating voltage V _DD .

The second end T32 of the third transistor T3 is directly connected to the third end T13 of the first transistor T1 and the first end T21 of the second transistor T2, respectively, and the third end T33 and the second end of the third transistor T3 The third end T23 of the transistor T2 is electrically connected. In addition, the second end T42 of the fourth transistor T4 is directly connected to the third end T23 of the second transistor T2, and is electrically connected to the third end T33 of the third transistor T3, and the fourth transistor T4 is The three-terminal T43 is electrically connected to a ground terminal. In addition, the second end T52 of the fifth transistor T5 is directly connected to the working voltage V _DD , and the third end T53 is directly connected to the third end T13 of the first transistor T1 and the second end T32 of the third transistor T3, respectively. .

In this embodiment, as shown in FIG. 2, the third end T33 of the third transistor T3 is electrically connected to the third end T23 of the second transistor T2 through the sixth transistor T6, and the fourth transistor T4 is connected. The second end T42 is electrically connected to the third end T33 of the third transistor T3 through the sixth transistor T6, and the third end T43 of the fourth transistor T4 is transmitted through the seventh transistor T7 and the ground. Electrical connection. Here, the second end T62 of the sixth transistor T6 and the third transistor T3 The third end T33 is directly connected, and the third end T63 is directly connected to the third end T23 of the second transistor T2 and the second end T42 of the fourth transistor T4. In addition, the second end T72 of the seventh transistor T7 is directly connected to the third end T43 of the fourth transistor T4, and the third end T73 is directly connected to the ground.

Therefore, when the input terminal A and the input terminal B of the digital logic circuit 2 are simultaneously logic 0 (0 V), the supply current (ie, the on current I _ON1 ) of the first transistor T1 and the supply current of the fifth transistor T5 are supplied. (ie, the on current I _ON3 ) will flow from the operating voltage V _DD to the second terminal T12 of the first transistor T1, the third terminal T13, and the second terminal T52 and the third terminal T53 of the fifth transistor T5 (the digital logic circuit 2) The output terminal V _O ) causes the potential of the output terminal V _O to gradually rise to a logic 1 (ie, rise to V _DD ). When the output terminal V _O is logic 1, the supply current (ie, the on current I _ON2 ) of the second transistor T2 (NMOS) operation will flow from the operating voltage V _DD to the second terminal T22 and the third end of the second transistor T2. T23, finally, the potential of the third terminal T23 of the second transistor T2, the third terminal T63 of the sixth transistor T6, and the second terminal T42 of the fourth transistor T4 is made close to the operating voltage V _DD . Therefore, the voltage difference between the second terminal T32 of the third transistor T3 and the third terminal T63 of the sixth transistor T6 will approach zero (ideally zero), and the first terminal T61 of the sixth transistor T6 The voltage difference from its third terminal T63 is negative. Since the third transistor T3 and the sixth transistor T6 are not turned on (NMOS), and the voltage difference between the second terminal T32 of the third transistor T3 and the third terminal T63 of the sixth transistor T6 approaches zero, The leakage current I _{OFF of the} three transistor T3 and the sixth transistor T6 will be minimized. Therefore, the digital logic circuit 2 reduces the leakage currents of the third transistor T3 and the sixth transistor T6 by controlling the second transistor T2. In other words, the digital logic circuit 2 causes the output terminal V _{O to} influence (truncate) the path through which the static leakage current (ie, the leakage current) conducts, thereby minimizing the static leakage current, thereby increasing the ratio of the transistor conduction current to the static leakage current, The digital logic circuit 2 can be correctly and robustly charged to logic 1. On the contrary, when the input terminal A and the input terminal B of the digital logic circuit 2 are logic 1 (V _DD ), the third to seventh transistors T3 to T7 will be turned on, and the potential of the output terminal V _O can pass through the third. The transistor T3 to the seventh transistor T7 are correctly discharged to a logic 0. Therefore, the digital logic circuit 2 has the capability of ultra-low voltage operation and self-tolerance process variation, and has minimal energy consumption and extremely low leakage current power consumption.

It is also mentioned that the Schmitt trigger concept is used and operated in other times. Compared with the NAND gate circuit of the threshold voltage or the near-threshold voltage, the conventional NAND gate circuit uses two sets of two stacked PMOSs (series). Since the carrier mobility of the NMOS is larger than that of the PMOS, it is in the same size. The current of the PMOS transistor is smaller than that of the NMOS transistor, so stacking the PMOS will make the on-current smaller (because the stacked transistor will have the threshold voltage of the transistor due to its influence of the body bias effect). When it becomes larger, the on-current of the transistor is further reduced, but since the current of the PMOS itself is relatively small, the phenomenon of stacking will make the on-current smaller, which is disadvantageous for charging, and the delay time becomes longer, resulting in the output end. The charging speed is slower (the circuit delay time becomes longer). However, the digital logic circuit 2 of the embodiment uses only two groups of one PMOS, so that the overall layout (Layout) area can be reduced compared with the conventional circuit. It can reduce the delay time and power loss of the circuit.

In addition, please refer to FIG. 3, which is a circuit diagram of the digital logic circuit 3 according to still another preferred embodiment of the present invention. Here, the digital logic circuit 3 is exemplified by a NOR Gate.

The digital logic circuit 3 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. In addition, the digital logic circuit 3 further includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first to seventh transistors T1 to T7 of the present embodiment are still applied to a transistor fabricated by a complementary metal oxide semiconductor process. The first transistor T1 and the fifth transistor T5 are respectively PMOS, and the second to fourth transistors T2 to T4, the sixth transistor T6 and the seventh transistor T7 are respectively exemplified by NMOS.

The first end T11 of the first transistor T1, the first end T31 of the third transistor T3, and the first end T41 of the fourth transistor T4 are directly connected and connected to one input terminal A of the digital logic circuit 3, and The first end T51 of the fifth transistor T5, the first end T61 of the sixth transistor T6, and the first end T71 of the seventh transistor T7 are directly connected and connected to one input terminal B of the digital logic circuit 1. In addition, the second end T12 of the first transistor T1 is directly connected to the operating voltage V _DD , and the second end T22 of the second transistor T2 is also directly connected to the operating voltage V _DD .

The second end T32 of the third transistor T3 is directly connected to the first end T21 of the second transistor T2, and is electrically connected to the third end T13 of the first transistor T1, and the third end T33 of the third transistor T3. It is directly connected to the third end T23 of the second transistor T2. In this embodiment, the third The second end T32 of the transistor T3 is electrically connected to the third end T13 of the first transistor T1 through the fifth transistor T5. The second end T52 of the fifth transistor T5 is directly connected to the third end T13 of the first transistor T1, and the third end T53 of the fifth transistor T5 and the first end T21 of the second transistor T2 are respectively The second end T32 of the tri-crystal T3 is directly connected.

In addition, the second end T42 of the fourth transistor T4 is directly connected to the third end T23 of the second transistor T2 and the third end T33 of the third transistor T3, and the third end T43 of the fourth transistor T4 is grounded. The terminal is directly connected.

The second end T62 of the sixth transistor T6 is directly connected to the first end T21 of the second transistor T2, the second end T32 of the third transistor T3, and the third end T53 of the fifth transistor T5, respectively. The third end T63 of the transistor T6 is directly connected to the third end T23 of the second transistor T2 and the third end T33 of the third transistor T3.

In addition, the first end T71 of the seventh transistor T7 is directly connected to the first end T51 of the fifth transistor T5 and the first end T61 of the sixth transistor T6, respectively, and the second end T72 of the seventh transistor T7 is respectively The third end T23 of the second transistor T2, the third end T33 of the third transistor T3, and the third end T63 of the sixth transistor T6 are directly connected, and the third end T73 of the seventh transistor T7 is directly connected to the ground. connection.

Therefore, when the input terminal A and the input terminal B of the digital logic circuit 3 are simultaneously logic 0 (0 V), the supply current of the first transistor T1 and the fifth transistor T5 (PMOS) is operated (ie, the on current I _ON1 ) Flowing from the operating voltage V _DD to the second terminal T12 and the third terminal T13 of the first transistor T1, and to the second terminal 52 of the fifth transistor T5 and the third terminal T53 thereof (the output terminal of the digital logic circuit 3 V _{O )} ), so that the potential of the output terminal V _O gradually rises to a logic 1 (ie, rises to V _DD ). When the output terminal V _O is logic 1, the supply current (ie, the on current I _ON2 ) of the second transistor T2 (NMOS) operation will flow from the operating voltage V _DD to the second terminal T22 and the third end of the second transistor T2. T23, finally, the potential of the third terminal T23 of the second transistor T2, the third terminal T33 of the third transistor T3, and the third terminal T63 of the sixth transistor T6 is made close to the operating voltage V _DD . Therefore, the voltage difference between the second end T32 of the third transistor T3 and the third end T33, the second end T62 of the sixth transistor T6 and the third end T63 thereof will respectively approach zero (ideally zero). The voltage difference between the first end T31 of the third transistor T3 and the third end T33, the first end T61 of the sixth transistor T6 and the third end T63 thereof is a negative value. The third transistor T3 and the sixth transistor T6 are not turned on (NMOS), and the voltage difference between the second terminal T32 of the third transistor T3 and the third terminal T33 thereof is close to zero, and the sixth transistor T6 is The voltage difference between the two terminals T62 and the third terminal T63 also approaches zero, so the leakage current I _{OFF1 of the} third transistor T3 will be minimized, and the leakage current I _{OFF2 of the} sixth transistor T6 will be minimized. Therefore, the digital logic circuit 3 reduces the leakage currents of the third transistor T3 and the sixth transistor T6 by controlling the second transistor T2. In other words, the digital logic circuit 3 causes the output terminal V _{O to} influence (cut off) the path through which the static leakage current (ie, the leakage current) conducts, thereby minimizing the static leakage current, thereby increasing the ratio of the transistor conduction current to the static leakage current, The digital logic circuit 3 can be charged to logic 1 correctly and robustly. On the other hand, when the input terminal A or the input terminal B of the digital logic circuit 3 is logic 1 (V _DD ), then the third transistor T3, the fourth transistor T4 and/or the sixth transistor T6, and the seventh transistor T7 Turning on, the potential of the output terminal V _O can be correctly discharged to the logic 0 through the third transistor T3, the fourth transistor T4, or the sixth transistor T6, and the seventh transistor T7. Therefore, the digital logic circuit 3 has the capability of ultra-low voltage operation and self-tolerance process variation, and has minimal energy consumption and extremely low leakage current power consumption.

Furthermore, the conventional NOR gate circuit uses four stacked PMOSs (series) in comparison with other conventional NOR gate circuits that use the Schmitt trigger concept and operate at sub-threshold voltage or near-threshold voltage. Since the carrier mobility of the NMOS is larger than that of the PMOS, the current of the PMOS transistor is smaller than that of the NMOS transistor under the same size, so the four stacked PMOSs will make the conduction current smaller, resulting in the charging speed of the output terminal. Slower (the circuit delay time becomes longer), however, the digital logic circuit 3 of the present embodiment uses only two stacked PMOSs, so that the overall layout area can be reduced and the delay of the circuit can be reduced as compared with the conventional circuit. Time and power loss.

In addition, by the above-mentioned digital logic circuits 1, 2, 3, and through, for example, a logic synthesizer, the Boolean function and the synthesis condition limit of the logic gate to be synthesized by the user can be automatically constructed to meet the requirements. Other logic gate circuits that are conditionally limited to form other digital logic circuits or digital logic elements. For example, a NO gate can be used to synthesize an AND gate or an OR gate, or a NAND gate can be used to synthesize other logic circuits, .... Thus, the digital logic elements of the present invention can be synthesized by a logic synthesizer and can include any of the above-described digital logic circuits (1, 2, 3). The digital logic component can be, for example but not limited to, an AND gate, an OR gate, a mutual exclusion or gate (XOR Gare), and an addition. , a subtractor, a multiplier, a divider, a central processing unit (CPU), a microcontroller (Micro Controller) or a digital signal processor (DSP), ... are not limited herein. Since the digital logic circuits (1, 2, 3) can operate robustly in the sub-threshold voltage region or near-critical voltage region to reduce the power consumption of the overall circuit and enable the logic circuit to have ultra-low voltage operation and self-tolerance process variation. Therefore, the synthesized digital logic elements also have the above advantages.

In summary, in the digital logic circuit and the digital logic component of the present invention, the concept of a Schmitt trigger is applied and can be operated in a sub-critical voltage region or a near-critical voltage region of the transistor. Among them, the connection between the digital logic circuit and the digital logic element affects (cuts off) the path of the static leakage current conduction by the connection relationship of the transistor, thereby minimizing the static leakage current, thereby increasing the transistor conduction current and the static leakage current. The ratio allows the digital logic to be correctly and robustly charged to logic 1. Therefore, the digital logic circuit and the digital logic element of the present invention have the capability of ultra-low voltage operation and self-tolerance process variation, and have minimal energy consumption and extremely low leakage current power consumption.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1‧‧‧Digital logic circuit

A‧‧‧ input

I _OFF ‧‧‧Leakage current

I _ON1 , I _ON2 ‧‧‧ conduction current

T1~T4‧‧‧O crystal

T11~T41‧‧‧ first end

T12~T42‧‧‧ second end

T13~T43‧‧‧ third end

V _DD ‧‧‧ working voltage

V _O ‧‧‧ output

Claims (10)

A digital logic circuit is a concept of applying a Schmitt trigger circuit, which is operated in a sub-critical voltage region or a near-critical voltage region of a transistor, and includes: a first transistor, a second end thereof and a first The working voltage is directly connected; a second transistor has a second end directly connected to the working voltage; and a third transistor has a first end directly connected to the first end of the first transistor, and a second end thereof Directly connected to the third end of the first transistor and the first end of the second transistor, the third end of which is electrically connected to the third end of the second transistor; and a fourth transistor, the first One end is directly connected to the first end of the third transistor, the second end is directly connected to the third end of the second transistor, and is electrically connected to the third end of the third transistor, and the third The terminal is electrically connected to a ground. The digital logic circuit of claim 1, wherein the third end of the third transistor is directly connected to the third end of the second transistor and the second end of the fourth transistor, respectively. The third end of the fourth transistor is directly connected to the ground. The digital logic circuit of claim 2, wherein the leakage current of the third transistor is reduced by controlling the second transistor. The digital logic circuit of claim 1, further comprising: a fifth transistor, wherein the second end is directly connected to the working voltage, and the third end is respectively connected to the third end of the first transistor; The second end of the third transistor is directly connected; a sixth transistor is electrically connected to the first end of the fifth transistor, and the second end is connected to the third end of the third transistor Directly connected, the third end of which is directly connected to the third end of the second transistor and the second end of the fourth transistor; and a seventh transistor, the first end thereof and the sixth transistor One end is directly connected, and the second end is directly connected to the third end of the fourth transistor, and the third end is directly connected to the ground end. A digital logic circuit is applied to the concept of a Schmitt trigger and is operable in a sub-critical voltage region or a near-critical voltage region of a transistor, the digital logic circuit comprising: a first transistor, a second end thereof and a first The working voltage is directly connected; a second transistor has a second end directly connected to the working voltage; a third transistor has a first end directly connected to the first end of the first transistor, and a second end Directly connected to the first end of the second transistor, and electrically connected to the third end of the first transistor, the third end of which is directly connected to the third end of the second transistor; and a fourth a first end of the crystal is directly connected to the first end of the third transistor, and a second end thereof is directly connected to the third end of the second transistor and the third end of the third transistor, respectively. The terminal is directly connected to a ground. The digital logic circuit of claim 5, further comprising: a fifth transistor, wherein the second end is directly connected to the third end of the first transistor, and the third end is respectively connected to the second transistor The first end is directly connected to the second end of the third transistor; a sixth transistor is directly connected to the first end of the fifth transistor, and the second end is respectively connected to the second end The first end of the crystal, the second end of the third transistor, and the third end of the fifth transistor are directly connected, and the third end thereof and the third end of the second transistor and the third transistor a three-terminal direct connection; and a seventh transistor, wherein the first end is directly connected to the first end of the fifth transistor and the first end of the sixth transistor, and the second end is respectively connected to the second end The third end of the crystal, the third end of the third transistor and the third end of the sixth transistor are directly connected, and the third end thereof is directly connected to the ground. The digital logic circuit of claim 4 or 6, wherein the leakage current of the third transistor and the sixth transistor is reduced by controlling the second transistor. The digital logic circuit of claim 1 or 5, wherein the operating voltage is close to a threshold voltage of the transistors. A digital logic element comprising at least one of the digital logic circuits of one of claims 1 to 8. The digital logic component of claim 9 includes a gate, a gate, a mutex or gate, an adder, a subtractor, a multiplier, a divider, and a central processing. , a microcontroller or a digital signal processor.