TW201519245A - Circuit and system of using junction diode as program selector for electrical fuses with extended area for one-time programmable devices - Google Patents

Abstract

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one diode or MOS that can be turned on through the channel or the source/drain junction. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.

Description

Single-time programmable memory, electronic system, operating single-time programmable memory method, and programmed single-time programmable memory method

This invention relates to a programmable memory element, and more particularly to a programmable resistive element for a memory array.

A programmable resistive element generally means that the resistive state of the component can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a One-Time Programmable (OTP) element (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP element. When a high current flows through the OTP element by turning the programming selector on, the OTP element will be programmed to be fired in a high or low resistance state (depending on whether it is a fuse or an antifuse).

Electrical fuses are a common type of OTP, and such programmable resistive elements can be connected by a length of interconnect, such as polysilicon, germanium polysilicon, germanide, metal, metal alloy, or combinations thereof. The metal can be aluminum, copper or other transition metal. The most commonly used electrical fuse is a CMOS gate made of deuterated polysilicon, used as an interconnect. The electrical fuse can also be one or more contacts or vias, rather than an internal connection of small segments. The high current can burn the contact point or layer indirectly into a high resistance state. The electrical fuse can be an anti-fuse, where a high voltage reduces the resistance rather than increasing the resistance. The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The anti-fuse can also be coupled to the CMOS body by a CMOS gate, which contains a gate oxide layer as Insulator.

The programmable resistive element can be a reversible resistive element that can be reprogrammed and reversibly programmable to a digital logic value of "0" or "1". The programmable resistive element can be fabricated from a phase change material such as germanium (Ge), germanium (Sb), germanium (Te), Ge2Sb2Te5 (GST-225) or consists of indium (In), tin (Sn) or selenium ( Se) GeSbTe type material. Another phase change material comprises a chalcogenide material such as AgInSbTe. The phase change material can be programmed to an amorphous high resistance state or a crystalline low resistance state via a high voltage short pulse or a low voltage long pulse. Another type of reversible resistance element is a type of memory called a resistive random access memory (RRAM) that is initially an insulating dielectric that can then be turned on via filamentation, defects, or metal migration. The dielectric may be a transition metal oxide such as NiO or TiO2; or a perovskite material such as Sr(Zr)TiO3 or PCMO; or a charge transfer complex such as CuTCNQ; or an organic donor-receptor system , such as Al AIDCN. The RRAM memory cell consists of a metal oxide between the electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt), titanium nitride/titanium oxide/yttria/titanium nitride (TiN/TiOx/HfO2/TiN) , titanium nitride / zinc oxide / platinum (TiN / ZnO / Pt), or tungsten / titanium nitride / ceria / bismuth (W / TiN / SiO2 / Si). The change in reversibility of the resistance state is via the polarity, intensity, and duration of the voltage or current pulse to create or destroy the conductive filament.

Another programmable resistive element like Resistive Random Access Memory (RRAM) is Conductive Bridge Random Access Memory (CBRAM). This memory is based on electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrode may be an oxidizable anode and an inert cathode, and the electrolyte may be a silver- or copper-containing chalcogenide glass such as strontium selenide (GeSe) or selenium sulphide (GeS). The change in reversibility of the resistance state is via the polarity, intensity, and duration of the voltage or current pulse to create or destroy the conductive bridge. Further, the programmable resistive element may be a magnetic memory (MRAM) composed of a magnetic tunnel junction (MTJ) made of a plurality of magnetic layers. Spin transfer torque (Spin Transfer Torque, STT) MRAM, the direction of the current applied to the MTJ determines the parallel or anti-parallel state, which in turn determines the low or high resistance state.

A conventional programmable resistance memory storage unit is shown in FIG. The memory cell 10 includes a resistive element 11 and an N-type MOS transistor (NMOS) programming selector 12. One end of the resistive element 11 is coupled to the drain of the NMOS and the other end is coupled to a positive voltage V+. The gate of NMOS 12 is coupled to select signal SEL and the source is coupled to a negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the NMOS 12 is turned on by raising the program select signal SEL, and the resistive element 10 can be programmed. 2 shows another programmable resistive memory cell 20' having a programmable resistive element 21' coupled to one of the diodes 22'. The cathode of the diode 22' can be switched to a low potential to turn on the diode 22' for further programming.

Figures 3a and 3b show some embodiments of electrical fuse elements 80 and 84 fabricated from interconnects. The resistive element has three parts: the anode, the cathode, and the body. The anode and cathode provide circuitry for the connection of the resistive element to other portions such that current can flow from the anode through the body to the cathode. The width of the body determines the current density, which in turn determines the electromigration threshold for the programming current. Figure 3a shows a conventional electrical fuse element 80 comprising an anode 81, a cathode 82, and a body 83. This embodiment has a large and symmetrical anode and cathode. Figure 3b shows another conventional electrical fuse element 84 comprising an anode 85, a cathode 86, and a body 87. The fuse elements 81 and 85 in Figures 3a and 3b are relatively large structures which make them unsuitable for some applications.

The programmable resistive element unit of the present invention will illustrate an embodiment using a junction diode as a programming selector. This programmable resistive element unit can use CMOS logic processes to reduce cell size and cost.

According to an embodiment, a programmable resistance element and a memory can be made by a P+/N well diode For the programming selector, the P and N terminals of the diode are the P+ and N+ active regions in the N well. The P+ and N+ active regions can also be used as the source or drain of the PMOS or NMOS. Similarly, the N well is preferred to break into the PMOS well in a standard CMOS logic process. By using a P+/N well diode in a standard CMOS process, the cell size can be reduced without any special process or mask. The junction diode can be fabricated in the N-well or P-well of the main body CMOS, or in an isolated active region in an SOI CMOS, bulk FinFET or SOI FinFET (or similar technology). As a result, costs can be significantly reduced to facilitate multiple uses (such as embedded applications).

According to an embodiment, the junction diode can be built by a standard CMOS logic process and used as a programming selector for a single programmable element. The single-time programmable component can be an electrical fuse (including, internal, local interconnect, contact/layer indirect anti-fuse, or gate oxide collapse antifuse, etc.). The programmable resistive element can have a heat sink to dissipate heat or a heating element to heat, thereby assisting in programming the programmable resistive element. If the programmable resistance element is an electrical fuse, the electrical fuse can have an extension region to aid in programming the programmable resistance element. If the programmable resistance element is a metal fuse, at least one contact point and/or multiple layer indirect points can be made in the programming path (one or more jumpers can be used) to generate more Joule heat and aid programming. The span is electrically conductive and can be made of metal, metal gate, local interconnect, polycrystalline germanium. The OTP element can have at least one OTP element coupled to at least one diode in the memory array. The diode can be fabricated from the P+ and N+ active regions in the N-well of the CMOS, or has an isolated active region as the P and N terminals. The OTP element can be polycrystalline germanium, metal germanium polycrystalline germanium, metal germanide, polycrystalline germanium metal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, CMOS metal gate or combinations thereof.

The invention can be implemented in various embodiments, including methods, systems, components or devices (including user graphical interfaces and computer readable media). Several embodiments of the invention are described below.

An embodiment of a programmable resistive device (PRD) memory includes at least a plurality of PRD units, at least one PRD unit including at least one PRD element coupled to a first voltage source line, and a programming option The device is coupled to the PRD element and a second voltage source line. At least a portion of the PRD element includes at least one heat sink, heating element or extension to aid in programming. The heat sink is built inside the PRD element or adjacent to the PRD element to enhance the heat dissipation effect. The heating element can be any high resistance material in the current path to increase the temperature of the PRD element. The heating element can comprise a plurality of inner connections and/or a plurality of contact points or layer indirect points as a span. The extended area is in one of the PRDs and there is a reduced current or no current flowing. The PRD element can be programmed to a different logic state via application of a voltage to the first and second voltage source lines.

An electronic system in accordance with an embodiment includes at least one processor and a PRD memory operatively coupled to the processor. This PRD memory contains a plurality of PRD units. The at least one PRD unit includes a PRD element operatively coupled to a first voltage source line, and a programming selector coupled to the PRD element and a second voltage source line. The PRD element is operatively coupled to at least one heat sink, heating element or an extension to aid programming. The heat sink is built inside the PRD element or adjacent to the PRD element to enhance the heat dissipation effect. The heating element can be any high resistance material in the current path to increase the temperature of the PRD element. The heating element can comprise a plurality of inner connections and/or a plurality of contact points or layer indirect points as a span. The extended area is in one of the PRDs and there is a reduced current or no current flowing. The PRD element can be programmed to a different logic state via application of a voltage to the first and second voltage source lines.

According to an embodiment, the method for operating a PRD memory includes the steps of: providing a plurality of PRD units, the at least one PRD unit comprising: (i) a PRD element operatively coupled to a first voltage source line; (ii) a A programming selector is coupled to the PRD element and a second voltage source line; and (iii) the PRD element is operatively coupled to the at least one heat sink, the heating element, or an extension region to aid programming. The heat sink is Built in or adjacent to the PRD element to improve heat dissipation. The heating element can be any high resistance material in the current path to increase the temperature of the PRD element. The heating element can comprise a plurality of inner connections and/or a plurality of contact points or layer indirect points as a span. The extended area is in one of the PRDs and there is a reduced current or no current flowing. The PRD element can be programmed to a different logic state via application of a voltage to the first and second voltage source lines.

According to an embodiment, the OTP memory includes a plurality of OTP cells. The at least one OTP unit includes at least: an OTP element including at least one electrical fuse operatively coupled to a first voltage source line; and a programming selector coupled to the OTP element and a second voltage source line. At least a portion of the electrical fuse has an extension region with a reduced current or no current flowing. The extension region has a reduced current or no current flowing through the application of a voltage to the first and second voltage source lines. The OTP element can be programmed to a different logic state by applying a voltage to the first and second voltage source lines and turning on the programming selector.

According to an embodiment of the invention, an electronic system includes: at least one processor and an OTP memory operatively coupled to the processor. This OTP memory contains multiple OTP units. The at least one OTP unit includes an OTP element including an electrical fuse operatively coupled to a first voltage source line, and a programming selector coupled to the OTP element and a second voltage source line. At least a portion of the electrical fuse includes an extension region having a reduced current or no current flowing therethrough. The OTP element can be programmed to a different logic state by applying a voltage to the first and second voltage source lines and turning on the programming selector.

According to an embodiment of the invention, an operation method for operating an OTP memory includes the steps of: providing a plurality of OTP units, the at least one OTP unit comprising: (i) an OTP element comprising operatively coupled to a first voltage source line At least one electrical fuse; (ii) a programming selector coupled to the OTP element and a second voltage source line; and (iii) at least a portion of the electrical fuse includes an extension region, the extension region having a subtraction The current or no current flows; and by applying a voltage to the first and second voltage source lines and turning on the programming selector, the OTP element can be programmed to a different logic state in a single pass.

[Practical Technology]

10,20’‧‧‧ storage unit

11‧‧‧Resistive components

12‧‧‧Program selector

21'‧‧‧Programmable resistance element

22’‧‧‧II

80,84‧‧‧Electrical fuse elements

81,85‧‧‧Anode

82,86‧‧‧ cathode

83,87‧‧‧Ontology

[this invention]

30‧‧‧ memory unit

30a‧‧‧resistive components

30b, 32, 32', 32", 832, 931-1‧ ‧ diode

31’, 32”, 831 ‧ ‧ active area

33,33’,33”,833,933‧‧‧P+ active zone

37,37’,837,937‧‧‧N+ active area 37

34,34’,34”‧‧‧N Well

35,35’,35”‧‧‧ base

36,36’,36”‧‧‧Shallow trench isolation

38’, 38”, 838, 938‧‧‧P+ implant layer

39’, 39”, 939 ‧ ‧ false MOS gate

932‧‧‧Fuse components

931-2‧‧‧Fuse elements

931-3‧‧‧Contact area

530,530’, 530”‧‧•Schottky diode

531,532,531’,531”‧‧‧ active area

535,536,535',536',535",536"‧‧‧ touch points

534,534’,534”‧‧‧P+ implant layer

533,533',533"‧‧‧N+ implant layer

538,538’,538”‧‧‧Metal

539’, 539” ‧ ‧ false gate

45‧‧‧Connected diode

31-1, 31-2, 31-3‧‧‧ islands

39-1, 39-2, 39-3‧‧‧ MOS gate

37-1, 2, 3‧‧‧N+ active zone

33-1, 2, 3‧‧‧P+ active zone

170,170'‧‧‧Programmable Resistor Element Unit

171,171’‧‧‧Programmable resistance elements

177‧‧‧ PMOS

172’‧‧‧ source

173’‧‧‧ gate

174’‧‧‧

176’‧‧‧N Well

175’‧‧‧N well connector

730, 730' ‧ ‧ unit

731,731’‧‧‧ Subject

732,732'‧‧‧Anode

733,733’‧‧‧ cathode

734,734’‧‧‧ active area

735,735'‧‧N+ implant

737,737’‧‧‧Cathodic contact points

736,736'‧‧‧P+ implant

738,738’‧‧‧Anode contact points

739,739‧‧‧Metal

88", 88''', 198, 198', 198", 198''', 298, 298', 298", 98', 98" ‧ ‧ electrical fuse elements

89", 89''', 199, 199', 190", 199''', 290, 290', 290", 99', 99" ‧ ‧ anode

80", 190, 190', 199", 190''', 299, 299', 299", 90', 90" ‧ ‧ cathode

81", 81''', 191, 191', 191", 191''', 291, 291", 91', 91", 93" ‧ ‧ subjects

83", 83''', 193, 193' ‧ ‧ active area

83'''‧‧‧Ozone Zone

195"‧‧‧ Heat sink

195'''‧‧‧ heating parts

197''', 297" ‧ ‧ active area

295,295'‧‧‧Extended cathode area

295”‧‧‧Extension Area

293"‧‧‧Metal

296”‧‧‧Shared touch points

95’‧‧‧ Notch

70,70”‧‧‧Electrical fuse unit

72,72"‧‧‧Fuse elements

73,74,73”,74”‧‧‧ active area

75,75"‧‧‧N well

70‧‧‧ diode

76,76"‧‧‧Metal

71,75”-1,2,3,4‧‧‧ touch points

78”‧‧‧False MOS gate

77”‧‧‧P+ implant layer

700‧‧‧Processor System

740‧‧‧ memory

744‧‧‧Programmable resistance element

742‧‧‧Unit array

710‧‧‧Central processor

715‧‧‧Common bus

720‧‧‧I/O

730‧‧‧ Hard disk

750‧‧‧CDROM

740‧‧‧ memory

760‧‧‧Other memory

Figure 1 shows a conventional programmable resistance memory unit.

Figure 2 shows another conventional programmable resistive memory cell with a diode as a programming selector.

Figures 3a, b show examples of internal connections as electrical fuses, respectively.

Figure 4a shows a block diagram of a memory cell using junction diodes.

Figure 4b shows the IV curve characteristics of an example electrical fuse programming process.

Figure 5a shows a cross-sectional view of another junction diode embodiment as a programming selector and isolated by STI.

Figure 5b shows a cross-sectional view of another junction diode embodiment as a programming selector and isolated by a dummy CMOS gate.

Figure 5c shows a cross-sectional view of another junction diode embodiment as a programming selector and isolated by SBL.

Figure 5d shows a cross section of another embodiment in which the junction diode is programmed as a selector and is isolated by a dummy CMOS gate in an insulating germanium (SOI) technique.

Figure 6a shows a top view of a junction diode that is used as a programming selector and isolated by a dummy CMOS gate of a dielectric germanium (SOI) or similar technique.

6b is a top view of a programmable resistor unit having a resistor element and a diode as a programming selector, and the diode is formed in a one-piece manner in the isolation active region. The ends of the diode are isolated by a false gate.

Figure 6c is a top view of a Schottky diode with STI isolation and as a programming selector.

Figure 6d shows a top view of a Schottky diode of an embodiment of the invention having CMOS gate isolation and as a programming selector.

Figure 6e shows a top view of a Schottky diode of an embodiment of the invention having SBL isolation and as a programming selector.

Figure 6f shows a perspective view of a junction diode embodiment that is an isolated program selector for a dummy CMOS gate using FinFET technology.

Figure 6g shows an embodiment in which a PMOS is used as a diode (or MOS) to provide a program or read selector.

Figure 6h shows a cross-sectional view of the cell of Figure 6g to show a programming/selection path diagram using a PMOS as a diode programming selector or a MOS read selector.

Figure 6i further shows that Figure 6g illustrates the operational state of a programmable resistance cell that uses a PMOS as a diode programming/reading selector.

Figure 6j further shows that Figure 6h illustrates the operational state of a programmable resistance cell that uses PMOS as a MOS program/read selector.

Figure 6k shows a schematic diagram of a programmable resistive element cell fabricated on a thermally isolated substrate that uses the dummy gate of the programming selector as the PRD element.

Figure 61 shows a schematic diagram of a programmable resistive element cell fabricated on a thermally isolated substrate that uses the MOS gate of the programming selector as the PRD element.

Figure 7a shows a top view of an electrical fuse element that uses thermal conduction but An electrically insulating heat sink is coupled to the anode.

Figure 7b shows a top view of an electrical fuse element used as a heat sink under the body and near a thin oxide of the anode.

Figure 7c shows a top view of an electrical fuse element used as a heat sink in one of the thin oxide regions under the anode.

Figure 7d shows a top view of an electrical fuse element using a thin oxide region near one of the anodes as a heat sink.

Figure 7e shows a top view of an electrical fuse element using an expanded anode as the heat sink.

Figure 7f shows a top view of an electrical fuse element using a high resistance region as the heating element.

Figure 7g shows a top view of an electrical fuse element having an extension region in the cathode.

Figure 7h shows a top view of an electrical fuse element having an extended region in the cathode and a borderless contact at the anode.

Figure 7i shows a top view of an electrical fuse element having an extended region in the cathode and a common contact point at the anode.

Figure 7j shows a top view of an electrical fuse element having at least one recess.

Figure 7k shows a top view of an electrical fuse element having a portion of an NMOS metal gate and a portion of a PMOS metal gate.

Figure 8a shows a top view of an electrical fuse unit having an electrical fuse unit P+/N well diode and a connecting contact.

Figure 8b shows a top view of a programmable resistor unit coupled to a junction diode having a dummy CMOS gate for isolation of P+ and N+.

Figure 9 is an example of a processor system.

Embodiments of the present invention are directed to programmable resistive elements that use P+/N well junction diodes as programming selectors. The diode may comprise P+ and N+ active regions in an N well region. The P+ and N+ active regions in the N-well region can be easily fabricated by a standard CMOS process, and the programmable resistive device of the present invention can be efficiently fabricated and reduced in cost. For standard SOI, FinFET or similar technologies, the isolated active region can be programmed with a selector diode or a programmable resistor element. The programmable resistive element can also be included in an electronic system.

In one or more embodiments, the junction diode can be fabricated in a standard CMOS process and used as a One-Time Programmable (OTP) component, such as an electrical fuse (including an interconnect fuse). , a local interconnect (fuse, contact/via fuse, contact/via antifuse or gate oxide collapse antifuse) programming selector. A heat sink, heating element, or extension may be included in a programmable resistive device (PRD) to aid programming. The heat sink includes at least one conductor that is adjacent to or within the PRD element for heat dissipation. The heating element can comprise a high resistance material in one of the current paths to generate heat. Internal connections, partial internal connections, turns, polysilicon, metal, conductors, single or multiple contact points or vias can be used as heating elements. The extended area is the area where no current flows through the PRD element or the reduced current flows. If the electrical fuse uses a metal fuse, at least one contact point and/or a plurality of vias can be fabricated in the programming path (multiple jumps can be used) to generate heat via the Joule effect as programming. Jumper is electrically conductive and can be metal or metal gate A pole, an inner connection or a partial inner connection is formed. In the memory unit, the OTP element includes at least one OTP element that is coupled to at least one diode. The diode can be fabricated in the P+ and N+ active regions in a CMOS well or in an isolated active region (as a diode P/N terminal). The OTP element can be polycrystalline germanium, metal germanium polycrystalline germanium, metal germanide, polycrystalline germanium metal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate or combinations thereof.

The embodiments of the present invention will be described below in conjunction with the drawings. However, those skilled in the art should understand that the scope of the present invention is not limited to the illustrated embodiments.

Figure 4a shows a block diagram of a memory cell 30 using junction diodes. The memory unit 30 includes a resistive element 30a and a junction diode 30b. The resistive element 30a is coupled to the anode of the junction diode 30b and the high voltage V+; the cathode of the diode 30b is coupled to the low voltage V-. According to an embodiment, the memory unit 30 is a fuse unit having a resistive element 30a as an electrical fuse. Junction diode 30b acts as a programming selector that can be fabricated using a standard CMOS process P+/N well using a P-type substrate, or an isolated active region in SOI, or using FinFET technology. The P+ and N+ active regions, which are anodes and cathodes, are the source and drain of the CMOS device. The N well is a CMOS well that is immersed in a PMOS device; in addition, the junction diode can also be made of a N+/P well or a CMOS process using an N-type substrate. The resistive element 30a and the junction diode 30b are also interchangeable between the voltage sources V+ and V-. Appropriate voltage is applied between the voltage sources V+ and V- at appropriate times, and the resistive element 30a can be programmed to a high resistance or low resistance state according to the magnitude and time of the voltage, so that the memory unit 30 can be programmed to store data (eg, one bit data). ). The P+ and N+ active regions of the diode can be isolated using a dummy CMOS gate, shallow trench isolation (STI), local oxidation (LOCOS), or a germanide barrier layer (SBL).

Figure 4b shows an IV characteristic curve for an example electrical fuse programming process. The IV curve shows that the electric fuse is applied with a voltage source as an X-axis parameter, and the corresponding response current is a Y-axis parameter. When the current is very low, the slope of the curve is the reciprocal of the initial resistance. As the current increases, the resistance increases as a result of Joule heat; assuming the temperature coefficient is positive, it can be seen that the curve begins to bend toward the X-axis. When the critical current (Icrit) is exceeded, the resistance of the electronic fuse begins to change rapidly or even becomes negative due to cracking, decomposition or melting. The traditional method of electrical fuse programming is to operate a current higher than Icrit, and its physical mode is like an explosion, so the resulting resistance is completely unpredictable. On the other hand, assuming that the operating current is lower than Icrit, the writing mechanism is only the electromigration mode. Due to the electromigration relationship, the write behavior becomes easy to control and deterministic. The electrical fuse can be programmed in multiple pulses, and the resistance is progressively varied with pulse application until the desired high resistance value is achieved and detected. The electrical fuse programmed according to the above manner can be 100% after programming, and the yield can be determined by the manufacturing defects before programming. The IV characteristic curve shown in Figure 4b can also be used for an OTP unit having at least one OTP element and a selector. Furthermore, the programmed state of the electrical fuse programmed in the above manner (whether programmed) cannot be seen by an optical microscope or a scanning electron microscope (SEM).

The present invention provides a reliable method of programming an electrical fuse comprising the steps of: (a) programming a portion of an OTP memory using a low programming voltage, gradually increasing the programming voltage until all OTP cells can be programmed and read. To confirm, this voltage is indicated as the lower limit of the programming voltage; (b) continuously increase the programming voltage to program the same part of the OTP unit until at least one OTP unit (regardless of whether it has been programmed) has been read and confirmed to fail, this voltage is Indicated as the upper limit of the programming voltage. In addition, the programming time can be adjusted to repeat steps (a) and (b) above until the lower limit, upper limit, or a programmed interval (the voltage range between the upper and lower limits) meets a standard value. A reliable programming interval for one of the electrical fuses is shown in Figure 4b. After defining the programming interval, other OTP cells can be programmed with voltages between the lower and upper limits, and in a unit voltage or current pulse mode.

The present invention provides a cell current measurement method comprising the following steps: (a) in a programming mode, applying a voltage to a programming pin VDDP, which is low enough to not program the OTP cell; (b) avoiding VDDP providing current to the non- The OTP circuit of the OTP memory array; (c) turns on (turns on) the selector of the OTP cell to be measured; (d) measures the current flowing through VDDP as the cell current of the selected OTP cell. This method can be applied to OTP units that are programmed or not programmed. This method can also be used as a criterion for determining whether the OTP cell is programmed, as long as the set represents the maximum programmed cell current and represents the unprogrammed minimum cell current to determine the upper and lower limits of the programming voltage when defining the characteristic.

An electrical fuse unit can be used as an example to illustrate the key implementation concepts. Figure 5a shows a cross section of a diode 32 in which a shallow trench isolated P+/N well diode is used as a programming selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37, which respectively constitute the P and N terminals of the diode 32, are the source or drain of the PMOS and NMOS in a standard CMOS logic process. The N+ active region 37 is coupled to an N-well 34 that embeds a PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as an electrical fuse, may be coupled to the P+ active region 33 at one end and to the high voltage power supply V+ at the other end. To program such a programmable resistive component, a high voltage is applied to V+, and a low voltage or ground potential is applied to the N+ active region 37. Therefore, a high current is programmed through the fuse element and the diode 32 to program the resistive element.

Figure 5b shows a cross-sectional view of another junction diode 32' embodiment as a programming selector and isolated by a dummy CMOS gate 39'. Shallow trench isolation 36' provides isolation of other active regions. The active region 31' is defined by a shallow trench isolation 36'. Here, the N+ and P+ active regions 37' and 33' are further defined by a mixture of a dummy CMOS gate 39', a P+ implant layer 38', and an N+ implant layer (complementary to the P+ implant layer 38'), respectively. N and P ends of the polar body 32'. The dummy MOS gate 39' is a CMOS gate fabricated in a standard CMOS process. The width of the dummy MOS gate 39' can be selected as the minimum width of the CMOS gate and can be less than Twice the width. The dummy MOS gate 39' may also have a thicker gate oxide for the input and output transistors. The diode 32' is fabricated as a PMOS-like component and includes 37', 39', 33', and 34' as the source, gate, drain, and N well; however, the source 37' is covered with N+ The implant layer, rather than the P+ implant layer 38' covered by a true PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage or spliced to the N+ active region 37' for the purpose of being used as a P+ active region 33' and an N+ active region 37' during fabrication. Isolation. The N+ active region 37' is coupled to the N-well 34', which is a body embedded in the PMOS in a standard CMOS logic process. The P substrate 35' is a matrix of P-type germanium. A resistive element (not shown in Figure 5b), such as an electrical fuse, can be coupled to P+ region 33' at one end and to a high voltage supply V+ at the other end. To program such a programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the fuse element and the diode 32' to program the resistance element. This embodiment has a relatively small size and low resistance.

A cross-section of another embodiment, shown in Figure 5c, in which the junction diode 32" is isolated by a telluride barrier (SBL) 39" and serves as a programming selector. Figure 5c is similar to Figure 5b, however the dummy CMOS gate 39' in Figure 5b is replaced by a telluride blocking layer 39" in Figure 5c to prevent the growth of germanide on top of the active region 31". If there is no dummy CMOS gate or germanium blocking layer, the N+ and P+ active regions will be shorted by the metal halide of the active region 31.

Figure 5d shows a cross section of another embodiment in which the junction diode 32" is programmed as a selector and uses an insulating germanium (SOI), FinFET or other similar technique. In SOI technology, the substrate 35" It is an insulator such as cerium oxide or the like, which has a thin layer of well grown on top. All NMOS and PMOS are in the well, separated from each other by a ceria or similar material and a substrate 35". An active region 31" via a dummy CMOS gate 39", a P+ implant layer 38" and an N+ implant layer ( The mixing of the P+ implant layer 38" is divided into an N+ active region 37", a P+ active region 33" and a body 34". This N+ initiative The region 37" and the P+ active region 33" respectively constitute the N terminal and the P terminal of the junction diode 32". The N+ active region 37" and the P+ active region 33" can respectively be used with the source of the NMOS and PMOS in the standard CMOS logic process. Alternatively, the dummy CMOS gate 39" can be the same as the CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39" can be biased at a fixed voltage for the purpose of isolation between the P+ active region 33" and the N+ active region 37" during fabrication. The width of the dummy MOS gate 39" can vary. However, depending on the embodiment, the minimum gate width of the CMOS gate can be approximated and can be less than twice the minimum gate width. The dummy MOS gate 39" may also have a thicker gate oxide layer to withstand higher voltages. The N+ active region 37" is coupled to a low voltage V-. A resistive element (not shown in Figure 5d), such as an electrical fuse, can be coupled to the P+ active region 33" at one end and to the high voltage supply V+ at the other end. To program such an electrical fuse storage unit, Gaohe The low voltage is applied to V+ and V-, respectively, and the conduction current flows through the fuse element and the junction diode 32" to program the resistance element. Other embodiments of CMOS isolation techniques, such as shallow trench isolation (STI), dummy CMOS gates, or germanium blocking layers (SBL) can be on one to four sides or on either side, which can be readily applied to corresponding CMOS SOI technologies.

Figure 6a shows a top view of a junction diode 832 corresponding to the cross-sectional view of Figure 5d. This junction diode 832 is used as a programming selector and is fabricated from an insulating active region using an insulating germanium (SOI), FinFET or other similar technique. The active region 831 is divided into an N+ active region 837, a P+ active region 833, and a body (in a pseudo CMOS gate) via a mixture of a dummy CMOS gate 839, a P+ implant layer 838, and an N+ implant layer (complementary to the P+ implant layer 838). Below 839).

Figure 6b is a plan view of a fuse element 932 made up of a fuse element 931-2, a diode 931-1 and a contact region 931-3; the diode 931-1 is used as The selector is programmed and formed in one piece on the isolated active area. The active regions 931-1, 931-2, 931-3 are isolated active regions constructed on the same structure as the diodes, fuse elements and contacts of the fuse element 932. Area. The isolation active region 931-1 is divided into regions 933 and 937 by the dummy CMOS gate 939, and the regions are covered by the P+ implant layer 938 and the N+ implant layer (complementary to the P+ implant layer 938) as the diode 931, respectively. P end and N end of -1. The P+ region 933 is coupled to the fuse element 931-2, which is further connected to the contact region 931-3. The contact points 931-3 and the cathode contacts of the diode 931-1 can be coupled to the V+ and V- power lines via one or more contact points.

If high and low voltages are applied to V+ and V-, respectively, a current will flow through fuse element 931-2 to program it to a high resistance state. According to an embodiment, the fuse element 931-2 may be all N-type or P-type. According to another embodiment, the fuse element 931-2 may be half P-type and N-type, such that the fuse element 931-2 is similar to a reverse biased diode when read. And after the programming, the metal halide at the top will be depleted. If there is no metal halide, the fuse element 931-2 (which is an OTP element) can be fabricated in N/P or P/N diode mode to collapse in forward or reverse bias. In this embodiment, the OTP element can be directly coupled to the diode as a programming selector without any contact points therebetween, thereby reducing cell area and cost.

As shown in Figures 6c-e, the diode as a programming selector can be fabricated from a standard CMOS process Schottky diode. A Schottky diode is a metal-semiconductor junction diode rather than a junction diode that is typically composed of semiconductor P+ and N+ doping. The Schottky diode is very similar to the junction diode, and the anode of the Schottky diode is connected by metal to the lightly doped N or P type, while the anode of the general junction semiconductor is connected by metal to heavy Doped with N or P type. The anode of the Schottky diode can be made of any metal such as aluminum, copper, metal alloys or metal halides. The metal anode of the Schottky diode can be connected to the N+ active region in the N well or the P+ active region in the P well can be the cathode. Schottky diodes can be fabricated in bulk CMOS or SOI CMOS, planar or FinFET CMOS. Those skilled in the art will recognize that the present invention also encompasses Schottky diodes of different processes.

Figure 6c shows a top view of a Schottky diode 530 in accordance with one embodiment of the present invention. The Schottky diode 530 is formed in an N well (not shown) and has an active region 531 (cathode) and an active region 532 (anode). Active region 531 is covered by N+ implant layer 533 and has externally connected contact points 535. The active region 532 is not covered by the N+ or P+ implant layer, and its doping concentration is substantially the same as that of the N well. The active region 532 has a metal telluride layer to create a Schottky barrier with the germanium and is further connected to the metal 538 via the anode contact 536. A P+ implant layer 534 can cover the active region 532 to reduce leakage current.

Figure 6d shows a top view of a Schottky diode 530' in accordance with one embodiment of the present invention. The Schottky diode 530' is formed in an N well (not shown) and has an active region 531' to break into the anode and cathode of the diode. The active region 531' is divided by the dummy gate 539' into a central anode and two outer cathodes. The cathode is covered by an N+ implant layer 533' and has externally connected contact points 535'. The central anode is not covered by the N+ or P+ implant layer, and its doping concentration is substantially the same as that of the N well. A central germanide layer has a metal telluride layer to create a Schottky barrier with germanium and is further coupled to metal 538' via anode contact 536'. A P+ implant layer 534' can cover a portion of the central anode to reduce leakage. According to other embodiments, the boundaries of the N+ implant layer 533' and the P+ implant layer 534' may fall on the cathode. Figure 6e shows a top view of a Schottky diode 530" according to an embodiment of the invention. The Schottky diode 530" is formed in an N-well (not shown) and has an active region 531" to break into the diode. The anode and cathode. The active region 531" is divided into a central anode and two outer cathodes by a telluride barrier layer 539". The cathode is covered by the N+ implant layer 533" and has externally connected contact points 535". The central anode is not N+ Or the P+ implant layer is covered to have a doping concentration substantially the same as that of the N-well. A metal telluride layer is formed on the central anode to create a Schottky barrier with the germanium, and further connected to the metal 538 via the anode contact 536". A P+ implant layer 534" can cover the central anode to reduce leakage current.

Figure 6f shows a cross-sectional view of another embodiment of a junction diode 45 that is a programming selector using a fin field effect transistor (FinFET) technology. FinFET is a fin-based The multi-gate transistor of the present invention. The FinFET technology is similar to conventional CMOS, but has a high and thin island, which is raised on the germanium substrate to serve as the body of the CMOS component. Its main body is like a traditional CMOS, which is divided into a source, a channel and a channel by a polysilicon or a non-aluminum metal gate. The main difference is that in FinFET technology, the body of the MOS device is lifted onto the substrate. The height of the island is twice the width of the channel, but the direction of current flow is still parallel to the surface of the crucible. Figure 6f shows an embodiment of a FinFET technique in which the germanium substrate 35 is an epitaxial layer built on top of an SOI insulating layer or other high resistance germanium substrate. The ruthenium substrate 35 can be etched into several tall rectangular island regions 31-1, 31-2, and 31-3. The island regions 31-1, 31-2, and 31-3 can cover both sides of the raised island region with MOS gates 39-1, 39-2, and 39-3, respectively, through the growth of the appropriate gate oxide layer. And define the source and channel regions. The source and drain regions are formed in the island regions 31-1, 31-2, and 31-3, and then filled with 矽/矽锗 to form extended source/drain regions 40-1, 40-2 for the combined The source and drain areas are large enough to drop the contact point. The extended source/drain regions 40-1, 40-2 can be fabricated from polysilicon, polysilicon/germanium, lateral epitaxy, or selective epitaxial growth (SEG) 矽/矽锗. The extended source/drain regions 40-1, 40-2 or other isolated active regions may be grown or deposited next to the island regions or at the ends of the island regions. In Figure 6f, the filled regions of the extended source/drain regions 40-1, 40-2 are only used to illustrate and reveal the cross-section, for example, the fill regions can be filled into the island regions 31-1, 31-2, and 31- The top of 3. In this embodiment, the active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by the P+ implant layer 38' and the N+ implant layer (complementary to the P+ implant layer 38') to form the junction. The P and N terminals of diode 45, rather than the PMOS like a conventional FinFET, are all covered by P+ implant layer 38'. The N+ active regions 37-1, 2, 3 are coupled to a low voltage power supply V-. The resistive element (not shown in Figure 6f), such as an electrical fuse, has one end coupled to the P+ active regions 33-1, 2, 3 and the other end coupled to a high voltage supply V+. In order to program such an electrical fuse, high and low voltages are applied to V+ and V-, respectively, to conduct current through the resistive element and junction diode 45, thereby programming the resistive element. Other embodiments of CMOS body technology isolation, such as shallow trench isolation (STI), dummy CMOS gate or 矽 The compound barrier layer (SBL) can be easily applied to the corresponding FinFET technology.

Figure 5d and Figures 6a, bf show schematic diagrams of the fabrication of a diode (as a programming selector) or an OTP element, respectively, in a fully or partially isolated active region. The diode as a programming selector can be made of an isolated active region such as an SOI or FINFET. The isolated active region can be fabricated as a diode with P+ and N+ implants at both ends (as two terminals of the diode), which is the same source/channel as the CMOS device. A dummy CMOS gate or a germanium blocking layer (SBL) can be used to isolate and avoid short circuits between the two terminals. In SBL isolation, the SBL layer can overlap with the N+ and P+ implant regions, and the N+ and P+ implant regions are spaced apart from each other. The breakdown voltage and leakage current of the diode can be adjusted by adjusting the width and doping level of the interval. A fuse as an OTP element can also be fabricated from an isolated active region. Because this OTP is thermally isolated, the heat generated in programming is difficult to eliminate, which can help increase the temperature to speed up programming. The OTP element can be a full N+ or P+ implant. If there is a metal telluride at the top of the active region, the OTP element may have a partial N+ implant and a partial N+ implant, so that the OTP element is similar to the reverse biased diode when read. And after the programming, the metal halide at the top will be depleted. If there is no metal telluride, the OTP element may have some N+ implants and some N+ implants, so that the OTP elements are similar to the diodes that will collapse when read. In both cases, the OTP element or diode can be fabricated in the same structure that isolates the active area to save area. In SOI or FinFET SOI technology, the active region can be isolated from the substrate and other active regions by cerium oxide or similar materials. Similarly, in the FINFET body technology, the active regions fabricated in the fin structure of the same substrate are isolated from each other on the surface, and the active regions can be coupled to each other by the extended source/drain regions.

Figure 6g shows an embodiment in which a PMOS is used as a diode (or MOS) to provide a program or read selector. The programmable resistive element unit 170 has a programmable resistive element 171 coupled to a PMOS 177. The gate of the PMOS 177 is coupled to a read word bar (WLRB), the drain is coupled to a programming word bar (WLPB), the source is coupled to the programmable resistive element 171, and the body is coupled to the drain . PMOS 177 The source junction configuration allows the PMOS 177 to operate as a diode when programming a selected cell. Moreover, the source junction or channel configuration of PMOS 177 allows the PMOS 177 to operate as a diode or MOS selector for read operations.

Figure 6h shows a cross-sectional view of the cell of Figure 6g to show a programming/selection path diagram using a PMOS as a diode programming selector or a MOS read selector. The programmable resistive element unit 170' has a programmable resistive element 171' coupled to a PMOS having a source 172', a gate 173', a drain 174', an N well 176', and an N well 175'. The PMOS has a special conduction mode that is difficult to find by conventional CMOS digits or analog techniques, that is, the drain 174' level is pulled to a very low voltage (such as ground) to turn on the junction diode at the source 172'. Further programming is provided as indicated by the dashed lines. Because the IV curve of the diode follows the exponential law rather than the MOS flat method, this mode of operation provides more current to reduce cell size and lower programming voltage. This PMOS can be turned on during reading to achieve low voltage reading.

Figures 6i and 6j further show the operational states of the elements illustrated in Figures 6g and 6h to illustrate the innovation of the particular unit. Figure 6i shows the programming and reading states of the diode. During programming, the WLPB of the selected cell is coupled to a very low voltage (eg, ground) to turn on the source junction diode, and WLRB can be coupled to VDDP (programming voltage) or ground. The WLPB and WLRB of the unselected cells can both be coupled to VDDP. During reading, the selected cell's WLRB is coupled to the VDD core voltage or to ground, and the WLPB is coupled to ground to turn on the source junction diode of PMOS 171 as shown in Figure 6g. WLPB and WLRB of unselected cells are coupled to VDD. Figure 6j shows the state of programming and reading by MOS. The mode of operation shown in this figure is similar to that shown in Figure 6i, except that the selected cells' WLRB and WLPB are coupled to 0 volts and VDD/VDDP, respectively, during reading and programming. Therefore, the PMOS can be turned on during programming or reading. This PMOS can be laid out by a conventional PMOS method, but its operating voltage is very different from that of the conventional PMOS. In other embodiments, the diodes and/or the MOS can also be combined for programming or reading, that is, in an embodiment. The diode is programmed and read by the MOS. In another embodiment, the diodes and MOS are programmed in different current directions for different data.

Figure 6k shows a schematic diagram of a programmable resistive element (PRD) unit 730 fabricated on a thermally isolated substrate such as SOI or polysilicon. The thermal isolation matrix has very poor thermal conductivity, and the programmable resistance element (PRE) can be shared with the gate of the programming selector while still maintaining high programming efficiency. The unit 730 has a PRE including a body 731, an anode 732, and a cathode 733. The body 731 of the PRE is also the gate of the dummy gate diode having the active region 734, the cathode with the N+ implant 735 and the cathode contact 737, and the P+ implant 736 and the anode contact. Point 738 anode. The cathode of the PRE is coupled to the anode of the dummy gate diode by a metal 739.

Figure 61 shows a schematic of a programmable resistive element (PRD) unit 730' fabricated on a thermally isolated substrate such as SOI or polysilicon. The thermal isolation matrix has very poor thermal conductivity, and the programmable resistance element (PRE) can be shared with the gate of the programming selector while still maintaining high programming efficiency. This unit 730' has a PRE comprising a body 731', an anode 732' and a cathode 733'. The main body 731 of PRE is also the gate of MOS. The MOS has an active region 734', a drain with a N+ implant 735' covering the drain contact point 737', and a source contact covered by a P+ implant 736'. Point 738' to the source. The cathode of the PRE is coupled to the source contact 738' of the MOS by a metal 739'. Similar to the operation of Figures 6g-j, the PRD unit 730' can be programmed or read by turning on the channel of the source junction diode or transistor of the MOS.

The PRD units 730, 730' shown in Figures 6k and 61 are for illustrative purposes only. The thermally isolating substrate can be an SOI or a polycrystalline germanium matrix. The active region can be a germanium, germanium, germanium, III V or II VI semiconductor material. The PRE may be an electrical fuse (including an anti-fuse), a phase change (PCM) film, a magnetic breakthrough interface (MTJ) film, a resistive memory (RRAM) film, or the like. The PRE can be fabricated with the heat sink shown in Figures 7a-e, the heater shown in Figure 7f or the extension shown in Figures 7g-i. The programming selector can be a diode or a MOS. MOS The selector can be programmed or read by turning on a MOS channel or a source junction. The present invention is susceptible to a variety of isochronous implementations and combinations, all of which are within the scope of the present invention.

Figure 7a shows a top view of an electrical fuse element 88". This electrical fuse element 88" uses a thermally conductive but electrically insulating heat sink to couple to the anode. The electrical fuse element 88" may, for example, use a resistive element 30a as shown in Figure 4a. The electrical fuse element 88" may comprise an anode 89", a cathode 80", a body 81" and an N+ active region 83". The N+ active region 83" of the P-type substrate is coupled to the anode 89" via the metal 84". In this embodiment, the N+ active region 83" and the conduction path are electrically insulated (ie, the N+/P secondary diode is inverted). To the bias), but thermally conductive to the P-type substrate to act as a heat sink. In other embodiments, the heat sink can be directly coupled to the anode 89" without other metal or internal connections. In other embodiments, the heat sink can also be coupled to the body, cathode, and anode of a fuse element. Part or all. The heat sink of this embodiment provides an accelerated thermal gradient for accelerated programming. In other embodiments, the body can be bent 45 degrees or 90 degrees one or more times.

Figure 7b shows a top view of another embodiment of an electrical fuse element 88"". This electrical fuse element 88'" is similar to that shown in Figure 7a, but has a thinner oxide region 83"" that is below the body 81"" and near the anode 89'" Heat sink. This electrical fuse element 88"' can use, for example, a resistive element 30a as shown in Figure 4a. The electrical fuse element 88"" can include an anode 89"", a cathode 80"", a body 81"" and an active region 83"" adjacent the anode 89"". The active region 83"" is positioned below the body 81"" such that the oxide layer of this region is thinner than other regions (e.g., a thin gate oxide rather than a thick STI oxide). The active region 83"' above the oxide is effectively dissipated to provide a thermal gradient that accelerates programming. According to other embodiments, the thin oxide region 83"" may be under a portion or all of the body, cathode, and anode of the fuse element to facilitate programming as a heat sink.

Figure 7c shows a top view of another embodiment of an electrical fuse element 198. Electrical fuse element The element 198 is similar to that shown in Figure 7a, but has a thinner oxide region 193 located on either side of the anode 199 to provide another form of heat sink. This electrical fuse element 198 can be, for example, a resistive element 30a as shown in Figure 4a. The electrical fuse element 198 can include an anode 199, a cathode 190, a body 191, and an active region 193 adjacent the anode 199. The active region 193 is below the anode 199 such that the oxide layer in this region is thinner than the other regions (e.g., a thin gate oxide rather than a thick STI oxide).

Figure 7d shows a top view of another embodiment of an electrical fuse element 198'. This electrical fuse element 198' is similar to that shown in Figure 7a, but has a thinner oxide region 193' near the anode 199' side to provide another form of heat sink. This electrical fuse element 198' can be, for example, a resistive element 30a as shown in Figure 4a. The electrical fuse element 198' can include an anode 199', a cathode 190', a body 191', and an active region 193' adjacent the anode 199'. The active region 193' is adjacent to the anode 199' such that the oxide layer of this region is thinner than other regions (e.g., thin gate oxide rather than thick STI oxide) and can be rapidly dissipated to provide a fast programmed thermal gradient. According to other embodiments, the thin oxide region may be adjacent to one side, two sides, three sides, four sides or any side of a body, cathode or anode of a fuse element to accelerate heat dissipation. According to other embodiments, at least one substrate contact point coupled to the active region (e.g., active region 193') can be provided to avoid latch-up. The contact post or metal at the contact point of the substrate acts as another heat sink.

Figure 7e is a top plan view of another example of an electrical fuse element 198" similar to that shown in Figure 7a, but with a heat sink 195" at the cathode. This electrical fuse element 198" For example, a resistive element 30a as shown in Fig. 4a can be used. The electrical fuse element 198" can include a cathode 199", an anode 190", a body 191", and a heat sink 195". According to other embodiments, the heat sink can also have only one side instead of both sides to properly fit Small cell space, and its length can be increased or decreased. According to other embodiments, the heat sink can also be an anode or a part of the body on one side (or both sides). In another embodiment, the aspect ratio of the heat sink Can be greater than 0.6 or greater than the design line width (design rule) required Small value.

Figure 7f is a top plan view of another example of an electrical fuse element 198"" similar to that shown in Figure 7a but having a heating element 195"" proximate to the cathode. This electrical fuse element 198"" may, for example, use a resistive element 30a as shown in Figure 4a. The electrical fuse element 198 ′′′ can include an anode 199 ′′′, a cathode 190 ′′′, a body 191 ′′′′, and a high resistance region 195 ′′′ as a heating member. This high resistance region 195"" can generate more heat to assist in programming this fuse element. According to an embodiment, the heating element may be an unmetallized polycrystalline germanium or an unmetallized active region to have a higher resistance value. According to another embodiment, the heating element can be a single or multiple contact points/vias that are connected in series to each other to increase the resistance value to generate more heat in the programmed path. The heating member 195"" may be placed at a portion or all of the cathode element, the anode, and the body of the fuse element. The active zone 197"" has a base contact point to avoid latching. The contact post in the active region 197"" can also serve as a heat sink.

Figure 7g shows a top view of an electrical fuse element 298 of another embodiment. This electrical fuse element 298 is similar to that shown in Figure 7a but has an extended region at the cathode. This electrical fuse element 298 can use a resistive element 30a as shown in Figure 4a. The electrical fuse element 298 can include a cathode 299, an anode 290, a body 291, and an extended cathode region 295. According to another embodiment, the extended cathode region 295 may also be adapted to the small cell space only on one side of the body 291, and its length may be increased or decreased. In a broader sense, the extended cathode region can be referred to as an extended region, that is, an extended cathode region is an example of an extended region. According to another embodiment, the extension zone can be an anode or a portion of the body on one or both sides. According to another embodiment, the aspect ratio of the extended area is greater than 0.6. This extension is any area that is longer than the design line's design rule and is coupled to the anode, cathode, or body with less current or no current.

Figure 7h shows a top view of another embodiment of an electrical fuse element 298' having an extended region in the cathode portion. The electrical fuse element 298' can comprise a cathode 299', a yang The pole 290' is a body 291'. The cathode 299' has an extended cathode region 295' adjacent to one or both sides of the body 291' for auxiliary (i.e., accelerated) programming. This extension 295' is the portion of the fuse element that extends closest to the cathode or anode contact point and is longer than the area required to design the line width design rule. The contact point of the anode 290' of the electrical fuse element 298' also has no boundaries, i.e., the contact point width is greater than the width of the fuse element below it. According to another embodiment, the cathode contact point is also borderless and/or the anode portion also has an extended region.

Figure 7i shows a top view of another embodiment of an electrical fuse element 298", which may include a cathode 299", an anode 290", a body 291". This cathode 299" has a proximity body 291 The extended area 295" on both sides is accelerated programming. This extended area 295" is a portion of the fuse element extending from the cathode and anode contact points and has a small current or no current, or its length is longer than the design line width rule (design Rule) the required length. The aspect ratio of the extension region 295" along the current path is greater than the value required for the design line width design rule, or may be greater than 0.6. The anode 290' has a common contact point 296". A metal 293" is positioned over the common contact 296" to interconnect the body 291' with the active region 297". According to an embodiment, the extended region can be adjacent to one side of the body 291" and/or Cathode or anode. According to another embodiment, the yang may have an extended area and/or the cathode may have a common contact point.

The heat sink provides an accelerated programming temperature gradient, as shown in Figures 7a-e for illustrative purposes. A heat sink can be a thin oxide region near the anode, the body or the cathode, below or on one side, two sides, three sides, four sides or any side of the cathode to accelerate heat dissipation. The heat sink can be an anode, a body or a cathode extension of the fuse element to accelerate heat dissipation. The heat sink may also be one or more conductors coupled to the anode, body or cathode of the fuse element (to contact or be close to) to accelerate heat dissipation. The heat sink can also be an anode or a cathode having a larger area (having one or more contact points/vias) to accelerate heat dissipation. The heat sink may also be an active region of the fuse element close to the cathode, the body or the anode (which may also have at least a contact post on the active region) to accelerate heat dissipation. OTP unit with shared contact points (ie metal with MOS gate) The pole and active regions are interconnected at a single contact point) and can also be considered as a heat sink embodiment for the MOS gate to allow heat to effectively dissipate into the active region.

The extension area shown in Fig. 7g-i is the extension of the fuse element from the contact point or the via hole. This part can be longer than the design line design value and has no or no flow. Current is passed through thereby accelerating programming. An extension zone (eg, 45 or 90 degree bends and may include multiple components) may be on the anode, body or cathode side, sides, sides, or sides of the fuse element or any side. An extension zone can also be a heat sink for auxiliary heat dissipation. Although the implementation structure can be approximated, the heat sink and extension are based on different physical mechanisms to speed up programming. An extension zone can act as a heat sink, but the heat sink is not necessarily an extension zone. Embodiments of the invention may be implemented individually or in combination.

In some embodiments, the thermal conductivity (ie, heat loss) of a fuse element may increase by 20% to 200% due to the heat sink. Similarly, a heating element can add more heat to assist in programming the fuse element. A heating element (e.g., element 195'" of Figure 7f) is typically located at or near the (or all) portion of the fuse element, the body or the high resistance region of the anode to generate more heat. A heating element can be realized by one or more unmetalized polysilicon, an unmetalized active region, one or more contact points or vias, or a combination thereof, or one or more high resistance internal connections in the programmed path. The heater may have a resistance value of 8 Ω to 200 Ω; in some embodiments, it may be 20 Ω to 100 Ω.

Fuse elements with heat sinks, heating elements or extensions may be polycrystalline germanium, metal deuterated polysilicon, metal telluride, polycrystalline germanium, metal, metal alloy, metal gate, local interconnect, zero metal (metal0), thermal isolation The active area or CMOS gate is fabricated. In addition, a variety of different combinations and variations are possible to provide a heat dissipating heat sink, a heat generating component that can generate heat, and an extended area to assist in programming, all of which are within the scope of the present invention.

Figure 7i shows a top view of an electrical fuse element 98' in accordance with another embodiment. Electrofusion The silk element 98' and the type shown in Figure 7a are shown, except that there is at least one notch in the body to aid in programming. In general, one of the target portions of the body 91' can be formed with a smaller area (e.g., thinner) to form a recess. This electrical fuse element 98' can be used, for example, for the resistive element 30a shown in Figure 4a. The electrical fuse element 98' includes an anode 99', a cathode 90', and a body 91'. The body 91' includes at least one notch 95' to allow the fuse element to be easily broken during programming.

Figure 7k shows a top view of an electrical fuse element 98" in accordance with another embodiment. The electrical fuse element 98" and the type shown in Figure 7a, except that the fuse element is a portion of the NMOS metal gate and portion PMOS metal gate. The electrical fuse element 98" can be used, for example, for the resistive element 30a shown in Figure 4a. The electrical fuse element 98" includes an anode 99", a cathode 90" and a PMOS metal gate and an NMOS metal gate, respectively. The main body of the production is 91" and 93". The use of different kinds of metals in the same fuse element, the temperature rise during programming can produce thermal expansion with large stresses, thereby breaking the fuse.

The OTP elements shown in Figures 7a-k illustrate only some of the embodiments. As mentioned above, this OTP element can be fabricated by any internal connection including, but not limited to, polycrystalline germanium, metal germanium polycrystalline germanium, metal germanide, local interconnect, polycrystalline germanium, metal, metal alloy, metal gate, thermal isolation active Zone or CMOS gate, or a combination of the above. The polycrystalline germanium metal is a sandwich structure of metal-metal nitride-polysilicon (ie, W/WNx/Si), which can be used to reduce the resistance of polysilicon. The OTP element can be N-type, P-type or partial N and partial P-type. Each OTP element has an anode, a cathode, and at least one body. For polycrystalline germanium/polycrystalline germanium/partially interconnected metal fuses, the number of contacts of the anode or cathode may not exceed two; for metal fuses, the number of contacts of the anode or cathode may not exceed four.

In other embodiments, the number of contacts of the anode or cathode may be only one. The contact point size can be greater than at least one contact point size outside of the OTP memory array. The periphery of the contact point may be smaller than the periphery of at least one of the contact points outside the OTP memory array. In other embodiments, the periphery may be a negative value, that is, a contact point It is wider than the contact area below, which is the so-called borderless contact point. The body may have an aspect ratio of 0.5-8, or in some embodiments may be 2-6 (polysilicon/local interconnect/polycrystalline germanium/metal gate body) or 10 or more (metal body). In addition to the above examples, the scope of the invention also includes combinations and parts of the above examples.

Polysilicon, which defines the CMOS gate and internal connections, can also be used as an OTP element in a high dielectric constant/metal gate CMOS process. The OTP element can be P type, N type or part N and part P type. For fuse elements with P+ and N+ doping, the resistance ratio before and after programming can be increased to create a diode after programming, such as polysilicon, polysilicon, thermally isolated active region, or high Dielectric coefficient / metal gate of metal gate CMOS. If the metal gate CMOS has a polysilicon sandwich structure between the metal alloy layers, the metal alloy layer can be operated by a mask produced by the layout database to create a diode in the fuse element. In an SOI or similar SOI process, a fuse element can be self-heating to isolate the active region so that the fuse element can be implanted with P+, N+ or partial N+ and partial P+ impurities at each end of the active region. If a fuse element is part of the N+ and part of the P+ type impurity, the fuse element behaves like a reverse biased diode, as the metal halide at the top is depleted due to programming. In one embodiment, if there is no metal halide at the top of the active region, the OTP element can also be formed from a portion of the N+ and a portion of the P+ doped isolation active region, which is similar in characteristics to a positive or reverse bias collapse. The diode. If an isolated active region is used to establish an OTP element, this OTP element can be combined with a programming selection diode in a single active island region to reduce the area of use.

For process technology that provides local interconnects, local interconnects can be used to do some or all of the OTP elements. The local interconnect, also known as the zeroth layer (M0), is a by-product produced in the metal telluride process and can directly interconnect the polysilicon (or MOS gate) with the active region. In advanced processes beyond 28nm, the scaling along the surface of the crucible progresses much faster than along the height. Therefore CMOS gate The aspect ratio (gate height to channel length ratio) becomes extremely high, resulting in higher manufacturing costs for contact points between metal 1 and source/drain or CMOS gates (eg, component area and cost considerations). The local interconnection can be used as the intermediate connection between the source/channel and the CMOS gate, the intermediate connection between the CMOS gate and the metal 1, or the source/channel and the metal 1 in the middle of one or two layers. . According to an embodiment, a local interconnect, a CMOS gate, or a combination thereof may be used as an OTP element. According to another embodiment, the OTP element and one end of the programming selector can be directly connected via a local internal connection (without any contact points) to save area. Therefore, the zeroth layer can be used to connect the source/drain to the same height of the metal gate so that the metal 1 connects the zeroth layer and the metal gate.

Those skilled in the art will appreciate that the above description is merely illustrative, and that the present invention encompasses variations and equivalents to fabricate electrical fuses, antifuse elements, or programming selectors in a CMOS process.

Figures 8a and 8b show P+/N well diodes and fuse elements fabricated in different isolation embodiments, respectively. If there is no isolation, the P+ and N+ active regions will be short-circuited due to the metal halide growing on them. One or four sides or any side of the cell may be provided by STI, a dummy CMOS gate, SBL, or a combination thereof to provide isolation. The P+ and N+ active regions of the diode P and the N terminal are the source and the drain of the CMOS device. Both the P+ and N+ active regions are located in the N well, which is the N well that breaks into the PMOS in a standard CMOS process. To simplify the description, Figures 8a and 7b show that there is only one N+ active region in a P+ active region, but the diode N+ active regions in most wells can be shared.

Figure 8a shows a top view of an electrical fuse unit 70 having a P+/N well diode and a contiguous contact, in accordance with an embodiment. The active regions 73 and 74 separated by the STI are covered by a P+ implant layer 77 and an N+ implant layer (complementary to the P+ implant layer 77) to form the P and N terminals of the diode 70, respectively. The active regions 73 and 74 are all located in an N-well 75, which is a well that breaks into the PMOS in a standard CMOS process. A fuse element 72 is coupled to the P+ active region via a metal 76 (in a single contact point 71) 73. This contact point 71 is significantly different from conventional contact points, one contact point can connect the fuse element via a metal and the other connection point connects the metal via the P+ active area. By directly connecting a fuse element to an active region via a metal within a single contact point, the cell area can be substantially reduced. The adjoining contact can be larger than the normal contact point and can be a square contact point and have twice the area of the square contact point of a typical CMOS process. The fuse element of this embodiment can be made of a CMOS gate (including polysilicon, metal germanium polysilicon, polysilicon metal, local interconnect, or non-aluminum metal CMOS gate) to provide a contiguous contact.

Figure 8b shows a top view of an electrical fuse unit 70" having a dummy MOS gate 78" for P+ and N+ (as both ends of the diode) in the N-well, in accordance with an embodiment. The isolation and having an electrical fuse element 72". An active region 71" is divided into an upper active region 73" and a lower active region 74" by a dummy MOS gate 78". The upper active region 73" and the lower active region The 74" is covered by the P+ implant layer 77 and the N+ implant layer (complementary to the P+ implant layer 77). In the cell 70", the upper active region 73" and the lower active region 74" form a diode. Both ends. A dummy MOS gate (e.g., a polysilicon) 78" provides isolation of the diode P+/N+ regions of cell 70" and may have a fixed bias or coupled to the cathode of the diode. The polysilicon 78" is a dummy MOS gate in a standard CMOS process and can be a metal gate in an advanced metal gate CMOS process. The width of the dummy MOS gate can be close to the minimum gate width of the CMOS technology. In an embodiment, the width of the dummy MOS gate is less than twice the minimum gate width of the CMOS technology. The dummy MOS gate can also be fabricated by an I/O device to withstand a higher voltage. The active region 71" is located at an N-well 75", this N The well is a well that breaks into the PMOS in a standard CMOS process. A fuse element 72" is coupled at one end to the P+ active region 73" via a metal 76" (via contact points 75"-2 and 75"-3), At the other end is coupled to a high voltage source line V+ (via contact point 75"-1). N+ region 74" is coupled via contact point 75-4" to a low voltage source line V-. According to an embodiment, the contact At least one of the points 75"-1, 2, 3, 4 is larger than the contact point outside the memory array to lower the resistance. When high and low voltages are applied to V+ and V-, respectively, a current flows through the fuse element 72" to program it in a high resistance state. state.

9 is an example of a processor system 700. Processor system 700 is included in one example in programmable resistive element 744 (eg, in cell array 742) in memory 740. Processor system 700 can be, for example, a computer system. The computer system includes a central processing unit 710 for communicating via a common bus 715, including various memory and peripheral devices (such as I/O 720, hard disk 730, CDROM 750, memory 740, and other memory 760). . The other memory 760 is a conventional memory such as SRAM, DRAM, flash memory, and is typically connected to the CPU 710 by a body controller. CPU 710 is typically a microprocessor, a digital signal processor or other programmable digital logic component. The memory 740 is preferably implemented in an integrated circuit comprising a memory array 742 having at least one programmable resistive element 744. Memory 740 is typically connectable to CPU 710 via a memory controller interface. If desired, memory 740 can be combined with a processor (e.g., CPU 710) in a single integrated circuit.

The invention can be implemented in part or in whole on a printed circuit board or in an integrated circuit of a system. The programmable resistive element can be a fuse, an anti-fuse or a new non-volatile memory. The fuse can be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a locally connected fuse, a metal fuse, a contact point fuse, a layer indirect fuse, or a fuse made by a CMOS gate. wire. The antifuse can be a gate oxide collapse antifuse, a contact point with a dielectric therebetween, or a layer indirect antifuse. The new non-volatile memory can be magnetic memory (MRAM), conductive bridge random access memory (CBRAM), or resistive random access memory (RRAM). Although the programming mechanism is different, the logic states are defined by different resistance values.

In summary, the present invention has industrial applicability, novelty and advancement, and the structure of the present invention has not been seen in similar products and publicly used, and fully complies with the requirements of the invention patent application, and converts The patent law applies.

30‧‧‧ memory unit

30a‧‧‧resistive components

30b‧‧‧ diode

Claims (41)

A single-time programmable (OTP) memory, comprising: a plurality of single-time programmable units, at least one single-time programmable unit comprising at least: a single-time programmable element comprising at least one electrical fuse, the electrical fuse The first voltage source line is coupled to the first voltage source line; and a programming selector is coupled to the single-time programmable element and a second voltage source line, wherein at least a portion of the electrical fuse has at least one extended area, the expansion The region has a reduced current or no current flowing; and wherein the single programmable element is programmable by applying a voltage to the first and second voltage source lines and turning on the programming selector, thereby Programmable elements change to different logic states. The single-time programmable memory of claim 1, wherein the electrical fuse is made of polysilicon, metal telluride, metal germanium polysilicon, CMOS metal gate, metal interconnect, polysilicon, local interconnect, metal alloy, or At least one of the thermally isolated active regions is fabricated. A single-time programmable memory as claimed in claim 1, wherein the width of the extended region is approximately equal to the minimum width and/or the aspect ratio is greater than 0.6 times the current path. A one-time programmable memory of claim 1, wherein at least a portion or extension of the electrical fuse has at least one bend of about 45 degrees or 90 degrees. The one-time programmable memory of claim 1, wherein the electrical fuse has two ends, and the electrical fuse has an aspect ratio of 2 to 8 between the two closest contact points of the two ends. A single-time programmable memory as claimed in claim 1, wherein the electrical fuse has only one contact point at at least one end. A single-time programmable memory as claimed in claim 1, wherein the electrical fuse has no more than two contact points at at least one end. The single-time programmable memory of claim 1, wherein the single-time programmable unit is a part of a single-time programmable memory array, wherein the electrical fuse or the programming selector has at least one contact point, The contact point is greater than at least one contact point outside the single programmable memory array. The one-time programmable memory of claim 1, wherein the one-time programmable single is a portion of a single-time programmable memory array, wherein the electrical fuse or the programming selector has at least one contact point periphery The periphery of the contact point is smaller than the periphery of at least one contact point outside the single-time programmable memory array. The one-time programmable memory of claim 1, wherein at least one contact point width of at least one end of the electrical fuse is equal to or greater than a fuse width value. The one-time programmable memory of claim 1, wherein the electrical fuse has at least one active region adjacent to the fuse, and/or at least one substrate contact is established on the active region. The one-time programmable memory of claim 1, wherein the programming selector comprises at least one diode or a MOS, which can be turned on via a channel or a source/drain junction. A single-time programmable memory as claimed in claim 1, wherein the programming selector is formed in a thermally isolated substrate or a three-dimensional fin structure. The one-time programmable memory of claim 1, wherein the programming selector has at least one diode, the diode having at least one first active region and one second active region isolated from the first active region, The first active region has a first type of doping, the second active region has a second type of doping, the first active region provides a first end of the diode, and the second active region provides the second second active region The first and second active regions are all located in a common CMOS well or on an isolation substrate, and at least one of the active regions is constructed by a source or a drain of the CMOS device. The single-time programmable memory of claim 14, wherein the single-time programmable memory comprises at least one shallow trench isolation, the shallow trench isolation isolating the first and second ends of the diode, and/ Or isolate adjacent single-time programmable units. The one-time programmable memory of claim 14, wherein the one-time programmable memory comprises at least one dummy CMOS gate, the dummy CMOS gate isolating the first and second ends of the diode, and/ Or isolate adjacent single-time programmable units. A one-time programmable memory of claim 1, wherein a portion of the gate of the programming selector has a gate oxide thickness greater than a gate oxide thickness of the core component. An electronic system comprising: at least one processor; and a single-time programmable (OTP) memory operatively coupled to the processor, the single-time programmable memory comprising: a plurality of single-time programmable units, at least one The sub-programmable unit includes: a single-time programmable element including at least one electrical fuse operatively coupled to a first voltage source line; and a programming selector coupled to the one-time programmable An element and a second voltage source line, wherein at least a portion of the electrical fuse has at least one extension region having a reduced current or no current flowing; and wherein the single programmable element is A voltage is applied to the first and second voltage source lines and the programming selector is turned on to program, thereby changing the one-time programmable element to a different logic state. The electronic system of claim 18, wherein the programming selector comprises at least one diode or a MOS, which can be turned on via a channel or a source/drain junction. The electronic system of claim 18, wherein the electrical fuse is comprised of polysilicon, metal telluride, metal deuterated polysilicon, CMOS metal gate, metal interconnect, polysilicon metal, local interconnect, metal alloy, or thermally isolated active region Made in at least one of them. An operation single-time programmable (OTP) memory method, comprising: providing a plurality of single-time programmable units, wherein at least one single-time programmable unit comprises (i) a single-time programmable element comprising at least one electrical fuse, The electrical fuse is coupled to a first voltage source line; (ii) a programming selector is coupled to the single programmable element and a second voltage source line, wherein at least a portion of the electrical fuse has at least An extension region having a reduced current or no current flowing; and programming the single programmable unit at least once by applying a voltage to the first and second voltage source lines and turning on the programming selector One unit to a different logic state. The one-time programmable memory method of claim 21, wherein the programming selector comprises at least one diode or a MOS, which can be turned on via a channel or a source/drain junction. The one-time programmable memory method of claim 21, wherein the electrical fuse is made of polysilicon, metal telluride, metal germanium polysilicon, CMOS metal gate, metal interconnect, polysilicon metal, local interconnect, metal alloy Or at least one of the thermally isolated active zones. A programmed one-time programmable (OTP) memory method comprising: providing a plurality of single-time programmable cells, wherein at least one single-time programmable cell comprises (i) a single-time programmable element comprising at least one electrical fuse, The electrical fuse is coupled to a first voltage source line; (ii) a programming selector is coupled to the single programmable element and a second voltage source line; and by applying a plurality of voltages or current pulses to the The first and second voltage source lines and the programming selector are turned on to gradually change the fuse resistance, thereby programming the at least one unit of the single programmable units to different logic states in a single pass. A method of programming a one-time programmable memory method of claim 24, wherein the step of programming at least one of the plurality of single-time programmable cells comprises: (a) obtaining a destructive programming current, the destructive programming At least one single programmable unit has an abrupt change in resistance; and (b) limits the programming current below the destructive programming current. A method of programming a one-time programmable memory method of claim 24, wherein the step of programming at least one of the plurality of single-time programmable cells comprises: (a) programming a single-time programmable memory using a low programming voltage In one part, the programming voltage is gradually increased until all single-time programmable cells can be programmed and confirmed correctly, thereby determining a lower programming voltage; and (b) continuously increasing the programming voltage to program the same portion of the single-time programmable unit Until an excessive voltage is asserted, at least one single programmable unit, whether programmed or not, has been acknowledged to fail under this excessive voltage application. This excessive voltage is a programming voltage upper limit. The method of programming a one-time programmable memory method of claim 26, wherein the step of programming at least one of the plurality of single-time programmable cells in a single pulse is performed in a single pulse manner between the upper and lower limits of the programming voltage. The method of programming a single-time programmable memory of claim 24, wherein the selector is a diode having a dummy gate to isolate the first end and the second end of the diode, or the selector For a MOS, the MOS can be turned on by a channel or a source/channel junction. The programming single-programmable memory method of claim 24, wherein the programming selector has at least one diode, the diode having at least one first active region and one of the second active regions isolated from the first active region a region, the first active region has a first type of doping, and the second active region has a second type of doping The first active region provides the first end of the diode, and the second active region provides the second end of the diode. The first and second active regions are all located in a common CMOS well or in an isolated substrate. At least one of the active regions is constructed by a source or a drain of a CMOS device. The one-time programmable memory method of claim 24, wherein the one-time programmable memory comprises at least one shallow trench isolation, the shallow trench isolation isolating the first and second ends of the diode, And/or isolate adjacent single-time programmable units. A method of programming a single-time programmable memory of claim 24, wherein the programming selector is formed in a thermally isolated substrate or a three-dimensional fin structure. A method of programming a one-time programmable memory according to claim 24, wherein the electrical fuse comprises a heat sink, a heating element or a portion of an extension. A one-time programmable memory method as claimed in claim 24, wherein the electrical fuse is made of polysilicon, metal telluride, metal germanium polysilicon, CMOS metal gate, metal interconnect, polysilicon, local interconnect, metal alloy Or at least one of the thermally isolated active zones. A programmable resistance element (PRD) memory includes: a plurality of programmable resistance element units, at least one programmable resistance element unit including at least one programmable resistance element (PRE) coupled to a first voltage source line, and at least one a metal oxide semiconductor (MOS) device having a source coupled to the programmable resistor element, coupled to a drain of a second voltage source line, coupled to a body of the drain, and coupled to the third a gate of the voltage source line, wherein a voltage is applied to the first, second, and/or third voltage source lines to turn on a source junction diode of the MOS or a MOS channel to program the programmable resistor Elements to different logical states. A programmable resistive element (PRD) memory according to claim 34, wherein the programmable resistive element can (a) pass a voltage to a source junction of the first, second and/or third voltage source line conducting MOS The diodes are programmed to the programmable resistance element to a different logic state; and (b) the channel is turned on by applying a voltage to the first, second, and third voltage source lines to read the programmable resistance element as a Logic state. A programmable resistive element (PRD) memory according to claim 34, wherein the programmable resistive element can (a) pass a voltage to a source junction of the first, second and/or third voltage source line conducting MOS The diode changes the programmable resistance element to a logic state; and (b) changes the programmable resistance element to another logic by applying a voltage to the first, second, and third voltage source lines to turn on the MOS channel status. The programmable resistive element (PRD) memory of claim 34 wherein the programmable resistance element is a single programmable element that is programmable only once. The programmable resistive element (PRD) memory of claim 34, wherein the programmable resistive element comprises at least one thin film, wherein the programmable resistive element is phase change memory (PCRAM), resistive random access memory (RRAM) ), conductive bridge random access memory (CBRAM) or magnetic memory (MRAM). A programmable resistive element (PRD) memory according to claim 34, wherein the programmable resistive element comprises a phase change material film comprising at least at least one of germanium (Ge), germanium (Sb), and germanium (Te). One. A programmable resistive element (PRD) memory according to claim 34, wherein the programmable resistive element comprises a metal oxide film between the metal electrode or the metal alloy electrode. A programmable resistive element (PRD) memory according to claim 34, wherein the programmable resistive element comprises a solid electrolyte film between the metal electrode or the metal alloy electrode.