CN104464816B - Single programmable memory body and its operating method and programmed method and electronic system - Google Patents

Abstract

A kind of single programmable memory body and its operating method and programmed method and electronic system, the single programmable memory body includes: multiple single programmable units, an at least single programmable unit includes at least: a single programmable element includes an at least electrical fuse, which is coupled to a first voltage source line；And one programming selector be coupled to the single programmable element and a second voltage source line, wherein the electrical fuse is at least a part of has an at least expansion area, which has decrement electric current or to flow through without electric current；And wherein the single programmable element can be programmed by applying voltages to first and second voltage source line and the programming selector being connected, and whereby change the single programmable element to Different Logic state.Programmable resistance cell of the invention will use junction rectifier to illustrate embodiment as the example of programming selector.This programmable resistance cell can be used CMOS logic technique to reduce unit size and cost.

Description

Single programmable memory body and its operating method and programmed method and electronic system

Technical field

The present invention relates to a kind of programmable memory body elements, particularly with regard to the programmable resistance member for memory array Part.

Background technique

The resistance states that programmable resistance element typically refers to element can change after programming.Resistance states can be by resistance Value determines.For example, resistance element can be single programmable (One-Time Programmable, OTP) element (such as electricity Property fuse), and programmed method can apply high voltage, pass through OTP element to generate high current.When high current will be by will program choosing It selects device conducting and flows through OTP element, OTP element will be burnt into high or low resistance states (depending on being fuse or antifuse) and be added With programming.

Electrical fuse is a kind of common OTP, and this programmable resistance element, can be by connecting in one section, such as polycrystalline Silicon, silicification polysilicon, silicide, metal, metal alloy or their combination.Metal can be aluminium, copper or other transition metal. The electrical fuse of most common of them is the CMOS gate made of silicification polysilicon, is used as interior connection (interconnect).Electrical fuse is also possible to one or more contact points (contact) or interlayer contact (via), without It is the interior connection of small fragment.Contact point or interlayer contact can be burnt into high resistance state by high current.Electrical fuse can be anti-molten Silk, high voltage appearance reduce resistance, rather than improve resistance.Antifuse can be by one or more contacts or interlayer contact group At, and therebetween containing insulator.Antifuse can also be coupled in CMOS ontology by CMOS gate, be regarded containing grid oxic horizon For insulator.

Programmable resistance element can be reversible resistive element, with overprogram and reversible can be programmed to digital logic value " 0 " or " 1 ".Programmable resistance element can be manufactured from phase-change material, as germanium (Ge), antimony (Sb), tellurium (Te) composition Ge2Sb2Te5 (GST-225) or including ingredient indium (In), the GeSbTe class material of tin (Sn) or selenium (Se).Another phase transformation material Material includes chalcogenide material, such as AglnSbTe.Via high voltage short pulse or low-voltage long pulse, phase-change material can be programmed At amorphous state high resistance state or crystalline state low resistance state.Another reversible resistance element is a kind of referred to as resistor type random access The memory body of access/memory body (RRAM) is originally insulative dielectric matter, after can via filament, defect or metal migrate and Conducting.Dielectric medium can be transition metal oxide, such as NiO or TiO₂；Or be perovskite material, such as Sr (Zr) TiO₃Or PCMO；Or For charge-transfer complex, such as CuTCNQ；Or be organic donor-acceptor systems, such as Al AIDCN.RRAM storage unit by Metal oxide between electrode, such as platinum/nickel oxide/platinum (Pt/NiO/Pt), titanium nitride/titanium oxide/hafnium oxide/titanium nitride (TiN/TiOx/HfO₂/ TiN), titanium nitride/zinc oxide/platinum (TiN/ZnO/Pt) or tungsten/titanium nitride/silica/silicon (W/ TiN/SiO₂/ Si) it is made.The reversible change of the resistance states is via voltage or the polarity of current impulse, intensity and to continue Time, to generate or eliminate conductive filament.

The programmable resistance element of another similar resistive random access memory body (RRAM), is exactly that conducting bridge is deposited at random Take memory body (CBRAM).This memory body is based on electrochemical deposition and to remove the solid-state between metal or metal alloy electrode Metal ion in electrolytic thin-membrane.Electrode can be an oxidable anode and inert cathode, and electrolyte can be and mix The chalcogenide glass such as Germanium selenide (GeSe) or selenizing sulphur (GeS) etc. of silver or copper.Reversible change of the resistance states is via electricity Polarity, intensity and the duration of pressure or current impulse, to generate or eliminate conducting bridge.Furthermore programmable resistance element can also For Magnetic Memory body (MRAM), the magnetic tunnel junction made by multi-layered magnetic layer (MTJ) is constituted.In spin-transfer torque (SpinTransfer Torque, STT) MRAM, the current direction for being applied to MTJ determine parallel or antiparallel state, in turn Determine low or high resistance state.

A kind of traditional programmable resistance memory storage unit is as shown in Figure 1.Storage unit 10 includes resistive element 11 and N Type MOS transistor (NMOS) programs selector 12.It is coupled to the drain electrode of NMOS, other end coupling in 11 one end of resistive element Close positive voltage V+.The grid of NMOS 12 is coupled to selection signal SEL, and source electrode is coupled to negative voltage V-.When high voltage is added in V+ And low-voltage opens NMOS 12 via programming selection signal SEL is improved when being added in V-, resistive element 10 can be then programmed.Figure 2 show another programmable resistance memory storage unit 20 ', the programmable resistance member for being coupled to diode 22 ' with one Element 21 '.The cathode of this diode 22 ' can switch to low potential with conducting diode 22 ', and then be programmed.

Fig. 3 a and Fig. 3 b show some electrical fuse elements 80 and 84 being fabricated to from interior connection (Interconnect) Embodiment.There are three parts for resistive element: anode, cathode and ontology.Anode and cathode offer resistive element is connected to it The circuit of his part allows electric current to pass through ontology to cathode from anode flow.The width of ontology determines current density, in turn Determine the electromigration critical value of program current.Fig. 3 a shows a kind of traditional electrical fuse element 80, includes anode 81, cathode 82 and ontology 83.This embodiment has a large-scale and symmetrical anode and cathode.Fig. 3 b shows another traditional electrical fuse Element 84 includes anode 85, cathode 86 and ontology 87.Fuse element 81 and 85 in Fig. 3 a and Fig. 3 b be compare it is biggish Structure, this makes them unsuitable for some applications.

Summary of the invention

The purpose of the present invention is to provide a kind of programmable resistance cells, and junction rectifier will be used to select as programming The example for selecting device illustrates embodiment.This programmable resistance cell can be used CMOS logic technique with reduce unit size and at This.

According to an embodiment, a programmable resistance element and memory body can use P+/N trap diode as programming selector, Wherein the P of diode and N-terminal are P+ the and N+ active region in N trap.This P+ and N+ active region can also be used as PMOS or NMOS Source electrode or drain electrode (drain).Same N trap preferably can be the trap that down enters PMOS in standard CMOS logic process.By By using P+/N trap diode in standard CMOS process, unit size can be reduced, and be not required to any special processes or light shield.It connects Face diode can make in the N trap or p-well of main body CMOS, by SOI CMOS, main body (bulk) FinFET or SOI Isolation active region production in FinFET (or similar techniques).Therefore cost can be greatly reduced, (such as embedding to be conducive to multiple use Enter formula application).

According to an embodiment, junction rectifier can be established and as single programmable element by standard CMOS logic process Program selector.This single programmable element can (including connection in interior connection, part, contact point/interlayer connects for electrical fuse Point antifuse or gate oxide collapse antifuse etc.).Programmable resistance element can have radiating piece to radiate or heating member With heating, and then assist the programming of programmable resistance element.If programmable resistance element is electrical fuse, this electrical fuse can have There is expansion area to assist the programming of programmable resistance element.If programmable resistance element is metal fuse, can be made in program path Make an at least contact point and/or multiple interlayer contacts (one or more bridgings can be used), to generate more Joule heats and assist compiling Journey.This across be all electric conductivity and can by being connected in metal, metal gates, part, polycrystalline silicon metal be made.OTP cell can have An at least OTP element for an at least diode is couple in memory array.Diode can by the N trap of CMOS P+ and The production of N+ active region, or with the isolation active region as P and N-terminal.OTP element can for polysilicon, metal silication polysilicon, Metal silicide, metal, metal alloy, connects in part, active region, CMOS gate, CMOS metal is thermally isolated polycrystalline silicon metal Grid or said combination.

The present invention can realize in different embodiments, (include user's figure comprising method, system, element or device Interface and readable in computer medium).Multiple embodiments of the invention are described below.

An implementation for programmable resistance element (programmable resistive device, PRD) memory body Example, it includes at least multiple PRD units, an at least PRD unit includes that an at least PRD element is coupled to a first voltage source line, And programming selector coupling so far PRD element and a second voltage source line.At least part of this PRD element includes at least one Radiating piece, heating member or expansion area are with aided programming.Radiating piece is to establish inside PRD element or adjacent to PRD element to mention Rise heat dissipation effect.Heating member can be any high resistance material in current path so that the temperature of PRD element can increase.Heating Part may include the multiple interior connections and/or multiple contact points or interlayer contact as bridging.Expansion area is in mono- area PRD Nei Domain, and have decrement electric current or flowed through without electric current.Via voltage is applied to first and second voltage source line, this PRD element can It is programmed to different logic states.

Electronic system according to an embodiment includes that an at least processor and a PRD memory operation are connected to this processing Device.This PRD memory body includes multiple PRD units.An at least PRD unit includes a PRD element, and operability is couple to one first electricity Potential source line and a programming selector couple so far PRD element and a second voltage source line.This PRD element operation be coupled to A few radiating piece, heating member or an expansion area are with aided programming.Radiating piece is to establish inside PRD element or adjacent to PRD member Element is with improving radiating effect.Heating member can be any high resistance material in current path so that the temperature of PRD element can rise It is high.Heating member may include the multiple interior connections and/or multiple contact points or interlayer contact as bridging.Expansion area is in PRD A region, and there is decrement electric current or to flow through without electric current.Via application voltage to first and second voltage source line, this PRD Element is programmable to different logic states.

According to an embodiment, the operating method of PRD memory body, which comprises the steps of, provides majority PRD unit, at least one PRD unit includes at least: (i) PRD element, operability are couple to a first voltage source line；(ii) a programming selector coupling So far PRD element and a second voltage source line；And (iii) this PRD element operation be coupled to an at least radiating piece, heating member or It is an expansion area with aided programming.Radiating piece is to establish inside PRD element or adjacent to PRD element with improving radiating effect.Add Warmware can be any high resistance material in current path so that the temperature of PRD element can increase.Heating member may include conduct Multiple interior connections of bridging and/or multiple contact points or interlayer contact.Expansion area is the region in PRD, and has decrement electricity It flows or is flowed through without electric current.Via voltage is applied to first and second voltage source line, this PRD element is programmable to different patrol The state of collecting.

According to an embodiment, OTP memory body includes multiple OTP units.At least an OTP unit includes at least: an OTP element An at least electrical fuse for a first voltage source line is couple to comprising operability；An and programming selector coupling so far OTP element An and the second voltage source line.At least part of this electrical fuse has an expansion area, has decrement electric current or does not have electric current stream It crosses.Via voltage is applied to first and second voltage source line, there is decrement electric current in this expansion area or flows through without electric current.Via applying Power-up is pressed onto first and second voltage source line and this programming selector is connected, this OTP element is programmable to different logic states.

An embodiment according to the present invention, an electronic system includes: an at least processor and OTP memory operation connection So far processor.This OTP memory body includes multiple OTP units.An at least OTP unit includes an OTP element, this OTP element packet The electrical fuse and a programming selector coupling so far OTP element and one the of a first voltage source line are couple to containing operability Two voltage source lines.At least part of this electrical fuse includes an expansion area, there are decrement electric current or no electric current in this expansion area It flows through.Via applying voltage to first and second voltage source line and this programming selector being connected, this OTP element is programmable to difference Logic state.

An embodiment according to the present invention, the operating method of an operation OTP memory body, which comprises the steps of, provides majority OTP Unit, at least an OTP unit include at least: (i) OTP element includes that operability is couple at least the one of a first voltage source line Electrical fuse；(ii) a programming selector couples so far OTP element and a second voltage source line；And (iii) this electrical fuse At least part includes an expansion area, there is decrement electric current in this expansion area or flows through without electric current；And via applying voltage to the One and the second voltage source line and be connected this programming selector, this OTP element can single be programmed to different logic states.

Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.

Detailed description of the invention

Fig. 1 shows an existing programmable resistance memory cell；

Fig. 2 shows another existing programmable resistance memory cell, and uses diode as programming selector；

Fig. 3 a and Fig. 3 b are shown respectively by the interior example for being connected to electrical fuse；

Fig. 4 a shows the block diagram of the memory cell using junction rectifier；

Fig. 4 b show an example electrical fuse programming process IV curve characteristic；

Fig. 5 a shows a sectional view of another junction rectifier embodiment, is isolated as programming selector and with STI；

Fig. 5 b shows a sectional view of another junction rectifier embodiment, as programming selector and with false CMOS grid Pole isolation；

Fig. 5 c shows a sectional view of another junction rectifier embodiment, is isolated as programming selector and with SBL；

The cross section of another embodiment shown in Fig. 5 d, wherein junction rectifier is worked as programming selector, and is used and insulated The false CMOS gate of silicon substrate (SOI) technology is isolated.

Fig. 6 a shows the top view of a junction rectifier, this junction rectifier is worked as programming selector, and uses insulating silicon Matrix (SOI) or the false CMOS gate of similar techniques do and are isolated；

Fig. 6 b is the top view of a programmable resistance unit, this programmable resistance unit has a resistive element and as volume The diode of journey selector, and diode is formed in a manner of one integral piece in isolation active region, and diode both ends are isolated with false grid；

Fig. 6 c is the top view of a Schottky diode, and there is STI to be isolated and as programming selector for this diode；

Fig. 6 d shows the top view of the Schottky diode of one embodiment of the invention, this diode is isolated with CMOS gate And as programming selector；

Fig. 6 e shows the top view of the Schottky diode of one embodiment of the invention, and there is this diode SBL to be isolated and make To program selector；

Fig. 6 f shows that a perspective view of junction rectifier embodiment, the junction rectifier are to use wing formula field effect transistor (FinFET) the false CMOS gate of technology makees the programming selector being isolated；

Fig. 6 g is shown using PMOS as diode (or MOS), to provide programming or read the embodiment of selector；

Fig. 6 h is shown in the unit cross-sectional view of Fig. 6 g, uses PMOS to program selector or MOS as diode using display Read programming/selection path schematic diagram of selector；

Fig. 6 i further displays the mode of operation of Fig. 6 g diagram programmable resistance unit, which is to use PMOS as two Pole pipe programs/read selector；

Fig. 6 j further display Fig. 6 h diagram programmable resistance unit mode of operation, the unit be use PMOS as MOS programs/read selector；

Fig. 6 k is shown in the programmable resistance cell schematic diagram for being thermally isolated and making on matrix, the programmable resistance element Unit uses the false grid of programming selector as PRD element；

Fig. 6 l is shown in the programmable resistance cell schematic diagram for being thermally isolated and making on matrix, the programmable resistance element Unit uses the mos gate pole of programming selector as PRD element；

Fig. 7 a shows the top view of an electrical fuse element, this electrical fuse element uses thermally conductive but electrical isolation radiating piece To be coupled to anode；

Fig. 7 b shows the top view of an electrical fuse element, this electrical fuse element is used under main body and close to anode One thin-oxide is as radiating piece；

Fig. 7 c shows the top view of an electrical fuse element, this electrical fuse element is used in the thin-oxide under anode Area is as radiating piece；

Fig. 7 d shows the top view of an electrical fuse element, this electrical fuse element uses the thin-oxide close to anode Area is as radiating piece；

Fig. 7 e shows the top view of an electrical fuse element, this electrical fuse element use expanded anode as heat dissipation Part；

Fig. 7 f shows the top view of an electrical fuse element, this electrical fuse element uses a high resistance area as heating Part；

Fig. 7 g shows the top view of an electrical fuse element, this electrical fuse element has in an expansion area of cathode；

Fig. 7 h shows the top view of an electrical fuse element, this electrical fuse element has in an expansion area of cathode, and There is non-boundary contact point in anode；

Fig. 7 i shows the top view of an electrical fuse element, this electrical fuse element has in an expansion area of cathode, and In the shared contact point of anode；

Fig. 7 j shows the top view of an electrical fuse element, this electrical fuse element has an at least recess；

Fig. 7 k shows the top view of an electrical fuse element, this electrical fuse element has part NMOS metal gates and portion Divide PMOS metal gates；

Fig. 8 a display according to an electrical fuse unit top view, this electrical fuse unit have a P+/N trap diode and Abutting contact point；

Top view of Fig. 8 b display according to a programmable resistance unit, this programmable resistance unit are coupled to two pole of a junction Pipe, this diode have a false CMOS gate using the isolation as P+ and N+；

Fig. 9 is the processor system of an example.

Specific embodiment

Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:

The embodiment of the present invention relates to the programmable resistance for using P+/N trap junction rectifier as programming selector Element.This diode may include P+ the and N+ active region in a N well region.It can be produced on N trap easily by the CMOS technology of standard The programmable resistance element that the P+ and N+ active Qu ﹐ in area is of the invention can effectively make and reduce cost.For standard SOI, FinFET or similar Ji Shu ﹐ isolation active region can make programming selector diode or programmable resistance element.This is programmable Resistive element can also be included in an electronic system.

In one or more embodiments Zhong ﹐ junction rectifier available standards CMOS technology Zuo ﹐ and as single programmable (One-Time Programmable, OTP) element, if electrical fuse (includes interior connection (interconnect) fuse, part Interior connection (local interconnect) fuse, contact point/guide hole fuse, contact point/guide hole antifuse or gate oxide Collapse antifuse) programming selector.At a programmable resistance element (programmable resistive device, PRD) In may include radiating piece, heating member or expansion area with aided programming.Radiating piece includes an at least Dao Ti ﹐ close to PRD element or position In the inner with heat dissipation.Heating member may include the high resistance material in current path to generate heat.Connect in interior connection, part It connects, silicon, polysilicon, metal, conductor, single or multiple contact point or guide hole all can be used as heating member.Extended area is in PRD There is no electric current that can flow through or be reduced the region that electric current flows through in element.If electrical fuse is to belong to Rong Si ﹐ using Jin on programming road Diameter can make an at least contact point and/or multiple guide holes (multiple bridgings can be used) to generate heat as volume via Joule effect Journey.Bridging (jumper) is electric conductivity and can be formed by connection in metal, metal gates, interior connection or part.In memory body Dan Yuanzhong ﹐ OTP cell includes that its lotus root of at least OTP member element ﹐ is connected to an at least diode.Diode can be by the P+ in CMOS trap And it N+ active region Zuo ﹐ or is made at isolated active region (as the end diode P/N).OTP element can be polysilicon, metal Silicification polysilicon, polycrystalline silicon metal, metal, metal alloy, connects in part, active region, CMOS grid is thermally isolated metal silicide Pole or combinations thereof.

Cooperation this invention of Detailed description of the invention Shi Shi Li ﹐ so should be known that this case range is not limited to illustrate to this technology well known below Embodiment.

Fig. 4 a shows the block diagram of the memory cell 30 using junction rectifier.This memory cell 30 includes resistance member A part 30a and junction rectifier 30b.Resistive element 30a is couple to the anode and high voltage V+ of junction rectifier 30b；Diode The cathode of 30b is then couple to low-voltage V-.According to a Shi Shi Li ﹐ memory cell 30 be Rong Dan Yuan ﹐ its with resistive element 30a is using as electrical fuse.Junction rectifier 30b is made as programming selector, the P+/N trap of available standards CMOS technology, And p-type substrate or the isolation active region in SOI are used, or use finfet technology.P+ and N+ master as anode and cathode Dynamic area is source electrode and the drain electrode of cmos element.N trap is the CMOS trap that down enters PMOS element；Furthermore junction rectifier can also It is made of N+/P trap or is made using the CMOS technology of N-type substrate.Resistive element 30a and junction rectifier 30b are in voltage source V + and V- between position it is also interchangeable.Appropriate voltage is applied with appropriate time between voltage source V+ and V-, resistive element 30a can It is programmed for high resistance or low resistance state according to voltage swing and time, memory cell 30 is made to be programmed for storage data (example Such as a bit data).False CMOS gate, shallow trench isolation (STI), selective oxidation can be used in P+ the and N+ active region of diode (LOCOS) or silicide barrier layer (SBL) is isolated.

Fig. 4 b show the IV characteristic curve 30' of an example electrical fuse programming process.Its IV curve is shown to be electricity Property fuse impose a voltage source be X-axis parameter, corresponding to response current be Y-axis parameter.When electric current is very low, curve Slope is the inverse of initial resistance.When a current increases, due to the reason of Joule heat, resistance also and then increases；Assuming that temperature system Number is positive, it can be seen that curve starts to be bent towards X-axis.When having crossed critical current (Icrit), due to rupturing, divide Solution or fusing, the resistance of electrical fuse start change dramatically and even become negative value.Traditional electrical fuse programmed method is operation Electric current higher than Icrit, multiplicative model seems explosion, therefore obtained resistance is completely not expected.On the other hand, Assuming that operation electric current is lower than Icrit, writing mechanism is just only electromigration (electeomigration) mode.Due to being that electricity moves The relationship of shifting, write-in behavior become easily controllable and tool certainty.Electrical fuse can repeatedly receive pulse mode and be compiled Journey, and resistance is the gradual variation with pulse application, until satisfactory high resistance may achieve and be detected as Only.According to the electrical fuse of aforesaid way programming, yield can be the hundred of percentage after programming, and yield can be by the system before programming Make defect to be determined.IV characteristic curve shown in Fig. 4 b can also be used to have at least OTP of an OTP element and a selector mono- Member.Furthermore the programming state (whether having programming) of the electrical fuse by aforesaid way programming, by optical microscopy or can not sweep Formula electron microscope (SEM) is retouched it appear that coming.

The present invention provides a kind of reliable method for programming electrical fuse, comprises the steps of (a) and uses a low program voltage A part of starting one OTP memory body of programming gradually increases program voltage until all OTP units can be programmed and read really Recognize, this voltage is denoted as program voltage lower limit；(b) same section for continuing to increase program voltage to program OTP unit is straight It is read confirmation failure to an at least OTP unit (in spite of programmed), this voltage is denoted as on program voltage Limit.In addition, programming time can be adjusted to repeat the above steps (a) and (b) until lower limit, the upper limit or a programming section (upper limit And the voltage range between lower limit) meet a standard value until.One reliable program section of electrical fuse is shown in Fig. 4 b.It is defining After programming section, other OTP units can be programmed in the voltage between lower limit and the upper limit, and with a cell voltage or electric current Pulse mode.

The present invention provides a kind of cell current measurement mode, comprises the steps of (a) in programming mode, applies a voltage To a programming pin VDDP, this voltage is sufficiently low not program OTP unit；(b) VDDP is avoided to provide current to non-for OTP memory The OTP circuit of volume array；(c) selector of (conducting) OTP unit to be measured is opened；(d) electric current for flowing through VDDP is measured to make For by the cell current of selection OTP unit.The method can be applied to be programmed or unprogrammed OTP unit.The method can also be made To judge the whether programmed criterion of OTP unit, as long as setting represents the largest unit electric current programmed and represents unprogrammed Minimum unit electric current, to determine the bound of the program voltage when defining characteristic.

Electrical fuse unit can be used as the example for illustrating Key Implementation concept.Fig. 5 a shows the cross section of diode 32, Use the P+/N trap diode of shallow trench isolation as programming selector in programmable resistance element.Respectively constitute diode 32 P and N terminal P+ active region 33 and N+ active region 37 be exactly PMOS and NMOS in standard CMOS logic process source electrode Or drain electrode.N+ active region 37 is coupled to N trap 34 (being formed in P matrix 35), this N trap is embedded in standard CMOS logic process PMOS.The active region of the isolation different elements of shallow trench isolation 36.Resistive element (is not explicitly shown Fig. 5 a), can such as electrical fuse It is coupled to P+ active region 33 with one end and the other end is coupled to high-voltage power supply V+.In order to program this programmable resistance type member Part, high voltage are added in V+, and low-voltage or earthing potential are applied to N+ active region 37.Therefore, high current passes through fuse element and two Pole pipe 32 carrys out programming resistors element.

Fig. 5 b shows a sectional view of another 32 ' embodiment of junction rectifier, as programming selector and with vacation CMOS gate 39 ' is isolated.Shallow trench isolation 36' provides the isolation of other active regions.Active region 31' is with shallow trench isolation 36' To be defined.Here N+ and P+ active region 37' and 33' is further respectively by false CMOS gate 39', P+ implant layer 38' and N + implant layer (complementation of P+ implant layer 38') mixes to be defined, and constitutes the end N and P of diode 32'.False mos gate pole 39' is The CMOS gate of standard CMOS process production.The width of false mos gate pole 39' may be selected to be the minimum widith of CMOS gate, and can Width less than twice.False mos gate pole 39' also can have transistor of the thicker grid oxic horizon for import and export end.It should Diode 32 ' is made into the element of similar PMOS, and contains 37', 39', 33' and 34' as source electrode, grid, drain electrode and N Trap；However N+ implant layer is covered on source electrode 37 ', rather than the P+ implant layer 38' that really PMOS is covered.False mos gate pole 39' It is preferably biased in a fixed voltage or lotus root is connected to N+ active region 37', its purpose is that in the production process actively as P+ Isolation between area 33' and N+ active region 37'.N+ active region 37' is coupled to N trap 34'(and is formed in P matrix 35'), this trap It is the ontology for being embedded in PMOS in standard CMOS logic process.P matrix 35' is the matrix of P-type silicon.Resistive element (does not have in Fig. 5 b Have display), such as electrical fuse, the area P+ 33' can be coupled to one end and the other end is coupled to a high-voltage power supply V+.In order to Program this programmable resistance element, high voltage is applied to V+, and low-voltage or is grounded to N+ active region 37'.Therefore, high current Flow through fuse element and 32 ' come programming resistors element of diode.This embodiment has smaller small size and low resistance.

The cross section of another embodiment shown in Fig. 5 c, wherein junction rectifier 32 " with silicide barrier layer (SBL) 39 " every From and as programming selector.Fig. 5 c is similar to Fig. 5 b, however the false CMOS gate 39 ' in Fig. 5 b is hindered by the silicide in Fig. 5 c Barrier 39 " is replaced, to prevent silicide growth at the top of active region 31 ".If hindered without false CMOS gate or silicide Barrier, N+ and P+ active region will be short-circuited by the metal silicide on 31 " surface of active area.In addition, in addition diagram shows P + active region 33 ", N trap 34 ", P matrix 35 ", shallow trench isolation 36 ", N+ active region 37 ", P+ implant layer 38 ".

The cross section of another embodiment shown in Fig. 5 d, wherein junction rectifier 32 " is worked as programming selector, and using insulation Silicon substrate (SOI), FinFET or other similar technology.In SOI technology, matrix 35 " is such as silica or similar material Insulator, this insulator have thin-layer silicon trap be grown in top.All NMOS and PMOS are in silicon trap, by silica or class As material isolation each other with matrix 35 ".One active region 31 " is via false CMOS gate 39 ", P+ implant layer 38 " and N+ implant layer The mixing of (complementation of P+ implant layer 38 ") is divided into N+ active region 37 ", P+ active region 33 " and ontology 34 ".This N+ active region 37 " and P+ active region 33 " respectively constitutes N-terminal and the end P of junction rectifier 32 ".N+ active region 37 " and P+ active region 33 " can respectively and The source electrode of NMOS and PMOS or drain electrode are identical in standard CMOS logic process.Equally, false CMOS gate 39 " can and standard CMOS The CMOS gate of process development is identical.False mos gate pole 39 " can be biased in a fixed voltage, its purpose is that in manufacturing process In as the isolation between P+ active region 33 " and N+ active region 37 ".The variable-width of false mos gate pole 39 ", but according to implementation The minimum grid width of the accessible CMOS gate of example, and it is smaller than twice of minimum grid width.False mos gate pole 39 " can also have Compared with thick grid oxic horizon to bear high voltage.N+ active region 37 " is coupled to low-voltage V-.Resistive element (does not have in Fig. 5 d Display), such as electrical fuse, P+ active region 33 " can be coupled to one end and the other end is coupled to high-voltage power supply V+.In order to This electrical fuse storage unit is programmed, high and low voltage is respectively applied to V+ and V-, and conducting electric current flows through fuse element and connects 32 " come programming resistors element of face diode.The other embodiments of CMOS isolation technology, such as shallow trench isolation (STI), false CMOS grid Pole or silicide barrier layer (SBL) can be on one to four side or any one side, this can be easily applied to corresponding CMOS SOI Technology.

Fig. 6 a shows the top view of a junction rectifier 832, the cross-sectional view of corresponding Fig. 5 d.This junction rectifier 832 Worked as programming selector, and uses insulation silicon substrate (SOI), FinFET or other similar technology with self-insulating active region system At.Active region 831 via false CMOS gate 839, P+ implant layer 838 and N+ implant layer (complementation of P+ implant layer 838) mixing It is divided into N+ active region 837, P+ active region 833 and ontology (under false CMOS gate 839).

Fig. 6 b is the top view of a fuse element 932, this fuse element 932 is by a fuse element 931-2, a diode 931-1 and a contact zone 931-3 are made；Diode 931-1 is as programming selector and in isolation active region with one integral piece (one Piece) mode is formed.The active region 931-1,931-2,931-3 are the isolation active regions of the construction in identical structure, to make For the diode, fuse element and contact zone of fuse element 932.Active region 931-1 is isolated, region is divided by false CMOS gate 939 933 and 937, and those areas are respectively by P+ implant layer 938 and N+ implant layer (complementation of P+ implant layer 938) covering using as two poles The end P of pipe 931-1 and N-terminal.The area P+ 933 is couple to fuse element 931-2, is more connected to contact zone 931-3.This contact zone The cathode contacts of 931-3 and diode 931-1 point can be couple to V+ and V- power supply line via one or more contact points.

If applying high and low-voltage respectively in V+ and V-, there is electric current that can flow through fuse element 931-2 so that its programming is supreme Resistance states.According to an embodiment, fuse element 931-2 can be all N-type or p-type.According to another embodiment, fuse element 931-2 can half be p-type half be N-type so that fuse element 931-2 is at the time of reading similar to the diode of reverse biased.And The metal silicide on top can be vague and general after programming.If without metal silicide, this fuse element 931-2 (for OTP element) It can be made with N/P or P/N diode fashion, to be collapsed in positive or reverse biased.In this embodiment, OTP element can To be coupled directly to the diode as programming selector and have no any contact point therebetween, reduce whereby cellar area and at This.

As shown in Fig. 6 c- Fig. 6 e, the diode as programming selector can be by the Schottky of standard CMOS process (Schottky) diode fabrication.Schottky diode is a kind of metal-semiconductor junction diode, rather than generally by partly leading Body P+ and N+ adulterate constituted junction rectifier.Schottky diode and junction rectifier are closely similar, and two pole of Schottky The anode of pipe is to be connected to that N or p-type is lightly doped by metal, and the anode of general junction semiconductor is to be connected to heavy doping by metal N or p-type.The anode of Schottky diode can be made of any metal, such as aluminium, copper, metal alloy or metal silicide.Xiao Te It is cathode that the metal anode of based diode, which can be connected in N trap P+ active region in N+ active region or p-well,.Schottky diode can It is made of ontology CMOS SOI CMOS, plane or FinFET CMOS.Those skilled in the art know that the scope of the invention also includes The Schottky diode of different process.

Fig. 6 c shows the top view of the Schottky diode 530 of one embodiment of the invention.Schottky diode 530 is formed in One N trap (not shown) and have active region 531 (cathode) and active region 532 (anode).Active region 531 is covered by N+ implant layer 533 Lid and the contact point 535 with external connection.Active region 532 is not covered by N+ or P+ implant layer, makes its doping concentration and N trap It is substantially the same.There is a metal silicide layer to generate Schottky energy barrier with silicon on active region 532, and further via positive contact Point 536 is connected to metal 538.One P+ implant layer 534 can cover active region 532 to reduce leakage current.

Fig. 6 d shows the top view of the Schottky diode 530 ' of one embodiment of the invention.The formation of Schottky diode 530 ' With down enter in a N trap (not shown) and with active region 531 ' anode and cathode of diode.Active region 531 ' is by false grid 539 ' are divided into a central anode and two outer cathodes.Cathode is covered by N+ implant layer 533 ' and the contact point with external connection 535'.Central anode is not covered by N+ or P+ implant layer, is substantially the same its doping concentration with N trap.Have one on central anode Metal silicide layer is further connected to metal 538 ' via positive contact point 536 ' to generate Schottky energy barrier with silicon.One P + implant layer 534 ' can covering part central anode with reduce electric leakage.According to other embodiments, N+ implant layer 533 ' and P+ implant layer 534 ' boundary can be fallen on cathode.Fig. 6 e shows the top view of the Schottky diode 530 " of one embodiment of the invention.Xiao Te Based diode 530 " is formed in a N trap (not shown) and is entered the anode and cathode of diode with down with active region 531 ".Actively Area 531 " is silicified object barrier layer 539 " and is divided into a central anode and two outer cathodes.Cathode is covered simultaneously by N+ implant layer 533 " Contact point 535 " with external connection.Central anode is not covered by N+ or P+ implant layer, makes its doping concentration and N trap substantially It is identical.There is a metal silicide layer to generate Schottky energy barrier with silicon on central anode, and further via positive contact point 536 " are connected to metal 538 ".One P+ implant layer 534 " can cover central anode to reduce leakage current.

Fig. 6 f shows that a sectional view of another 45 embodiment of junction rectifier, the junction rectifier 45 are to imitate using wing formula field Answer the programming selector of transistor (FinFET) technology.FinFET refers to that wing formula (fin) is basic multi-gated transistor. Finfet technology has high and thin silicon island similar to traditional CMOS, increases on silicon substrate using as cmos element Main body.Its main body is divided into source electrode, drain electrode and channel as traditional cmos, by polysilicon or non-aluminum metal grid.Main difference It is in finfet technology, the ontology of MOS element is thus lifted on substrate, and twice of island area height is about the width in channel Degree, however the flow direction of electric current is still on the surface for being parallel to silicon.Fig. 6 f shows the embodiment of finfet technology, silicon substrate 35 be an epitaxial layer, is built on similar SOI insulating layer or other high resistance silicon substrates.Silicon substrate 35 can be etched into several Tall and big rectangle island area 31-1,31-2 and 31-3.Via grid oxic horizon appropriate grow up, island area 31-1,31-2 and 31-3 to cover the both sides in raised island area and can define source electrode and drain electrode area with mos gate pole 39-1,39-2 and 39-3 respectively. Source electrode and drain electrode area is formed in island area 31-1,31-2 and 31-3, is subsequently filled silicon/SiGe, extends source/drain regions to be formed Domain 40-1,40-2 allow the source electrode and drain electrode area of merging to be large enough to put down contact point.Extend regions and source/drain 40-1, 40-2 can be made by polysilicon, polysilicon/SiGe, lateral epitaxy SiGe or selection epitaxy growth (SEG) silicon/SiGe.Extend The other isolation active regions of regions and source/drain 40-1,40-2 can beside island area or the growth of island area end or It is depositing.In Fig. 6 f, the filling region for extending regions and source/drain 40-1,40-2 is used only to illustrate and appear cross section, Such as filling region can be filled into the top of island area 31-1,31-2 and 31-3.In this embodiment, active region 33-1,2,3 It is covered by P+ implant layer 38' and N+ implant layer (complementation of P+ implant layer 38') respectively with 37-1,2,3 to constitute junction rectifier 45 P and N-terminal, rather than as the PMOS of traditional FinFET is all covered by P+ implant layer 38'.N+ active region 37-1,2,3 is by coupling Close low voltage power supply V-.Resistive element (does not show) that such as electrical fuse, one end is coupled to P+ active region 33- in Fig. 6 f 1,2,3, the other end is coupled to high-voltage power supply V+.In order to program this electrical fuse, high and low voltage is respectively applied to V+ On V-, resistive element and junction rectifier 45, and then programming resistors element are flowed through with conducting electric current.The isolation of CMOS agent technology Other embodiments can be easily applied to such as shallow trench isolation (STI), false CMOS gate or silicide barrier layer (SBL) Corresponding finfet technology.

Fig. 5 d and Fig. 6 a, Fig. 6 b and Fig. 6 f are respectively displayed on isolation active region completely or partially and make diode (as volume Journey selector) or OTP element schematic diagram.Diode as programming selector can be by the isolation master of such as SOI or FINFET Dynamic area is made.Isolation active region can make the diode that there are P+ and N+ implant (two terminals as diode) at both ends, this cloth It plants identical with the source/drain implant of cmos element.False CMOS gate or silicide barrier layer can be used between this two terminals (SBL) it does isolation and avoids short circuit.Be isolated in SBL, SBL layer can and the overlapping of the implantation area N+ and P+, and the implantation area N+ and P+ is each other There is an interval.The breakdown voltage and leakage current of diode can be adjusted by the width and doping level that adjust this interval.As The fuse of OTP element can also be made by isolation active region.Because OTP is thermally isolated in a manner known thus, generated heat is difficult to arrange in programming It removes, can be conducive to improve temperature to accelerate to program.OTP element can be complete N+ or P+ implant.If there is metal at the top of active region Silicide, this OTP element can have part N+ implant, part N+ implant, so that OTP element is at the time of reading similar to the two of reverse biased Pole pipe.And the metal silicide on top can be vague and general after programming.If this OTP element can have part N without metal silicide + implant, part N+ implant, so that OTP element is at the time of reading similar to the diode that will be collapsed.In this two, OTP element or two Pole pipe can make in the identical structure of isolation active region to save area.In SOI or FinFET SOI technology, active region can It is isolated by silica or similar material with matrix and other active regions.Likewise, in FINFET agent technology, same Silicon substrate fin structure production active region be isolated from each other on the surface, these active regions can by extension regions and source/drain that This coupling.

Fig. 6 g is shown using PMOS as diode (or MOS), to provide programming or read the embodiment of selector.It can compile There is journey resistive element unit 170 programmable resistance element 171 to be coupled to a PMOS 177.The grid of this PMOS 177 is coupled to One reads character stick (WLRB), and drain electrode is coupled to programming character stick (WLPB), and source electrode is coupled to programmable resistance element 171, and Main body is coupled to drain electrode.The source junction construction of PMOS 177 can make this PMOS 177 when for selected unit programming, can be such as Operation as diode.And the source junction or channel construction of PMOS 177 can make this PMOS 177 (having internal node N) exist When for read operation, it can be operated such as diode or MOS selector

Fig. 6 h is shown in the unit cross-sectional view of Fig. 6 g, uses PMOS to program selector or MOS as diode using display Read programming/selection path schematic diagram of selector.Programmable resistance cell 170 ' has programmable resistance element 171 ' It is coupled to a PMOS, this PMOS has source electrode 172 ', grid 173 ', drain electrode 174 ', N trap 176 ' and N trap connector 175 '.This PMOS It is difficult to seek the special conduction mode seen with existing cmos digital or analogy-based reasoning, the 174 ' levels that will also drain are drawn to extremely low Voltage (such as ground connection) provides programming as shown by dashed lines so that the junction rectifier in source electrode 172 ' is connected.Because of two poles The IV curve of pipe follows index rule rather than square rule of MOS, and such operation mode can provide more high current with reducing unit Size and reduction program voltage.This PMOS can be connected at the time of reading to realize that low-voltage is read.

Fig. 6 i and Fig. 6 j further display the mode of operation of Fig. 6 g and Fig. 6 h diagram element, to illustrate the innovation of special element Property.Fig. 6 i shows programming and reading state by diode.In programming, the WLPB of selected unit is coupled to extremely low voltage (example Such as ground connection) source junction diode is connected, and WLRB may be coupled to VDDP (program voltage) or ground connection.Unselected cells WLPB and WLRB can be coupled to VDDP.At the time of reading, the WLRB for selecting unit is coupled to VDD core voltage or ground connection, and WLPB is coupled to ground connection so that the source junction diode of PMOS 171 shown in Fig. 6 g is connected.The WLPB and WLRB of unselected cells are It is couple to VDD.Fig. 6 j shows the state for being programmed by MOS and being read.Operation mode shown in this figure is similar with Fig. 6 i those shown, removes The WLRB and WLPB of selected unit are respectively coupled to except 0 volt and VDD/VDDP in reading and programming.Therefore PMOS can be It is connected when programming or reading.This PMOS can be laid out by traditional PMOS mode, and so it operates voltage and existing PMOS extremely not Together.In other embodiments, can also be combined by diode and/or MOS to be programmed or read, that is, an embodiment by Diode is programmed and is read by MOS.In another embodiment, for data with different with diode and MOS different current directions into Row programming.

Fig. 6 k is shown in programmable resistance element (PRD) unit for being thermally isolated and making on matrix (such as SOI or polysilicon) 730 schematic diagrames.The thermal conductivity that matrix is thermally isolated is very poor, and programmable resistance element (PRE) can be shared with the grid of programming selector And still possess high programming efficiency.This element 730 has a PRE, and it includes a main body 731, anode 732 and cathodes 733.PRE's Main body 731 is also the grid of false grid diode, this false grid diode has active region 734, with N+ implant 735 and cathode The cathode of contact point 737 and anode with P+ implant 736 and positive contact point 738.The cathode of this PRE by a metal 739 and It is coupled to the anode of false grid diode.

Fig. 6 l is shown in programmable resistance element (PRD) unit for being thermally isolated and making on matrix (such as SOI or polysilicon) 730 ' schematic diagrames.The thermal conductivity that matrix is thermally isolated is very poor, and programmable resistance element (PRE) can be shared with the grid of programming selector And still possess high programming efficiency.This element 730 ' has a PRE, and it includes a main body 731 ', anode 732 ' and cathodes 733 '. The main body 731 ' of PRE also be MOS grid, this MOS have active region 734 ', have by N+ implant 735 ' covering drain contact 737 ' drain electrode and have by P+ implant 736 ' cover source contact 738 ' source electrode.The cathode of this PRE is by a metal 739 ' And it is coupled to the source contact 738 ' of MOS.The operation of similar Fig. 6 g-j, can by conducting MOS source junction diode or The channel of transistor programs or reads this PRD unit 730 '.

PRD unit 730,730 ' is only illustrative purposes shown in Fig. 6 k and Fig. 6 l.It can be SOI or more that matrix, which is thermally isolated, Crystal silicon matrix.Active region can be silicon, germanium, SiGe, III V or II VI semiconductor material.PRE can be (including anti-for electrical fuse Fuse), phase transformation (PCM) film, magnetism penetrate interface (MTJ) film, resistive memory body (RRAM) film etc..PRE can be with figure Expansion area shown in radiating piece shown in 7a- Fig. 7 e, heating member shown in Fig. 7 f or Fig. 7 g- Fig. 7 i makes together.Programming choosing Selecting device can be diode or MOS.MOS selector can be programmed or be read by one channel MOS of conducting or a source junction It takes.The present invention can implement there are many grade schools and combination, all within the scope of the invention patent.

Fig. 7 a shows the top view of an electrical fuse element 88 ".This electrical fuse element 88 " uses thermally conductive but electrical isolation Radiating piece is to be coupled to anode.Resistive element 30a as shown in fig. 4 a for example can be used in this electrical fuse element 88 ".This electrical property Fuse element 88 " may include an anode 89 ", a cathode 80 ", a main body 81 ", a P+ implant layer 82 " and a N+ active region 83 ". It is to be coupled to anode 89 " via metal 84 " in the N+ active region 83 " of p-type matrix.In this embodiment, it N+ active region 83 " and leads Path electrical isolation (that is, N+/P diode is reverse biased), but pass to p-type matrix thermal conductivity as radiating piece.In other Embodiment, this radiating piece can be directly coupled to anode 89 " without other metals or interior connection.In other embodiments, this Radiating piece can also be couple to the main body of a fuse element, cathode and an anode fully or partially.The radiating piece of this embodiment can The sharply thermal gradient for accelerating programming is provided.In other embodiments, this main body can bend 45 degree 90 degree it is primary or repeatedly.

Fig. 7 b shows the electrical fuse element 88 ' of another embodiment " top view.This electrical fuse element 88 ' " and Fig. 7 a institute The person of showing is similar, but has the lower and close anode 89 " of a relatively thin oxide region 83 " ', as in main body 81 " ' ' radiating piece. Resistive element 30a as shown in fig. 4 a for example can be used in this electrical fuse element 88 ' ".This electrical fuse element 88 " ' may include One anode 89 " ', a cathode 80 " ', a main body 81 " ', a P+ implant layer 82 " ' and one are close to anode 89 " ' active region 83 " '. Active region 83 " ' position is in main body 81 " ' the lower oxide layer for making this region it is thin compared with other regions (such as thin gate oxide and The sti oxide of non-thickness).In the upper active region 83 " of oxide ' it can effectively radiate to provide the thermal gradient for accelerating programming.According to According to other embodiments, thin-oxide region 83 " ' can the main body of a fuse element, cathode and an anode fully or partially under Side, can accelerate to program as radiating piece.

Fig. 7 c shows 198 top view of electrical fuse element of another embodiment.Shown in this electrical fuse element 198 and Fig. 7 a Person is similar, but has a relatively thin oxide region 193, positioned at 199 two sides of anode to provide another form of radiating piece.This electrical property Resistive element 30a as shown in fig. 4 a for example can be used in fuse element 198.This electrical fuse element 198 may include an anode 199, the active region 193 of a cathode 190, a main body 191, a P+ implant layer 192 and one close to anode 199.Active region 193 exists The lower oxide layer for making this region of anode 199 it is thin compared with other regions (such as thin gate oxide rather than thickness STI oxidation Object).

Fig. 7 d shows the 198 ' top view of electrical fuse element of another embodiment.This electrical fuse element 198 ' and Fig. 7 a institute The person of showing is similar, but has a relatively thin oxide region 193 ', is bordering on 199 ' side of anode to provide another form of radiating piece.This Resistive element 30a as shown in fig. 4 a for example can be used in electrical fuse element 198 '.This electrical fuse element 198 ' may include one Anode 199 ', a cathode 190 ', a main body 191 ', a P+ implant layer 192' and one close to anode 199 ' active region 193 '.It is main Dynamic area 193 ' makes the oxide layer in this region thin compared with other regions (such as thin gate oxide rather than thickness close to anode 199 ' Sti oxide) and can rapidly radiate to provide the thermal gradient of speed programming.According to other embodiments, this thin-oxide area is close to The main body of one fuse element, the side of cathode or anode, two sides, three sides, four sides or any side are to accelerate to radiate.According to other Embodiment, it is possible to provide at least one is coupled to the substrate contact point of active region (such as active region 193 ') to avoid latch.It is connect in matrix Contact point column or metal on contact can be used as another radiating piece.

Fig. 7 e is the 198 " top view of electrical fuse element of another example, the electrical fuse element 198 " and Fig. 7 a those shown It is similar, but there is the radiating piece 195 " positioned at cathode.Resistance as shown in fig. 4 a for example can be used in this electrical fuse element 198 " Element 30a.This electrical fuse element 198 " may include a cathode 199 ", an anode 190 ", a main body 191 " and a radiating piece 195".According to other embodiments, this radiating piece can also only have one side rather than both sides suitably to cooperate junior unit space, and it is grown Degree can increase and decrease.According to other embodiments, this radiating piece can also be a part of anode main body on one side (or both sides). In another embodiment, minimum needed for the length-width ratio of radiating piece can be greater than 0.6 or be greater than design line width regular (design rule) Value.

Fig. 7 f is the 198 " ' top view of electrical fuse element of another example, shown in the electrical fuse element 198 " ' and Fig. 7 a Person is similar, but has the heating member 195 " for being bordering on cathode '.This electrical fuse element 198 " ' for example can be used as shown in fig. 4 a Resistive element 30a.This electrical fuse element 198 " ' may include an anode 199 " ', a cathode 190 " ', a main body 191 " ' and one High resistance area 195 " as heating member '.This high resistance area 195 " ' it can produce more heat to assist to program this fuse element.According to According to an embodiment, this heating member can be non-metal silication polysilicon or non-metal silication active region to there is high electrical resistance value.According to According to another embodiment, this heating member can be single or multiple contact point/guide hole concatenated with one another to increase resistance value, to program More heat are generated on path.Heating member 195 " ' cathode, anode, ontology of some or all of fuse element can be placed on Place.Active region 197 " ' have substrate contact point to avoid latch.In active region 197 " ' contact stud can also be used as radiating piece.

Fig. 7 g shows 298 top view of electrical fuse element of another embodiment.Shown in this electrical fuse element 298 and Fig. 7 a Person is similar, but with one in the expansion area of cathode.Resistive element 30a as shown in fig. 4 a can be used in this electrical fuse element 298. This electrical fuse element 298 may include a cathode 299, an anode 290, a main body 291 and an extending cathode area 295.According to another One embodiment, extending cathode area 295 can also be only on 291 one side of main body to be suitble to junior unit space, and its length can increase and decrease.More In the broadest sense, extending cathode area can be described as expansion area, that is, extending cathode area is one example of expansion area.According to another embodiment, Expansion area can be a part of anode main body on one side or both sides.According to another embodiment, the length-width ratio of expansion area is big In 0.6.This extension fauna is any to be longer than regular (design rule) desired zone of design line width, and be coupled to anode, cathode or It is that main body has smaller current or no electric current.

Fig. 7 h shows that the 298 ' top view of electrical fuse element of another embodiment, this electrical fuse element 298 ' have in yin The expansion area of pole part.This electrical fuse element 298 ' may include a cathode 299 ', an anode 290 ', a main body 291 '.This yin Pole 299 ' has close to the extending cathode area 295 ' on 291 ' one side of main body or both sides with auxiliary (that is, acceleration) programming.This extension Area 295 ' is the fuse element portions by extending out closest to cathode or positive contact point, and is longer than design line width rule (design rule) desired zone.290 ' the contact point 296' of anode of this electrical fuse element 298 ' also non-boundary, that is, contact Point width is greater than the fuse element width under it.According to another embodiment, cathode contacts point is also non-boundary, and/or anode portion Dividing also has expansion area.

Fig. 7 i shows the 298 " top view of electrical fuse element of another embodiment, this electrical fuse element 298 " may include one Cathode 299 ", an anode 290 ", a main body 291 ".This cathode 299 " has the expansion area 295 " close to 291 both sides of main body to add Speed programming.This expansion area 295 " be the fuse element portions to be extended out by cathode and an anode contact point and have smaller current or Length needed for not having electric current or its length to be longer than design line width regular (design rule).Expansion area 295 " is along current path Length-width ratio be greater than regular (design rule) desirable value of design line width, or 0.6 can be greater than.Anode 290 ' has one to share Contact point 296 ".This is located at by a metal 293 " and shares the upper of contact point 296 ", so that main body 291 ' and active region 297 " interconnect. According to an embodiment, this expansion area is close to the side of main body 291 ", and/or is connected to cathode or anode.According to another implementation Example, sun can have expansion area, and/or cathode can have shared contact point.

Radiating piece can provide the temperature gradient for accelerating programming, the radiating piece as shown in Fig. 7 a- Fig. 7 e is illustrative purposes.One dissipates Warmware can be the thin oxidation of the side, two sides, three sides, four sides or any side of neighbouring anode, main body or cathode, lower section or top Object area, to accelerate to radiate.Radiating piece can be an expansion area of the anode of fuse element, main body or cathode to accelerate to radiate.It dissipates Warmware can also be one or more conductors of the anode for being coupled to and (contact and be bordering on) fuse element, main body or cathode to accelerate Heat dissipation.Radiating piece can also be that the anode or cathode (having one or more contact point/guide holes) with large area are dissipated with acceleration Heat.Radiating piece can also be that the active region of fuse element close to cathode, main body or anode (also has at least on active region Contact stud) to accelerate to radiate.OTP unit with shared contact point (that is, connects mos gate pole and active region single with metal Contact interconnection) it also can be considered radiating piece embodiment for mos gate pole, so that heat effectively spills into active region.

The expansion area as shown in Fig. 7 g- Fig. 7 i is by fuse element from contact point or the part that extends out of guide hole, this portion Regular (design rule) desirable value of design line width can be longer than and be reduced or do not flow through electric current by dividing, and accelerate programming whereby. One expansion area (such as 45 degree or 90 degree of bending and may include multiple components) can be in fuse element anode, main body or cathode one Side, two sides, three sides or four sides or any side.One expansion area can also be the radiating piece of auxiliary heat dissipation.It can be very although implementing structure Approximation, radiating piece and extension fauna are based on different physical mechanisms to accelerate to program.One expansion area can be used as radiating piece, but radiate Part is not necessarily expansion area.The embodiment of the present invention can individually or combination is implemented.

20% to 200% can be increased because of radiating piece in the thermal conductivity (that is, heat loss) of section Example, a fuse element. Identical, a heating member can increase more heat with the programming of auxiliary fuse element.One heating member (such as element 195 " of Fig. 7 f ') usually Be position or be bordering on fuse element part (or all) cathode, main body or anode high resistance area to generate more heat. One heating member can by one or more non-metal silication polysilicons, non-metal silication active region, one or more contact points or guide hole or It connects and realizes in a combination thereof, or one or more high resistance in program path.The resistance value of heater can be 8 Ω to 200 Ω； In some embodiments can be 20 Ω to 100 Ω.

It can be by polysilicon, metal silication polysilicon, metal silication with radiating piece, heating member or the fuse of expansion area element Object, metal, metal alloy, metal gates, connection, level 0 metal (metal0) in part, is thermally isolated actively polycrystalline silicon metal The production such as area or CMOS gate.Furthermore there are many various combination and can still change to provide the radiating piece that can be radiated, can produce The heating member of heat and the expansion area for assisting programming, these combinations and variation are all within the scope of the present invention.

Fig. 7 j shows the top view of the electrical fuse element 98 ' according to another embodiment.This electrical fuse element 98 ' and figure 7a those shown's class is shown, in addition to having an at least recess with aided programming in main body.By and large, a target part of this main body 91 ' There can be smaller area (such as relatively thin) when formation, to form recess.This electrical fuse element 98 ' for example can be used for shown in Fig. 4 a Resistive element 30a.This electrical fuse element 98 ' includes an anode 99 ', a cathode 90 ' and a main body 91 '.This main body 91 ' packet Containing an at least recess 95 ' be broken this fuse element can easily in programming.

Fig. 7 k shows the top view of the electrical fuse element 98 " according to another embodiment.This electrical fuse element 98 " and figure 7a those shown's class is shown, in addition to this fuse element is part NMOS metal gates and part PMOS metal gates.This electrical fuse member Element 98 " for example can be used for resistive element 30a shown in Fig. 4 a.This electrical fuse element 98 " includes an anode 99 ", a cathode 90 " And the main body 91 " and 93 " made respectively by PMOS metal gates and NMOS metal gates.It is used in identical fuse element different Type of metal, the heating in programming can produce the thermal expansion with big stress, rupture this fuse whereby.

The only declaratives embodiment of the OTP element as shown in Fig. 7 a- Fig. 7 k.As previously mentioned, this OTP element can be by any interior Connection production, connection is including but not limited to connection, polycrystalline in polysilicon, metal silication polysilicon, metal silicide, part in this Metal, metal alloy, metal gates, active region or CMOS gate or combinations of the above is thermally isolated in silicon metal.Polysilicon gold Category is metal-metal nitride-polysilicon (that is, W/WNx/Si) interlayer structure, can be used for reducing the resistance of polysilicon Value.OTP element can be N-type, p-type or part N and part p-type.Every OTP element has an anode, a cathode and at least one Main body.For connecting metal fuse in polysilicon/polycrystalline silicon metal/part, the contact point number of anode or cathode can be no more than Two；For metal fuse, the contact point number of anode or cathode can be no more than four.

It can be only one in the contact point number of other embodiments, anode or cathode.OTP memory can be greater than by contacting spot size At least one contact spot size outside volume array.Contact point periphery is smaller than at least one contact point outside OTP memory array Periphery.In other embodiments, periphery can be negative value, that is, contact point is wide compared with the contact area under it, this is so-called non-boundary Contact point.The length-width ratio of main body can be 0.5-8, or in some embodiments can be 2-6 (connection in polysilicon/part/polysilicon gold Category/metal gates main body) or be 10 or 10 or more (metal masters).In addition to above-mentioned example, the scope of the present invention also includes above-mentioned The combination of example and part.

It can also be used in high-dielectric coefficient/metal gates CMOS technology as the polysilicon for defining CMOS gate and interior connection Make OTP element.OTP element can be p-type, N-type or part N and part p-type.For the fuse member with P+ type and the doping of N+ type Element, the resistance ratio for programming front and back can be elevated to establish a diode after programming, this fuse element such as polysilicon, polysilicon gold Belong to, active region or high-dielectric coefficient/metal gates CMOS metal gates are thermally isolated.If metal gates CMOS has Polysilicon interlayer structure between metal alloy layer, metal alloy layer can be operated by the light shield that layout data bank generates in fuse A diode is generated in element.In SOI or similar SOI technology, active region foundation can be thermally isolated in a fuse element certainly, so that molten Silk element can be in the every one end of active region by implant P+ type, N+ type or part N+ and part P+ type impurity.If a fuse element System be part N+ and part P+ type impurity, this fuse characteristic of elements similar to reverse biased diode, such as the metal at top Silicide is because vague and general after programming.In one embodiment, if without metal silicide, OTP element at the top of active region It can also be established from the isolation active region that part N+ and part P+ type are adulterated, characteristic is similar in the collapse of positive or reverse biased Diode.If this OTP element can be in single active island area and programming selection two using isolation active region to establish OTP element Pole pipe merges to reduce using area.

For can provide the technology connected in part, connection can do OTP element fully or partially in part.Office In portion connect, also referred to as level 0 (M0) is a kind of byproduct generated in metal silicide technology, and can by polysilicon (or It is mos gate pole) and active region direct interconnection.In the advanced technologies for surmounting 28nm, along silicon face scaling progress far beyond along Short transverse is come fastly.Therefore the length-width ratio (gate height and passage length ratio) of CMOS gate becomes high, causes in metal 1 And the contact point cost of manufacture between source/drain or CMOS gate gets higher and (such as considers element area and cost).Connect in part Connect in the centre that can be used as source/drain and CMOS gate in the centre of connection, CMOS gate and metal 1 connection or source electrode/ Drain electrode connects in the centre of one or two layers with metal 1.According to an embodiment, the interior connection in part, CMOS gate or its group Conjunction can be used as OTP element.According to another embodiment, OTP element and the one end for programming selector can be straight via connection in part It connects in succession and (is not required to any contact point), to save area.Therefore, level 0 can be used for connecting source/drain, to pad metal gate Extremely identical height, so that metal 1 connects level 0 and metal gates.

Above-mentioned narration known to those skilled in the art is only illustrative example, and the present invention still includes different variations and equivalent way, with Electrical fuse, antifuse element or programming selector are made in CMOS technology.

Fig. 8 a and Fig. 8 b show P+/N trap diode and fuse element made by different isolation embodiments respectively.If nothing Isolation, P+ and N+ active region can be short-circuit due to the metal silicide grown up above.Unit one to four while or it is any while can By STI, false CMOS gate, SBL or combinations thereof to provide isolation.P+ and N+ active region as diode P and N-terminal is CMOS The source electrode of element and drain electrode.P+ and N+ active region is all located at N trap, this N trap is to enter the N trap of PMOS in standard CMOS process down. To simplify explanation, Fig. 8 a and Fig. 7 b, which are shown in a P+ active region, only has a N+ active region, so in the diode N+ master of most traps Dynamic area can share.

Top view of Fig. 8 a display according to an electrical fuse unit 70 of an embodiment, this electrical fuse unit 70 have one P+/N trap diode and abutting contact point.The active region 73 and 74 being isolated by STI 79 is implanted by P+ implant layer 77 and N+ respectively Layer (complementation of P+ implant layer 77) covering, to form the P and N-terminal of diode 70.Active region 73 and 74 is all located at a N trap 75, this N Trap is the trap that down enters PMOS in standard CMOS process.One fuse element 72 is via a metal 76 (in single contact point 71) It is coupled to P+ active region 73.There were significant differences with conventional contacts point for this contact point 71, and a contact point can be connected via a metal Fuse element and another tie point then connects this metal via P+ active region.By a fuse element via in single contact point A metal and be directly connected to an active region, cellar area can be greatly reduced.Abutting contact point can be greater than general contact point, and It can be for a square contact point and with square contact twice of area of point of about general CMOS technology.The fuse element of the present embodiment can By a CMOS gate (comprising being connected in polysilicon, metal silication polysilicon, polycrystalline silicon metal, part or non-aluminum metal CMOS Grid) it is made, to provide abutting contact point.

Top view of Fig. 8 b display according to an electrical fuse unit 70 " of an embodiment, this electrical fuse unit 70 " have One false mos gate pole 78 " using in N trap as the isolation of P+ and N+ (as diode both ends), and with an electrical fuse element 72".One active region 71 " is divided into upper active region 73 " and lower active region 74 " by a false mos gate pole 78 ".Upper 73 " Ji Xiazhu of active region Dynamic area 74 " is covered by P+ implant layer 77 " and N+ implant layer (complementation of P+ implant layer 77 ") respectively.In unit 70 ", master on this Dynamic area 73 " and lower active region 74 " constitute the both ends of diode.False mos gate pole (a such as polysilicon) 78 " provides the two of unit 70 " The area pole pipe P+/N+ is isolated and can have a fixed-bias transistor circuit or be coupled to the cathode of diode.This polysilicon 78 " is one in standard The false mos gate pole of CMOS technology, and can be a metal gates in advanced metal gates CMOS technology.The width of false mos gate pole It is close to the minimum grid width of CMOS technology.According to an embodiment, CMOS technology of the width less than twice of false mos gate pole is most Small grid width.False mos gate pole can also be made by I/O element to bear high voltage.Active region 71 " is located at a N trap 75 ", this N Trap is the trap that down enters PMOS in standard CMOS process.One fuse element 72 " is coupled to P+ master via a metal 76 " at one end Dynamic area 73 " (via contact point 75 " -2 and 75 " -3), is coupled to a high voltage source line V+ (via contact point 75 "-in the other end 1).The region N+ 74 " is coupled to a low-voltage source line V- via contact point 75-4 ".One embodiment of foundation, contact point 75 " -1,2,3, At least one in 4 is greater than the contact point outside memory array, to reduce resistance value.When high and low-voltage be applied separately to V+ and V- has electric current that can flow through this fuse element 72 " to be programmed in high resistance state.

Fig. 9 is the processor system 700 of an example.Processor system 700 is included in the one of memory body 740 in one example Programmable resistance element 744 (such as in cell array 742).Processor system 700 for example can be computer system.Electricity Brain system contains central processing unit 710, is communicated by a common busbar connector 715, including various memory bodys and periphery Equipment (such as I/O 720, hard disk 730, CDROM750, memory body 740 and other memory bodys 760) communication.Other memory bodys 760 be conventional memory body, for example SRAM, DRAM, flash memory, is connected to CPU 710 typically via note body body controller. CPU 710 be usually a microprocessor, a digital signal processor or other can program editing digital logic element.Memory Body 740 is realized preferably with IC regime, contains the memory array at least one programmable resistance element 744 742.Memory body 740 can generally be connected to CPU 710 by memory controller interface.If desired, memory body 740 can be with place Reason device (for example CPU 710) is incorporated in a single integrated circuit.

The present invention can be in the fully or partially realization of a printed circuit board or the integrated circuit in a system.It can compile Journey resistive element can be fuse, antifuse or new non-volatility memory.Fuse can be the polycrystalline of silication or non-silicidated Silicon fuse, be thermally isolated active region fuse, connect in part fuse, metal fuse, contact point fuse, interlayer contact fuse or The fuse made by CMOS gate.Antifuse can collapse antifuse for gate oxide, have dielectric medium contact point therebetween or It is interlayer contact antifuse.New non-volatility memory can be Magnetic Memory body (MRAM), conducting bridge random access memory (CBRAM) or resistive random access memory body (RRAM).Although programming mechanism is different, its logic state is not all by It is defined with resistance value.

Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention Shape all should fall within the scope of protection of the appended claims of the present invention.

Claims (35)

1. a kind of single programmable memory body, characterized by comprising:

Multiple single programmable units, at least a single programmable unit include at least:

One single programmable element includes an at least electrical fuse, which is coupled to a first voltage source line；And

One programming selector is coupled to the single programmable element and a second voltage source line,

Wherein (1) at least electrical fuse it is at least a part of have an at least expansion area, the expansion area have decrement electric current or It is that no electric current flows through, or (2) at least electrical fuse includes a radiating piece；And

Wherein the single programmable element can be selected by applying voltages to first and second voltage source line and the programming being connected Device and program, the single programmable element is changed to Different Logic state whereby.

2. single programmable memory body according to claim 1, which is characterized in that the electrical fuse is by polysilicon, metal Silicide, metal silication polysilicon, CMOS metal grid, connection in metal, polycrystalline silicon metal, connection in part, metal alloy, Or at least one in active region is thermally isolated and is made.

3. single programmable memory body according to claim 1, which is characterized in that the expansion area along current path length Width is than being greater than design line width rule desirable value.

4. single programmable memory body according to claim 1, which is characterized in that the expansion area has at least one 45 degree Or 90 degree of bendings.

5. single programmable memory body according to claim 1, which is characterized in that the electrical fuse has both ends, and should Electrical fuse two of both ends closest to the length-width ratio between contact point be 2 to 8.

6. single programmable memory body according to claim 1, which is characterized in that the electrical fuse only has at least one end One contact point.

7. single programmable memory body according to claim 1, which is characterized in that the electrical fuse has at least one end No more than two contact points.

8. single programmable memory body according to claim 1, which is characterized in that at least a single programmable unit is for this A part of one single programmable memory array, wherein the electrical fuse or the programming selector have an at least contact point, The contact point area is greater than at least contact point area outside the single programmable memory array.

9. single programmable memory body according to claim 1, which is characterized in that at least a single programmable unit is for this A part of one single programmable memory array, wherein the electrical fuse or the programming selector have outside an at least contact point It encloses, which is less than at least contact point periphery area outside the single programmable memory array.

10. single programmable memory body according to claim 1, which is characterized in that the electrical fuse at least one end is extremely A few contact point width is identical as fuse widths value or is greater than fuse widths value.

11. single programmable memory body according to claim 1, which is characterized in that an at least single programmable unit With an at least active region adjacent to the electrical fuse, or at least a substrate contact point is built on the active region.

12. single programmable memory body according to claim 1, which is characterized in that the programming selector includes at least one Diode or a MOS element, the MOS element can be connected via channel or source/drain junction.

13. single programmable memory body according to claim 1, which is characterized in that the programming selector builds on a heat It is isolated in matrix or a three-dimensional aliform structure.

14. single programmable memory body according to claim 1, which is characterized in that the programming selector has at least one Active region is isolated into one first active region and one second active region by a mos gate pole, which mixes with the first kind Miscellaneous, which there is the first kind or Second Type to adulterate, which is all located at a common CMOS In trap or on an isolation matrix, which is coupled to single programmable element, and the second active region is coupled to second Voltage source line and the mos gate pole are coupled to tertiary voltage source line, which can be by application voltage to first voltage source Line, the second voltage source line and/or tertiary voltage source line are connected.

15. single programmable memory body according to claim 14, which is characterized in that the single programmable memory body includes The programming selector, and/or the single programmable unit that isolation is adjacent is isolated in an at least shallow trench isolation, the shallow trench isolation.

16. single programmable memory body according to claim 14, which is characterized in that the single programmable memory body includes The active region of the programming selector, or the single programmable unit that isolation is adjacent is isolated in an at least CMOS gate, the CMOS gate.

17. single programmable memory body according to claim 1, which is characterized in that a part of grid of the programming selector Pole oxidated layer thickness is greater than the thickness of grid oxide layer of core element.

18. a kind of electronic system, characterized by comprising:

An at least processor；And

One single programmable memory operation is connected to the processor, which includes:

Multiple single programmable units, at least a single programmable unit include:

One single programmable element includes an at least electrical fuse, which is coupled to a first voltage source line； And

One programming selector is coupled to the single programmable element and a second voltage source line,

Wherein (1) at least electrical fuse it is at least a part of have an at least expansion area, the expansion area have decrement electric current or It is that no electric current flows through；Or (2) at least electrical fuse includes a radiating piece；And

Wherein the single programmable element is by applying voltages to first and second voltage source line and the programming selector is connected And program, the single programmable element is changed to Different Logic state whereby.

19. electronic system according to claim 18, which is characterized in that the programming selector include an at least diode or One MOS element, the MOS element can be connected via channel or source/drain junction.

20. electronic system according to claim 18, which is characterized in that the electrical fuse by polysilicon, metal silicide, Metal silication polysilicon, CMOS metal grid, connection in metal, polycrystalline silicon metal, in part connection, metal alloy or heat every It is made from least one in active region.

21. a kind of operation single programmable memory body method, characterized by comprising:

Multiple single programmable units are provided, an at least single programmable unit includes that (i) single programmable element includes extremely A few electrical fuse, the electrical fuse are coupled to a first voltage source line；(ii) a programming selector, which is coupled to the single, to compile Cheng Yuansu and a second voltage source line, wherein (1) at least electrical fuse is at least a part of to have an at least expansion area, it should There is decrement electric current in expansion area or flows through without electric current；Or (2) at least electrical fuse includes a radiating piece；And

By applying voltages to first and second voltage source line and the programming selector be connected and single programs multiple single At least one unit of programmable unit is to Different Logic state.

22. operation single programmable according to claim 21 remembers body method, which is characterized in that the programming selector packet Containing an at least diode or a MOS element, which can be connected via channel or source/drain junction.

23. operation single programmable according to claim 21 remembers body method, which is characterized in that the electrical fuse is by more Crystal silicon, metal silicide, metal silication polysilicon, CMOS metal grid, connection in metal, polycrystalline silicon metal, connection in part, Metal alloy is thermally isolated at least one in active region and is made.

24. a kind of programming single programmable memory body method, characterized by comprising:

Multiple single programmable units are provided, an at least single programmable unit includes that (i) single programmable element includes extremely A few electrical fuse, the electrical fuse are coupled to a first voltage source line；(ii) a programming selector, which is coupled to the single, to compile Cheng Yuansu and a second voltage source line；And

It is extremely somebody's turn to do by the program voltage being made of multiple voltage pulses or the program current being made of multiple current impulses is applied First and second voltage source line and the programming selector is connected and gradually changes fuse resistor, and then single programs multiple single At least one unit of programmable unit is to Different Logic state；

Wherein (1) at least electrical fuse it is at least a part of have an at least expansion area, the expansion area have decrement electric current or It is that no electric current flows through, or (2) at least electrical fuse includes a radiating piece.

25. programming single programmable according to claim 24 remembers body method, which is characterized in that single programming is multiple The step of at least one unit of single programmable unit, includes:

(a) a destructive program current is obtained, it is sharply electric that this destructive program current has an at least single programmable unit Resistive；And

(b) program current being made of multiple current impulses is limited lower than the destructiveness program current.

26. programming single programmable according to claim 24 remembers body method, which is characterized in that single programming is multiple The step of at least one unit of single programmable unit, includes:

(a) using a part of a low program voltage starting programming single programmable memory body, gradually increase program voltage until All single programmable units of the single programmable memory body are programmed and confirm correctly, are determined under a program voltage whereby Limit；And

(b) continue to increase program voltage to program the single programmable memory body until an excess voltage is identified, in this Under excess voltage applies, regardless of whether an at least single programmable unit for the single programmable memory body is in the shape of programming Under condition, at least a single programmable unit has been identified failure for this, this excess voltage is a program voltage upper limit.

27. programming single programmable according to claim 26 remembers body method, which is characterized in that single programming is multiple The step of at least one unit of single programmable unit is to be applied between the program voltage upper limit and lower limit in a pulsed fashion Voltage carries out.

28. programming single programmable according to claim 24 remembers body method, which is characterized in that the programming selector is One diode, the diode have a false grid with isolating diode first end and second end or the programming selector for a MOS Element, the MOS element can be connected by channel or source/drain junction.

29. programming single programmable according to claim 24 remembers body method, which is characterized in that the programming selects utensil There is an at least active region to be isolated into one first active region and one second active region by a mos gate pole, which has the There is the first kind or Second Type to adulterate for the doping of one type, second active region, which is all located at one In common CMOS trap or on an isolation matrix, which is coupled to single programmable element, the second active region coupling It is connected to the second voltage source line, which is coupled to tertiary voltage source line, which can be by application voltage to the first electricity Potential source line, the second voltage source line and/or tertiary voltage source line are connected.

30. programming single programmable according to claim 24 remembers body method, which is characterized in that the programming selector is built One is stood on to be thermally isolated in matrix or a three-dimensional aliform structure.

31. programming single programmable according to claim 24 remembers body method, which is characterized in that the electrical fuse more wraps Containing a heating member.

32. programming single programmable according to claim 24 remembers body method, which is characterized in that the electrical fuse is by more Crystal silicon, metal silicide, metal silication polysilicon, CMOS metal grid, connection in metal, polycrystalline silicon metal, connection in part, Metal alloy is thermally isolated at least one in active region and is made.

33. a kind of programmable resistance element memory body, characterized by comprising:

Multiple programmable resistance cells, at least a programmable resistance cell include:

An at least programmable resistance element is coupled to a first voltage source line, and at least one programming selector, this at least one can be compiled Journey resistive element is an at least electrical fuse；

There is the programming selector an at least active region to be isolated into one first active region and one second active region by a mos gate pole, First active region is adulterated with the first kind, which there is the first kind or Second Type to adulterate, this first and Second active region is all located in a common CMOS trap or on an isolation matrix, which is coupled to first voltage source Line, the second active region are coupled to the second voltage source line, which is coupled to tertiary voltage source line, which can be by Apply voltage to be connected to first voltage source line, the second voltage source line and/or tertiary voltage source line；

Wherein via applying voltages to first, second and third voltage source line, or via applying voltages to this first and second Voltage source line, the channel of source junction diode or MOS that MOS can be connected are patrolled with programming programmable resistance element to the difference The state of collecting；

Wherein (1) at least electrical fuse it is at least a part of have an at least expansion area, the expansion area have decrement electric current or It is that no electric current flows through；Or (2) at least electrical fuse includes a radiating piece.

34. programmable resistance element memory body according to claim 33, which is characterized in that the programmable resistance element can (a) via applying voltages to first, second and third voltage source line, or via applying voltages to first and second voltage source The source junction diode of MOS can be connected to program the programmable resistance element to a Different Logic state in line；Or (b) via The channel for applying voltages to first, second and third voltage source line conducting MOS is patrolled with reading the programmable resistance element as one The state of collecting.

35. programmable resistance element memory body according to claim 33, which is characterized in that the programmable resistance element can (a) via applying voltages to first, second and third voltage source line, or via applying voltages to first and second voltage source The source junction diode of MOS can be connected to change the programmable resistance element to a kind of logic state in line；Or (b) via applying Power-up is depressed into the channel of first, second and third voltage source line conducting MOS to change the programmable resistance element as another kind Logic state.