TW201517215A - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

The present invention provides a method for manufacturing semiconductor package, including placing a plurality of semiconductor elements respectively on a plurality of accommodating slots of a support plate, then installing a medium plate having a plurality of conductive through holes on the support plate, and making the conductive through holes electrically connect to the semiconductor elements, therefore the fabrication time can be shortened, and manufacturing yield can be increased. Further, the present invention includes the semiconductor package.

Description

Semiconductor package and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor package and, more particularly, to a semiconductor package that is advantageous for mass production and a method of fabricating the same.

Nowadays, with the advancement of technology, electronic products manufacturers have developed a variety of different types of semiconductor packages. At present, the size of semiconductor wafers tends to be miniaturized. Therefore, it is necessary to continuously improve and overcome the process technology of semiconductor packages. It is matched with miniaturized semiconductor wafers and conforms to the trend of light and thin modern technology products.

In the flip chip packaging process, since the thermal expansion coefficients of the wafer and the package substrate are very different, the bumps on the periphery of the wafer cannot form a good bond with the corresponding contacts on the package substrate, so that the bumps are easily peeled off from the package substrate. On the other hand, as the degree of integration of the integrated circuit increases, the thermal stress and warpage caused by the mismatch of the thermal expansion coefficient between the wafer and the package substrate It is also becoming more serious, and as a result, the reliability between the wafer and the package substrate is lowered, and the reliability test fails.

In order to solve the above problems, we have developed a semiconductor substrate as an intermediary. The structure of the three-dimensional integrated circuit (3D-IC) process is to add a silicon interposer between a package substrate and a semiconductor wafer. Since the germanium interposer is close to the material of the semiconductor wafer, the problem caused by the mismatch of the thermal expansion coefficients can be effectively avoided.

The three-dimensional integrated circuit is a high-order packaging technology that connects a single wafer to the interposer by soldering or by soldering the interposer by Chip On Wafer On Substrate technology.

1A to 1F are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package 1.

As shown in FIG. 1A, a carrier 10 having an adhesive layer 11 is provided.

As shown in FIG. 1B, an interposer 12 is provided having an opposite crystallizing side 12a and an interposing side 12b, and a plurality of conductive vias 120 communicating with the interposing side 12a and the interposing side 12b, and the interposing side 12b The first conductive element 13 is electrically connected to the conductive via 120. The interposer 12 is bonded to the adhesive layer 11 of the carrier 10 with the intermediate side 12b, so that the first conductive elements 13 are embedded in the adhesive layer 11.

As shown in FIG. 1C, the plurality of semiconductor elements 14 are flip-chip bonded to the seed side 12a of the interposer 12 by a plurality of second conductive elements 15 by soldering.

As shown in FIG. 1D, a primer 16 is formed on the crystallizing side 12a by dispensing to cover the second conductive members 15.

As shown in FIG. 1E, the carrier 10 and the adhesive layer 11 are removed to expose the first conductive elements 13.

As shown in Fig. 1F, along the cutting path S as shown in Fig. 1E The single process is performed to obtain a plurality of semiconductor packages 1.

In the subsequent process, as shown in FIG. 1G, the semiconductor package 1 is disposed on a package substrate 9 by the first conductive elements 13.

However, in the method of fabricating the conventional semiconductor package 1, when the plurality of semiconductor elements 14 are combined, the semiconductor elements 14 need to be soldered one by one, and heating is required at each of the semiconductor elements 14 (for example, 5 to Each semiconductor element 14 can be bonded to the interposer 12 after 10 minutes of heating time, so that it takes a lot of time to complete the arrangement of the semiconductor elements 14, resulting in a very low unit per hour (UPH). Increase the cost of the process.

Therefore, how to solve the lack of the prior art is a technical problem that is currently being solved by all walks of life.

In order to solve the problems of the above-mentioned prior art, the present invention discloses a semiconductor package comprising: a carrier board having at least one receiving groove; a semiconductor component disposed in the receiving groove; and an interposer The interposer is disposed on the carrier and the semiconductor device, and the interposer has a plurality of conductive vias electrically connected to the semiconductor device.

In the above semiconductor package, an insulating layer is formed between the interposer and the carrier, and between the interposer and the semiconductor element. For example, the side of the interposer, the side of the insulating layer, and the side of the carrier are flush.

In the above semiconductor package, the side of the interposer and the side of the carrier are flush.

The present invention further provides a method of fabricating a semiconductor package, comprising: providing a carrier having at least one receiving trench; placing a semiconductor component in the receiving recess; and disposing an interposer having a plurality of conductive vias on the carrier The conductive vias are electrically connected to the semiconductor component.

In the above method, the interposer is disposed on the carrier by a pressing process. For example, the pressing process is to bond the interposer and the carrier by an insulating layer, and heat the insulating layer to make the intermediary. The board bonds the semiconductor element by the insulating layer.

For example, the insulating layer is formed on the semiconductor element before the interposer is disposed on the carrier, and a plurality of conductive elements are formed on the interposer, so that after the interposer is disposed on the carrier, the The insulating layer covers the conductive elements, and electrically connects the conductive elements to the conductive elements.

Or forming a plurality of conductive elements and the insulating layer on the semiconductor element, so that the insulating layer covers the conductive elements, and after the interposer is disposed on the carrier, the conductive elements are electrically connected to the conductive materials. Perforating the semiconductor component.

Or forming a plurality of conductive elements and the insulating layer on the interposer, so that the insulating layer covers the conductive elements, and after the interposer is disposed on the carrier, the conductive elements are electrically connected to the conductive materials. Perforating the semiconductor component.

Or forming a plurality of conductive elements on the semiconductor element, and forming the insulating layer on the interposer, so that after the interposer is disposed on the carrier, the insulating layer covers the conductive elements, and the Conductive component electrical The conductive vias are connected to the semiconductor component.

In the above method, the singulation process is performed after the interposer is disposed on the carrier.

In the above semiconductor package and the method of manufacturing the same, the material of the carrier is made of an organic material or an inorganic material.

In the foregoing semiconductor package and method of fabricating the same, the interposer has a line redistribution structure electrically connected to the conductive via.

In addition, in the foregoing semiconductor package and the manufacturing method thereof, before the interposer is disposed on the carrier, a plurality of conductive elements are formed on the interposer or the semiconductor element, so that the interposer is disposed on the carrier Afterwards, the conductive elements are electrically connected to the conductive vias and the semiconductor component.

As can be seen from the above, the semiconductor package of the present invention and the method of manufacturing the same, by mounting a plurality of semiconductor elements in a receiving groove of the carrier, and bonding the interposer to the carrier, to complete the semiconductor device and the Since the combination of the interposer, the present invention can greatly shorten the completion time of setting the semiconductor elements compared to the conventional techniques of soldering the semiconductor elements one by one, thereby increasing the throughput and reducing the cost of the process.

1,2,2',2",3,3',3"‧‧‧ semiconductor packages

10,20‧‧‧ Carrier Board

11‧‧‧Adhesive layer

12,22‧‧‧Intermediary board

12a, 22a‧‧ ‧ crystallized side

12b, 22b‧‧‧Intermediate side

120,220‧‧‧Electrical perforation

13‧‧‧First conductive element

14,24‧‧‧Semiconductor components

15‧‧‧Second conductive element

16,90‧‧‧Bottom

20a‧‧‧ surface

20c, 22c, 26c‧‧‧ side

202‧‧‧ accommodating slots

204‧‧‧ openings

206‧‧‧ bottom

21‧‧‧Line redistribution structure

23,25‧‧‧Conductive components

24a‧‧‧Action surface

24b‧‧‧Non-active surface

240‧‧‧electrode pads

26‧‧‧Insulation

34‧‧‧ Temporary joints

340‧‧‧bonding layer

9‧‧‧Package substrate

S, S’‧‧‧ cutting path

1A to 1F are schematic cross-sectional views showing the fabrication and application of a conventional semiconductor package; FIG. 1G is a schematic cross-sectional view showing the application of a conventional semiconductor package; and FIGS. 2A to 2H are a method of fabricating the semiconductor package of the present invention. A schematic cross-sectional view; wherein the 2C' diagram is another embodiment of the 2C diagram, 2D' And the 2D" diagram is another embodiment of the 2D diagram, the 2G' diagram is another embodiment of the 2G diagram, and the 2E' diagram is another embodiment of the 2E diagram, 2H' and 2H" The drawings are other embodiments of the 2Hth diagram; the 3rd, 3' and 3" diagrams are another embodiment of the 2H, 2H' and 2H" diagrams; and the 4th, 4' and 4" diagrams are the invention. A schematic cross-sectional view of the application of the semiconductor package.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "side", "one" and "bottom" are used to describe the scope of the invention, and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

2A to 2H are schematic cross-sectional views showing an embodiment of a method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a plurality of accommodating grooves 202 are formed on the surface 20a of a carrier 20 by etching, and the accommodating grooves 202 have a bottom surface 206 and an opening 204 communicating with the surface 20a of the carrier 20.

In this embodiment, the carrier 20 can be selectively designed with a circuit layer (not shown), and the carrier 20 is made of an inorganic material, such as a semiconductor material, and can contain germanium (such as SiC, SiO ₂ , glass). ), gallium arsenide (GaAs), gallium arsenide-phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenic (GaAlAs), indium gallium phosphide (InGaP), etc.; or, the carrier 20 may be made of an organic material. Such as glass fiber reinforced (bismaleimide-triazine, BT) resin, FR-4 fiberglass reinforced epoxy resign, or epoxy resin (Epoxy).

As shown in FIG. 2B, a semiconductor element 24 is placed in the corresponding accommodating groove 202, respectively.

In this embodiment, the semiconductor device 24 has an opposite active surface 24a and a non-active surface 24b. The active surface 24a has a plurality of electrode pads 240, and the semiconductor component 24 is coupled to the receiving portion by its non-active surface 24b. The bottom surface 206 of the groove 202 is such that the action surface 24a faces the opening 204 of the accommodating grooves 202.

Furthermore, the active surface 24a may be flush with the surface 20a of the carrier 20; alternatively, the active surface 24a may be higher or lower than the surface 20a of the carrier 20.

Moreover, the semiconductor element 24 and the sidewall of the accommodating groove 202 may have a small gap (not shown).

As shown in FIG. 2C, an insulating layer 26 is formed on the surface of the carrier 20 20a is on the active surface 24a of the semiconductor elements 24.

In this embodiment, the insulating layer 26 is a non-conductive film (NCF), for example, an anisotropic conductive paste (ACP), an anisotropic conductive film (Anisotropic Conductive Film, ACF).

As shown in FIGS. 2D and 2E, an interposer 22 is disposed on the insulating layer 26, and the interposer 22 is electrically connected to the semiconductor device 24.

In this embodiment, the interposer 22 is a slab having an opposite crystallizing side 22a and an intermediate side 22b, and a plurality of conductive vias 220 communicating with the interposing side 22a and the interposing side 22b, and by pressing The interposer 22 is disposed on the insulating layer 26.

In addition, a plurality of conductive elements 25 may be formed on the crystallizing side 22a of the interposer 22 to embed the interposer 22 on the insulating layer 26, and the conductive elements 25 are embedded in the insulating layer 26, The conductive vias 220 are electrically connected to the electrode pads 240 of the semiconductor device 24 by the conductive elements 25 .

Alternatively, as shown in FIG. 2C', a plurality of conductive elements 25 may be formed on the electrode pads 240 of the semiconductor device 24 to form the insulating layer 26 on the surface 20a of the carrier 20 and the semiconductor elements 24. The insulating layer 26 covers the conductive elements 25 when the surface 24a is applied. Then, the structure shown in FIG. 2C is pressed onto the interposer 22 by the insulating layer 26 to form a structure as shown in FIG. 2E, so that the electrode pads 240 of the semiconductor device 24 are used. The conductive element 25 is electrically connected to the conductive via 220.

In another embodiment, as shown in FIG. 2D', the plurality of conductive elements can be The member 25 and the insulating layer 26 are both formed on the crystallizing side 22a of the interposer 22, and the carrier 20 and the interposer 22 are combined; or, as shown in FIG. 2D, a plurality of conductive elements 25 may be formed. The insulating layer 26 is formed on the electrode side 22a of the interposer 22 on the electrode pad 240 of the semiconductor device 24, and the carrier 20 and the interposer 22 are bonded.

Further, a plurality of conductive elements 23 may be formed on the intermediate side 22b of the interposer 22.

In addition, a temporary bonding member 34 can be bonded to the intermediate side 22b of the interposer 22 by a bonding layer 340 (such as a release film), so that the conductive member 23 on the interposing side 22b is embedded in the bonding layer 340. The conductive element 23 on the intermediate side 22b is protected.

As shown in FIG. 2E, after the press-bonding process is completed, the insulating layer 26 is heated so that the interposer 22 can bond the semiconductor element 24 and the carrier 20 by the insulating layer 26.

In another embodiment, as shown in FIG. 2E', the insulating layer 26 may not be formed, but a plurality of conductive elements 25 are formed on the interposer 22 or the semiconductor element 24 to bond the conductive elements 25 The interposer 22 and the carrier 20 are electrically connected to the conductive vias 220 and the semiconductor component 24.

As shown in FIG. 2F, the temporary bonding member 34 and the bonding layer 340 are removed by ultraviolet light (UV) or laser light to expose the conductive elements 23.

As shown in FIGS. 2G and 2H, a singulation process is performed along the dicing path S to obtain a plurality of semiconductor packages 2 having a plurality of semiconductor elements 24.

In this embodiment, the cutting method is a knife cutting or a laser cutting. But not limited to this.

Furthermore, the side surface 22c of the interposer 22, the side surface 26c of the insulating layer 26, and the side surface 20c of the carrier board 20 are flush.

In another embodiment, as shown in FIG. 2G′, when the interposer 22 is provided, the crystallizing side 22a and the interposing side 22b are selectively designed to electrically connect the conductive vias 220. (Redistribution layer, RDL) 21, and the conductive elements 23, 25 are coupled to the circuit redistribution structure 21, such that the conductive elements 23, 25 are electrically connected to the conductive via 220 by the line redistribution structure 21. . In other embodiments, the line redistribution structure (RDL) 21 may be formed only on one of the crystallizing side 22a or the intermediate side 22b.

In addition, as shown in FIGS. 2H' and 2H", when the singulation process is performed, the dicing path S' as shown in FIG. 2G' can be obtained to obtain a plurality of semiconductor packages 2 having a single semiconductor component 24. ',2".

According to the process shown in Fig. 2E', the semiconductor packages 3, 3', 3" as shown in Figs. 3, 3' and 3" will be obtained.

In the method of the present invention, the plurality of semiconductor elements 24 are correspondingly disposed in the accommodating grooves 202 of the carrier 20, and then the interposer 22 is bonded to the carrier 20 to complete the semiconductor device 24 and the substrate. The combination of the interposer 22, so the method of the present invention only needs to perform a bonding process (ie, a press-bonding process) and a heating process (ie, heating) compared to the process of soldering each of the semiconductor components to the interposer. The insulating layer 26) can greatly shorten the completion time for providing the semiconductor elements 24, resulting in an increase in the unit per hour (UPH), thereby reducing the cost of the process.

The present invention provides a semiconductor package 2, 2', 2", 3, 3', 3", which is packaged A carrier 20 having at least one accommodating groove 202, a semiconductor element 24 disposed in each of the accommodating grooves 202, and an interposer 22 provided on the carrier 20 and the semiconductor element 24.

The material of the carrier 20 is made of organic material or inorganic material.

The interposer 22 has a plurality of conductive vias 220 electrically connected to the semiconductor component 24.

In one embodiment, the side surface 22c of the interposer 22 and the side surface 20c of the carrier board 20 are flush.

In one embodiment, the semiconductor package 2, 2', 2", 3, 3', 3" includes a plurality of conductive elements 25 between the interposer 22 and the semiconductor element 24, and is electrically The conductive vias 220 are connected to the semiconductor component 24.

In one embodiment, the semiconductor package 2, 2', 2" includes an insulating layer 26 formed between the interposer 22 and the carrier 20, and the interposer 22 and the semiconductor device. For example, the conductive elements 25 are embedded in the insulating layer 26, and the side surface 22c of the interposer 22, the side surface 26c of the insulating layer 26, and the side surface 20c of the carrier board 20 are flush.

As shown in Figures 4, 4' and 4", in a subsequent application, the semiconductor package 2, 2', 2" (or the semiconductor package 3, 3', 3") can be passed through the middle side thereof. The conductive element 23 on the 22b is bonded and electrically connected to a package substrate 9, and the semiconductor package 2, 2', 2" (or the semiconductor package 3, 3', 3") and the package substrate 9 A primer 90 is formed to cover the conductive members 23.

In summary, in the semiconductor package of the present invention and the method of fabricating the same, the plurality of semiconductor elements are disposed in the receiving grooves of the carrier, and then the intermediate When the board is bonded to the carrier board, the combination of the semiconductor element and the interposer can be completed, so that only one bonding process and one heating process are required, thereby shortening the time for setting all the semiconductor components and improving the productivity.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

20‧‧‧ Carrier Board

20c, 22c, 26c‧‧‧ side

22‧‧‧Intermediary board

24‧‧‧Semiconductor components

25‧‧‧Conductive components

Claims (22)

A semiconductor package includes: a carrier board having at least one receiving groove; a semiconductor component disposed in the receiving groove; and an interposer disposed on the carrier and the semiconductor component, and the intermediary The board has a plurality of electrically conductive vias electrically connected to the semiconductor component. The semiconductor package according to claim 1, wherein the material of the carrier is an organic material or an inorganic material. The semiconductor package of claim 1, wherein the interposer has a line redistribution structure electrically connected to the conductive via. The semiconductor package of claim 1, further comprising a plurality of conductive elements disposed between the interposer and the semiconductor element, and electrically connecting the conductive vias and the semiconductor element. The semiconductor package of claim 1, further comprising an insulating layer formed between the interposer and the carrier, and between the interposer and the semiconductor device. The semiconductor package of claim 1, wherein the insulating layer is a non-conductive adhesive layer. The semiconductor package of claim 6, further comprising a plurality of conductive elements embedded in the insulating layer and electrically connecting the conductive vias to the semiconductor element. The semiconductor package of claim 6, wherein the side of the interposer, the side of the insulating layer, and the side of the carrier are flush. The semiconductor package of claim 1, wherein the side of the interposer and the side of the carrier are flush. A method of manufacturing a semiconductor package, comprising: providing a carrier having at least one receiving groove; placing a semiconductor component in the receiving groove; and disposing an interposer having a plurality of conductive vias on the carrier The conductive vias are electrically connected to the semiconductor component. The method of manufacturing a semiconductor package according to claim 10, wherein the material of the carrier is an organic material or an inorganic material. The method of fabricating a semiconductor package according to claim 10, wherein the interposer has a line redistribution structure electrically connected to the conductive via. The method of fabricating a semiconductor package according to claim 10, wherein the interposer is disposed on the carrier by a pressing process. The method of fabricating a semiconductor package according to claim 13, wherein the pressing process is to bond the interposer and the carrier by an insulating layer. The method of fabricating a semiconductor package according to claim 14, wherein the insulating layer is a non-conductive adhesive layer. The method of fabricating a semiconductor package according to claim 14, further comprising heating the insulating layer such that the interposer bonds the carrier by the insulating layer. The method for fabricating a semiconductor package according to claim 14, further comprising forming the insulating layer before the interposer is disposed on the carrier Forming a plurality of conductive elements on the interposer, and forming the interposer on the carrier, the insulating layer encapsulating the conductive elements, and electrically connecting the conductive elements These conductive vias are associated with the semiconductor component. The method for manufacturing a semiconductor package according to claim 14, further comprising forming a plurality of conductive elements and the insulating layer on the semiconductor element before the interposer is disposed on the carrier, and coating the insulating layer The conductive elements are electrically connected to the conductive vias and the semiconductor components after the interposer is disposed on the carrier. The method for manufacturing a semiconductor package according to claim 14, further comprising forming a plurality of conductive elements and the insulating layer on the interposer before the interposer is disposed on the carrier, so that the insulating layer is coated The conductive elements are electrically connected to the conductive vias and the semiconductor components after the interposer is disposed on the carrier. The method for manufacturing a semiconductor package according to claim 14, further comprising forming a plurality of conductive elements on the semiconductor element before the interposer is disposed on the carrier, and forming the insulating layer on the interposer After the interposer is disposed on the carrier, the insulating layer covers the conductive elements, and the conductive elements are electrically connected to the conductive vias and the semiconductor element. The method for manufacturing a semiconductor package according to claim 10, further comprising forming a plurality of conductive elements on the interposer or the semiconductor element before the interposer is disposed on the carrier, to set the interposer After the carrier board, the conductive elements are electrically connected to the conductive vias With the semiconductor component. The method for manufacturing a semiconductor package according to claim 10, further comprising the step of performing a singulation process after the interposer is disposed on the carrier.