TW201511003A - Semiconductor device - Google Patents

Abstract

The present invention stably supplies a current to each memory cell in a semiconductor device in which writes to a plurality of memory cells are performed simultaneously, even when the number of bits to which first data is written is not uniform. The semiconductor device is provided with a plurality of memory cells, a plurality of write registers for retaining a plurality of write data to be written to the plurality of memory cells, a ratio determination circuit for determining a ratio of first data to second data in the plurality of write data retained in the plurality of write registers, and a voltage regulator circuit for generating a first power source voltage used in writing the first data and a second power source voltage used in writing the second data. The voltage regulator circuit controls the electrical current supply capacity of the first power source voltage and/or the second power source voltage on the basis of output from the ratio determination circuit.

Description

Semiconductor device (for the record of related applications)

The present invention is based on the constitutional claim of Japanese Patent Application No. 2013-081408 (filed on Apr. 9, 2013), the entire contents of which are incorporated herein by reference. .

The present invention relates to a semiconductor device. In particular, the present invention relates to a power supply circuit that supplies a write current to a memory cell.

In the internal power supply circuit of the memory system, a circuit having two or more circuits having different current supply amounts and switching the circuit via mode setting (for example, active mode and standby mode) is proposed. According to such an internal power source generating circuit, when the current is supplied in response to the operation mode, the power consumption can be reduced.

Patent Document 1 discloses an internal power supply circuit including a circuit (VDLACT) having a large current supply capability for active use and a circuit (VDLSTY) having a small current supply capability for waiting (refer to Patent Document) Figure 1).

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-159145

The following analysis was obtained from the viewpoint of the present invention.

In a memory system that simultaneously supplies current to a plurality of memory cells and writes, the logical value of the data is written as "1" (first data = High bit, the same applies hereinafter), and the logical value is "0" (2nd) The ratio of the data = Low bit, the same below) is not constant. When the logical value "1" or "0" is simultaneously written, the number of bits written is not constant. Therefore, there is a problem that the current value supplied to each memory cell does not become constant. As a result, there is a possibility that the state of the memory cell after writing is uneven, and the margin of writing cannot be obtained.

The internal power source generating circuit described in Patent Document 1 does not control the amount of current supplied in accordance with the number of bits to be written, and the above problems are not solved.

Therefore, in the memory system in which the current is supplied to the memory cell and written, the number of bits to be simultaneously written is not constant, and the internal power supply circuit for supplying current to each memory cell can be realized. It is expected.

The semiconductor device according to the first aspect of the present invention includes: a plurality of memory cells, and a plurality of write registers that hold a plurality of write data written to the plurality of memory cells, and the determination is maintained a ratio determining circuit for ratios of the first data and the second data of the plurality of written data of the plurality of write registers of the plurality of write registers, and a first power supply voltage used for writing the first data, and A voltage regulator circuit of the second power supply voltage used for writing the second data. Here, the voltage regulator circuit controls a current supply capability of at least one of the first power supply voltage and the second power supply voltage in accordance with an output of the ratio determination circuit.

According to the semiconductor device of the present invention, even if the number of bits to be simultaneously written is not constant, a semiconductor device which can contribute to the case where the current is supplied to each memory cell by stabilization can be provided.

1a~1j, 2a~2j, 3a~3j‧‧‧Source Line Driver (SDRV)

4, 5, 6‧‧‧ Common source line (SL)

7a~7d, 8a~8d, 9a~9d‧‧‧ memory cell array

10‧‧‧Semiconductor device

11, 13, ‧ ‧ main character line driver (MWD)

12‧‧‧Memory Cell Array

14‧‧‧ address input circuit

16‧‧‧ address latch circuit

18‧‧‧Command input circuit

20‧‧‧ instruction decoding circuit

21a~21d, 23a~23d, 25a~25d‧‧‧Sub-character line driver (SWD)

24‧‧‧ column control circuit

26‧‧‧ line control circuit

28‧‧‧data register

30‧‧‧Output and input circuit

32‧‧‧Internal power generation circuit

32a, 132a‧‧‧Internal power generation circuit A

32b‧‧‧Internal power generation circuit B

34‧‧‧clock input circuit

38‧‧‧ Timing generator

41a~h‧‧‧Write Amplifier (WAMP)

51a~h‧‧‧Y switch (YSW)

52‧‧‧Y-switch of position unit (YSW)

60‧‧‧ bit line selection switch

61‧‧‧ bit line common source line connection switch

62, 64, 91, 98, 160, 183a‧‧‧ inverter circuits

71, 72‧‧‧ Impedance-varying memory unit

81, 82‧‧‧ Impedance variable components

93, 94, 171a~c, P1‧‧‧ PMOS transistors

95, 96, 97, 102, 181a, 182a, N1~3, Na0~1023, Nb0~1023, Nc0~1023‧‧‧ NMOS transistors

104, 105‧‧‧ unit transistor

141‧‧‧ Ratio Detection Department

142‧‧‧ Ratio Comparison Department

150‧‧‧Write to scratchpad

152‧‧‧Rate determination circuit

154, 254‧‧ ‧ voltage regulator circuit

156a~c, 170a~c, 180a‧‧‧ comparator

158‧‧‧Delay circuit

162‧‧‧AND circuit

164‧‧‧ capacitor

166L‧‧‧VSETGEN_L (VSET voltage regulator circuit (for high current))

166M‧‧‧VSETGEN_M (VSET voltage regulator circuit (for medium current))

166S, 266S‧‧‧VSETGEN_S (VSET voltage regulator circuit (for small current))

168L‧‧‧VRESETGEN_L (VRESET regulator circuit (for high current))

168M‧‧‧VRESETGEN_M (VRESET regulator circuit (for current))

168S‧‧‧VRESETGEN_S (VRESET regulator circuit (for small current))

172a~c‧‧‧PMOS transistor (output transistor)

190a‧‧‧Extracted circuit

200‧‧‧ Ratio detection wiring (internal wiring)

263‧‧‧NAND circuit

MWL‧‧‧ main character line

WL‧‧‧(sub)word line

BL‧‧‧ bit line

IO_0~IO_7‧‧‧IO line

Y1‧‧‧Upper column selection signal

Y2‧‧‧ lower column selection signal

FX‧‧‧ line selection signal

SET0‧‧‧ setting signal

RESET0‧‧‧Reset signal

NS, Nout‧‧‧ nodes

Potential of ARSELREF‧‧‧ ratio detection wiring

APREB, DEC‧‧‧ control signals

VINTREF‧‧‧ (constant current source) bias voltage

VCREF1, VCREF2‧‧‧ reference potential

VSETREF, VRESETREF‧‧‧ reference voltage

Fig. 1 is a block diagram showing the overall configuration of a semiconductor device according to a first embodiment.

Fig. 2 is a block diagram showing a memory cell array of the semiconductor device of the first embodiment.

Fig. 3 is a block diagram showing a memory cell array of the semiconductor device of the first embodiment.

4 is a circuit diagram of a memory cell of a semiconductor device according to the first embodiment, a Y-switch of a bit unit, a write amplifier, and a source line driver.

Fig. 5 is a circuit diagram showing an internal power supply circuit A of the semiconductor device according to the first embodiment.

Fig. 6 is a circuit diagram showing a regulator circuit of the first power supply voltage of Fig. 5.

FIG. 7 is a circuit diagram showing a regulator circuit of a first power supply voltage of the semiconductor device according to the first modification of the first embodiment.

Fig. 8 is a timing chart showing the operation of the semiconductor device of the first embodiment.

FIG. 9 is a view for explaining the operation of the ratio detecting unit of the semiconductor device according to the first embodiment.

Fig. 10 is a circuit diagram showing an internal power supply circuit A of the semiconductor device of the second embodiment.

Fig. 11 is a timing chart showing the operation of the semiconductor device of the second embodiment.

First, an outline of an embodiment will be described. However, in the description of the general description of the embodiments, the reference numerals are mainly for the purpose of facilitating understanding, and are not intended to be limited to the illustrated form. Condition.

As shown in FIG. 1, the semiconductor device 10 of the embodiment includes an internal power supply circuit A (32a) that generates a first power supply voltage (voltage VSET in FIG. 5) and a second power supply voltage (voltage VRESET in FIG. 5). Semiconductor device. Here, the internal power source generating circuit A (32a) of the semiconductor device 10 is provided with a plurality of memory cells and a plurality of write data holding a plurality of memory cells written to the plurality of memory cells as shown in FIG. Writing to the register 150, and determining the ratio of the first data (for example, High bit) and the second data (for example, Low bit) of the plurality of written data held in the plurality of write registers 150 The ratio determination circuit 152 and the first power supply voltage (voltage VSET) used for writing the first data and the second power supply voltage (voltage VRESET) used for writing the second data are voltage-stabilized. Circuit 154. Here, the voltage regulator circuit 154 controls the current supply capability of at least one of the first power supply voltage (voltage VSET) and the second power supply voltage (voltage VRESET) in accordance with the output of the ratio determination circuit 152 (FIG. 5). In the internal power generating circuit A (32a), the current supply capability of both the first power supply voltage and the second power supply voltage is controlled. Further, as shown in the internal power supply generating circuit A (132a) of FIG. 10, only one of the power supplies may be controlled. The voltage (the configuration of the current supply voltage in the case of FIG. 11 is the first power supply voltage).

According to the configuration described above, in the memory system in which the plurality of memory cells are simultaneously and (in the same time) supplied with the current and written, the ratio of the first data and the second data is determined to be controlled. According to this ratio, the current supply capability of the power supply voltage supplied at the time of writing is such that even if the number of write bits is not constant, the current supply can be stably performed for each memory cell.

As shown in FIG. 5, the voltage regulator circuit 154 includes two or more voltage regulator circuits having different current supply capacities for the first power supply voltage (voltage VSET) and the second power supply voltage (voltage VRESET) ( For the voltage VSET, VSETGEN_L, VSETGEN_M, VSETGEN_S; for the voltage VRESET, VRESETGEN_L, VRESETGEN_M, VRESETGEN_S), according to the output of the ratio determination circuit 152 (S1, S2, S3), as a regulator circuit of 2 or more In the choice, the regulator circuit can be used.

Further, the voltage regulator circuit 254 shown in FIG. 10 has two or more voltage regulators having different current supply capacities for one of the first power supply voltage (voltage VSET) and the second power supply voltage (voltage VRESET). The circuit (in FIG. 11, for the voltage VSET, VSETGEN_L, VSETGEN_M, VSETGEN_S), according to the output (S1, S2, S3) of the ratio determination circuit 152, is selected as the regulator circuit of 2 or more. The regulator circuit can also be used.

The current driving capabilities of the output transistors of the above two or more regulator circuits (the output transistor systems 172a to c of the voltage regulator circuits VSETGEN_S, VSETGEN_M, and VSETGEN_L of FIG. 6) are preferably different from each other.

As shown in FIG. 5, the ratio determination circuit 152 includes internal wiring (ratio for detecting ratio) 200, and writes by plural Each of the plurality of write elements held by the register 150 is controlled to be turned on/off by a plurality of first switching elements (NMOS transistors Na0 to 1023), and one end of the plurality of first switching elements is internally and internally Wiring (ratio for detecting ratio) 200 is connected. Further, the internal wiring (ratio detecting wiring) 200 is precharged at a specific potential VDD, and the precharged electric charge is discharged through the first switching element in the on state by the plurality of first switching elements. The potential of the internal wiring (ratio detecting wiring) 200 (ARSELREF in FIG. 9) is determined, and the above ratio may be determined.

In the ratio determination circuit 152, as shown in FIG. 5, for each of the plurality of first switching elements (NMOS transistors Na0 to 1023), a constant current source (NMOS transistors Nc0 to 1023) is connected in series. Also.

As shown in FIG. 5, the ratio determination circuit 152 further includes comparators (156a to c) that compare one or more potentials of two input terminals, and has a ratio detection as an input terminal for one of the comparators. The wiring 200 is supplied with one or more reference potentials (VCREF1, VCREF2, etc.) to the other input terminal of each of the comparators, and outputs a ratio detecting wiring in accordance with the output of each of the comparators (156a to c). The magnitude of 200 (ARSELREF in FIG. 10) may be related to the magnitude of the reference potential (VCREF1, VCREF2, etc.) of 1 or more.

As shown in FIG. 5, the ratio determination circuit 152 further includes a delay circuit 158 as a period from the end of precharge to the delay. After the delay time generated by the circuit 158 (after the τ of FIG. 9), comparison by the comparators (156a-c) may be performed.

As shown in FIG. 5, the voltage regulator circuit 154 is a magnitude relationship (for example, the magnitude of the potential of the ratio detecting wiring 200 and the reference potentials VCREF1 and VCREF2) which is outputted by the response ratio determining circuit 152. The above regulator circuit (for the voltage VSET, VSETGEN_L, VSETGEN_M, VSETGEN_S of FIG. 5; for the voltage VRESET, VRESETGEN_L, VRESETGEN_M, VRESETGEN_S of FIG. 5), the regulator circuit to be used may be selected.

The voltage regulator circuit 254 shown in FIG. 10 includes two or more voltage regulator circuits (VSETGEN_S, VSETGEN_M, and VSETGEN_L) having different current supply capacities for the first power supply voltage (voltage VSET), and In the case of the power supply voltage (voltage VRESET), only one regulator circuit (VRESETGEN_L) supplies the second power supply voltage (voltage VRESET) as a memory unit corresponding to each of the first and second data. After the writing of the second data is performed, the first power supply voltage (voltage VSET) may be supplied to the memory unit corresponding to the first data to write the first data.

Further, contrary to FIG. 10, the voltage regulator circuit includes a regulator circuit of 2 or more different in current supply capability for the second power supply voltage (voltage VRESET), and a first power supply voltage (voltage VSET) In the case of only one voltage regulator circuit, the first power is supplied to the memory unit corresponding to each of the first and second data. After the first data is written by the source voltage (voltage VSET), the second power supply voltage (voltage VRESET) may be supplied to the memory unit corresponding to the second data to write the second data.

The memory cell pair may have different impedance states corresponding to the first and second data (for example, when the first data is written, the low impedance state; when the second data is written, the high impedance state) ) The impedance change type element (81, 82, etc. in Fig. 4) is written.

Hereinafter, each embodiment disclosed in the present application will be described in detail with reference to the drawings.

[First Embodiment] (Configuration of the first embodiment)

The configuration of the first embodiment will be described with reference to Fig. 1 . Fig. 1 is a block diagram showing the entire semiconductor device 10 of the first embodiment.

In FIG. 1, the memory cell array 12 includes a plurality of impedance-variable memory cells (71, 72, and the like in FIG. 4) arranged in a quadratic element. Each of the impedance change type memory cells is constituted by a Resistive Random Access Memory (ReRAM) (81, 82, etc. in FIG. 4) and a cell transistor (104, 105, etc. in FIG. 4). Here, the impedance change type element (ReRAM) has, for example, a laminated structure of a lower electrode and a metal oxide and an upper electrode, and changes in impedance characteristics when an electrical stress is applied between the lower electrode and the upper electrode. Memory element. Each impedance-changing component is a memory high-impedance state and The impedance state of either of the low impedance states functions as a non-volatile memory element. Further, the unit cell (104, 105, etc. in Fig. 4) is preferably an NMOS transistor from the viewpoint of current control, and for example, a bipolar transistor or the like can also be applied. The semiconductor device 10 selects an impedance change type memory cell accessed in the memory cell array 12, performs SET writing to change the high impedance state to a low impedance state, and changes the low impedance state to a high impedance state RESET write. In, the action of reading the impedance state. Here, in the present specification, the low impedance state is set to "1", and the high impedance state is set to "0". That is, the SET write system reads "1" and the RESET write reads "0."

In FIG. 1, cells other than the memory cell array 12 control the above-described operations for the memory cell array 12.

First, the address input circuit 14 inputs the address ADD of the access impedance change memory unit. Next, the address latch circuit 16 latches the input address ADD, separates it into a row address ADD_row, and a column address ADD_column, and supplies them to the row control circuit 26 and the column control circuit 24.

Here, the row control circuit 26 has a row decoder (not shown), and decodes the row selection signal from the row address ADD_row. The (sub)word line selected by the above-described row selection signal (hereinafter referred to as "selection (sub)word line") becomes active. Here, the column control circuit 24 has a column decoder (not shown), and decodes the column selection signal from the column address ADD_column. The (sub)word line (hereinafter referred to as "selection bit line") selected via the above column selection signal becomes active.

The plurality of impedance-changing memory cells in the memory cell array 12 are arranged in a quadratic manner at an intersection of a complex (sub)word line and a complex bit line, among which, the selection is connected to the selection ( The sub-word line and the impedance-changing memory unit of both sides of the bit line are selected and accessed. Specifically, for example, BL0 of FIG. 4 is a select bit line, and (sub)word line WL of FIG. 4 is a case of selecting (sub)word line, and cell transistor 104 is turned on, at a common source. A voltage is applied between the line 4 and the selected bit line BL0, and a current is supplied to the impedance change element 81 of the impedance varying memory unit 71 to perform a write operation.

The clock input circuit 34 receives the external clock signal CK, /CK supplied from the outside to the complement of the semiconductor device 10, generates an internal clock ICLK, and supplies it to the timing generator 38. The timing generator 38 generates various necessary clock signals in the semiconductor device 10 based on the internal clock ICLK, and supplies them to the respective units. However, in the present specification, the signal name is a signal indicating that the Low level is active.

The data input/output terminal DQ is connected to the input/output circuit 30, and when input data is input to the data input/output terminal DQ, the write data is placed in the input/output circuit 30. Further, the input/output circuit 30 is connected to the data register 28, and the written data is temporarily stored in the data register 28. Thereafter, the write data stored in the data register 28 is output to the IO line inside the memory cell array 12 (IO_0-7 of FIG. 3, etc.) at a specific time. Further, the signals of the respective IO lines are supplied to the write amplifier (WAMP: 41a to h of FIG. 3, etc.).

Next, the command input circuit 18 serves as a control signal, and inputs a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and the like. The command decoding circuit 20 decodes the signals /RAS, /CAS, /WE, etc., and outputs control signals necessary for the execution of the decoded instructions to the respective units in the semiconductor device 10.

Next, the internal power generating circuit 32 is constituted by two units of the internal power generating circuit A (32a) and the internal power generating circuit B (32b) as shown in FIG. Here, the internal power source generating circuit B (32b) receives the power supplies VDD and VSS supplied from the outside, and generates voltages VPP, VERRRD, VPERI, and the like necessary for each unit in the semiconductor device 10, and supplies them to the respective units.

On the other hand, the internal power generation circuit A (32a) inputs the power supply VDD and VSS supplied from the outside, generates a voltage VSET (first power supply voltage), and generates a voltage VRESET (second power supply voltage), and supplies it to the memory cell array. 12. Here, the voltage VSET is supplied to the write amplifier (41a to h of FIG. 3, etc.) and used for SET writing. Further, the voltage VRESET is supplied to the source line driver (1a to j, 2a to j, 3a to j, etc. in Fig. 2), and is used for RESET writing. In the internal power generating circuit A (32a), the current supply capability of the voltage VSET and the voltage VRESET is controlled in accordance with the 1024-bit Data_0-1023 supplied from the data register 28 (details will be described later).

Next, the configuration of the memory cell array 12 will be described in more detail with reference to FIG. As shown in FIG. 2, the memory cell array 12 includes a plurality of memory cell pads (7a-7d, 8a-8d, 9a~9d) and constructed. These memory cell pads are arranged in a two-dimensional element. In FIG. 2, a case where the memory cell array 12 is formed by four memory rows of memory cell pads is exemplified. However, the arrangement of the memory cell pads is not limited to this, and any configuration can be performed.

As shown in FIG. 2, the memory cell pads of the four rows and M columns are divided into column units, and the source lines are common to the respective ranges. Specifically, a common source line 4 is disposed for the memory cell pad of the 0th column, and a common source line 5 is disposed for the memory cell pad of the first column, for the M-th The memory cell pads of one column are provided with a common source line 6.

In the same figure, in the range of column units, the source lines are arranged in five rows, and two columns are arranged in the column direction, but the common source lines (4, 5, 6) are Actually, for example, it is composed of a common diffusion layer or a solid layer of wiring.

Further, a Y switch group (YSW group) and a write amplifier group (WAMP group) are disposed on both sides of each memory cell pad.

In addition, the word line system is structured by a hierarchical structure of the main word line and the sub word line, and the main word line driver (MWD) is arranged in each column, and the sub word line driver (SWD) is applied. Configured in each memory unit gasket. In this hierarchical structure, the sub-word line is directly connected to the impedance-changing type memory unit.

In addition, at least one source line driver is provided for each memory cell pad, but the view of the current supply from stability is provided. It is desirable that, as shown in Fig. 2, in the first embodiment, the source is disposed on both sides of the sub-line driver SWD (21a to 21d, 23a to 23d, 25a to 25d) of each memory cell pad. Polar line driver (1a~1j, 2a~2j, 3a~3j). However, the present invention is not limited thereto, and the source line driver can be configured arbitrarily.

Next, referring to Fig. 3, the configuration of the memory cell pad 7a, i.e., the memory cell pad of 0 rows and 0 columns, which is related to one memory cell pad 7a (indicated by a dotted line in Fig. 2), will be described in more detail. In FIG. 3, the memory cell pad 7a has an impedance change type memory cell which is arranged in a quadratic element. The row address ADD_row is 9 bits, and the 6 bits of the 9 bits are used when one of the main character lines is selected. Further, the remaining three bits are used to select one of the row selection signals FX_0-7, and are supplied to the sub-word line driver 21a.

On the other hand, the column address ADD_column is also 9 bits, but each of ADD_column_h, ADD_column_m, and ADD_column_l separated into 3 bits is decoded. Here, ADD_column_h is the upper side 3 bits, and ADD_column_l is the lower side 3 bits. In addition, ADD_column_m is the remaining three bits in the middle. Further, eight column selection signals of ADD_column_h are decoded as Y1_0-7, and eight column selection signals of ADD_column_m are decoded as Y2_0-7, and eight column selection signals of ADD_column_1 are decoded as Y3_0-7.

Positioned on the selected (sub)word line via the above-described row select signal FX_0-7, and via the above-described column select signals Y1_0-7, Y2_0- 7. The impedance change memory unit at the intersection of the selected bit lines of Y3_0-7 is accessed.

Further, two write amplifier groups (WAMP groups) disposed on both sides of the memory cell pad 7a of FIG. 2 are as shown in FIG. 3, and one of them includes four write amplifiers (41a, 41c, 41e, 41g), while the other contains 4 write amplifiers (41b, 41d, 41f, 41h).

Further, two Y-switch groups (YSW groups) disposed on both sides of the memory cell pad 7a of FIG. 2 are shown in FIG. 3, and one Y-switch group includes four Y switches (51a, 51c, 51e, 51g), and the other Y switch group includes four Y switches (51b, 51d, 51f, 51h).

Further, among the four source line drivers (1a, 1b, 1c, 1d) disposed adjacent to the memory cell pad 7a of Fig. 2, in Fig. 3, the source line drivers 1c, 1d are shown ( The source line drivers 1a, 1b are not shown in Fig. 3, but are actually connected adjacent to the memory cell pads 7a).

The source line driver (1c, 1d) that controls the potential of the common source line 4 is supplied with a setting signal SET0 and a reset signal RESET0 as a control signal from a control circuit (not shown). On the other hand, the write amplifiers (41a to 41h) for controlling the potential of the selected bit line are supplied with the setting signal SET0 and the reset signal RESET0 as control signals from the control circuit.

In addition, in FIG. 3, eight IO lines (IO_0-7) are wired. Eight IO lines (IO_0-7) are externally input and output terminals DQ holds a signal corresponding to each bit of the write data of the 8-bit input by the input/output circuit 30 and the data register 28. Further, the 8-bit write is completed, and when the external DQ is input and output to the next 8-bit write data, the signals of the eight IO lines (IO_0-7) are updated.

Next, the relationship between the column selection signals Y1, Y2, Y3, and the selected bit line will be described in detail. The 512-bit line BL_0-511 is divided into 8 groups of 64 bit lines. Group 1 group BL_0-63, group 2 group BL_64-127, group 3 group BL_128-191, group 4 group BL_192-255, group 5 group BL_256-319, group 6 group BL_320-383, group 7 group BL_384-447, group 8 group BL_448-511.

Among the above-described first to eighth group groups, which group is selected is determined by the column selection signal Y1_0-7. As shown in FIG. 3, the column selection signal Y1_0 is supplied to the eight Y switches (51a to 51h) connected to the bit lines BL_0-63 of the first group. Thus, the column selection signal Y1_0 is active, and the bit line BL_0-63 of the first group is selected. Similarly, for the column selection signals Y1_1, Y1_2, ..., Y1_7, the bit lines of the second group group, the third group group, ..., the eighth group group are selected.

Next, among the eight Y switches in the respective groups, which Y-open relationship is selected is determined by the column selection signal Y3_0-7. For example, as shown in FIG. 3, in the case of the first group, for each of the eight Y switches 51a to 51h, each of the supply column selection signals Y3_0 to Y3_7 is selected. Among the selection signals Y3_0-7, a Y switch that is connected to the active wiring is connected.

Further, as shown in FIG. 3, the even-numbered bit lines and the odd-numbered bit lines are alternately distributed to the Y switches on both sides for wiring. Each Y open relationship is connected to eight bit lines. Specifically, the Y switch 51a is connected to the bit lines BL0, BL2, ..., BL14. The Y switch 51b is connected to the bit lines BL1, BL3, ..., BL15. The Y switch 51c is connected to the bit lines BL16, BL18, ..., BL30. The Y switch 51d is connected to the bit lines BL17, BL19, ..., BL31. The Y switch 51e is connected to the bit lines BL32, BL34, ..., BL46. The Y switch 51f is connected to the bit lines BL33, BL35, ..., BL47. The Y switch 51g is connected to the bit lines BL48, BL50, ..., BL62. The Y switch 51h is connected to the bit lines BL49, BL51, ..., BL63.

Next, in each of the Y switches, which bit line is selected is determined by the column selection signal Y2_0-7 supplied to each Y switch. For example, in the Y switch 51a, any one of the bit lines BL0, BL2, ..., BL14 is selected in accordance with the column selection signal Y2_0-7. Specifically, when Y2_0 is active, bit line BL0 is selected, and Y2_1 is active. When bit line BL2 is selected and Y2_7 is active, bit line BL14 is selected.

As described above, according to the column selection signals Y1, Y2, and Y3, one bit line is selected as the selection bit line. However, in FIG. 3, a plurality of bit lines may also be used as the selection bit line. For example, will column When the selection signal Y3_0-7 is set to the High level (active), one bit line of each group can be used as the selection bit line from the eight Y switches in each group. By doing so, it is possible to simultaneously access eight impedance-change memory cells.

Further, as shown in FIG. 3, for each of the Y switches (51a to 51h, etc.), since the write amplifiers (41a to 41h, etc.) are provided, it is ensured that the plurality of selected bit lines are simultaneously performed. The ability to supply voltage.

Next, with reference to Fig. 4, the configuration of the Y-switch 52 of the source line driver 1c and the write amplifier 41a will be described in more detail. Figure 4 is a block diagram showing in detail the extent of the dashed box in Figure 3. However, in Fig. 4, among the Y switches included in the eight bit units of the Y switch 51a, only the Y switch 52 of one bit unit is displayed. Further, the Y switch 52 in the bit unit is displayed, and the impedance change type memory unit 71 is connected by the bit line BL_0.

In FIG. 4, the source line driver 1c includes a PMOS transistor 93, an NMOS transistor 102, and an inverter circuit 91. A PMOS transistor 93 and an NMOS transistor 102 are connected in series between the voltage source VRESET and ground. Specifically, the source of the PMOS transistor 93 is connected to the voltage source VRESET, and the drain of the PMOS transistor 93 and the drain of the NMOS transistor 102 are simultaneously connected to the node NS, and the source of the NMOS transistor 102 Connect to ground. Further, the gate of the PMOS transistor 93 is connected to the wiring of the reset signal RESET0 by the inverter circuit 91. another Further, the gate of the NMOS transistor 102 is connected to the wiring of the reset signal SET0. Further, the node NS is connected to the common source line 4.

Next, the configuration of the Y switch 52 in the bit unit will be described in detail. The bit switch Y switch 52 is constituted by a bit line selection switch 60, a bit line common source line connection switch 61, and inverter circuits 62, 64, and a NAND circuit 263. Here, the bit line selection switch 60 and the bit line common source line connection switch 61 are transmission gate circuits each configured via a PMOS transistor and an NMOS transistor. The bit line selection switch 60 controls the output of the write amplifier 41a and the on/off switch of the bit line BL0. On the other hand, the bit line common source line connection switch 61 is a switch that controls the conduction/non-conduction of the common source line 4 and the bit line BL0.

The bit line selection switch 60 and the bit line common source line connection switch 61 are complementarily controlled via the control signal C1 output from the inverter circuit 64. Specifically, when the control signal C1 is at the High level, the bit line selection switch 60 is turned on, and the bit line common source line connection switch 61 is in a non-conduction state. As a result, the bit line BL0 is turned on to the write amplifier 41a. On the other hand, when the control signal C1 is at the Low level, the bit line selection switch 60 is in a non-conduction state, and the bit line common source line connection switch 61 is in an on state. As a result, the bit line BL0 is electrically connected to the common source line 4.

Next, the configuration of the portion related to the generation of the control signal C1 will be described. For the three input terminals of the NAND circuit 263, input column selection signals Y1_0, Y2_0, and Y3_0 are input. For column selection When the signal Y1_0=Y2_0=Y3_0=1, the control signal C1=1, and the bit line BL0 is turned on by the write amplifier 41a to become the selected bit line. Further, in the case other than the above, the control signal C1=0, and the bit line BL0 is not turned into the selected bit line, but is turned on toward the common source line 4 side.

However, in FIG. 4, the Y switch 52 for the bit unit has been described, but the Y switch of the other bit unit has the same configuration as the Y switch 52 of the bit unit, and only supplies Y1_i, Y2_j, The points of the column selection signals of the combination of Y3_k (i, j, k = 0 to 7) are different.

Next, the configuration of the write amplifier (WAMP) 41a of Fig. 4 will be described. The write amplifier (WAMP) 41a supplies a write current to the impedance change type element (81, 82, etc.) by a Y switch (52 or the like) in a bit unit at the time of SET writing and RESET writing. However, the configuration of each write amplifier (WAMP) included in the semiconductor device 10 of FIG. 3 is the same as that of the write amplifier (WAMP) 41a shown in FIG. As shown in FIG. 5, the write amplifier 41a includes a PMOS transistor 94, NMOS transistors 95 to 97, and an inverter circuit 98. Between the voltage source VSET and the ground, the PMOS transistor 94 and the NMOS transistors 95-97 are connected in series. The gates of the PMOS transistor 94 and the NMOS transistor 96 are connected to the wiring of IO_0 by the inverter circuit 98. Further, the gate of the NMOS transistor 95 is connected to the wiring of the setting signal SET0. Further, the gate of the NMOS transistor 97 is connected to the wiring of the reset signal RESET0.

According to the above configuration, in the write amplifier 41a, when IO_0 is the High level, and the setting signal SET0 is at the High level, the PMOS transistor 94 and the NMOS transistor 95 are turned on, and the NMOS transistors 96, 97 are turned off. . Thereby, the wiring having the voltages VSET to OUT_0 is supplied. On the other hand, when IO_0 is the Low level and the reset signal RESET0 is the High level, the PMOS transistor 94 and the NMOS transistor 95 are turned off, and the NMOS transistors 96, 97 are turned on. As a result, the wiring of OUT_0 is electrically connected to the ground. In addition, in the case other than the above, the voltage source VSET and the node Nout, and the node Nout and the ground are both non-conductive, and there is no current flowing path, and the current does not flow to the impedance variable element. (81, 82, etc. in Figure 4).

As shown in FIG. 4, the node Nout of the write amplifier 41a is connected to the Y switch 52 of the bit unit by the wiring of OUT_0. At the time of SET writing, the write amplifier 41a applies a voltage VSET to one end of the impedance change type memory unit 71 (A of FIG. 4) by the wiring of OUT_0, and supplies a write current to the impedance change type element 81. Further, for SET writing, the node NS of the source line driver 1c is electrically connected to the ground. Thereby, from A of FIG. 4, a current flows to the direction of B, and SET writing is performed. On the other hand, in the case of RESET writing, the source line driver 1c applies a voltage VRESET to the other end of the impedance change type memory unit 71 (B of FIG. 4), and supplies a write current to the impedance varying element 81. Thereby, from the direction B of FIG. 4, the current flows to the direction of A, and the write amplifier 41a is electrically connected by the wiring of OUT_0. The flow is directed to ground. The RESET write is performed by this.

Next, the configuration of the internal power generating circuit A (32a) will be described with reference to Fig. 5 . Fig. 5 is a circuit diagram showing an internal power supply circuit A (32a) of the semiconductor device 10 of the first embodiment. As shown in FIG. 5, the internal power generating circuit A (32a) is configured by a plurality of write registers 150, a ratio determining circuit 152, and a voltage regulator circuit 154.

As shown in FIG. 1, the data register 28 is a register for temporarily storing a plurality of written data. The data register 28 is written into the 1024-bit write data Data_0-1023 of the memory cell array 12 from the plurality of write data temporarily stored, and transmitted to the internal power supply circuit 32. Each of the write registers 150 of the internal power generating circuit A (32a) holds the transferred data of 1024 bits, Data_0-1023. However, in the present embodiment, it is assumed that the 1024-bit writer is simultaneously performed. However, the present invention is not limited thereto, and the number of write bits can be simultaneously set to an arbitrary number. Preferably, the number of bits, such as the bit width of the set signal Data, and the number of write registers 150 are preferred.

As shown in FIG. 5, corresponding to the data of each write register 150, an output voltage is applied to 1024 EIO lines (EIO<0>~<1023>). For the EIO wiring, when the write register 150 is a High bit (data "1"), the voltage of the High level is output, and the write register 150 is a Low bit (data "0"). , to output the voltage of the Low level.

Next, the ratio determination circuit 152 will be described. ratio The rate decision circuit 152 has a function of determining the ratio of the High bits of the plurality of write registers 150. However, in FIG. 5, although the ratio of the High level is determined, it may be configured to determine the ratio of the Low level.

As shown in FIG. 5, the ratio determination circuit 152 is configured by the ratio detecting unit 141 and the ratio comparing unit 142. The ratio detecting unit 141 includes a ratio detecting wiring 200, NMOS transistors (first switching elements) Na0 to 1023, NMOS transistors Nb0 to 1023, NMOS transistors Nc0 to 1023, PMOS transistors P1, and 164. Here, three NMOS transistors (Nai, Nbi, Nci, i = 0 to 1023) are connected in series between the ratio detecting wiring 200 and the ground. Further, the gate of the NMOS transistor Nai (i = 0 to 1023) is connected to the wiring of each corresponding EIO <i> (i = 0 to 1023). Further, a supply control signal DEC is supplied to the gate of the NMOS transistor Nbi (i = 0 to 1023). Further, a bias voltage VINTREF is supplied to the gate of the NMOS transistor Nci (i = 0 to 1023), and the NMOS transistor Nci (i = 0 to 1023) operates as a constant current source.

Further, the PMOS transistor P1 is connected between the power supply VDD (for example, about 1.5 V) and the ratio detecting wiring 200, and the gate signal of the PMOS transistor P1 is applied with the control signal APREB.

Next, the operation of the ratio detecting unit 141 will be described with reference to Fig. 9 . First, the control signal APREB is used as the Low bit. The PMOS transistor P1 is turned on, and the ratio detecting wiring 200 and the capacitor 164 are precharged at the potential VDD. As a result, as shown in FIG. 9, the potential of the ratio detecting wiring 200 rises to the potential VDD.

Next, the control signal APREB is returned to the High level to end the precharge period, and the control signal DEC is set to the High level. Thereby, the NMOS transistor Nbi (i = 0 to 1023) is turned on. Further, among the NMOS transistors Nai (i = 0 to 1023), the voltage of EIO < i > (i = 0 to 1023) is turned on in response to the NMOS transistor of the High level. As a result, the voltage of EIO<i>(i=0~1023) is turned on in accordance with the three NMOS transistors Nai, Nbi, and Nci of the High level, and a path through which a current flows is formed.

The precharged charge is discharged by the flow path of the current. Here, the greater the ratio of the high bits of the plurality of write registers 150, the number of turns on in the NMOS transistor Nai (i = 0 to 1023) increases, and the flow path of the current increases. The speed of discharge is faster. On the other hand, the ratio of the high bit of the plurality of write registers 150 is small, and the number of turns on in the NMOS transistor Nai (i = 0 to 1023) is small, and the flow path of the current is small. Therefore, the speed of discharge becomes slower. With respect to Fig. 10, the waveform of ARSELREF (the potential of the ratio detecting wiring 200) at the time of discharge is shown for the ratio of the High bit of three channels.

The NMOS transistor Nci (i = 0 to 1023) operates as a constant current source, and stabilizes the current flowing during discharge.

In addition, the control signal DEC is input by the delay circuit 158. After a certain time τ, return to the Low level and the discharge action ends. As shown in FIG. 9, the ratio of the High bit is small, and in the case of a large one, the potential of the ARSELREF after the specific time τ becomes V1, V2, and V3.

As described above, in the ratio detecting unit 141 of the ratio determining circuit 152, as described with reference to FIG. 9, the potential of the ratio detecting wiring 200 is output in accordance with the ratio of the high bit of the plurality of write registers 150 (Fig. 9 of V1, V2, V3, etc.).

Next, returning to FIG. 5, the ratio comparison unit 142 of the ratio determination circuit 152 will be described. The ratio comparing unit 142 has a function of the magnitude of the potential of the ratio detecting wiring 200 after the discharge by the output ratio detecting unit 141 and the magnitude of the reference potential. Here, the reference potential system for comparison may be plural, and in FIG. 5, the potential of the ratio detecting wiring 200 is equal to two reference voltages VCREF1 (for example, about 0.75 V), and VCREF2 (for example, 1.2 V). )comparing.

In FIG. 5, the ratio comparison unit 142 includes comparators 156a, 156b, and 156c, an inverter circuit 160, and an AND circuit 162. The non-inverting input terminal of the comparator 156a is connected to the ratio detecting wiring 200. The reference input potential VCREF2 is supplied to the inverting input terminal of the comparator 156a. As a result, when the output S1 of the comparator 156a is ARSELREF ≧ VCREF2, it becomes a High level, and when it is other than the other, it becomes a Low level.

The non-inverting input terminal of the comparator 156b is connected to the ratio detecting wiring 200. In addition, for the inversion of the comparator 156b The input terminal is supplied with a reference potential VCREF1. As a result, when the output of the comparator 156b is ARSELREF ≧ VCREF1, it becomes a High level, and otherwise, it becomes a Low level. Further, the input terminal of one of the AND circuits 162 is supplied with the output S1 of the comparator 156a via the inverter circuit 160, and the other input terminal of the AND circuit 162 is connected to the output terminal of the comparator 156b. . As a result, when the output S2 of the AND circuit 162 is VCREF1 ≦ ARSELREF < VCREF2, it becomes the High level, and otherwise becomes the Low level.

The inverting input terminal of the comparator 156c is connected to the ratio detecting wiring 200. Further, a reference potential VCREF1 is supplied to the non-inverting input terminal of the comparator. As a result, when the output S3 of the comparator 156c is ARSELREF<VCREF1, it becomes the High level, and when it is other than the other, it becomes the Low level. However, instead of setting the comparator 156c, the inverted output of the comparator 156b is connected to S3.

When the concentration is equal to or greater than the above, the ratio comparing unit 142 outputs the magnitude relationship between the ARSELREF (the potential of the ratio detecting wiring 200) and the reference potentials VCREF1 and VCREF2 after the electric charge is discharged. That is, when the outputs S1, S2, and S3 are each of ARSELREF ≧ VCREF2, VCREF1 ≦ ARSELREF < VCREF2, and ARSELREF < VCREF1, the High level is output, and otherwise, the Low level is output. However, in the above-described magnitude relationship, there is substantially no difference between ≧ and >, and ≦ and <, and it is determined whether or not it is.

Next, the voltage regulator circuit 154 will be described. The voltage regulator circuit 154 has a voltage VSET (first power supply voltage) used for SET writing, and a voltage VRESET (second power supply voltage) for RESET writing, which is supplied to the memory cell array 12. Write the functions of the amplifier (41a~h in Figure 3) and the source line driver (1c in Figure 3, etc.).

As shown in FIG. 5, the voltage regulator circuit 154 includes VSETGEN_S (166S), VSETGEN_M (166M), and VSETGEN_L (166L) which generate three voltage regulator circuits of the voltage VSET. Here, the current supply capacities of the three voltage regulator circuits are VSETGEN_L (166L), VSETGEN_M (166M), and VSETGEN_S (166S) in order of magnitude. That is, VSETGEN_L (166L), VSETGEN_M (166M), and VSETGEN_S (166S) are voltage regulator circuits for high current, medium current, and small current.

Further, the voltage regulator circuit 154 includes VRESETGEN_S (168S), VRESETGEN_M (168M), and VRESETGEN_L (168L) which generate three voltage regulator circuits of the voltage VRESET. Here, the current supply capacities of the three voltage regulator circuits are VRESETGEN_L (168L), VRESETGEN_M (168M), and VRESETGEN_S (168S) in order of magnitude. That is, VRESETGEN_L (168L), VRESETGEN_M (168M), and VRESETGEN_S (168S) are voltage regulator circuits for high current, medium current, and small current.

As shown in FIG. 5, a signal S1 is input to the regulator circuit VSETGEN_S (166S; for small current) and VRESETGEN_L (168L; for large current). Through this, for writing in the plural The ratio of the High bit of the register 150 is low, and the signal S1 becomes the High level, and the voltage supply circuit with the selected voltage VSET is small, the voltage regulator circuit VSETGEN_S (166S; for small current), and the voltage The current supply capability of VRESET is a large regulator circuit VRESETGEN_L (168L; for large current).

Further, a signal S2 is input to the regulator circuit VSETGEN_M (166M; medium current) and VRESETGEN_M (168M; medium current). Thus, for the case where the ratio of the High bit of the plurality of write registers 150 is the middle level and the signal S2 becomes the High level, the current supply capability of the selection voltage VSET is the intermediate voltage regulator circuit VSETGEN_M The current supply capability of (166M; medium current) and voltage VRESET is intermediate voltage regulator circuit VRESETGEN_M (168M; medium current).

In addition, a signal S3 is input to the regulator circuit VSETGEN_L (166L; for large current) and VRESETGEN_S (168S; for small current). Thus, for the case where the ratio of the High bit of the plurality of write registers 150 is high and the signal S3 becomes the High level, the voltage supply circuit VSETGEN_L having the current supply capability of the selection voltage VSET is large ( 166L; for high current) and voltage VRESET current supply capacity is small regulator circuit VRESETGEN_S (168S; for small current).

The voltage regulator circuit (166S, 166M, and 166L) for voltage VSET is supplied with a voltage VSETREF which becomes a reference voltage. Voltage regulator circuit for voltage VRESET (168S, 168M and 168L) are input with a voltage VSETREF which becomes a reference voltage.

Further, the wirings of S1, S2, and S3 supplied from the ratio comparing unit 142 are connected to the ground, and the NMOS transistors N1, N2, and N3 are connected. The gates of these NMOS transistors are each supplied with a control signal /APREB. Thus, during the precharge period shown in FIG. 9, the wirings of S1, S2, and S3 are pulled down to the Low level, and the six voltage regulator circuits included in the voltage regulator circuit 154 are kept non- Action state.

Next, the configuration of the voltage regulator circuit for the voltage VSET will be described with reference to FIG. 6(A), (B), and (C) are circuit diagrams of VSETGEN_S (166S; for small current), VSETGEN_M (166M; for medium current), and VSETGEN_L (166L for large current).

In FIG. 6(A), VSETGEN_S (166S) is configured via a comparator 170a and PMOS transistors 171a and 172a. The reference input potential VSETREF is supplied to the inverting input terminal of the comparator 170a. Further, for the non-inverting input terminal of the comparator 170a, the output VSET of VSETGEN_S (166S) is fed back. The drain of the PMOS transistor (output transistor) 172a is connected to the wiring of the output voltage VSET. Further, a voltage VPP is supplied to the source of the PMOS transistor 172a. Further, the gate of the PMOS transistor 172a is connected to the output terminal of the comparator 170a. Through the above configuration, for the case of the output voltage VSET < VSETREF, the PMOS The transistor 172a is turned on, and when the wiring of the output voltage VSET is charged by the PMOS transistor 172a via the voltage source VPP, the output voltage VSET is controlled in accordance with the reference voltage VSETREF.

Further, the drain of the PMOS transistor 171a is connected to the output terminal of the comparator 170a and the gate of the PMOS transistor 172a. Further, a voltage VPP is supplied to the source of the PMOS transistor 171a. Further, a signal S1 is supplied to the gate of the PMOS transistor 171a. Thus, for the case where S1 is a Low level (not selected), the PMOS transistor 171a is turned on, and the gate of the PMOS transistor 172a is pulled up to a High level. Thereby, the PMOS transistor (output transistor) 172a is turned off, and the regulator circuit VSETGEN_S (166S) is kept in a non-operating state. Further, when the signal S1 is supplied to the comparator 170a and S1 is at the Low level (not selected), the comparator 170a is stopped, and the current flowing through the comparator itself is reduced.

6(B) and (C), VSETGEN_M (166M) and VSETGEN_L (166L) are the same as the VSETGEN_S (166S) of FIG. 6(A) described above, and the description thereof will be omitted. However, the current drive capacities of the output transistors 172a, 172b, and 172c of the three regulator circuits are 172a, 172b, and 172c in a small order. In general, the current drive capability of a transistor can vary via gate width, channel length, threshold voltage, and the like. When increasing the gate width, shortening the channel length, and lowering the threshold voltage, the current drive capability is increased. Conversely, when the gate width is reduced, the channel length is increased, and the channel length is increased. At the threshold voltage, the current drive capability is reduced. Accordingly, the current drive capability of the output transistors 172a, 172b, and 172c in the above-described order is used as a factor of one or more of the gate width, the channel length, and the threshold voltage.

However, the configuration of the voltage regulator circuit for the voltage VRESET is not shown, but is the same as the configuration of the voltage regulator circuit for the voltage VSET of FIG. However, in the regulator circuit for voltage VRESET, the voltage VRESETREF is input as the reference potential.

(Operation of the first embodiment)

Next, the operation of the first embodiment will be described with reference to Fig. 8 . In the following description of the operation, in order to simplify the description, it is assumed that the number of written data to be simultaneously written is 8. In this case, the number of write registers 150 in FIG. 5 is 8, and eight EIO wiring systems EIO<i> and i=0 to 7 are output from each write register 150. Further, an impedance change type memory cell in which eight write data are written is used as a memory cell spacer shown in FIG. In addition, the 8-bit data is written (11010111). In this case, the ratio of the High bits in the plurality of write registers 150 is 0.75. In addition, the 8-bit write data (11010111) is in the internal IO line, and sequentially corresponds to the signals of IO_0, IO_1, ..., IO_6, and IO_7 from the left side. Further, the above 8-bit data and the column selection signal Y3_0-7 are all active, and eight impedance-change memory cells are selected via the upper column selection signals Y1 and Y2, and the data of each bit element is written.

Fig. 8 is a timing chart showing the operation of the semiconductor device 10 of the first embodiment. 8 is a sequential display, each display command (COM), reset signal RESET0, column select signal Y1, Y2, column select signal Y3, IO line signal IO_0-7, set signal SET0, write data (Write data ).

The operations at times t1 to t6 in Fig. 8 will be described. First, an activity command (not shown) is issued to select a (sub)word line, and then, at time t1, as shown in Fig. 8, a PROG command is issued. Here, the PROG instruction is an instruction to write data to the memory unit.

In the initial state of time t1 to t2, the column selection signals Y1, Y2, and Y3 are all unselected, and are Low levels. Therefore, the control signal C1 of FIG. 4 is a Low level in all the cells, and the bit line common source line connection relationship of the Y switch of each bit unit is turned on, and all the bit lines BL_0-511 are connected. The common source line 4 is turned on. Further, in the initial state, the reset signal RESET0 and the set signal SET0 are in the Low level. In addition, the potential of the common source line 4 and all of the bit lines BL_0-511 maintains the Low level.

Next, the time t2 to t3 is the operation period of the ratio detecting unit 141 of the internal power source generating circuit 32a described with reference to Fig. 9 . During this operation period, charging and discharging of the ratio detecting wiring 200 are performed. However, as shown in FIG. 8, at time t2, write data is set, and for a plurality of write registers 150, write data is held (11010111). In addition, for the IO line (IO_0-7), also lose There is a signal corresponding to the written data.

In the above example of writing data, the ratio of the High bits in the plurality of write registers 150 is 0.75. In the ratio detecting unit 141 of the ratio determining circuit 152 of FIG. 5, the ratio detecting wiring 200 is discharged at a high speed after precharging, and ARSELREF (the potential of the ratio detecting wiring 200) is lowered to a low voltage after discharging. Therefore, in the ratio comparing unit 142, S3 is in the High level, and in the voltage regulator circuit 154, the voltage regulator circuit VSETGEN_L (166L; for large current) and VRESETGEN_S (168S; for small current) are selected. ). As a result, a voltage VSET having a high output current supply capability and a voltage VRESET having a low current supply capability are provided.

Next, at time t3, RESET writing is started. Each of the column selection signals Y1, Y2 sets the column selection signal Y3_0-7, all of which are High levels (active), and eight bit lines are used as the selection bit lines. In addition, the reset signal RESET0 is taken as the High level. Thereby, the node NS of the source line driver (1c of FIG. 4, etc.) becomes the potential VRESET, and the potential VRESET is supplied to the common source line 4.

Further, in the Y-switch circuit (52 of FIG. 4, etc.) selected by the column selection signals Y1, Y2, and Y3, the control signal C1 becomes the High level, and the bit line selection switch 60 is turned on. The eight selected bit lines are turned on with the write amplifiers (41a to 41h). In addition, in the write amplifiers (41a to 41h), the reset signal RESET0 is the High level, corresponding to the IO line, the node Nout of the write amplifiers of the IO_2 and IO_4 of the Low level is grounded. Turn on, Becomes potential 0.

As described above, during the period from time t3 to time t4, the selected bit line corresponding to IO_2 and IO_4 becomes the potential 0, and the common source line 4 becomes the potential VRESET. And, the cell transistor corresponding to the selected sub-character line WL is turned on, and in the two impedance-varying memory cells corresponding to IO_2 and IO_4, from the common source line 4 to the direction of the selected bit line, by An impedance-changing element flows with a current. At this time, since the voltage regulator circuit VRESETGEN_S (168S) having a low current supply capability is selected, even if the ratio to the Low bit is low (the ratio of the high bit is high), for a small number of impedance-varying memory cells. In the case of performing RESET writing, it is also possible to supply an appropriate current from the source line driver (1c of FIG. 4, etc.) to the impedance varying element.

Then, after the selected two impedance change type elements are changed to the high impedance state, at time t4, the reset signal RESET0 and the column selection signal Y3_0-7 which are transferred to the RESET write are returned to the original Low level. . However, all of the bit lines BL_0-511 also serve as the potential 0.

Next, at time t5, SET writing is started. The signal IO_0-7 of the eight IO lines remains the same as the voltage of the signal of the data pattern (11010111) as in the case of RESET writing. Further, when the setting signal SET0 is shifted to the High level, the node NS of the source line driver (1c of FIG. 4, etc.) becomes the potential 0, and the potential 0 is supplied to the common source line 4.

In addition, in the write amplifiers (41a~41h), SET0 is the High level, corresponding to the IO0, IO_1, IO_3, IO_5, IO_6, IO_7 write amplifier nodes of the High level among the IO lines. Nout is turned on with the voltage source VSET and becomes the potential VSET.

As described above, during the period from time t5 to time t6, the selected bit line corresponding to IO_0, IO_1, IO_3, IO_5, IO_6, and IO_7 becomes the potential VSET, and the common source line 4 becomes the potential 0. And, the cell transistor corresponding to the selected sub-character line WL is turned on, and is selected from the common source line 4 in the six impedance-varying memory cells corresponding to IO_0, IO_1, IO_3, IO_5, IO_6, and IO_7. In the direction of the bit line, a current flows through the impedance varying element. At this time, since the voltage regulator circuit VSETGEN_L (166L) having a high current supply capability is selected, even if the ratio of the High bit is high, the SET writing is performed for a plurality of memory cells. The current supply is insufficient, and a suitable current is supplied from the write amplifier (41a of FIG. 4, etc.) to the impedance change type element.

At time t6, the signal that was migrated at the time of SET writing is returned to the original state, and is in the same state as the initial state t1.

However, in the above example, the case where the 8-bit write data is (11010111) and the High bit ratio becomes 0.75 is exemplified, but the ratio of the 8-bit high-order bit of the written data is not for sure. For example, there are various cases such as (00010000), where the ratio of High bits is low, and there is also the case where (11001010), the ratio of High bits is intermediate. Internal power generation circuit A in this embodiment In (32a), even if the number of write bits is not constant, the current supply amount of the voltage VRESET at the time of RESET writing and the current supply of the voltage VSET at the time of SET writing can be made in accordance with the ratio of the High bit. The amount is set to be appropriate.

As described above, according to the semiconductor device 10 of the first embodiment, the effects described below can be obtained.

First of all, even in the case of a plurality of written data, the number of write bits is not constant, and it is possible to select the best according to the ratio (or the ratio of Low bits) in the High bit of the written data. The regulator of the current supply capability. As a result, it is possible to obtain an effect of providing a stable current supply to each memory cell. As a result, it is possible to suppress unevenness in the impedance state of the memory cell after writing, and to secure a sufficient write margin.

Further, in the case where the number of write bits is small, it is possible to obtain an effect of reducing unnecessary power consumption by a regulator having a low current supply capability.

Further, as shown in FIG. 5, the ratio detecting unit 141 of the internal power generating circuit A can be configured via the PMOS transistor P1, the capacitor 164, and three NMOS transistors for each write register. Small wafer area and installer.

However, in FIG. 8, although eight write data are simultaneously written to the impedance change type memory cell in the memory cell pad of FIG. 3, it is not limited to this. In general, n is written to the register 150 (n is an arbitrary natural number, for example, Fig. 5 shows a case where n = 1024), and can be applied to the case where n impedance-change type memory cells are arranged for a plurality of memory cell pads which are distributed in the memory cell array 12. By.

However, in the voltage regulator circuit of FIG. 5, three voltage regulator circuits having different current supply capacities are prepared and switched, but the present invention is not limited thereto. For example, switching may be performed as a regulator circuit that prepares two current supply capacities. Alternatively, it is also possible to switch between the four or more voltage regulator circuits having different current supply capacities and to set the current supply capability to be finer.

In addition, in FIG. 5, one regulator circuit is selected as the outputs S1, S2, and S3 corresponding to the ratio comparison unit 142, but the present invention is not limited thereto. For example, as the output of the response ratio comparison unit 142, a regulator circuit of two or more may be combined and selected. As a result, the current supply capability can be set more finely.

(Modification 1 of the first embodiment)

Next, a modification 1 of the first embodiment will be described with reference to Fig. 7 . Fig. 7 is a circuit diagram showing a voltage regulator circuit (266S; for a small current) of a voltage VSET of the semiconductor device according to the first modification of the first embodiment. When comparing FIG. 7 with FIG. 6(A), it can be understood that the extraction circuit 190a is newly added to the regulator circuit (266S; for small current) of FIG. When the extraction circuit 190a performs the control for making the output voltage VSET match the reference voltage VSETREF, the wiring of the output voltage VSET is made for the case of VSET>VSETREF. In the grounded state, the electric charge of the wiring of the output voltage VSET is discharged to the ground to lower the output voltage VSET, and the output voltage VSET is controlled in accordance with the reference voltage VSETREF.

In FIG. 7, the extraction circuit 190a is configured via a comparator 180a, an NMOS transistor (181a, 182a), and an inverter circuit 183. The reference input potential VSETREF is supplied to the inverting input terminal of the comparator 180a. Further, for the non-inverting input terminal of the comparator 180a, the output voltage VSET of VSETGEN_S (266S) is fed back. The drain of the NMOS transistor 181a is connected to the wiring of the output voltage VSET. Further, the source of the NMOS transistor 181a is connected to the ground. Further, the gate of the NMOS transistor 181a is connected to the output terminal of the comparator 180a. According to the above configuration, when the output voltage VSET>VSETREF, the NMOS transistor 181a is turned on, and the electric charge of the wiring of the output voltage VSET is discharged by the NMOS transistor 181a, the output voltage VSET is at the reference potential. VSETREF is controlled consistently.

Further, the drain of the NMOS transistor 182a is connected to the output terminal of the comparator 180a and the gate of the NMOS transistor 181a. Further, the source of the NMOS transistor 182a is connected to the ground. Further, the gate of the NMOS transistor 182a is supplied with the signal S1 via the inverter circuit 183a. Thus, for the case where S1 is a Low level (not selected), the NMOS transistor 182a is turned on, and the gate of the NMOS transistor 181a is pulled down to the Low level. Thereby, the NMOS transistor 181a is turned off, and the regulator circuit is VSETGEN_S (166S) remains in the inactive state.

As described above, in the case where the output voltage VSET>VSETREF is applied, the output voltage VSET can be made high-speed and high-accuracy as the reference voltage VSETREF.

However, in FIG. 7, an example of the additional extraction circuit 190a is shown only for the voltage regulator circuit for the small current of the voltage VSET, but for the other five voltage regulator circuits (FIG. 5, 166M, 166L, 168S, 168M) In addition, 168L) is similarly added to the circuit, and the control of each regulator circuit can be made high speed and high precision.

As described above, according to the first modification of the first embodiment, the effect of the first embodiment can be obtained, and the effect of voltage control in each regulator circuit can be performed at high speed and with high precision. As a result, it is possible to stabilize the writing operation for the memory unit.

(Second embodiment)

Next, the second embodiment will be described with reference to Figs. 10 and 11 . Fig. 10 is a circuit diagram showing an internal power supply circuit A (132a) of the semiconductor device of the second embodiment. When comparing FIG. 10 with FIG. 5 (the first embodiment), it can be understood that in the internal power supply generating circuit A (132a) of FIG. 10, in the voltage regulator circuit 254, the voltage for RESET writing is used. The current supply capability of VRESET is not variably controlled, but is generated only by the regulator circuit VRESETGEN_L (168L; for large current). The other points are the same as in the first embodiment, and the same reference numerals are attached. The explanation is omitted.

As described above, the case where the current supply capability of the voltage VRESET is generated only via VRESETGEN_L (168L; for large current) is optimal for executing the write sequence shown in FIG. That is, regardless of the write data, after the RESET write is performed on the impedance change type element corresponding to all the bits, the SET write is performed on the impedance change type element corresponding to the High bit among the write data. The situation.

Next, the operation of the semiconductor device according to the second embodiment will be described with reference to Fig. 11. The reason why the configuration of Fig. 10 is optimized in the write sequence of Fig. 11 will be described. In the second embodiment, similarly to FIG. 8 (the first embodiment), it is assumed that eight write data (11010111) are simultaneously written.

First, in FIG. 11, the time t12 is the same as that from FIG. 8 to the time t2, and the description thereof is omitted. Next, at time t12 to t13, RESET writing of (00000000) is performed without writing data by the eight impedance change type memory cells corresponding to the write data. In this case, the signal IO_i (i = 0 to 7) of the IO line, and the plurality of write registers 150 are set to (00000000).

In this case, the ratio of the High bit in the plurality of write registers 150 is often 0, because the RESET write is performed for the memory unit which is often the maximum number (eight in this case). The voltage regulator circuit 254 is preferably a voltage VRESET having a high output current supply capability. Therefore, in the second embodiment, as the voltage regulator circuit for the voltage VRESET, only VRESETGEN_L (168L; for large current) is provided. As a voltage VRESET having a high output current supply capability. Accordingly, the voltage regulator circuit (168M, 168S) for the voltage VRESET of the first embodiment can be eliminated, and the circuit scale can be reduced.

In addition, the following advantages can be obtained by using the write sequence of FIG. As shown in FIG. 2, in the case where the source lines are shared to form a common source line (4 to 6), when the potential of the common source line (4 to 6) is frequently changed, there is a peak. The problem of current. In order to deal with this problem, as shown in FIG. 11, when the RESET writing is performed once, the potential of the common source line (4 to 6) is not frequently changed, and the generation of the peak current is suppressed.

Next, when the RESET write of time t12 to t13 is completed, at time t13, the reset signal RESET0 and the column selection signal Y3 which are written and transferred by RESET are returned to the original state.

Next, the time t14 to t15 is the same period as the time t2 to t3 of Fig. 8 (first embodiment). During this period, charging and discharging of the ratio detecting wiring 200 are performed. The description of the operation in this period is omitted by repeating the first embodiment.

Next, at time t15 to t16, SET writing is started. The operation in this period is the same as the time t5 to t6 in Fig. 8 (first embodiment), and the description thereof is omitted.

Finally, at time t16, the signal that was migrated at the time of SET writing is returned to the original state, which is the same state as the initial state t11.

As described above, in the second embodiment, the effect of the first embodiment is obtained, and the circuit scale of the reduced voltage regulator circuit can be obtained. Effect. In particular, as shown in FIG. 11, the impedance change corresponding to the High bit in the write data after the RESET write is performed regardless of the write data, and for the impedance change type element corresponding to all the bits. The voltage regulator circuit 254 of the second embodiment is preferably the case where the type of the device is written in the SET write sequence.

However, the second embodiment can be modified as follows. In other words, in the voltage regulator circuit, the voltage VSET at the time of SET writing can be formed only by the voltage regulator circuit having a high current supply capability, and the current supply capability of the voltage VRESET at the time of RESET writing can be used. Variable control. Such a voltage regulator circuit is replaced by the write sequence of FIG. 11, regardless of the write data, and for the impedance change type element corresponding to the full bit, after the SET write, the correspondence to the write data It is preferable to perform the RESET write sequence for the impedance change type element of the Low bit.

[Industry use possibility]

The present application discloses that a memory system in which a current is supplied to a memory cell and a write mode is applied is generally applicable. Especially for a memory system in which the number of written bits is not constant, it is optimal for the user.

However, within the framework of the full disclosure of the present invention (including the scope and drawings of the patent application), according to the basic technical idea, the embodiment may be changed. Adjustment. In addition, within the framework of the entire disclosure of the present invention, various combinations of the disclosed elements (including each element of each application, each element of each embodiment, each element of each drawing, etc.) can be made. select. That is, the present invention naturally includes the full disclosure of the scope of the patent application and the drawings, and various modifications and corrections that can be made with the technical idea of the company. In particular, any numerical value or even a small range that is included in the range of the specification is to be construed as being specifically described.

32a‧‧‧Internal power generation circuit A

141‧‧‧ Ratio Detection Department

142‧‧‧ Ratio Comparison Department

150‧‧‧Write to scratchpad

152‧‧‧Rate determination circuit

154‧‧‧Voltage regulator circuit

156a, 156b, 156c‧‧‧ comparator

158‧‧‧Delay circuit

160‧‧‧Inverter circuit

162‧‧‧AND circuit

164‧‧‧ capacitor

166S‧‧‧VSETGEN_S (VSET regulator circuit (for small current))

166L‧‧‧VSETGEN_L (VSET voltage regulator circuit (for high current))

168S‧‧‧VRESETGEN_S (VRESET regulator circuit (for small current))

168L‧‧‧VRESETGEN_L (VRESET regulator circuit (for high current))

166M‧‧‧VSETGEN_M (VSET voltage regulator circuit (for medium current))

168M‧‧‧VRESETGEN_M (VRESET regulator circuit (for current))

200‧‧‧ Ratio detection wiring (internal wiring)

VDD‧‧‧ potential

APREB‧‧‧ control signal

DEC‧‧‧ supply control signal

VINTREF‧‧‧ bias voltage

EIO<0>~<1023>‧‧‧ wiring

Na0~Na1023, Nb0~Nb1023, Nc0~Nc1023‧‧‧ NMOS transistor

VCREF1, VCREF2‧‧‧ reference potential

S1, S2, S3‧‧‧ output

N1, N2, N3‧‧‧ NMOS transistors

/APREB‧‧‧Control signal

VSET, VSETREF, VRESET, VRESETREF‧‧‧ voltage

P1‧‧‧ PMOS transistor

Claims (11)

A semiconductor device comprising: a plurality of memory cells; and a write register holding a plurality of write data written in a plurality of memory cells of said plurality of memory cells, and determining to remain in said plurality of writes a ratio determination circuit for ratios of the first data and the second data of the plurality of written data of the temporary register, and a first power supply voltage used for writing the first data, and the second data The voltage regulator circuit of the second power supply voltage used for writing, the voltage regulator circuit controlling at least one of the first power supply voltage and the second power supply voltage based on an output of the ratio determination circuit Current supply capability. The semiconductor device according to claim 1, wherein the voltage regulator circuit includes at least one of a current supply capability different from at least one of the first power supply voltage and the second power supply voltage. The regulator circuit selects the regulator circuit to be used among the two or more voltage regulator circuits in accordance with the output of the ratio determination circuit. The semiconductor device according to claim 2, wherein the current driving capability of the output transistors of the two or more voltage regulator circuits is different from each other. Such as the semiconductor package described in the second or third paragraph of the patent application The ratio determination circuit includes: an internal wiring; and a first switching element that controls the conduction/non-conduction of each of the plurality of write data held by the plurality of write registers; One end of each of the plurality of first switching elements is connected to the internal wiring, and the internal wiring is precharged at a specific potential, and the precharged electric charge is passed through the plurality of first switching elements. The potential of the internal wiring at the time of discharge is performed in the first switching element in the on state, and the ratio is determined. The semiconductor device according to claim 4, wherein in the ratio determination circuit, a constant current source is connected in series to each of the plurality of first switching elements. The semiconductor device according to claim 4, wherein the ratio determination circuit further includes: a comparator that compares potentials of two input terminals by one or more, and inputs to one of the comparators The terminal is connected to the ratio detecting wiring, and one of the reference potentials of one or more is supplied to the other input terminal of each of the comparators, and the potential of the ratio detecting wiring is output in accordance with the output of each of the comparators. It is related to the magnitude of the reference potential of 1 or more. The semiconductor device according to claim 6, wherein the ratio determination circuit further includes a delay circuit, and compares the time from the completion of the precharge to the delay time generated by the delay circuit, and then compares the comparators. By. The semiconductor device according to claim 6 or 7, wherein the voltage regulator circuit selects the voltage regulator circuit according to the magnitude relationship output by the ratio determination circuit. The aforementioned regulator circuit is used. The semiconductor device according to the second aspect of the invention, wherein the voltage regulator circuit includes: a regulator circuit having two or more different current supply capacities for the first power supply voltage; (2) only one of the power supply voltages, after the second power supply voltage is supplied to the memory unit corresponding to each of the first and second data, and the second data is written And writing the first data to the memory unit corresponding to the first data by supplying the first power supply voltage. The semiconductor device according to the second aspect of the invention, wherein the voltage regulator circuit includes: a regulator circuit having two or more different current supply capacities for the second power supply voltage; a voltage regulator circuit of only one power supply voltage, in the memory of the plural number corresponding to each of the first and second data The unit supplies the first power supply voltage and writes the first data, and supplies the second power supply voltage to the memory unit corresponding to the second data to perform the writing of the second data. The semiconductor device according to any one of claims 1 to 10, wherein the memory unit corresponds to the first and second materials, and has impedances written in mutually different impedance states. Variant components.