TW201510706A - Power-on-reset circuit - Google Patents

Power-on-reset circuit Download PDF

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TW201510706A
TW201510706A TW102132671A TW102132671A TW201510706A TW 201510706 A TW201510706 A TW 201510706A TW 102132671 A TW102132671 A TW 102132671A TW 102132671 A TW102132671 A TW 102132671A TW 201510706 A TW201510706 A TW 201510706A
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reset
power
reset signal
reference voltage
unit
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TW102132671A
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TWI497267B (en
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Chun-Chi Chang
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Himax Tech Ltd
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Abstract

A power-on-reset circuit includes a voltage reference detect unit coupled to receive a bandgap voltage reference. A first compare unit is configured to compare a first power with the bandgap voltage reference; and a second compare unit is configured to compare a second power with the bandgap voltage reference. When outputs of the voltage reference detect unit, the first compare unit and the second compare unit are identified, a first reset signal generating unit outputs a first reset signal that switches from a reset mode to a normal mode. When a trigger signal becomes active, a second reset signal generating unit outputs a second reset signal that switches from a reset mode to a normal mode according to the first reset signal.

Description

電源開啟重置電路Power on reset circuit

本發明係有關一種電源開啟重置電路,特別是關於一種僅使用單一能隙參考電壓的電源開啟重置電路。The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit that uses only a single bandgap reference voltage.

電源開啟重置(power-on-reset, POR)電路普遍使用於積體電路中,用以偵測積體電路的供給電源並據以產生重置信號,使得積體電路進行初始化而得以進入預設的狀態。A power-on-reset (POR) circuit is commonly used in an integrated circuit to detect the supply of the integrated circuit and generate a reset signal to initialize the integrated circuit. Set the status.

能隙(bandgap)參考電壓由於不受溫度變化而改變電壓輸出,因此廣泛使用於電源開啟重置電路及其他電路中作為參考電壓。由於當今的積體電路通常包含有數位電路及類比電路,因此需要分別供給數位電路電源及類比電路電源。由於數位電路電源及類比電路電源的電壓位準不同,因此電源開啟重置電路需要使用二能隙參考電壓(一為高壓(HV)能隙參考電壓,另一為低壓(LV)能隙參考電壓),因而佔用相當的電路面積且增加製造成本。The bandgap reference voltage is widely used in the power-on reset circuit and other circuits as a reference voltage because it does not change the voltage output due to temperature changes. Since today's integrated circuits usually include digital circuits and analog circuits, it is necessary to separately supply digital circuit power and analog circuit power. Since the voltage level of the digital circuit power supply and the analog circuit power supply are different, the power-on reset circuit needs to use the two-gap reference voltage (one is the high voltage (HV) bandgap reference voltage, and the other is the low voltage (LV) bandgap reference voltage. ), thus occupying a considerable circuit area and increasing manufacturing costs.

因此亟需提出一種新穎的電源開啟重置電路,用以解決傳統電源開啟重置電路的缺點且不會犧牲重置的效能。Therefore, it is urgent to propose a novel power-on reset circuit to solve the shortcomings of the conventional power-on reset circuit without sacrificing the performance of the reset.

鑑於上述,本實施例提出一種電源開啟重置電路,其僅使用單一能隙參考電壓,用以節省相當的電路面積。In view of the above, the present embodiment proposes a power-on reset circuit that uses only a single bandgap reference voltage to save considerable circuit area.

根據本發明實施例,電源開啟重置電路包含能隙參考電壓、參考電壓偵測單元、第一比較單元、第二比較單元、第一重置信號產生單元及第二重置信號產生單元。參考電壓偵測單元接收能隙參考電壓的輸出,用以偵測能隙參考電壓是否已啟動。第一比較單元比較調整之第一電源與能隙參考電壓;第二比較單元比較調整之第二電源與能隙參考電壓。第一重置信號產生單元接收參考電壓偵測單元的輸出、第一比較單元的輸出與第二比較單元的輸出,當參考電壓偵測單元、第一比較單元與第二比較單元的所有輸出皆確認時,第一重置信號產生單元所輸出的第一重置信號由重置模式轉變為正常狀態。第二重置信號產生單元根據第一重置信號及觸發信號以產生第二重置信號,當觸發信號為主動時,第二重置信號產生單元即根據第一重置信號而使得第二重置信號由重置模式轉變為正常狀態。According to an embodiment of the invention, the power-on reset circuit includes a bandgap reference voltage, a reference voltage detecting unit, a first comparing unit, a second comparing unit, a first reset signal generating unit, and a second reset signal generating unit. The reference voltage detecting unit receives the output of the bandgap reference voltage to detect whether the bandgap reference voltage has been activated. The first comparing unit compares the adjusted first power source with the bandgap reference voltage; and the second comparing unit compares the adjusted second power source with the bandgap reference voltage. The first reset signal generating unit receives the output of the reference voltage detecting unit, the output of the first comparing unit, and the output of the second comparing unit, when all outputs of the reference voltage detecting unit, the first comparing unit, and the second comparing unit are Upon confirmation, the first reset signal output by the first reset signal generating unit is changed from the reset mode to the normal state. The second reset signal generating unit generates a second reset signal according to the first reset signal and the trigger signal. When the trigger signal is active, the second reset signal generating unit makes the second weight according to the first reset signal. The set signal changes from the reset mode to the normal state.

第一圖顯示本發明實施例之電源開啟重置(power-on-reset, POR)電路100的系統方塊圖。本實施例之電源開啟重置電路100可適用於雙電源(例如數位電路電源VDDD及類比電路電源VDDA)系統以進行電源開啟重置。The first figure shows a system block diagram of a power-on-reset (POR) circuit 100 in accordance with an embodiment of the present invention. The power-on reset circuit 100 of the present embodiment can be applied to a dual power supply (for example, a digital circuit power supply VDDD and an analog circuit power supply VDDA) system for power-on reset.

電源開啟重置電路100包含參考電壓偵測單元12,其接收能隙(bandgap)參考電壓11的輸出,用以偵測能隙參考電壓11是否已啟動(start up)或者是否已達穩定的輸出。電源開啟重置電路100還包含二比較單元,亦即,第一比較單元13與第二比較單元14。其中,第一比較單元13比較調整之第一電源VDDD(例如數位電路電源)與能隙參考電壓11,該調整之第一電源VDDD可由分壓器而得到,如第一圖所示。類似的情形,第二比較單元14比較調整之第二電源VDDA(例如類比電路電源)與能隙參考電壓11,該調整之第二電源VDDA可由分壓器而得到,如第一圖所示。The power-on reset circuit 100 includes a reference voltage detecting unit 12 that receives an output of a bandgap reference voltage 11 for detecting whether the bandgap reference voltage 11 has been started up or has reached a stable output. . The power-on reset circuit 100 further includes two comparison units, that is, a first comparison unit 13 and a second comparison unit 14. The first comparing unit 13 compares the adjusted first power source VDDD (for example, a digital circuit power source) with the band gap reference voltage 11, and the adjusted first power source VDDD can be obtained by a voltage divider, as shown in the first figure. In a similar situation, the second comparison unit 14 compares the adjusted second power supply VDDA (eg, analog circuit power supply) with the bandgap reference voltage 11, and the adjusted second power supply VDDA can be obtained by a voltage divider, as shown in the first figure.

電源開啟重置電路100還包含第一重置信號產生單元15,其接收參考電壓偵測單元12的輸出BG、第一比較單元13的輸出CMP_D與第二比較單元14的輸出CMP_A。當參考電壓偵測單元12、第一比較單元13與第二比較單元14的所有輸出皆確認時(亦即,能隙參考電壓11已啟動,調整之第一電源VDDD大於能隙參考電壓11,且調整之第二電源VDDA大於能隙參考電壓11時),第一重置信號產生單元15所輸出的第一重置信號NEWPU由重置(reset)模式轉變為正常(normal)狀態,使得數位系統由重置模式轉為正常模式。The power-on reset circuit 100 further includes a first reset signal generating unit 15 that receives the output BG of the reference voltage detecting unit 12, the output CMP_D of the first comparing unit 13, and the output CMP_A of the second comparing unit 14. When all the outputs of the reference voltage detecting unit 12, the first comparing unit 13 and the second comparing unit 14 are confirmed (that is, the bandgap reference voltage 11 is activated, the adjusted first power source VDDD is greater than the bandgap reference voltage 11, And the adjusted second power source VDDA is greater than the bandgap reference voltage 11), the first reset signal NEWPU output by the first reset signal generating unit 15 is changed from a reset mode to a normal state, so that the digit The system changes from reset mode to normal mode.

此外,電源開啟重置電路100包含第二重置信號產生單元16,其根據第一重置信號NEWPU及觸發信號TP*4以產生第二重置信號Reset_C。在本實施例中,觸發信號TP*4係於第一重置信號NEWPU由重置模式轉為正常狀態後,藉由計數電路(未顯示於圖式中)計數達到一段預設時間(例如四個週期)後所產生。當觸發信號TP*4為主動時,第二重置信號產生單元16即根據第一重置信號NEWPU而使得第二重置信號Reset_C由重置(reset)模式轉變為正常(normal)狀態,使得類比系統由重置模式轉為正常模式。In addition, the power-on reset circuit 100 includes a second reset signal generating unit 16 that generates a second reset signal Reset_C according to the first reset signal NEWPU and the trigger signal TP*4. In this embodiment, the trigger signal TP*4 is counted by the counting circuit (not shown in the figure) after the first reset signal NEWPU is changed from the reset mode to the normal state (for example, four). Generated after each cycle). When the trigger signal TP*4 is active, the second reset signal generating unit 16 causes the second reset signal Reset_C to transition from the reset mode to the normal state according to the first reset signal NEWPU, such that The analog system switches from reset mode to normal mode.

第二圖顯示第一圖之電源開啟重置電路100的實施例詳細電路圖。圖式中的HV代表高壓(high voltage),LV則代表低壓(low voltage),而LS則代表位移(level shift)。在本實施例中,參考電壓偵測單元12包含複數串聯緩衝器(例如反向緩衝器)且並聯有電容器。第一比較單元13與第二比較單元14分別由比較器組成,其中,第一比較單元13的比較器之正輸入端接收調整之第一電源VDDD,而負輸入端接收能隙參考電壓11。類似的情形,第二比較單元14的比較器之正輸入端接收調整之第二電源VDDA,而負輸入端接收能隙參考電壓11。The second figure shows a detailed circuit diagram of an embodiment of the power-on reset circuit 100 of the first figure. In the figure, HV stands for high voltage, LV stands for low voltage, and LS stands for level shift. In the present embodiment, the reference voltage detecting unit 12 includes a plurality of series buffers (for example, an inverting buffer) and has capacitors connected in parallel. The first comparison unit 13 and the second comparison unit 14 are respectively composed of comparators, wherein the positive input terminal of the comparator of the first comparison unit 13 receives the adjusted first power supply VDDD, and the negative input terminal receives the energy gap reference voltage 11. In a similar situation, the positive input of the comparator of the second comparison unit 14 receives the adjusted second power supply VDDA and the negative input receives the energy gap reference voltage 11.

本實施例之第一重置信號產生單元15主要包含三輸入之反及閘(NAND),其三個輸入端分別接收參考電壓偵測單元12的輸出BG、第一比較單元13的輸出CMP_D與第二比較單元14的輸出CMP_A。第一重置信號產生單元15之後還可串接至少一緩衝器(例如反向緩衝器)17。The first reset signal generating unit 15 of the present embodiment mainly includes a three-input NAND gate, and the three input terminals respectively receive the output BG of the reference voltage detecting unit 12 and the output CMP_D of the first comparing unit 13 and The output CMP_A of the second comparison unit 14. The first reset signal generating unit 15 may be followed by at least one buffer (for example, an inverting buffer) 17 in series.

本實施例之第二重置信號產生單元16主要包含閂鎖器(latch)161及反或閘(NOR)162。其中,閂鎖器161接收第一重置信號產生單元15之反及閘的輸出NAND及觸發信號TP*4,而反或閘162的二輸入端則分別接收第一重置信號產生單元15之反及閘的輸出NAND及閂鎖器161的輸出TP。第二重置信號產生單元16之反或閘162還可包含第三輸入端,以輸入一強制重置信號Reset,用以強制進行重置。第二重置信號產生單元16之後還可串接至少一緩衝器(例如反向緩衝器)18。The second reset signal generating unit 16 of this embodiment mainly includes a latch 161 and a reverse OR gate (NOR) 162. The latch 161 receives the output NAND of the reverse gate of the first reset signal generating unit 15 and the trigger signal TP*4, and the two inputs of the inverse gate 162 receive the first reset signal generating unit 15 respectively. The output NAND of the gate and the output TP of the latch 161 are reversed. The inverse OR gate 162 of the second reset signal generating unit 16 may further include a third input terminal for inputting a forced reset signal Reset for forcibly resetting. The second reset signal generating unit 16 may also be followed by at least one buffer (e.g., an inverting buffer) 18.

第三圖例示第二圖之電源開啟重置電路100主要信號的時序圖,其中第二電源VDDA的啟動早於第一電源VDDD。於時間t1,參考電壓偵測單元12的輸出BG、第一比較單元13的輸出CMP_D與第二比較單元14的輸出CMP_A皆確認(例如,高準位),此時第一重置信號產生單元15之反及閘的輸出NAND轉為低準位,因而使得第一重置信號NEWPU由重置模式(低準位)轉變為正常狀態(高準位)。於時間t2,觸發信號TP*4轉為主動(高準位),使得閂鎖器161的輸出TP轉為低準位,因而使得第二重置信號Reset_C由重置模式(高準位)轉變為正常狀態(低準位)。第四圖例示第二圖之電源開啟重置電路100主要信號的另一時序圖。與第三圖不同的是,第四圖當中第一電源VDDD的啟動係早於第二電源VDDA。第四圖之電源開啟重置電路100的運作類似於第三圖,其細節因此省略。The third diagram illustrates a timing diagram of the main signal of the power-on reset circuit 100 of the second diagram, wherein the second power supply VDDA is activated earlier than the first power supply VDDD. At time t1, the output BG of the reference voltage detecting unit 12, the output CMP_D of the first comparing unit 13 and the output CMP_A of the second comparing unit 14 are all confirmed (for example, a high level), and the first reset signal generating unit at this time The output NAND of the reverse gate of 15 turns to a low level, thus causing the first reset signal NEWPU to transition from the reset mode (low level) to the normal state (high level). At time t2, the trigger signal TP*4 is turned to active (high level), so that the output TP of the latch 161 is turned to a low level, thereby causing the second reset signal Reset_C to be changed from the reset mode (high level). It is in the normal state (low level). The fourth diagram illustrates another timing diagram of the main signal of the power-on reset circuit 100 of the second diagram. Different from the third figure, the first power supply VDDD in the fourth figure is activated earlier than the second power supply VDDA. The operation of the power-on reset circuit 100 of the fourth diagram is similar to the third diagram, and the details thereof are therefore omitted.

根據上述實施例,電源開啟重置電路100僅使用單一能隙(bandgap)參考電壓11,例如高壓(HV)能隙參考電壓。相較於傳統雙電源之電源開啟重置電路需使用二能隙參考電壓(一為高壓(HV)能隙參考電壓,另一為低壓(LV)能隙參考電壓),本實施例因僅使用單一能隙參考電壓11,因而可以節省相當的電路面積。According to the above embodiment, the power-on reset circuit 100 uses only a single bandgap reference voltage 11, such as a high voltage (HV) bandgap reference voltage. Compared with the traditional dual power supply, the reset circuit needs to use the two-gap reference voltage (one is the high voltage (HV) bandgap reference voltage and the other is the low voltage (LV) bandgap reference voltage). This embodiment is only used. A single bandgap reference voltage of 11, thus saving considerable circuit area.

以上所述僅為本發明之較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

100‧‧‧電源開啟重置電路
11‧‧‧能隙參考電壓
12‧‧‧參考電壓偵測單元
13‧‧‧第一比較單元
14‧‧‧第二比較單元
15‧‧‧第一重置信號產生單元
16‧‧‧第二重置信號產生單元
161‧‧‧閂鎖器
162‧‧‧反或閘
17‧‧‧緩衝器
18‧‧‧緩衝器
VDDD‧‧‧第一電源
VDDA‧‧‧第二電源
BG‧‧‧參考電壓偵測單元的輸出
CMP_D‧‧‧第一比較單元的輸出
CMP_A‧‧‧第二比較單元的輸出
NEWPU‧‧‧第一重置信號
Reset_C‧‧‧第二重置信號
TP*4‧‧‧觸發信號
NAND‧‧‧反及閘的輸出
TP‧‧‧閂鎖器的輸出
Reset‧‧‧強制重置信號
100‧‧‧Power-on reset circuit
11‧‧‧Gap gap reference voltage
12‧‧‧Reference voltage detection unit
13‧‧‧ first comparison unit
14‧‧‧Second comparison unit
15‧‧‧First reset signal generating unit
16‧‧‧Second reset signal generating unit
161‧‧‧Latch
162‧‧‧Anti-gate
17‧‧‧ buffer
18‧‧‧ buffer
VDDD‧‧‧first power supply
VDDA‧‧‧second power supply
BG‧‧‧ Output of reference voltage detection unit
CMP_D‧‧‧ Output of the first comparison unit
CMP_A‧‧‧ Output of the second comparison unit
NEWPU‧‧‧First reset signal
Reset_C‧‧‧Second reset signal
TP*4‧‧‧ trigger signal
NAND‧‧‧ anti-gate output
TP‧‧‧Latch output
Reset‧‧‧Forced reset signal

第一圖顯示本發明實施例之電源開啟重置電路的系統方塊圖。 第二圖顯示第一圖之電源開啟重置電路的實施例詳細電路圖。 第三圖例示第二圖之電源開啟重置電路主要信號的時序圖。 第四圖例示第二圖之電源開啟重置電路主要信號的另一時序圖。The first figure shows a system block diagram of a power-on reset circuit in accordance with an embodiment of the present invention. The second figure shows a detailed circuit diagram of an embodiment of the power-on reset circuit of the first figure. The third figure illustrates a timing diagram of the main signals of the power-on reset circuit of the second figure. The fourth figure illustrates another timing diagram of the main signal of the power-on reset circuit of the second figure.

100‧‧‧電源開啟重置電路 100‧‧‧Power-on reset circuit

11‧‧‧能隙參考電壓 11‧‧‧Gap gap reference voltage

12‧‧‧參考電壓偵測單元 12‧‧‧Reference voltage detection unit

13‧‧‧第一比較單元 13‧‧‧ first comparison unit

14‧‧‧第二比較單元 14‧‧‧Second comparison unit

15‧‧‧第一重置信號產生單元 15‧‧‧First reset signal generating unit

16‧‧‧第二重置信號產生單元 16‧‧‧Second reset signal generating unit

VDDD‧‧‧第一電源 VDDD‧‧‧first power supply

VDDA‧‧‧第二電源 VDDA‧‧‧second power supply

BG‧‧‧參考電壓偵測單元的輸出 BG‧‧‧ Output of reference voltage detection unit

CMP_D‧‧‧第一比較單元的輸出 CMP_D‧‧‧ Output of the first comparison unit

CMP_A‧‧‧第二比較單元的輸出 CMP_A‧‧‧ Output of the second comparison unit

NEWPU‧‧‧第一重置信號 NEWPU‧‧‧First reset signal

Reset_C‧‧‧第二重置信號 Reset_C‧‧‧Second reset signal

TP*4‧‧‧觸發信號 TP*4‧‧‧ trigger signal

Claims (12)

一種電源開啟重置電路,包含:        一能隙參考電壓;        一參考電壓偵測單元,其接收該能隙參考電壓的輸出,用以偵測該能隙參考電壓是否已啟動;        一第一比較單元,其比較調整之第一電源與該能隙參考電壓;        一第二比較單元,其比較調整之第二電源與該能隙參考電壓;        一第一重置信號產生單元,其接收該參考電壓偵測單元的輸出、該第一比較單元的輸出與該第二比較單元的輸出,當該參考電壓偵測單元、該第一比較單元與該第二比較單元的所有輸出皆確認時,該第一重置信號產生單元所輸出的第一重置信號由重置模式轉變為正常狀態;及        一第二重置信號產生單元,其根據該第一重置信號及觸發信號以產生第二重置信號,當該觸發信號為主動時,該第二重置信號產生單元即根據該第一重置信號而使得該第二重置信號由重置模式轉變為正常狀態。A power-on reset circuit includes: a bandgap reference voltage; a reference voltage detecting unit that receives an output of the bandgap reference voltage to detect whether the bandgap reference voltage has been activated; a first comparing unit Comparing the adjusted first power source with the bandgap reference voltage; a second comparing unit comparing the adjusted second power source with the bandgap reference voltage; a first reset signal generating unit receiving the reference voltage The output of the measuring unit, the output of the first comparing unit, and the output of the second comparing unit, when the output of the reference voltage detecting unit, the first comparing unit, and the second comparing unit are all confirmed, the first The first reset signal outputted by the reset signal generating unit is changed from the reset mode to the normal state; and a second reset signal generating unit is configured to generate the second reset signal according to the first reset signal and the trigger signal When the trigger signal is active, the second reset signal generating unit is based on the first reset Such that the number of second reset signal changes from the reset mode to the normal state. 根據申請專利範圍第1項所述之電源開啟重置電路,更包含一分壓器,用以提供該調整之第一電源。The power-on reset circuit according to claim 1 of the patent application scope further includes a voltage divider for providing the adjusted first power source. 根據申請專利範圍第1項所述之電源開啟重置電路,更包含一分壓器,用以提供該調整之第二電源。The power-on reset circuit according to claim 1 of the patent application scope further includes a voltage divider for providing the adjusted second power source. 根據申請專利範圍第1項所述之電源開啟重置電路,其中該觸發信號係於該第一重置信號由重置模式轉為正常狀態後,藉由計數電路計數達到一段預設時間後所產生。The power-on reset circuit according to the first aspect of the patent application, wherein the trigger signal is after the first reset signal is changed from the reset mode to the normal state, and after the counting circuit reaches a preset time period, produce. 根據申請專利範圍第1項所述之電源開啟重置電路,其中該參考電壓偵測單元包含複數串聯緩衝器,及並聯的電容器。The power-on reset circuit of claim 1, wherein the reference voltage detecting unit comprises a plurality of series buffers, and capacitors connected in parallel. 根據申請專利範圍第1項所述之電源開啟重置電路,其中該第一比較單元包含一比較器,其正輸入端接收該調整之第一電源,且負輸入端接收該能隙參考電壓。The power-on reset circuit of claim 1, wherein the first comparison unit comprises a comparator, the positive input terminal receives the adjusted first power source, and the negative input terminal receives the energy gap reference voltage. 根據申請專利範圍第1項所述之電源開啟重置電路,其中該第二比較單元包含一比較器,其正輸入端接收該調整之第二電源,且負輸入端接收該能隙參考電壓。The power-on reset circuit of claim 1, wherein the second comparison unit comprises a comparator, the positive input terminal receives the adjusted second power supply, and the negative input terminal receives the energy gap reference voltage. 根據申請專利範圍第1項所述之電源開啟重置電路,其中該第一重置信號產生單元包含三輸入之反及閘(NAND),其三個輸入端分別接收該參考電壓偵測單元的輸出、該第一比較單元的輸出與該第二比較單元的輸出。The power-on reset circuit according to claim 1, wherein the first reset signal generating unit includes a three-input NAND gate, and three input terminals respectively receive the reference voltage detecting unit. An output, an output of the first comparison unit, and an output of the second comparison unit. 根據申請專利範圍第1項所述之電源開啟重置電路,更包含至少一緩衝器,串接於該第一重置信號產生單元之後。The power-on reset circuit of claim 1 further includes at least one buffer connected in series after the first reset signal generating unit. 根據申請專利範圍第8項所述之電源開啟重置電路,其中該第二重置信號產生單元包含:        一閂鎖器,其接收該第一重置信號產生單元之反及閘的輸出及該觸發信號;及        一反或閘(NOR),其二輸入端分別接收該第一重置信號產生單元之反及閘的輸出及該閂鎖器的輸出。The power-on reset circuit of claim 8, wherein the second reset signal generating unit comprises: a latch that receives an output of the reverse gate of the first reset signal generating unit and the a trigger signal; and a reverse OR gate (NOR), the two input terminals respectively receiving the output of the reverse gate of the first reset signal generating unit and the output of the latch. 根據申請專利範圍第10項所述之電源開啟重置電路,其中該第二重置信號產生單元之反或閘更包含第三輸入端,以輸入一強制重置信號,用以強制進行重置。The power-on reset circuit according to claim 10, wherein the inverse of the second reset signal generating unit further includes a third input terminal for inputting a forced reset signal for forcibly resetting . 根據申請專利範圍第1項所述之電源開啟重置電路,更包含至少一緩衝器,串接於該第二重置信號產生單元之後。The power-on reset circuit of claim 1 further includes at least one buffer connected in series with the second reset signal generating unit.
TW102132671A 2013-09-10 2013-09-10 Power-on-reset circuit TWI497267B (en)

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Cited By (2)

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US9673808B1 (en) 2016-01-12 2017-06-06 Faraday Technology Corp. Power on-reset circuit
CN111426866A (en) * 2019-01-10 2020-07-17 新唐科技股份有限公司 Voltage monitoring system and method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673808B1 (en) 2016-01-12 2017-06-06 Faraday Technology Corp. Power on-reset circuit
TWI613542B (en) * 2016-01-12 2018-02-01 智原科技股份有限公司 Power-on-reset circuit
CN111426866A (en) * 2019-01-10 2020-07-17 新唐科技股份有限公司 Voltage monitoring system and method thereof
CN111426866B (en) * 2019-01-10 2023-02-03 新唐科技股份有限公司 Voltage monitoring system and method thereof

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