TW201508743A - Spin transfer torque based memory elements for programmable device arrays - Google Patents

Abstract

Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Description

Memory component based on spin transfer torque for a programmable array of devices

The present invention relates generally to the field of integrated circuits used in high-capacity computer architectures and reconfigurable systems including wafer systems (SoCs), and more particularly to non-volatile memories using spin transfer torque (STT) effects. Body devices and systems.

The programmable device array is the basic building block for configurable logic circuits in a computer system. Examples of programmable device arrays include Field Programmable Gate Arrays (FPGAs), Composite Programmable Logic Arrays (CPLAs), and the like.

Current FPGAs use static random access memory (SRAM) cells or anti-fuse to program logic cells and crossbar switches (ie, matrix switches that connect multiple inputs to multiple outputs). Fuse-based FPGAs can only be single-programmed, so their use is limited. SRAM-based FPGAs have also suffered several known problems. For example, a logical cell The element usually has a high leakage power. In addition, although the SRAM uses a bistable latch circuit to store the bits, it is still a volatile type of memory in the sense that the data will eventually be lost if the memory device is not externally powered. Therefore, whenever the FPGA is powered up, the entire SRAM must be reloaded with configuration data. This makes external non-volatile memory (eg flash memory) and configuration-specific input/output (I/O) necessary and leads to considerable programming time at startup. A further disadvantage is that there may be security issues associated with storing configuration data on the off-chip memory array, requiring additional complex encryption schemes.

The non-volatile type of RAM has characteristics suitable for embedding high speed high density logic circuits. Spin Transfer Torque Random Access Memory (STTRAM) is a non-volatile RAM that is commonly used in more conventional memory circuits such as caches, auxiliary storage, and the like. Current high-speed, high-density logic circuits, such as FPGA/CPLA, typically do not use STTRAM or other STT-based components. Some researchers have proposed to implement a CMOS-STTRAM non-volatile FPGA configuration with a complementary metal oxide semiconductor (CMOS)-based FPGA design and STTRAM hybrid. For example, see the 2008 IEEE/ACM International Computer-Aided Design Seminar, pp. 589-592, titled "Hybrid CMOS-STTRAM Non-Volatile FPGA: Design Challenges and Optimization Approaches" by Paul et al. . However, there is still room to bring the STTRAM closer to the logic level and embed the non-volatile memory bits into the reconfigurable logic that will be used for the high-capacity computer architecture and interface. The present invention proposes an apparatus using an STT-based component and Its related processes, in response to the shortcomings of the currently available solutions.

10‧‧‧System

20‧‧‧Microprocessor

25‧‧‧Cache

27‧‧‧Logic Module

30‧‧‧ memory controller

40‧‧‧ memory

50‧‧‧ peripheral components

102‧‧‧ Logical cells

104‧‧‧ Peripheral I/O pads

106, 108‧‧‧ routing channels

202‧‧‧Resistive components

204‧‧‧Optoelectronics

206‧‧‧ word line

208‧‧‧ source line

210‧‧‧ bit line

402, 404‧‧‧ logical blocks, logic elements, logical cells

406‧‧‧STTRAM storage

408‧‧‧Switch box (or router)

412‧‧‧ Logical cells

414‧‧‧Multiplexer (MUX)

500‧‧‧ logical cells

501‧‧‧ input

502‧‧‧LUT structure

504‧‧‧Factor elements

506‧‧‧ clock signal

508‧‧1 bit STTRAM component

510‧‧‧Multiplexer (MUX)

512‧‧‧MUX output signal

514‧‧‧ Output signal

602‧‧‧No selector STTRAM cell

604‧‧‧Resistors

606‧‧‧Vertical channel

608‧‧‧ horizontal channel

The embodiments of the present invention are illustrated by way of example and not limitation.

FIG. 1A depicts a high level block diagram of selected aspects of the elaboration system in accordance with an embodiment of the present invention.

FIG. 1B depicts a basic architecture of a CPLA or FPGA including logical cells and interconnects in accordance with an embodiment of the present invention.

2A-B2B depict a schematic diagram of a typical one transistor (1T1R) device showing a bit line (BL), a word line (WL), and a source line (SL).

Figure 3 depicts simulation results showing the performance improvement of an STTRAM based device in accordance with various aspects of the present invention.

4A-4B depict two different embodiments of an STTRAM-based logic circuit in accordance with aspects of the present invention.

Figure 5 depicts an FPGA version using a lookup table (LUT) in accordance with various aspects of the present invention.

Figure 6 depicts a switch box layout for displaying STTRAM elements in a crossbar configuration in accordance with aspects of the present invention.

Figure 7 depicts an additional simulation result showing the resistance of the STTRAM device as a function of applied voltage, in accordance with aspects of the present invention.

In the following description, like components are given the same element symbols, whether or not they are shown in different embodiments. The embodiments of the invention are illustrated in a clear and concise manner, and the drawings are not necessarily to scale, and some features may be shown in a somewhat schematic form. Features described and/or illustrated with respect to one embodiment may be used in one or more other embodiments, and/or in combination with or in place of other embodiments.

In accordance with various embodiments of the present invention, an array of semiconductor devices using memory elements based on high density spin transfer torque (STT), such as FPGAs and CPLAs, is proposed.

STT is an effect in which a spin-polarized current can be used to modify the orientation of the magnetic layer in a magnetic tunnel junction (MTJ) device. In an STT-based MJT, the device resistance can be high or low depending on the relative angular difference between the magnetic polarization directions on both sides of the tunnel junction.

STT-based memory components can be used in stand-alone FPGA/CPLA, or can be embedded in microprocessors and/or digital signal processors (DSPs) to provide design flexibility for low power, scalable, and Reconfigured hardware architecture. Those skilled in the art will appreciate that microprocessors and wafer systems (SoCs) are increasingly embedded in reconfigurable structures to enhance customization and configurability. Embodiments of the present invention make the embedded FPGA/CPLA self-contained, secure, high performance, and low power.

In addition, note that although mainly referring to the illustrative paradigm The FPGA/CPLA is used to describe systems and procedures, but it will be appreciated that certain aspects, architectures, and principles of the present invention are equally applicable to other types of device memory and logic arrays in view of the disclosure herein.

Referring to the drawings, FIG. 1A is a high level block diagram illustrating selected aspects of a system being implemented, in accordance with an embodiment of the present invention. System 10 can represent any of a number of electronic and/or computing devices, which can include a memory device. Such electronic and/or computing devices may include servers, desktops, laptops, mobile devices, smart phones, gaming devices, tablets, network devices, and the like. In an alternate embodiment, system 10 may include more components, fewer components, and/or different components. Moreover, while system 10 can be described as including separate components, it will be appreciated that such components can be integrated on a platform, such as a SoC. In an illustrative example, system 10 includes a microprocessor 20, a memory controller 30, a memory 40, and a peripheral component 50. The microprocessor 20 includes a cache 25 that can be part of the memory hierarchy to store instructions and data, and the system memory 40 can also be part of the memory hierarchy. The cache 25 can include an SRAM device. Communication between the microprocessor 20 and the memory 40 can be facilitated by a memory controller (or chipset) 30 that can also facilitate communication with the peripheral components 50. Microprocessor 20 may also include one or more logic modules 27. Logic module 27 can include an FPGA/CPLA.

The SRAM device includes an array of memory cells (M columns and N rows). The SRAM device can also include a column decoder, a timer device, and an I/O device (or I/O output). For efficient I/O design, the bits of the same memory character can be separated from each other. Can be used during read operations A device (MUX) to connect the lines to the desired circuit. During a write operation, another MUX can be used to connect the rows to the write driver.

Section 1B illustrates the basic architecture of FPGA and CPLA. As discussed above, FPGAs and CPLAs provide reconfigurability with a low stylized burden. The basic structure of the FPGA includes an array of individual logical cells 102, and routing channels (106 and 108) are arranged in a grid-like manner between the peripheral I/O pads 104, thereby providing a cell from one cell to the other. The link can be reconfigured. It is noted that in related art, CPLA is sometimes referred to as CPLD (Composite Programmable Logic Device).

In the conventional FPGA/CPLA, the configuration data of the operation and routing of the logical cells is stored in the local memory. This is primarily based on the conventional volatile SRAM. Additional packages (on package) or onboard non-volatile storage (primarily flash) are required to store copies of the reconfigured material. When the FPGA/CPLD is powered up, the local SRAM memory is loaded into the configuration data. This conventional solution suffers from various problems such as: (a) high leakage power from SRAM bit cells; (c) long boot time, loading of configuration settings in the SRAM array, and (d) Possible safety issues with configuration data stored in external memory outside the chip. In order to circumvent these problems, the inventor of the present invention proposed to use STTRAM to locally store configuration bits. The STTRAM component stores two binary states as two different resistance values and maintains the stored data when the power supply is removed.

STTRAM uses a special write mechanism that is based on spin-polarized current induced magnetization switching, which greatly enhances its adjustability by reducing the power consumed by the write. 2A-B2B show schematic diagrams of the basic elements of the STTRAM cell, including a transistor 204 and a variable resistance element _Rmem (element 202). The combined structure is called 1T1R (one transistor and one resistor) cell. The bit line (BL, element 210), word line (WL, element 206), and source line (SL, element 208) of the cell are displayed in a more conspicuous manner in FIG. 2B, and correspondingly Voltages V _BL , V _WL , and V _SL . The transistor 204 acts as a selector switch, and the resistive element 202 is a magnetic tunnel junction (MTJ) device comprising two ferromagnetic layers separated by a junction layer, one layer having a fixed "reference" magnetization direction and the other layer Has a variable magnetization direction. Figure 2B shows that although there is only one read direction (arrow marked with RD), the write operation can be bidirectional (double-headed arrow labeled WR). Thus, this 1T1R structure can be described as a 1T-1STT MTJ memory cell with unipolar "read" and bipolar "write".

Figure 3 shows a simulation result 300 showing how the average write time "Avg T _WR " decreases as the current density increases. The third diagram shows the wide operating range of the STTRAM bit cells. By increasing the current density J _C , the switching time of the bit cells is reduced, allowing for different operating currents and times, as required by system level specifications.

The FPGA/CPLD architecture can be achieved by arranging the basic 1T1R cells in various ways (see Figure 2A - Figure 2B). Two illustrative example embodiments are shown in Figures 4A and 4B. In both embodiments 400A and 400B, the configuration data (or routing table) is stored locally in the STTRAM. Both embodiments allow low power, non-routing of the routing table. Volatile implementation. The entire configuration data can be stored locally in each switch box or in a central array of STTRAM bit cells (shown as element 406). In an embodiment 400A, each switch box includes a partially embedded STTRAM that stores a routing configuration and routes data between various logical blocks (e.g., 402 and 404). Many such components can be combined in an array to implement large reconfigurable logic circuits. In an embodiment 400B, the routing table for the entire circuit is stored in a central STTRAM array and the necessary configuration data is routed to the local switch box. In the switch box, this is used as a multiplexer (MUX) selection signal to route data from one logical block to another. In both cases, the appropriate configuration is in place each time the FPGA/CPLD is powered up. This will result in a faster start.

In an embodiment 400A, configuration data for routing between logic elements 402 and 404 can open or close a switch connection at a switch box (or router) 408. In an alternative embodiment 400B, the STTRAM store 406 can store the MUX selection material for the router, and the logical cell 412 is driven by the correct signal. Element 414 is the MUX.

Some versions of the FPGA use a lookup table (LUT) to store configuration data. As mentioned previously, conventional SRAM-based FPGAs with LUTs also suffer from known problems such as high leakage, non-volatile external storage that requires construction, high startup time, and the like. Current inventors propose to provide low power, non-volatile storage configuration data using STTRAM-based LUTs in logical cells. This is an STTRAM array of 1T1R cells that store configuration data. Whenever you need two or more logic When a link is established between the tiles, the STTRAM array is read and a link is established in the LUT based on the value read. FIG. 5 shows a logical cell 500 that includes an LUT structure 502 and N inputs 501. LUT 502 is implemented by a 1-bit STTRAM element 508. As shown in the exploded view in FIG. 500A, the 1b-STTRAM element 508 in the N-input LUT 502 is coupled to the MUX 510. The flip flop element 504 receives the clock signal 506 and the MUX output signal 512 to process the output signal 514 of the logic cell 500.

As previously described, the STTRAM element shows two states with two different resistance values - low and high - depending on whether the magnetic polarization is parallel (P) or anti-parallel (AP). If the difference in resistance between the two states of the STTRAM component is large enough, the selector switch can be removed, opening up the probability of a higher density device package. In this case, the crossbar structure can be used to locally store the routing configuration, rather than in a separate memory block, as shown. This no selector configuration 600, referred to as a switch box configuration, can be seen in Figure 6. The no-selector STTRAM cell 602 is used to reconfigure the vertical and horizontal channels 606 and 608. As shown in inset 600A, the only element in the cell is resistor 604, in which the transistor used as the selector switch shown in the schematic diagrams of Figures 2A-2B is removed. This leads to an increase in the bulk density, but still provides non-volatility and low power.

Figure 7 shows the simulation results from a numerical solution predicting the change in device resistance in accordance with the varying voltage. Two different states of the resistor (i.e., AP (180°) and P (0°) cases) can be easily noted from the drawing. The simulation methodology involves a Landau-Lifshitz-Gilbert (LLG) equation from a compatible uncoupling dynamics by transmission based on a non-equilibrium Green's function (NEGF). For reference, see the December 2007 IEDM Technical Digest, pages 121-124, entitled "Quantum Transport Simulation of Tunneling Based Spin Torque Transfer (STT) Devices: Design Tradeoffs and Torque" by S. Salahuddin et al. "Efficient" article. For various corrected physical parameters, such as the Fermi energy energy (E _F ) shown in Figure 7, the splitting (△) of ferromagnets, the electron mass of ferromagnets and oxides (m _FM and m _OX ) And a special case of Ub (oxide barrier high) simulation, indicating a resistance change greater than 2X. For AP (180°) and P (0°) cases, the simulation results are the same as those from Sankey et al., Vol. 4, No. 1, 67-71, January 2008, by Sankey et al. The experimental data obtained by the article "The Spin-Transfer-Torque Vector in Magnetic Tunnel Junctions" is consistent.

Thus, in summary, embodiments of the present invention address several issues that plague existing SRAM-based FPGA/CPLA and enable low power and high density FPGA/CPLA based on STTRAM. Providing on-wafer STTRAM non-volatile memory allows for at least some of the following benefits in existing architectures:

. The need for external flash memory (construction or onboard) is eliminated, reducing costs and saving space on the board.

. Instant start is allowed. Since the configuration is stored in the FPGA/CPLA wafer itself, there is no need to load the configuration from the external storage each time the device is powered up. Eliminating configuration I/O traffic in addition to instant start Power saving and possible pin counts are reduced.

. Security is greatly improved by eliminating the need to store configuration data in external memory. Since the configuration data never leaves the wafer, the configuration data cannot be observed or modified by external means.

Having described the novel concepts and principles of the STTRAM-based memory and logic circuits, those skilled in the art will understand that the foregoing detailed description is intended to be illustrative and not limiting. Even if not specifically stated herein, those skilled in the art will recognize various modifications, improvements, and alterations. Such changes, modifications, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the invention. In addition, the order in which the processing elements or sequences are recited, or the use of numbers, letters, or other names, should not limit the order of the claimed procedures and methods unless otherwise indicated in the scope of the claims. While the above description is by way of example, the various aspects of the present description are considered to be useful, but it should be understood that such details are only for that purpose, and the scope of the appended claims should not be limited to the disclosed form. Modifications and equivalent configurations of the spirit and scope of the disclosed forms.

102‧‧‧ Logical cells

104‧‧‧ Peripheral I/O pads

106, 108‧‧‧ routing channels

Claims (20)

A system comprising: an array of programmable devices, the programmable device array comprising: a non-volatile memory portion for locally storing configuration data in a plurality of uses of spin transfer torque (STT) effects a plurality of logical cells; a routing channel that couples each logical cell of the plurality of logical cells to a corresponding memory component storing the configuration data; and a circuit that controls the correlation The locally stored configuration data is routed to the plurality of logical cells. A system as claimed in claim 1, wherein the programmable device array comprises one of a field programmable gate array (FPGA) and a composite programmable logic array (CPLA). The system of claim 1, wherein the non-volatile memory portion comprises a central array of STT random access memory (STTRAM) elements. A system as claimed in claim 1, wherein the non-volatile memory portion comprises a decentralized array of STTRAM elements co-located with corresponding logical cells. A system as claimed in claim 3, wherein the circuit for controlling the routing of the associated configuration data comprises a lookup table (LUT). A system as claimed in claim 5, wherein the LUT comprises: N inputs for receiving configuration data from an array of N 1-bit STTRAM memory elements; A multiplexer (MUX) circuit that establishes a connection between the desired bits in the LUT by reading the received configuration data and outputs the desired data to the corresponding logical cell. The system of claim 1, wherein the difference between the two resistance values of the individual STTRAM elements is sufficiently large that a selector switch integrated with the STTRAM element is not required. A system as claimed in claim 7 wherein the individual STTRAM elements are coupled in a switch box configuration using a routing channel of a crossbar structure. A system as claimed in claim 1, wherein the array is one of: an independent STTRAM array that can be coupled to the logic circuit; and an embedded STTRAM array integrated with the logic circuit. A method of implementing a programmable device array in an electronic system, the method comprising: locally storing configuration data in a plurality of memory components included in a non-volatile memory portion, the memory components Using a spin transfer torque (STT) effect; providing routing channels that couple logical cells of a plurality of logical cells to corresponding memory elements storing the configuration data; and controlling groups associated with local storage The routing of the data to the plurality of logical cells. The method of claim 10, wherein the programmable device array comprises one of a field programmable gate array (FPGA) and a composite programmable logic array (CPLA). The method of claim 10, wherein the non-volatile memory portion comprises a central array of STT random access memory (STTRAM) elements. The method of claim 10, wherein the non-volatile memory portion comprises a decentralized array of STTRAM elements co-located with corresponding logical cells. The method of claim 12, wherein the routing of the associated locally stored configuration data comprises providing a lookup table (LUT). The method of claim 14, wherein the LUT comprises: receiving configuration data from an array of N 1-bit STTRAM memory elements; and installing the received configuration data in the LUT Create a link between the desires and output the desired data to the corresponding logical cell. The method of claim 10, wherein the method further comprises: making the difference between the two resistance values of the individual STTRAM elements large enough that a selector switch integrated with the STTRAM element is not required. The method of claim 16, wherein the method further comprises: configuring the individual STTRAM elements in a switch box configuration; and configuring the routing channels in a crossbar configuration coupling the individual STTRAM elements. The method of claim 10, wherein the array is One of the following: an independent STTRAM array that can be coupled to a logic circuit; and an embedded STTRAM array integrated with the logic circuit. A method for implementing a programmable device array in a wafer system (SoC) by embedded spin transfer torque random access memory (STTRAM), the method comprising: locally storing configuration data in a plurality of STTRAM components The plurality of STTRAM elements are in proximity to one or more corresponding logical cell entities; and the routing channels are configured in a crossbar configuration to couple the logical cells to corresponding STTRAM elements storing the configuration data. The method of claim 19, wherein the programmable device array comprises one of a field programmable gate array (FPGA) and a composite programmable logic array (CPLA).