TW201506930A - Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits - Google Patents

Abstract

The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

Description

Method and device for adjusting threshold of memory of cell with address and adjacent bit

The present invention relates to non-volatile memory, and more particularly to a method and apparatus for adjusting the bias voltage of a memory cell having addressed and adjacent bits.

For example, a charge trapping memory cell of a tantalum nitride read only memory (NROM) can be programmed into portions of different regions of the tantalum nitride storage layer by a mechanism such as channel hot electron injection (CHE). A single memory cell can store data of different addresses in different portions of the tantalum nitride storage layer near the source and near the drain. The threshold voltage range of the memory cell is related to different data values that can be stored in each part of the memory cell. For example, in each portion of a multi-level memory cell, the four threshold voltage ranges can represent four different data values that store two bits. In a three-class memory cell, eight threshold voltage ranges can represent eight different data values stored in three bits.

However, because the data stored in different portions of the tantalum nitride storage layer affect each other's second bit effect, it limits the threshold voltage interval available for a memory cell. These different portions are referred to herein as "addressed bits" and "adjacent bits" of the same memory cell. In this specification, a "bit" is not limited to storing a single data bit, but refers to a different physical location of a charge storage layer that can store 1, 2, 3 or more bits of data. The addressed bit refers to the location of the physical data that can be addressed in a command such as a stylized or read command, and the adjacent bit refers to the location of the physical data adjacent to the addressed bit in the same memory cell.

U.S. Patent No. 6,011,725 describes the implementation of a reverse read operation to read this memory cell. The address portion is hereby incorporated by reference, in which the polarity of the voltage applied to the source and the drain is opposite to the polarity of the voltage applied to the address bit of the memory cell during the hot metal stylization operation of the channel. The reverse read operation performed by the address bit of the memory cell must "break down" the channel underneath the adjacent bit of the same memory cell. When the data value stored by the neighboring cell of the memory cell is related to a high threshold voltage, the reverse read current is reduced. "Lyue Hang-Ting et al." "Studies of the reverse read method and second-bit effect of 2 bit/cell nitride-trapping device by quesi-two-dimensional model", IEEE Transactions on Electron Devices, Vol.43, No .1, page 119, January 2006 describes such a second bit effect that narrows the available threshold voltage range and is also cited here.

This second bit effect can be resolved by increasing the magnitude of the applied voltage during this reverse read operation. However, increasing the voltage level in this way encounters the problem of read disturb effects that would erroneously program adjacent bits when reading the addressed bits.

Therefore, it is desirable to be able to provide a wider threshold voltage interval by improving the second bit effect while reducing the disadvantages associated with, for example, read disturb stylization.

The technique described herein pertains to a memory circuit having a non-volatile memory cell and a control circuit. The non-volatile memory cell includes a first current load terminal (source or drain), a second current load terminal (drain or source), and a gate. The non-volatile memory cell has a plurality of storage portions that can store data separately. A first storage portion is adjacent to the first current load terminal and stores the first data. A second storage portion is adjacent to the second current load terminal and stores the second data. The first storage portion and the second storage portion may be different portions of a tantalum nitride storage layer.

The control circuit applies a read current bias to the first current load terminal of the non-volatile memory cell, the second current load terminal and the gate, and the read programming bias voltage is applied to read the first data And one of the second materials, the read programming bias is based on the other of the first data and the second data. For example, the first data determines a first voltage data applied to the first current load terminal in the read programming bias to read Take the second data. In the reverse read operation performed by the second data, electrons flow from the second current load terminal to the first current load terminal. In order to reduce the second bit effect, the reverse read current is increased by increasing the voltage applied to the first current load terminal. In order to avoid reading interference (the first data is not intended to be stylized), if the first data represented by a first threshold voltage of the first storage portion exceeds a minimum threshold voltage, an increase is applied to the first The voltage of the current load terminal. If the first data represented by a first threshold voltage of the first storage portion does not exceed a minimum threshold voltage, a smaller voltage is applied to the first current load terminal. Some embodiments of the technology include: a memory storage data bit is determined by whether a threshold voltage representing the first data exceeds a minimum threshold voltage, wherein the control circuit reads the data bit from the memory Controlling whether the first voltage or the second voltage is applied to the first current load terminal in the stylized verification programming bias to programmatically verify the second data.

Similarly, the second data determines a voltage applied to the second current load terminal during the read programming bias operation to read the first data. As described for the first current load terminal, in order to avoid read disturb (the first data is not intended to be stylized), if the second data represented by a second threshold voltage of the second storage portion exceeds one The minimum threshold voltage increases the voltage applied to the second current load terminal. If the second data represented by a second threshold voltage of the second storage portion does not exceed a minimum threshold voltage, a smaller voltage is applied to the second current load terminal.

Whether to increase the voltage of the first current load terminal or the second current load terminal, the current terminal of the increased voltage is called a drain voltage terminal, because the drain terminal is a higher voltage current load terminal, Is the destination of the electron flow (in the opposite direction of the current). In addition, whether the first data in the first storage portion is read, or the second data in the second storage portion is read, the stored portion that is read is referred to as an addressed bit, and the stored portion that is not read is called It is an adjacent bit. As previously described, a "bit" in this specification refers to a particular storage location in a memory cell and is not limited to storing a single data bit. Each of the addressed bits and adjacent bits can store different physical locations of the charge storage layer of 1, 2, 3 or more bits of data.

When the drain voltage is increased, the sensing threshold is caused because the second bit effect is reduced. The offset of the pressure range. Therefore, multiple stylized threshold voltage ranges can be associated with the same sense threshold voltage range. For a given bit, the data stored in the adjacent bit determines the sensing threshold voltage range corresponding to the particular programmed threshold voltage range. In addition, the overall number of programmed threshold voltage ranges exceeds the overall number of sensing threshold voltage ranges.

As described above, the read programming bias reads one of the first data and the second data stored in the memory cell, and the read programming bias is based on the first data and the second The other of the information. In some embodiments of the technique, the data determines the other of the first data and the second data prior to applying the read programming bias. In some embodiments of the technology, a read operation determines the other of the first data and the second data.

Other embodiments of this technique are also described herein. These embodiments are concerned with replacing the read with stylized verification.

Another embodiment of the present invention is to apply a stylized verification programming bias instead of adding a read programming bias. A stylized verification operation determines whether a minimum number of stylizations are performed in a memory cell, wherein a read operation determines whether a threshold voltage of a memory cell is higher or lower than a minimum threshold voltage range associated with different data values. An intermediate threshold voltage.

The stylized verification programming bias is applied to programmatically verify one of the first data and the second data stored by the memory cell, and the stylized verification programming bias is based on the first data and the first The other of the two materials. This data determines the other of the first data and the second data prior to applying the stylized verification programming bias. In some embodiments of the technology, a read operation determines the other of the first data and the second data. In still other embodiments of the technology, the input data of a stylized command determines the other of the first data and the second data.

Other embodiments of this technique are also described herein. These embodiments are concerned with replacing the read with stylized verification.

Another embodiment of the present invention is directed to a memory method comprising: applying a read current bias to a first current load terminal of a non-volatile memory cell, a second current load terminal, and a gate applied The reading and programming biasing system reads the first capital And reading the programming bias according to the other of the first data and the second data, the first data being stored in a first storage portion adjacent to the first current load The terminal and the second data are stored in a second storage portion adjacent to the second current load terminal.

Other embodiments of this technique are also described herein. These embodiments are concerned with replacing the read with stylized verification.

Another embodiment of the present invention is directed to a memory method comprising: applying a stylized verification programming bias to a first current load terminal, a second current load terminal, and a gate of a non-volatile memory cell, The stylized verification programming biasing system reads one of the first data and the second data, and the reading programming bias is based on the other of the first data and the second data, the first The data is stored in a first storage portion adjacent to the first current load terminal and the second data is stored in a second storage portion adjacent to the second current load terminal.

Other embodiments of this technique are also described herein. These embodiments are concerned with replacing the read with stylized verification.

3450‧‧‧Integrated circuit

3400‧‧‧Non-volatile memory cell array

3401‧‧‧ column decoder

3402‧‧‧ character line

3403‧‧ ‧ row decoder

3404‧‧‧ bit line

3405‧‧‧ Busbar

3407‧‧‧ data bus

3406‧‧‧Sense Amplifier/Data Input Structure/Dension Line Circuit

3409‧‧‧Stylized verification and read orchestration bias state mechanism determines the bucker voltage and stylized VT based on adjacent bits

3408‧‧‧ bias adjustment supply voltage

3411‧‧‧ data input line

3415‧‧‧ data output line

Figures 1 to 2 are schematic diagrams of a non-volatile memory cell having address bits and neighboring bits for storing data, respectively.

Figures 3 through 5 are graphical representations of the threshold voltage, showing the second bit effect caused by the "adjacent bits" of an "addressed bit".

Figures 6-7 are graphical representations of the threshold voltage, showing that increasing the gate voltage can reduce the second bit effect caused by the "adjacent bit" of an "addressed bit".

Figures 8~23 are plots of threshold voltages for an "addressed bit" and an "adjacent bit", showing the arrangement of different "addressed bits" and "adjacent bits", and in many types of data. The second bit effect is reduced.

Figures 24 and 25 are graphical representations of threshold voltages showing different "addressed bits" Stylized threshold voltage range and sensing threshold voltage range for data arrangement with "adjacent bits".

Figure 26 shows the threshold voltage distribution for different buckling biases, which will adjust the buckling bias based on the value of the data in an adjacent bit.

Figure 27 is a block diagram of a drain line driver circuit block having a drain voltage determined by data stored in a static random access memory (SRAM).

Figure 28 is a typical static random access memory SRAM block that generates a signal from a drain line driver circuit block to control the drain voltage.

Figure 29 is a circuit diagram showing an example of a drain line driving circuit.

Figure 30 is a flow chart showing one of the read operations of adjusting the gate bias based on the value of the adjacent bit.

Figures 31-33 are flow diagrams of the stylized operation of adjusting the gate bias based on the values of adjacent bits.

Figure 34 shows a simplified block diagram of an integrated circuit having the improved and memory arrays described herein in accordance with an embodiment of the present invention.

The example shown here has four possible data values in a memory cell. Other examples may be having two possible data values, having eight possible data values, or having other numbers of possible data values.

Figures 1 to 2 are schematic diagrams of a non-volatile memory cell having address bits and neighboring bits for storing data, respectively.

Figure 1 shows a non-volatile memory cell with data stored in different parts of the tantalum nitride storage layer. These different parts of the same memory cell are referred to herein as "addressed bits" and "adjacent bits." In this description, the term "bit" refers to a different physical location in the charge storage layer that can store 1, 2, 3 or more bits. material. This memory cell has a gate terminal, two current load terminals - a drain terminal and a source terminal. The bucker terminal voltage will vary depending on the value of the data near the source terminal. Because this particular current load terminal will change as the terminal of the inrush current, the specific current load terminal of the bungee terminal will also change. In Figure 1, the address bit is the current load terminal on the left side of the memory cell charge storage layer and close to the left side, and the adjacent bit cell is the current load terminal on the right side of the memory cell charge storage layer and close to the right side. . The right and left current load terminals are set to a lower voltage source and a higher voltage drain, and the direction of the electron flow is to the drain, showing different "addressed bits" and "adjacent bits" And reverse read operations.

Figure 2 shows a non-volatile memory cell with data stored in different parts of the tantalum nitride storage layer, similar to Figure 1. However, unlike FIG. 1, the address bit is the current load terminal on the right side of the memory cell charge storage layer and close to the right side, and the adjacent bit cell is on the left side of the memory cell charge storage layer and close to the left side. Current load terminal. Since the positions of the "addressed bit" and the "adjacent bit" are reversed in Fig. 2, the positions of the source and the drain and the direction of the electron flow are also opposite to those of Fig. 1.

Figures 3 through 5 are graphical representations of the threshold voltage, showing the second bit effect caused by the "adjacent bits" of an "addressed bit". A low drain voltage VBLR_1 is applied to the drain terminal when sensing the addressed bit. The sensed threshold voltage (VT) distribution of the addressed bit and the actual location of the addressed bit in the memory cell are shown in the solid line in the figure. The sensed VT distribution of this neighboring bit and the actual position of this neighboring cell in this memory cell are shown in the dashed line in the figure.

In Figure 3, the addressed bit has an initial sensed VT distribution. The attached bitmap shows that the address bit is the left portion of the charge storage layer of the memory cell. Neighboring bits have not been programmed to a high VT distribution, so there is no second bit effect.

In Figure 4, the neighboring bits are programmed to a high VT distribution. Attached figure The adjacent bit is shown in the right part of the charge storage layer of the memory cell.

In Figure 5, the addressed bit is offset from this initial sensed VT distribution to a higher sensed VT distribution. The offset of this "sensing VT distribution" does not reflect the change in the "stylized VT distribution" because no charge is programmed into this addressed bit. Rather, the sensed VT distribution offset of the addressed bit is caused by the second bit effect. The higher offset of the sensed VT distribution of the addressed bit is due to the higher threshold voltage of the channel portion below the adjacent bit, which reduces the sense current and increases the sensed VT distribution of the addressed bit.

Figures 6-7 are graphical representations of the threshold voltage, showing that increasing the gate voltage can reduce the second bit effect caused by the "adjacent bit" of an "addressed bit". The sensed VT distribution of this addressed bit is shown in the solid line in the figure. The sensed VT distribution of this neighboring bit is shown in the dashed line in the figure.

In Figure 6, the value of the adjacent bit is sensed to determine the sense of the drain voltage of the addressed bit. A word line read voltage is applied to adjacent bits to sense this neighboring bit. If the sensing VT of the neighboring bit exceeds the threshold voltage VT of the word line reading voltage, the result is data 0, Nb_h (adjacent bit high level) = 1, Nb_l (near level low level) = 0. If the sense VT of the adjacent bit does not exceed the threshold voltage VT of the word line read voltage, the result is data 1, Nb_h=0, Nb_l=1. In this example, the sense VT of the adjacent bit does not exceed the threshold voltage VT of the word line read voltage, and the result is data 1, Nb_h = 0, Nb_l = 1.

In Fig. 7, because of the result of Fig. 6, a high drain voltage VBLR_h is applied to sense the addressed bit. This high buckling voltage tends to increase the sense current and tends to counteract the second bit effect. Because of the reduction in the second bit effect, the VT distribution offset of this addressed bit is also reduced. This reduction in VT distribution offset widens the available VT intervals.

Figures 8~23 are plots of threshold voltages for an "addressed bit" and an "adjacent bit", showing the arrangement of different "addressed bits" and "adjacent bits", and in many types of data. The second bit effect is reduced. Separate bit data values and neighbors The "H" or "L" above the near-bit data value indicates whether a high-thaw voltage VBLR_h or a low-thaw voltage VBLR_1 is applied when sensing a particular bit. If the sensed VT of such neighboring bits does not exceed the minimum threshold value VGN, a low drain voltage VBLR_1 is applied to sense the address bit data value. If the sensed VT of such neighboring bits exceeds the minimum threshold value VGN, a high drain voltage VBLR_h is applied to sense the address bit data value. If the sensed VT of the addressed bit does not exceed the minimum threshold VGN, a low drain voltage VBLR_1 is applied to sense the adjacent bit data value. If the sensed VT of the addressed bit exceeds the minimum threshold VGN, a high drain voltage VBLR_h is applied to sense the adjacent bit data value. The minimum threshold shown in the figure is between the stylized critical distributions of the data values "3" and "4". Other embodiments may apply other minimum thresholds.

Figures 8-11 are graphical representations of the threshold voltages when the data value of the addressed bit is "1" (from the lowest to the highest VT value of 1 to 4). In Fig. 8, the adjacent bit has a data value of "1". In Fig. 9, the adjacent bit has a data value of "2". In Fig. 10, the adjacent bit has a data value of "3". In Fig. 11, the adjacent bit has a data value of "4". Since the sense VT of the adjacent bit exceeds the minimum threshold VGN, the high drain voltage VBLR_h is applied to sense the address bit data value. Because of the reduced VT "0A", the stylized VT "1" of this addressed bit is sensed. Although different stylized VT distributions are displayed, the VTs of "1" and "0A" can be considered identical because both are less than the difference between the lowest VT data value and any higher VT data values. The value of the VG1 threshold.

Figures 12 to 15 are graphs showing the threshold voltages when the data value of the addressed bit is "2" (from the lowest to the highest VT value of 1 to 4). In Fig. 12, the adjacent bit has a data value of "1". In Fig. 13, the adjacent bit has a data value of "2". In Fig. 14, the adjacent bit has a data value of "3". In Fig. 15, the adjacent bit has a data value of "4". Since the sense VT of the adjacent bit exceeds the minimum threshold VGN, the high drain voltage VBLR_h is applied to sense the address bit data value. The stylized VT "2A" of this addressed bit is sensed as a reduced VT "2". Addressing bit Stylized to VT "2A" makes it sense that VT is "2".

Figures 16 to 19 are graphical representations of the threshold voltages when the data value of the addressed bit is "3" (from the lowest to the highest VT value of 1 to 4). In Fig. 16, the adjacent bit has a data value of "1". In Fig. 17, the adjacent bit has a data value of "2". In Fig. 18, the adjacent bit has a data value of "3". In Fig. 19, the adjacent bit has a data value of "4". Since the sense VT of the adjacent bit exceeds the minimum threshold VGN, the high drain voltage VBLR_h is applied to sense the address bit data value. The stylized VT "3A" of this addressed bit is sensed as a reduced VT "3". This addressed bit is programmed to VT "3A" so that the sensed VT is "3". Since this address bit "3A" also exceeds the minimum threshold VGN, the neighboring bit is also sensed to have a high drain voltage VBLR_h. This neighboring bit VT is programmed to VT "4A" such that the neighboring bit VT is sensed as a reduced VT "4". Otherwise, if the neighboring bit VT is held at VT "4" without being programmed to VT "4A", then this neighboring bit VT is sensed as VT "4B" which is reduced by VT "4".

Figures 20 to 23 are graphical representations of the threshold voltages when the data value of the addressed bit is "4" (from the lowest to the highest VT value of 1 to 4). In Fig. 20, the adjacent bit has a data value of "1". In Fig. 21, the adjacent bit has a data value of "2". In Fig. 22, the adjacent bit has a data value of "3". In Fig. 23, the adjacent bit has a data value of "4". As shown in Fig. 19, which is the reverse of the arrangement of Fig. 22, the address bit is swapped with the adjacent bit, and the stylized VT of the adjacent bit VT is "3A", which is sensed to be reduced. VT "3". Since the sense VT "3A" of the adjacent bit exceeds the minimum threshold VGN, the neighboring bit is sensed to have a high drain voltage VBLR_h. This addressed bit is programmed to VT "4A" such that the addressed bit VT is sensed as a reduced VT "4". If the addressed bit VT is held at VT "4" without being programmed to VT "4A", then the addressed bit VT is sensed as a VT "4B" that is reduced by VT "4". In Fig. 23, the adjacent bit has a data value of "4". Since the neighboring bit exceeds the minimum threshold value VGN, the high drain voltage VBLR_h is applied to sense the address bit. This addressed bit is stylized to VT "4A" causes the addressed bit VT to be sensed as VT "4". Since the addressed bit "4A" also exceeds the minimum threshold VGN, the neighboring bit is also sensed to have a high drain voltage VBLR_h. This neighboring bit is programmed to VT "4A" such that the neighboring bit VT is sensed as VT "4". Otherwise, if the neighboring bit VT is held at VT "4" without being programmed to VT "4A", then this neighboring bit VT is sensed as VT "4B" which is reduced by VT "4".

Figures 24 and 25 are graphical representations of threshold voltages showing the stylized threshold voltage range and sensing threshold voltage range for different "addressed bits" and "adjacent bits" data arrangements. The "addressed bit" has a bottom line and the "adjacent bit" does not have a bottom line.

Figure 24 shows the stylized VT distribution defined by the added charge when staging this memory cell. Because the charge stored under a memory cell typically does not change during sensing (except for read disturb effects), this stylized VT distribution typically does not change when the read bias changes.

Figure 25 shows the variation in the sensed VT distribution as it senses the applied drain voltage. The sense VT in Fig. 25 directly determines the sensed data values stored in a memory cell, and the number of sensed VT distributions is equal to the number of data values represented by the addressed bits or adjacent bits.

As discussed in Figures 15, 19, 22 and 23, this stylized VT distribution is expected to be a VT offset caused by a high drain voltage and a sense VT distribution. Therefore, the stylized VT distribution of Figure 24 does not include the effect of high-bias bias biasing the VT distribution to a smaller value. The sensed VT distribution of Figure 25 includes the effect of high-bend bias biasing the VT distribution to a smaller value. Therefore, the <addressed bit> <adjacent bit> stylized VT distribution <2><4> in Fig. 24 is shifted to the lower sensed VT distribution in Fig. 25. A similar self-programmed VT distribution offset to a lower VT size of the sensed VT distribution is also shown in <addressed bits> <adjacent bits> combined <3><4>, <4><3> and <4><4>.

The stylized VT distribution of Fig. 24 and the sensed VT distribution indication of Fig. 25 A particular sensed data value can be represented by multiple stylized VT ranges. In addition, the number of sensed VT ranges is equal to the number of data values that can be stored by the addressed bit or neighboring bits, and the number of programmed VT ranges is greater than that that can be stored by the addressed bit or neighboring bits. The number of data values.

Figure 26 shows the threshold voltage distribution for different buckling biases that adjust or not adjust the buckling bias based on the data values in an adjacent bit.

The vertical axis is a logarithmic representation showing that the number of bits in the analog test memory array has a particular sense VT on the horizontal axis. The dashed trace corresponds to a sensing procedure that does not adjust the drain bias based on the data values in adjacent bits. The solid line trajectory corresponds to a sensing program that adjusts the 偏压 bias according to the data value in the adjacent bit. This illustration shows that adjusting the 偏压 bias will widen the VT interval, especially between the two lowest VT distributions, with a widened VT spacing of approximately 0.5V.

Figure 27 is a block diagram of a drain line driver circuit block having a drain voltage determined by data stored in a static random access memory (SRAM). From top to bottom, this block contains an adjacent bit SRAM block, SENAMP sense amplifier, YMUX line multiplexer and ARRAY memory array.

Figure 28 is a typical static random access memory SRAM block that generates a signal from a drain line driver circuit block to control the drain voltage. An SRAM memory generates Nb_h and Nb_1 signals as shown in FIG. If the sensing VT of the neighboring bit exceeds the threshold voltage VT of the word line read voltage, the high drain voltage can be applied to sense the addressed bit, Nb_h (adjacent bit high level) = 1, Nb_l (adjacent bit low level) = 0. Suppose the sensing VT of the adjacent bit does not exceed the threshold voltage VT of the word line read voltage, so that the low drain voltage can be applied to sense the addressed bit, Nb_h (adjacent bit high level) = 0 , Nb_l (adjacent bit low level) = 1.

Figure 29 is a circuit diagram showing an example of a drain line driving circuit. Two parallel The gate sequence is connected to the Vdd supply voltage and the DL drain line. The reverse gate series on the left receives the gate voltages Vblr_h and Nb_h. The reverse gate sequence on the right side receives the gate voltages Vblr_l and Nb_l. If Nb_h (adjacent bit high level) = 1, Nb_l (adjacent bit low level) = 0, then the left and right gate series are turned on and the right side is closed. The DL drain line has a value of Vblr_h (less than a transistor VT). If Nb_h (adjacent bit high level) = 0, Nb_l (adjacent bit low level) = 1, the left side of the reverse gate sequence is closed and the right side of the reverse gate sequence is turned on. The DL drain line has a value of Vblr_l (less than a transistor VT).

Figure 30 is a flow chart showing one of the read operations of adjusting the gate bias based on the value of the adjacent bit. At step 12, a "read command" and a memory "address of the addressed bit" are received. In step 14, the address of the addressed bit is stored, and based on the addressed bit, the address of the neighboring bit is obtained. A table can simultaneously index the address of the addressed bit and the address of the adjacent bit, allowing the addressed bit to be remapped to the adjacent bit. At step 16, the neighboring bit is sensed using the address of the neighboring bit. The default value is to use a low drain voltage. As shown in Figure 6, storing this data indicates that the neighboring bit values have a sufficiently high VT to allow high drain voltages to sense the address bits. An example memory as shown in Figure 28 stores this material. At step 18, the input address of the addressed bit stored in step 14 is retrieved. At step 20, the neighboring bit SRAM is checked and based on the data stored in step 16, it is determined whether the sensed VT of the neighboring bit exceeds the critical VT. At step 22, if the sense VT of the neighboring bit exceeds the critical VT, the drain voltage is vblr_h. At step 24, if the sense VT of the adjacent bit does not exceed the critical VT, then the drain voltage is vblr_1. At step 26, the address bit is sensed using the vbrl_h or vblr_l drain voltage. At step 28, this read command is ended.

Figures 31-33 are flow diagrams of the stylized operation of adjusting the gate bias based on the values of adjacent bits. In Fig. 31, the drain voltage is initially determined based on the sensed data. In Figures 32 and 33, the drain voltage is initially determined based on the input data along with the stylized commands.

In Figure 31, in step 30, a "stylized command" with a stylized address is received. Stylized data. In step 32, based on the data to be programmed in step 30, the content to be programmed into the addressed bit is processed to determine if the corresponding VT exceeds the one shown in Figure 6. The critical VT, and the result is stored in SRAM1, and the content to be programmed to the adjacent bit is processed to determine whether the corresponding VT exceeds the critical VT shown in Figure 6, and the result is stored in SRAM 2. 34, reading adjacent bits, the preset value is to use a low drain voltage. As shown in Figure 6, storing this data indicates that the adjacent bit value has a sufficiently high VT to allow high drain voltage sensing The address bit stores the data as an example memory as shown in Figure 28. At step 36, based on the data stored in step 34, the address bit is stylized to verify that the addressed bit has a high or low drain bias. The address bit is read at step 38, the default value of which is to use a low drain voltage. This data is stored which indicates whether the addressed bit has a sufficiently high VT to allow high drain voltage to sense adjacent bits. 40, according to the data stored in step 38, the program Verify that the neighboring bit has a high or low drain bias. In step 42, it is determined if the stylized verify operation in steps 36 and 40 has passed. In step 44, if the stylized verify operation in steps 36 and 40 fails. The program then programs the neighboring bits and/or the addressed bits, and the process repeats from step 34. At step 46, if the stylized verify operation in steps 36 and 40 is passed, the stylized command is terminated.

In Fig. 32, at step 50, a "stylized command" having a stylized address and "material to be stylized" are received. At step 52, based on the data to be programmed in step 50, the content to be programmed to the addressed bit is processed to determine if the corresponding VT exceeds the critical VT shown in Figure 6, and the result The content stored to SRAM1 and intended to be programmed to adjacent bits is processed to determine if the corresponding VT exceeds the critical VT shown in Figure 6, and the result is stored in SRAM2. At step 54, the data stored in SRAM1 and SRAM2 is examined to determine if a higher drain voltage is applied to programmatically verify adjacent bits. The data in SRAM1 and SRAM2 is checked because the contents of both the addressed bit and the adjacent bit determine the VT, as shown in Figures 24-25. At step 56, the neighboring bit is programmatically verified using the drain voltage of the data according to the address bits in SRAM1. At step 58, the data stored in SRAM1 and SRAM2 is checked to determine whether A higher drain voltage is applied to programmatically verify the addressed bits. The data in SRAM1 and SRAM2 is checked because the contents of both the addressed bit and the adjacent bit determine the VT, as shown in Figures 24-25. At step 60, the data of the neighboring bits in the general storage SRAM 2 as shown in FIG. 28 is stored in the adjacent bit SRAM, and the gated voltage of the stylized verification is set for the addressed bit. At step 62, it is determined whether the stylized verification operation at steps 56 and 60 has passed. At step 64, if one or both of the stylized verification operations in steps 56 and 60 fail, the neighboring bits and/or addressing bits are programmed, and the process begins with step 54. At step 66, if the stylized verification operation in steps 56 and 60 is passed, the stylized command is terminated.

In Fig. 33, at step 70, a "stylized command" having a stylized address and "material to be stylized" are received. At step 72, based on the data to be programmed in step 70, the content to be programmed to the addressed bit is processed to determine if the corresponding VT exceeds the critical VT shown in Figure 6, and the result The content stored to SRAM1 and intended to be programmed to adjacent bits is processed to determine if the corresponding VT exceeds the critical VT shown in Figure 6, and the result is stored in SRAM2. At step 74, the data stored in SRAM1 and SRAM2 is examined to determine whether a higher drain voltage is applied to programmatically verify the addressed bit and adjacent bits. The data in SRAM1 and SRAM2 is checked because the contents of both the addressed bit and the adjacent bit determine the VT, as shown in Figures 24-25. At step 76, the neighboring bit is programmatically verified using the drain voltage of the data in accordance with the addressed bit in SRAM1, and the addressed bit is programmed to verify using the drain voltage based on the data of the adjacent bit in SRAM2. At step 78, it is determined if the stylized verification operation at step 76 has passed. At step 80, if the stylized verification operation at step 76 fails, the neighboring bits and/or addressing bits are programmed, and the flow repeats from step 74. At step 82, if the stylized verification operation at step 76 is passed, the stylized command ends.

Figure 34 shows a simplified block diagram of an integrated circuit having the improved and memory arrays described herein in accordance with an embodiment of the present invention. The integrated circuit 3450 includes a memory array 3400. A word line (column) decoder and block selection decoder 3401 and a plurality of word lines 3402 arranged along the column direction of the memory array 3400 And serial selection line coupling and electrical communication. A one-line (row) decoder and driver 3403 is coupled and electrically communicated with a plurality of bit lines 3404 arranged along the row direction of the memory array 3400 to read data and write from the memory cells of the memory array 3400. data. The address is provided by the bus 3405 to the word line decoder and block select decoder 3401 and bit line decoder 3403. The sense amplifier and data input structure in block 3406, including the drain line circuit and SRAM memory as shown in FIG. 28, is coupled to the bit line decoder 3403 via bus bar 3407. The data is supplied to the data input line 3434 via the input/output port on the integrated circuit 3450 to the data input structure in block 3406. The data is provided by the sense amplifier in block 3406, via the data output line 3415, to the input/output ports on the integrated circuit, or to other internal/external data sources of the integrated circuit 3450. The stylized verification and read orchestration bias state mechanism 3409 determines the application of the gate voltage and the stylized VT and the control bias adjustment supply voltage 3408 based on neighboring bits of the addressed bit in the same memory cell.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

Claims (12)

An integrated circuit comprising: a non-volatile memory cell, comprising: a first current load terminal, a second current load terminal and a gate; a first storage portion adjacent to the first current load terminal, and storing the first a second storage portion is adjacent to the second current load terminal and stores the second data; the control circuit applies a stylized verification programming bias to the first current load terminal, the second current load terminal and the gate; The stylized verification programming bias applied is based on one of the first data and the second data to programmatically verify the other of the first data and the second data. The integrated circuit of claim 1, wherein the first data determines a first voltage data applied to the first current load terminal in the stylized verification programming bias, and the stylized Verifying that the programming bias is used to programmatically verify the second data; wherein the second data determines a second voltage data applied to the second current load terminal of the stylized verification programming bias, and the applied The stylized verification programming bias is used to programmatically verify the first data. The integrated circuit of claim 1, wherein the first data represented by a first threshold voltage of the first storage portion exceeds a minimum threshold voltage, and one of the stylized verification programming biases is applied. The first voltage is applied to the first current load terminal to programmatically verify the second data; and the first data represented by a second threshold voltage of the first storage portion does not exceed a minimum threshold voltage, and the stylized A second voltage is applied to the first current load terminal to verify the second data; the first voltage is greater than the second voltage. For example, the integrated circuit of claim 3 includes: a memory storage data bit is determined by whether a threshold voltage representing the first data exceeds a minimum threshold voltage, wherein the control circuit reads from the memory The data bit is taken to control whether the first voltage or the second voltage is applied to the first current load terminal to read the second data in the read programming bias. For example, in the integrated circuit of claim 1, wherein each of the first data and the second data is one of a plurality of data values, the plurality of data values have a first total data value, The plurality of data values are represented by a plurality of stylized threshold voltage ranges having a second total number of programmed threshold voltage ranges greater than the first total number. For example, in the integrated circuit of claim 1, wherein each of the first data and the second data is one of a plurality of data values, the plurality of data values are represented by a plurality of stylized threshold voltage ranges, One of the plurality of data values is represented by a plurality of stylized threshold voltage ranges in the plurality of programmed threshold voltage ranges. For example, in the integrated circuit of claim 1, wherein each of the first data and the second data is one of a plurality of data values, the plurality of data values are represented by a plurality of stylized threshold voltage ranges, One of the plurality of data values is represented by a plurality of stylized threshold voltage ranges in the plurality of programmed threshold voltage ranges, the first data being one of the plurality of programmed threshold voltage ranges according to the second data Representative of a specific person. The integrated circuit of claim 1, wherein the first storage portion and the second storage portion are different portions of a tantalum nitride storage layer. For example, the integrated circuit of claim 1 of the patent scope, wherein the first data and the second data Each of them is a multiple bit. The integrated circuit of claim 1, wherein the input data of a stylized command determines the first data before applying the stylized verification programming bias according to the other of the first data and the second data And the other of the second information. The integrated circuit of claim 1, wherein the reading operation determines the first data and the first before applying the stylized verification programming bias according to the other of the first data and the second data The other of the two materials. A memory operation method includes: applying a stylized verification programming bias to a first current load terminal, a second current load terminal, and a gate of a non-volatile memory cell; applying the stylized verification programming offset Pressing one of the first data and the second data to read the other of the first data and the second data; the first data is stored in a first storage portion adjacent to the first The current load terminal and the second data are stored in a second storage portion adjacent to the second current load terminal.