CN103325413B - There is integrated circuit and the method for operating thereof of the storage unit of addressing and adjacent bit - Google Patents
There is integrated circuit and the method for operating thereof of the storage unit of addressing and adjacent bit Download PDFInfo
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- CN103325413B CN103325413B CN201210075735.1A CN201210075735A CN103325413B CN 103325413 B CN103325413 B CN 103325413B CN 201210075735 A CN201210075735 A CN 201210075735A CN 103325413 B CN103325413 B CN 103325413B
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Abstract
The invention discloses and a kind of there is the integrated circuit of the storage unit of addressing and adjacent bit and the method for operating of this storage unit.The storage layer of one nonvolatile memory cell is such as silicon nitride, and it has two storage compartments and stores addressable data respectively, is contiguous source terminal and drain terminal usually respectively.When sense be stored in the data of one of them of storage compartment time, the drain voltage applied is the data according to being stored in wherein another of storage compartment.If the data be stored in wherein another of storage compartment exceed representated by a threshold voltage of minimum threshold voltage by one, then increase the drain voltage applied.This technology can make threshold voltage interval broaden in read operation and program verification operate.
Description
Technical field
The present invention relates to memory technology field, especially a kind of have the integrated circuit of the storage unit of addressing and adjacent bit and the method for operating of this storage unit.
Background technology
The such as charge capturing storage unit of silicon nitride ROM (NROM) is can by being such as that the mechanism that channel hot electron injects (CHE) is programmed in the zones of different part of so far silicon nitride storage layer.One single memory cell can store in the different piece of data close source electrode and close drain electrode in this silicon nitride storage layer of different address respectively.The threshold voltage ranges of storage unit is relevant to the different pieces of information value that can be stored in every part in this storage unit.For example, in every part of multi-level cell memory, four threshold voltage ranges can represent four different pieces of information values of storage two positions.In three class's storage unit, eight threshold voltage ranges can represent eight different pieces of information values in storage three positions.
But, because be stored in the second effect that the data in the different piece in silicon nitride storage layer can affect each other, and limit a storage unit can threshold voltage interval.These different pieces are called " address bit " and " juxtaposition " of same memory cell herein.In this description, " position " is not limited to the data storing single data bit, and refers to the different entities position of the electric charge storage layer that can store 1,2,3 or more bit data.This address bit refers to one be such as programming or the order of reading in can be addressed solid data position, juxtaposition then refers to solid data position contiguous with address bit in a same memory cell.
US Patent No. 6011725 describes execution one reverse read operation and reads an addressable portion of this storage unit, be incorporated by reference data at this, the polarity of voltage being applied to source electrode and drain electrode be wherein with when channel hot electron programming operation to apply the polarity of voltage of the address bit of so far storage unit contrary.In this storage unit address bit performed by reverse read operation passage under the juxtaposition being positioned at same memory cell " must be punctured ".When this storage unit juxtaposition stored by data value relevant to a high threshold voltage, then this reverse read electric current reduce.Paper people such as LueHang-Ting " Studiesofthereversereadmethodandsecond-biteffectof2bit/c ellnitride-trappingdevicebyquesi-two-dimensionalmodel ", IEEETransactionsonElectronDevices, Vol.43, No.1, page119, describe second effect so in January2006 and can reduce available threshold voltage interval, be also incorporated by reference data at this.
This second effect can solve by increasing applied voltage swing when this reverse read operation.But, so increase voltage swing and can run into again the reading disturbing effect problem with juxtaposition of programming mistakenly when reading address bit.
Therefore, wishing can be interval by improving second effect to provide wider threshold voltage, and reduces the shortcomings such as adjoint such as reading interference programming simultaneously.
Summary of the invention
Technology described herein is that it has a nonvolatile memory cell and a control circuit about a memory circuit.This nonvolatile memory cell comprises one first current loading terminal (source electrode or drain electrode), one second current loading terminal (drain electrode or source electrode) and a grid.This nonvolatile memory cell has multiple storage compartment, and it can distinguish storage data.One first storage compartment is close to this first current loading terminal and stores the first data.One second storage compartment is close to this second current loading terminal and stores the second data.This first storage compartment and this second storage compartment can be the different pieces in a silicon nitride storage layer.
This control circuit applies one and reads this first current loading terminal that layout is biased into this nonvolatile memory cell, this the second current loading terminal and this grid, this reading layout bias voltage applied reads one of them of these first data and these the second data, and this reading layout bias voltage is according to wherein another of these first data and these the second data.For example, these first data determine that one first voltage data being applied to this first current loading terminal in this reading layout bias voltage is to read this second data.At the reverse read operation performed by these second data, electronics from this second current loading end flow to this first current loading terminal.In order to reduce second effect, increase reverse read electric current by increasing the voltage being applied to this first current loading terminal.And in order to avoid reading the interference programming of wish (first data not), if these first data representated by a first threshold voltage of this first storage compartment are more than a minimum threshold voltage, then increase the voltage being applied to this first current loading terminal.If these first data representated by a first threshold voltage of this first storage compartment are not more than a minimum threshold voltage, then the voltage that applying one is less is to this first current loading terminal.Some embodiment of this technology comprises, whether one memory storage data bit is decided more than a minimum threshold voltage by the threshold voltage representing these the first data, and wherein this control circuit reads this data bit to control whether to apply in this program verification layout bias voltage this first voltage or this second voltage to this first current loading terminal with these second data of program verification from this storer.
Similarly, these second data determine that the voltage being applied to this second current loading terminal in this reading layout biased operation is to read this first data.As described by this first current loading terminal, in order to avoid reading the interference programming of wish (first data not), if these second data representated by a Second Threshold voltage of this second storage compartment are more than a minimum threshold voltage, then increase the voltage being applied to this second current loading terminal.If these second data representated by a Second Threshold voltage of this second storage compartment are not more than a minimum threshold voltage, then the voltage that applying one is less is to this second current loading terminal.
Whether increase by this first current loading terminal or by the voltage of this second current loading terminal, this current interruption being increased voltage is called drain voltage terminal, because drain terminal is the current loading terminal of a high voltage, it is the destination (contrary with sense of current) of electron stream.In addition, whether read in the first data of the first storage compartment, or read in the second data of the second storage compartment, the storage compartment be read is called address bit, and the storage compartment be not read is called juxtaposition.As described before, " position " refers to a specific storage position in a storage unit in this description and is not limited to store the data of single data bit.Each address bit and juxtaposition can store the different entities position of the electric charge storage layer of 1,2,3 or more bit data.
When drain voltage is increased, the skew of sensing threshold voltage ranges can be caused because second effect reduces.Therefore, multiple programmed threshold voltage ranges can be had corresponding with identical sensing threshold voltage ranges.To the position of an addressing, be stored in the sensing threshold voltage ranges corresponding to data decision certain programmed threshold voltage ranges of juxtaposition.In addition, the overall number of programmed threshold voltage ranges exceedes the overall number of sensing threshold voltage ranges.
As described before, reading layout bias voltage is read one of them that be stored in these first data and these the second data in storage unit, and this reading layout bias voltage is according to wherein another of these first data and these the second data.In some embodiment of this technology, before this reading layout bias voltage of applying, these data determine wherein another of these first data and these the second data.In some embodiment of this technology, a read operation determines wherein another of these first data and these the second data.
Other embodiments of this technology are also described herein.These embodiments utilize program verification to replace about by reading.
Another embodiment of the present invention applies program verification layout bias voltage instead of adds a reading layout bias voltage.One program verification operation determines the programming whether carrying out a minimum number in a storage unit, and wherein a read operation determines that whether the threshold voltage of a storage unit is higher or lower than the intermediate threshold voltage between two minimum threshold voltage scopes relevant to different pieces of information value.
This program verification layout bias voltage applies one of them of these first data stored by this storage unit of program verification and these the second data, and this program verification layout bias voltage is according to wherein another of these first data and these the second data.Before applying program verification layout bias voltage, these data determine wherein another of these first data and these the second data.In some embodiment of this technology, a read operation determines wherein another of these first data and these the second data.In other embodiments of this technology, the input data of a program command determine wherein another of these first data and these the second data.
Other embodiments of this technology are also described herein.These embodiments utilize program verification to replace about by reading.
Another embodiment of the present invention is about a kind of method operating storage unit, comprising:
Apply one to read layout and be biased into one first current loading terminal of a nonvolatile memory cell, one second current loading terminal and a grid, this reading layout bias voltage applied is one of them of reading first data and the second data, this reading layout bias voltage is according to wherein another of these first data and these the second data, and this first data storing is in one first storage compartment this first current loading terminal contiguous and this second data storing in one second storage compartment this second current loading terminal contiguous.
Other embodiments of this technology are also described herein.These embodiments utilize program verification to replace about by reading.
Another embodiment of the present invention is about a kind of method operating storage unit, comprising:
Apply a program verification layout and be biased into one first current loading terminal of a nonvolatile memory cell, one second current loading terminal and a grid, this program verification layout bias voltage applied is one of them of reading first data and the second data, this reading layout bias voltage is according to wherein another of these first data and these the second data, and this first data storing is in one first storage compartment this first current loading terminal contiguous and this second data storing in one second storage compartment this second current loading terminal contiguous.
Other embodiments of this technology are also described herein.These embodiments utilize program verification to replace about by reading.
Accompanying drawing explanation
The schematic diagram of Fig. 1 to Fig. 2 nonvolatile memory cell, it has address bit and the juxtaposition of storage data respectively.
Fig. 3 to Fig. 5 is the icon of threshold voltage, the second effect that " juxtaposition " that show one " address bit " causes.
Fig. 6 to Fig. 7 is the icon of threshold voltage, and display increases the second effect that its " juxtaposition " that can reduce by one " address bit " of drain voltage causes.
Fig. 8 to Figure 23 is the threshold voltage icon of one " address bit " and one " juxtaposition ", shows the data ordering of different " address bit " and " juxtaposition ", and the minimizing of second effect in many kinds of data ordering.
Figure 24 and Figure 25 is the icon of threshold voltage, shows the programmed threshold voltage ranges of the data ordering of different " address bit " and " juxtaposition " and sensing threshold voltage ranges.
Figure 26 shows the threshold voltage distribution of different drain bias, and it can adjust according to the data value in a juxtaposition can not adjust this drain bias.
Figure 27 is the block schematic diagram of drain line driving circuit block, and it has the drain voltage determined by the data be stored in a static RAM SRAM.
Figure 28 is usual static RAM SRAM block, and it produces signal to control drain voltage from a drain line driving circuit block.
Figure 29 is a sample circuit diagram of a drain line driving circuit.
Figure 30 is the process flow diagram of a read operation according to the value of juxtaposition with adjustment drain bias.
Figure 31 to Figure 33 is the process flow diagram of the programming operation according to the value of juxtaposition with adjustment drain bias.
Figure 34 display has the simplification block schematic diagram of the integrated circuit of improvement described herein and storage array according to one embodiment of the invention.
[main element symbol description]
3450: integrated circuit
3400: array of nonvolatile memory cells
3401: column decoder
3402: wordline
3403: line decoder
3404: bit line
3405: bus
3407: data bus
3406: sensing amplifier/data input structure/drain line circuit
3409: program verification and reading layout bias state mechanism determine drain voltage and programming VT according to juxtaposition
3408: bias voltage adjustment supply voltage
3411: Data In-Line
3415: DOL Data Output Line
Embodiment
Example shown here is have four possible data values in a storage unit.Other example can be have two possible data values, have eight possible data values or have the possible data values of other numbers.
The schematic diagram of Fig. 1 to Fig. 2 nonvolatile memory cell, it has address bit and the juxtaposition of storage data respectively.
Fig. 1 shows a nonvolatile memory cell and has data storing among the different piece of silicon nitride storage layer.These different pieces in same storage unit are called " address bit " and " juxtaposition " herein.In the description herein, " position " one word refer to provider locations different in electric charge storage layer it can store the data of 1,2,3 or more multidigit.This storage unit has a gate terminal, two current loading terminal-drain terminal and source terminal.Drain terminal voltage can change according to the data value near source terminal.Because specific currents load terminal for this reason can change as the terminal of the electric current that bleeds, and to cause be that this specific currents load terminal of drain terminal also can along with variation.In FIG, address bit is the left part at this storage unit electric charge storage layer and the current loading terminal near the left side, and juxtaposition is the right part at this storage unit electric charge storage layer and the current loading terminal near the right.On the right of this and the current loading terminal profile on the left side be the source electrode of low voltage and the drain electrode of high voltage, and the direction of electron stream flows to drain electrode, the situation in the programming of display different " address bit " and " juxtaposition " and reverse read operation.
Fig. 2 shows a nonvolatile memory cell and has data storing among the different piece of silicon nitride storage layer, and it is similar to Fig. 1.But be the right part at this storage unit electric charge storage layer and the current loading terminal near the right with Fig. 1 unlike, address bit, and juxtaposition is the left part at this storage unit electric charge storage layer and the current loading terminal near the left side.Because the position of " address bit " and " juxtaposition " is exchanged in fig. 2, the position of its source electrode and drain electrode and the direction of electron stream are also contrary with Fig. 1.
Fig. 3 to Fig. 5 is the icon of threshold voltage, the second effect that " juxtaposition " that show one " address bit " causes.When sensing this address bit, a low drain voltage VBLR_1 is applied to drain terminal.The sensing VT distribution of this address bit and the physical location of this address bit in this storage unit are shown in the solid line in figure.The sensing VT distribution of this juxtaposition and the physical location of this juxtaposition in this storage unit are shown in the dotted line in figure.
In figure 3, address bit has an initially sensing VT distribution.Appended graphic middle display addressing position is the left part of the electric charge storage layer in this storage unit.Juxtaposition is not yet programmed to a high VT distribution, so there is not second effect.
In the diagram, juxtaposition is programmed to a high VT distribution.Appended graphic middle display juxtaposition is the right part of the electric charge storage layer in this storage unit.
In Figure 5, address bit initially senses VT distributions shift to higher sensing VT since then and distributes.The skew of this " sensing VT distribution " the change of unreacted in " programming VT distribution ", because electric charge is not programmed so far address bit.But the sensing VT distributions shift of address bit caused by second effect.The higher skew of the sensing VT distribution of address bit, be because juxtaposition under channel part there is higher threshold voltage, and reduce current sensor and increase address bit sensing VT distribute caused by.
Fig. 6 to Fig. 7 is the icon of threshold voltage, and display increases the second effect that its " juxtaposition " that can reduce by one " address bit " of drain voltage causes.The sensing VT of this address bit distributes the solid line be shown in figure.The sensing VT of this juxtaposition distributes the dotted line be shown in figure.
In figure 6, the value of juxtaposition is sensed, to determine the drain voltage sensing this address bit.Apply the word line read voltage of juxtaposition to sense this juxtaposition.If the sensing VT of this juxtaposition exceedes the threshold V T of word line read voltage, then consequently data 0, Nb_h (juxtaposition high level)=1, Nb_l (juxtaposition low level)=0.If the sensing VT of this juxtaposition does not exceed the threshold V T of word line read voltage, then consequently data 1, Nb_h=0, Nb_l=1.In this example, the sensing VT of juxtaposition does not exceed the threshold V T of word line read voltage, then consequently data 1, Nb_h=0, Nb_l=1.
In the figure 7, because the result of Fig. 6, apply high drain voltage VBLR_h to sense this address bit.This high drain voltage tendency can increase current sensor, and tendency counter second effect.Because the minimizing of second effect, the VT distributions shift of this address bit also reduces.The minimizing of this VT distributions shift makes available VT interval broaden.
Fig. 8 to Figure 23 is the threshold voltage icon of one " address bit " and one " juxtaposition ", shows the data ordering of different " address bit " and " juxtaposition ", and the minimizing of second effect in many kinds of data ordering." H " or " L " respectively above address bit data value and juxtaposition data value indicates when sensing one certain bits is apply high drain voltage VBLR_h or low drain voltage VBLR_l.If the sensing VT of this juxtaposition does not exceed lowest critical value VGN, then apply low drain voltage VBLR_l to sense address bit data value.If the sensing VT of this juxtaposition exceedes lowest critical value VGN, then apply high drain voltage VBLR_h to sense address bit data value.If the sensing VT of this address bit does not exceed lowest critical value VGN, then apply low drain voltage VBLR_l to sense juxtaposition data value.If the sensing VT of this address bit exceedes lowest critical value VGN, then apply high drain voltage VBLR_h to sense juxtaposition data value.Lowest critical value shown in figure is between data value " 3 " and the programming threshold distribution of " 4 ".Other embodiment can apply other lowest critical value.
Fig. 8 ~ Figure 11 is the icon of the threshold voltage of when the data value of address bit is " 1 " (from minimum in the highest VT value 1 to 4).In fig. 8, juxtaposition has data value " 1 ".In fig .9, juxtaposition has data value " 2 ".In Fig. 10, juxtaposition has data value " 3 ".In fig. 11, juxtaposition has data value " 4 ".Because the sensing VT of juxtaposition exceedes lowest critical value VGN, so apply high drain voltage VBLR_h to sense address bit data value.Because the programming VT " 1 " of VT " 0A " this address bit reduced is sensed.Although show different programming VT to distribute, the VT of this " 1 " and " 0A " can be considered to identical, because both are all the VG1 critical values be less than for sensing difference between minimum VT data value and any higher VT data value.
Figure 12 ~ Figure 15 is the icon of the threshold voltage of when the data value of address bit is " 2 " (from minimum in the highest VT value 1 to 4).In fig. 12, juxtaposition has data value " 1 ".In fig. 13, juxtaposition has data value " 2 ".In fig. 14, juxtaposition has data value " 3 ".In fig .15, juxtaposition has data value " 4 ".Because the sensing VT of juxtaposition exceedes lowest critical value VGN, so apply high drain voltage VBLR_h to sense address bit data value.The programming VT " 2A " of this address bit is sensed the VT " 2 " into reducing.It is " 2 " that this address bit is programmed to that VT " 2A " makes to sense VT.
Figure 16 ~ Figure 19 is the icon of the threshold voltage of when the data value of address bit is " 3 " (from minimum in the highest VT value 1 to 4).In figure 16, juxtaposition has data value " 1 ".In fig. 17, juxtaposition has data value " 2 ".In figure 18, juxtaposition has data value " 3 ".In Figure 19, juxtaposition has data value " 4 ".Because the sensing VT of juxtaposition exceedes lowest critical value VGN, so apply high drain voltage VBLRh to sense address bit data value.The programming VT " 3A " of this address bit is sensed the VT " 3 " into reducing.It is " 3 " that this address bit is programmed to that VT " 3A " makes to sense VT.Because address bit " 3A " is also above lowest critical value VGN for this reason, juxtaposition is also sense to have high drain voltage VBLR_h.This juxtaposition VT be programmed to VT " 4A " make juxtaposition VT be sensed into reduce VT " 4 ".Otherwise if juxtaposition VT is maintained at VT " 4 " and is not programmed to VT " 4A ", then this juxtaposition VT is sensed the VT " 4B " into comparatively VT " 4 " minimizing.
Figure 20 ~ Figure 23 is the icon of the threshold voltage of when the data value of address bit is " 4 " (from minimum in the highest VT value 1 to 4).In fig. 20, juxtaposition has data value " 1 ".In figure 21, juxtaposition has data value " 2 ".In fig. 22, juxtaposition has data value " 3 ".In fig 23, juxtaposition has data value " 4 ".As shown in Figure 19, it is the arrangement contrary with Figure 22, and its address bit and juxtaposition are exchanged, and the programming VT of this juxtaposition VT is " 3A ", and it is sensed the VT " 3 " into reducing.Because the sensing VT " 3A " of juxtaposition exceedes lowest critical value VGN, so juxtaposition sensing is for having high drain voltage VBLR_h.This address bit be programmed to VT " 4A " make address bit VT be sensed into reduce VT " 4 ".If address bit VT is maintained at VT " 4 " and is not programmed to VT " 4A ", then this address bit VT is sensed the VT " 4B " into comparatively VT " 4 " minimizing.In fig 23, juxtaposition has data value " 4 ".Because juxtaposition exceedes lowest critical value VGN, apply high drain voltage VBLR_h to sense address bit.This address bit is programmed to VT " 4A " and makes address bit VT be sensed to be VT " 4 ".Because address bit " 4A " is also above lowest critical value VGN, juxtaposition is also sense to have high drain voltage VBLR_h.This juxtaposition is programmed to VT " 4A " and makes juxtaposition VT be sensed to be VT " 4 ".Otherwise if juxtaposition VT is maintained at VT " 4 " and is not programmed to VT " 4A ", then this juxtaposition VT is sensed the VT " 4B " into comparatively VT " 4 " minimizing.
Figure 24 and Figure 25 is the icon of threshold voltage, shows the programmed threshold voltage ranges of the data ordering of different " address bit " and " juxtaposition " and sensing threshold voltage ranges." address bit " has bottom line and " juxtaposition " does not have bottom line.
Figure 24 display by when programming this storage unit increase the programming VT that electric charge defines and distribute.Because electric charge stored under one storage unit in time sensing can not change usually (except reading disturbing effect), this programming VT is distributed in read when bias voltage changes and usually also can not changes.
Figure 25 display by sensing VT distribute, its sense apply drain voltage time change.Sensing VT in fig. 25 directly determines the sense data value be stored in a storage unit, and the number of sensing VT distribution is equal with the number of the data value representated by address bit or juxtaposition.
As what discuss in Figure 15, Figure 19, Figure 22 and Figure 23, this programming VT distribution expection by high drain voltage and sensing VT distribute cause VT skew.So the programming VT distribution of Figure 24 does not comprise high drain bias by VT distributions shift to the effect of smaller value.The sensing VT distribution of Figure 25 then comprises high drain bias by VT distributions shift to the effect of smaller value.Therefore, the lower sensing VT that the < address bit >< juxtaposition > programming VT distribution <2><4GreatT.Grea T.GT in Figure 24 is offset in Figure 25 distributes.Similar self-programming VT distributions shift to the sensing VT distribution of lower VT size be also shown in < address bit >< juxtaposition > combine in <3><4GreatT.Grea T.GT, <4><3GreatT.Grea T.GT and <4><4GreatT.Grea T.GT.
The specific sense data value of instruction one that to distribute with the sensing VT of Figure 25 of being distributed by the programming VT of Figure 24 can be represented by multiple P VT scope.In addition, the number of sensing VT scope with can the number of data value stored by address bit or juxtaposition equal, the number of VT scope of programming then is above can the number of data value stored by address bit or juxtaposition.
Figure 26 shows the threshold voltage distribution of different drain bias, and it can adjust according to the data value in a juxtaposition or not adjust this drain bias.
This longitudinal axis is that the position counting represented in logarithmic fashion in this emulation testing storage array of display has a specific sensing VT on transverse axis.Dashed trace is corresponding with not having the detection procedure adjusting drain bias according to the data value in juxtaposition.Solid line track is then that participant is corresponding according to the detection procedure of the data value adjustment drain bias in juxtaposition.VT interval can broaden by this icon display adjustment drain bias, and particularly between two minimum VT distributions, it has a VT spacing being about 0.5V broadened.
Figure 27 is the block schematic diagram of drain line driving circuit block, and it has the drain voltage determined by the data be stored in a static RAM SRAM.From top to bottom, this block comprises a juxtaposition static RAM SRAM block, SENAMP sensing amplifier, the capable multiplexer of YMUX and ARRAY storage array.
Figure 28 is usual static RAM SRAM block, and it produces signal to control drain voltage from a drain line driving circuit block.One SRAM memory produces Nb_h, Nb_l signal as Fig. 6.If the sensing VT of this juxtaposition exceedes the threshold V T of word line read voltage, make high drain voltage can be applied in sense this address bit, Nb) h (juxtaposition high level)=1, Nb_l (juxtaposition low level)=0.If the sensing VT of this juxtaposition does not exceed the threshold V T of word line read voltage, make low drain voltage can be applied in sense this address bit, Nb_h (making peri position high level)=0, Nb_l (juxtaposition low level)=1.
Figure 29 is a sample circuit diagram of a drain line driving circuit.Two parallel Sheffer stroke gate serials are connected with Vdd supply voltage and DL drain line.Sheffer stroke gate serial received grid voltage Vblr_h and Nb_h in left side.Sheffer stroke gate serial received grid voltage Vblr_l and Nb_l on right side.Nb_h if (juxtaposition high level)=1, Nb_l (juxtaposition low level)=0, then left side Sheffer stroke gate serial unlatching and right side Sheffer stroke gate serial close.DL drain line then has the value (being less than a transistor VT) of Vblr_h.Nb_h if (juxtaposition high level)=0, Nb_l (juxtaposition low level)=1, then left side Sheffer stroke gate serial closedown and right side Sheffer stroke gate serial open.DL drain line then has the value (being less than a transistor VT) of Vblr_l.
Figure 30 is the process flow diagram of a read operation according to the value of juxtaposition with adjustment drain bias.In step 12, receive one " reading order " and a storage unit " address of address bit ".In step 14, store the address of address bit, and according to this address bit, obtain the address of juxtaposition.A form can produce index to the address of address bit and the address of juxtaposition simultaneously, allows address bit again to video to juxtaposition.In step 16, the address of juxtaposition is used to sense juxtaposition.Its default value uses low drain voltage.As shown in Figure 6, store the contiguous place value of its instruction of these data and there is sufficiently high VT to allow high drain voltage to sense address bit.An exemplary memory as shown in Figure 28 stores this data.In step 18, again obtain the Input Address of address bit stored at step 14.In step 20, check juxtaposition SRAM and according to data stored in step 16, determine whether the sensing VT of juxtaposition exceedes critical VT.In step 22, if the sensing VT of juxtaposition exceedes critical VT, then drain voltage is vblr_h.In step 24, if the sensing VT of juxtaposition does not exceed critical VT, then drain voltage is vblr_l.In step 26, utilize vbrl_h or vblr_l drain voltage to sense address bit.In step 28, terminate this reading order.
Figure 31 to Figure 33 is the process flow diagram of the programming operation according to the value of juxtaposition with adjustment drain bias.In Figure 31, drain voltage initially determines according to sense data.In Figure 32 and Figure 33, drain voltage initially determines according to the input data together with program command.
In Figure 31, in step 30, receive " program command " and " data for being programmed " with programming address.In step 32, according to the data for being programmed received in step 30, content for being programmed to address bit is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM1, and the content for being programmed to juxtaposition is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM2.In step 34, read juxtaposition, its default value uses low drain voltage.As shown in Figure 6, store the contiguous place value of its instruction of these data and there is sufficiently high VT to allow high drain voltage to sense address bit.An exemplary memory as shown in Figure 28 stores this data.In step 36, according to data stored in step 34, this address bit of program verification has high or low drain bias.In step 38, read address bit, its default value uses low drain voltage.Store its instruction address bit of these data and whether there is sufficiently high VT to allow high drain voltage to sense juxtaposition.In step 40, according to data stored in step 38, this juxtaposition of program verification has high or low drain bias.In step 42, determine whether pass through in the program verification operation of step 36 and 40.In step 44, if failed in the program verification operation one of step 36 and 40, then programme juxtaposition and/or address bit, and also this flow process starts repetition from step 34.In step 46, if pass through in the program verification operation of step 36 and 40, then terminate this program command.
In Figure 32, in step 50, receive " program command " and " data for being programmed " with programming address.In step 52, according to the data for being programmed received in step 50, content for being programmed to address bit is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM1, and the content for being programmed to juxtaposition is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM2.In step 54, check whether the data be stored in SRAM1 and SRAM2 apply higher drain voltage with decision and carry out program verification to juxtaposition.Because address bit and the content both juxtaposition can determine this VT, as shown in Figure 24 ~ Figure 25 to the data inspection in SRAM1 and SRAM2.In step 56, use the drain voltage of the data according to address bit in SRAM1, program verification juxtaposition.In step 58, check whether the data be stored in SRAM1 and SRAM2 apply higher drain voltage with decision and carry out program verification to address bit.Because address bit and the content both juxtaposition can determine this VT, as shown in Figure 24 ~ Figure 25 to the data inspection in SRAM1 and SRAM2.In step 60, in general storage SRAM2 as shown in Figure 28, the data of juxtaposition are in juxtaposition SRAM, to the drain voltage of address bit setting program verification.In step 62, determine whether pass through in the program verification operation of step 56 and 60.In step 64, if failed in the program verification operation one or both of step 56 and 60, then programme juxtaposition and/or address bit, and also this flow process starts repetition from step 54.In step 66, if pass through in the program verification operation of step 56 and 60, then terminate this program command.
In fig. 33, in step 70, receive " program command " and " data for being programmed " with programming address.In step 72, according to the data for being programmed received in step 70, content for being programmed to address bit is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM1, and the content for being programmed to juxtaposition is processed to determine that whether corresponding VT is more than the critical VT shown in Fig. 6, and its result is stored to SRAM2.In step 74, check whether the data be stored in SRAM1 and SRAM2 apply higher drain voltage with decision and carry out program verification to address bit and juxtaposition.Because address bit and the content both juxtaposition can determine this VT, as shown in Figure 24 ~ Figure 25 to the data inspection in SRAM1 and SRAM2.In step 76, use the drain voltage of the data according to address bit in SRAM1, program verification juxtaposition, and use the drain voltage according to the data of juxtaposition in SRAM2, program verification address bit.In step 78, determine whether pass through in the program verification operation of step 76.In step 80, if in the program verification operation failure of step 76, then programme juxtaposition and/or address bit, and also this flow process starts repetition from step 74.In step 82, if pass through in the program verification operation of step 76, then terminate this program command.
Figure 34 display has the simplification block schematic diagram of the integrated circuit of improvement described herein and storage array according to one embodiment of the invention.Wherein integrated circuit 3450 comprises storage array 3400.One wordline (row) code translator and block select code translator 3401 to couple with along many wordline 3402 of storage array 3400 column direction arrangement and serial selection line and electrically link up.One bit line (OK) code translator and driver 3403 couple with the multiple bit lines 3404 along the arrangement of storage array 3400 line direction and electrically link up, to read data and write data from the storage unit of this storage array 3400.Address is supplied to word-line decoder by bus 3405 and block selects code translator 3401 and bit line decoder 3403.Sensing amplifier in square 3406 and data input structure, comprise drain line circuit as shown in Figure 28 and SRAM memory, couples via bus 3407 and bit line decoder 3403.Data are supplied to Data In-Line 3434 by the input/output end port on integrated circuit 3450 and input to data input structure in square 3406.Data, by the sensing amplifier in square 3406, via DOL Data Output Line 3415, are provided to the I/O port on integrated circuit, or to the data source of other inner/outer of integrated circuit 3450.Program verification and reading layout bias state mechanism 3409 decide this drain voltage and programming VT according to the juxtaposition of address bit in a same memory cell, and control the application of bias voltage adjustment supply voltage 3408.
Preferred embodiment of the present invention and example disclose as above in detail, but are to be appreciated that above-mentioned example is only as example, are not used to the scope limiting patent.With regard to the people knowing skill, from modifying and combination to correlation technique according to appended claims easily.
Claims (11)
1. an integrated circuit, comprises:
One nonvolatile memory cell, comprising:
One first current loading terminal, one second current loading terminal and a grid;
One first storage compartment this first current loading terminal contiguous, and store the first data; And
One second storage compartment this second current loading terminal contiguous, and store the second data;
In one reads or a program verification operates, control circuit applies a reading or a program verification layout is biased into this first current loading terminal, this the second current loading terminal and this grid, this reading applied or program verification layout bias voltage read one of them of these first data and these the second data, and this reading or program verification layout bias voltage are wherein another according to a sensing voltage of these the first data and a sensing voltage of these the second data.
2. integrated circuit according to claim 1,
Wherein the sensing voltage of these the first data determines one first voltage data in this reading or program verification layout bias voltage, and it is applied to this first current loading terminal to read this second data;
Wherein the sensing voltage of these the second data determines one second voltage data in this reading or program verification layout bias voltage, and it is applied to this second current loading terminal to read this first data.
3. integrated circuit according to claim 1, wherein respond these first data representated by a first threshold voltage of this first storage compartment more than a minimum threshold voltage, in this reading or program verification layout bias voltage, apply one first voltage to this first current loading terminal to read this second data;
Response these first data representated by a Second Threshold voltage of this first storage compartment, not more than a minimum threshold voltage, apply one second voltage to this first current loading terminal to read this second data in this reading or program verification layout bias voltage;
This first voltage is large compared with this second voltage.
4. integrated circuit according to claim 3, more comprises:
One storer, wherein whether stored data bit is decided more than a minimum threshold voltage by the threshold voltage representing these the first data, and wherein this control circuit reads this data bit to control whether will to apply in this reading or program verification layout bias voltage this first voltage or this second voltage to this first current loading terminal to read this second data from this storer.
5. integrated circuit according to claim 1, wherein each of these first data and these the second data is in multiple data value, the plurality of data value has the data value of one first sum, the plurality of data value is represented by multiple programmed threshold voltage ranges, the plurality of programmed threshold voltage ranges has the programmed threshold voltage ranges of one second sum, and this second sum is greater than this first sum.
6. integrated circuit according to claim 1, wherein each of these first data and these the second data is in multiple data value, the plurality of data value is represented by multiple programmed threshold voltage ranges, and a data value in the plurality of data value is represented by the multiple programmed threshold voltage ranges in the plurality of programmed threshold voltage ranges.
7. integrated circuit according to claim 1, wherein each of these first data and these the second data is in multiple data value, the plurality of data value is represented by multiple programmed threshold voltage ranges, a data value in the plurality of data value is represented by the multiple programmed threshold voltage ranges in the plurality of programmed threshold voltage ranges, and these first data represent by according to the particular one in the plurality of programmed threshold voltage ranges of these the second data.
8. integrated circuit according to claim 1, wherein this first storage compartment and this second storage compartment are the different pieces in a silicon nitride storage layer.
9. integrated circuit according to claim 1, wherein each of these first data and these the second data is multiple positions.
10. integrated circuit according to claim 1, wherein before applying this reading or program verification layout bias voltage according to the another one of these first data and these the second data, this read operation determines the another one of these first data and these the second data.
11. 1 kinds of memory operating methods, comprising:
In one reads or a program verification operates, applying one reading or a program verification layout are biased into one first current loading terminal of a nonvolatile memory cell, one second current loading terminal and a grid, this layout bias voltage applied is one of them of reading first data and the second data, this reading or program verification layout bias voltage are according to wherein another of a sensing voltage of these the first data and a sensing voltage of these the second data, this first data storing is close to this second current loading terminal in one first storage compartment this first current loading terminal contiguous and this second data storing in one second storage compartment.
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| JPH0729383A (en) * | 1993-07-12 | 1995-01-31 | Toshiba Corp | Semiconductor memory and reading method therefor |
| TW200929225A (en) * | 2007-12-25 | 2009-07-01 | Powerchip Semiconductor Corp | Memory programming method and data access method |
| CN101499318A (en) * | 2008-02-03 | 2009-08-05 | 力晶半导体股份有限公司 | Memory programming method and data access method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0729383A (en) * | 1993-07-12 | 1995-01-31 | Toshiba Corp | Semiconductor memory and reading method therefor |
| TW200929225A (en) * | 2007-12-25 | 2009-07-01 | Powerchip Semiconductor Corp | Memory programming method and data access method |
| CN101499318A (en) * | 2008-02-03 | 2009-08-05 | 力晶半导体股份有限公司 | Memory programming method and data access method |
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