TW201506929A - Semiconductor storage device - Google Patents

Abstract

The purpose of the present invention is to reduce chip area. The present invention is provided with a bit line pair, sense amplifier circuits which are connected between the bit line pair and which are configured with 2 CMOS inverter circuits for which input and output are mutually connected, an equalizer circuit connected between the bit line pair, and a drive transistor which drives a drive line of the sense amplifier circuits; wherein one transistor configuring the CMOS inverter circuits, a transistor group configuring the equalizer circuit, and the drive transistor are of a first conductivity type and have the same first threshold.

Description

Semiconductor memory device (about the record of the related application)

The present invention claims priority to Japanese Patent Application No. 2013-033288 (filed on Feb. 22, 2013), the entire content of which is incorporated herein by reference.

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a sense amplifier.

In a semiconductor memory device typified by a SDRAM (Synchronous Dynamic Random Access Memory), a transistor having a lower threshold value is used for speeding up the operation of the sense amplifier or its peripheral circuits.

For example, Patent Document 1 discloses a semiconductor memory device in which the threshold value of the precharged transistor is set to be lower than the threshold value of the memory cell and the peripheral transistor to shorten For the pre-charging time of the bit line, high-speed operation is possible. Moreover, it is also revealed that the threshold value of the sensing amplifying transistor is set to be larger than the memory cell. The lower limit of the crystal and the peripheral transistor is lower, so that the sensing time can be shortened and the high-speed operation can be performed.

Further, Patent Document 2 discloses a semiconductor memory device characterized in that even if the voltage reduction of the semiconductor memory device progresses, the transistor can be driven by the sense amplification, and the sense amplification can be performed. A pre-charged transistor uses a low-threshold transistor, and these are driven by a negative voltage to improve the driving ability of each transistor, thereby enabling the amplification of the sense amplifier and the bit line and sense. The pre-charging operation of the measuring and amplifying portion is speeded up, and the subthreshold leak at the time of inactivation can also be reduced.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. Hei 10-178161

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2000-293986

The following analysis is performed by the invention of the present invention.

In addition, in the development of the tip process, the size of the memory cell region tends to be reduced due to miniaturization. On the other hand, the miniaturization at the peripheral portion of the sense amplifier or the sub-line driver or the like is less advanced than the memory cell, and the reduction in the size of this region is a new problem. In particular, at the sense amplifier, this tendency is In order to remarkably, in the future, while further miniaturization is achieved, it is also desired to suppress an increase in the area of the wafer at the sense amplifier portion.

A semiconductor memory device of one aspect (side) of the present invention is provided with: a bit line pair; and a sense amplifying circuit which is connected between the bit line pairs and connects the input and output to each other 2 a CMOS inverter circuit; and an equalization circuit connected between the bit line pairs; and a driving transistor that drives the driving line of the sensing amplifying circuit to form a transistor of one of the CMOS inverting circuits The transistor group and the driving transistor that constitute the equalization circuit are first conductivity type and have the same first threshold value.

According to the present invention, the area of the wafer can be reduced.

1‧‧‧Semiconductor memory device

10‧‧‧Control logic

20‧‧‧ row decoder & timing signal generation circuit

30‧‧‧ Column Decoder & Timing Signal Generation Circuit

40‧‧‧ memory cell array

50‧‧‧Sense Amplifier

60‧‧‧Amplification & Buffer Department

70‧‧‧Data input and output department

BLEQ‧‧‧ equalization circuit

BUF1, BUF2‧‧‧ buffer circuit

DEC1, DEC2‧‧‧ decoding circuit

LS1, LS2‧‧‧ level traversing circuit

MN1~MN8‧‧‧NMOS transistor

MP1~MP3‧‧‧ PMOS transistor

N-Well‧‧‧N well area

P-Well‧‧‧P well area

SA1, SA2‧‧‧ transistor pairs

YS‧‧‧Y switch circuit

Fig. 1 is a block diagram showing the configuration of a semiconductor memory device of a first embodiment.

Fig. 2 is a circuit diagram of a sense amplifying portion of the first embodiment.

Fig. 3 is a view schematically showing the layout of the sense amplifying portion of the first embodiment.

Fig. 4 is a block diagram showing the configuration of a drive circuit of the sense amplifier unit of the second embodiment.

[Fig. 5] is a diagram for explaining the occurrence of an OFF LEAKAGE CURRENT.

Hereinafter, one embodiment of the disclosure of the present invention will be briefly described. In addition, the symbols of the drawings that are added to the following detailed description are merely illustrative for the purpose of understanding, and are not intended to limit the invention.

The semiconductor memory device of one embodiment includes: a bit line pair (BL3T, BL3B in FIG. 2); and a sense amplifier circuit (corresponding to SA1 and SA2 in FIG. 2) connected to the bit element. a two-phase CMOS (Complementary Metal Oxide Semiconductor) inverter circuit that connects the input and output to each other; and an equalization circuit (BLEQ of FIG. 2) is connected between the bit line pairs; The driving transistor (MN6 of FIG. 2) drives the driving line of the sensing amplifying circuit, constitutes a transistor of one of the CMOS inverting circuits (MN1, MN2 of FIG. 2), and a transistor group constituting the equalizing circuit (FIG. 2) MN3~MN5) and the driving transistor are first conductivity type and have the same first threshold.

In the semiconductor memory device, the transistor constituting one of the CMOS inverting circuits and the transistor group and the driving transistor constituting the equalizing circuit may be disposed in one well region of the second conductivity type (Fig. Within 3 P-Well).

In the semiconductor memory device, one of the second conductivity type well regions may be formed in one direction, and one of the equalization circuits and one of the ones of the sense amplifier circuits. The order of one of the transistor, the driving transistor, the transistor in one of the other sensing amplifier circuits, and the other equalizing circuit is used to separate the components. The way the area is included. In addition, in order to set a transistor whose threshold value is different, a channel doping corresponding to each transistor is required or an LDD (Lightly Doped Drain) is required. To cope with this, it is necessary to introduce impurities for introducing the transistor. The separation area of the implanted region is separated, and the so-called element separation region herein refers to the separation margin. Therefore, the element isolation region here is different from the separation region due to separation of a field region such as an STI (Shallow Trench Isolation) in which an insulating film is buried.

In a semiconductor memory device, the so-called one direction can also be the direction in which the bit line pairs are arranged.

In the semiconductor memory device, the first threshold value is set to Vt1, and the input/output line pair is connected to the transistor for controlling the bit line pair (MN7, MN8 of FIG. 2). When the threshold value is Vt2 and the threshold value of the transistor constituting the lanthan control circuit is Vt3, it is configured to satisfy Vt1 < Vt2 < Vt3.

In the semiconductor memory device, the driving transistor may be configured to be driven by a single sensing amplifier circuit and other sensing amplifier circuits to be a common driving line.

In the semiconductor memory device, the first level traversing circuit for generating the first driving signal based on the potential lower than the potential of the source of the driving transistor may be provided (FIG. 4) LS1), the gate of the driving transistor, is driven by the first driving signal.

The semiconductor memory device may be configured to include a second level traverse circuit for generating a second driving signal having a lower potential than a potential of a source of the driving transistor (FIG. 4) LS2), the respective gates of the transistor group constituting the equalization circuit are driven by the second driving signal.

According to the above general semiconductor memory device, the transistor constituting one of the CMOS inverter circuits and the transistor group constituting the equalization circuit and the driving transistor are disposed in one well region without providing the component isolation region. The ground is formed. Therefore, the area of the wafer to be connected to the sense amplifying portion can be reduced by omitting the element isolation region.

Hereinafter, the embodiment will be described in detail with reference to the drawings.

[Example 1]

Fig. 1 is a block diagram showing the configuration of the semiconductor memory device of the first embodiment. In FIG. 1, a semiconductor memory device 1 is composed of a control logic 10, a row decoder & timing signal generating circuit 20, a column decoder & timing signal generating circuit 30, a memory cell array 40, and a sense amplifier 50. And the amplification & buffer unit 60 and the data input/output unit 70 are configured.

The control logic 10 receives the commands supplied from the outside and generates various internal signals (the control logic 10 is equivalent to the above-described control circuit). Specifically, if the control logic 10 is supplied with a start command from the outside, an internal start command signal IACT is generated, and if a read command is supplied from the outside, an internal read command signal IRD is generated, and if When a write command is supplied externally, an internal write command signal IWRT is generated.

The internal start command signal IACT maintains the HIGH level of the active level until a precharge command is supplied.

The control logic 10 generates a timing signal TCCDT that becomes a HIGH level as an active level during the tCCDmin period when a write command is supplied from the outside. Here, in the case of the tCCDmin period, when the read operation or the write operation is repeated (continuously), the read command or the read command is received until the next write command or It is the time until the instruction is read, and it is the period of the lower limit. During tCCDmin, it can be expressed by the number of clock cycles.

The control logic 10 is internally provided with a TCCDT generating circuit that receives the clock signal CK supplied from the outside and counts the clock signal CK to generate the timing signal TCCDT. The internal start command signal IACT is output to the row decoder & timing signal generating circuit 20. The internal read command signal IRD, the internal write command signal IWRT, and the timing signal TCCDT are output to the column decoder & timing signal generating circuit 30.

The row decoder & timing signal generating circuit 20 receives the address signal ADD as a row address in response to the internal enable command signal IACT. The row decoder & timing signal generating circuit 20 outputs control signals of various line systems in response to the internal start command signal IACT and the row address. Specifically, the word line selection signal WLS is output to the memory cell array 40, and the switching control signal S1, the sense amplifier activation signal CSP, and the CSN are output to the sense amplifier 50.

Further, the row decoder & timing signal generating circuit 20 includes a plurality of local input/output equalization signal generating circuits LIOEQSC1 to LIOEQSCk (k is a positive integer, the same applies hereinafter). The plurality of local input and output equalization signal generating circuits LIOEQSC1~LIOEQSCk respectively generate equalization signals EQ1~EQk and local input/output line equalization signals LEQ2B1~LEQ2Bk. A partial input/output equalization signal generating circuit LIOEQSCi selected by a row address in a plurality of local input/output equalization signal generating circuits LIOEQSC1 to LIOEQSCk (i is a positive integer of 1 or more and k or less, the same applies hereinafter In the first period, the equalization signal EQi is set to an inactive level, and the local input/output line equalization signal LEQ2Bi is set to be controlled according to the burst signal BSTFLGT and the input/output equalization control signal IOEQB. status. On the other hand, the remaining complex digital partial input/output equalization signal generating circuit which is not selected by the row address maintains the equalization signal EQ at the active level and maintains the local input/output line equalization signal LEQ2B as Inactive level. The equalization signals EQ1~EQk and the local input/output line equalization signals LEQ2B1~LEQ2Bk are output to the sense amplifier 50 places.

The column decoder & timing signal generating circuit 30, when supplied with the internal read command signal IRD, receives the address signal ADD as a column address in response to the internal read command signal IRD. Further, the column decoder & timing signal generating circuit 30 outputs control signals of various columns in response to the internal read command signal IRD and the column address. Specifically, the Y-switch selection signal YS is outputted to the sense amplifier 50, and the read enable signal RE and the main amplifier connection signal TGB are output to the amplification & buffer unit 60.

Further, the column decoder & timing signal generating circuit 30 selects the main amplifier equalization signal MAEQB and the input/output equalization control signal IOEQB in response to the internal read command signal IRD, respectively, in the second period and the third period, respectively. The LOW level of the bit is set to the HIGH level of the inactive level. On the other hand, the burst signal BSTFLGT and the write enable signal WE are maintained at an inactive level. The main amplifier equalization signal MAEQB and the write enable signal WE are output to the amplification & buffering unit 60, and the input/output equalization control signal IOEQB and the burst signal signal BSTFLGT are output to the row decoder & timing signal generating circuit. 20 and the enlargement & buffer portion 60.

The column decoder & timing signal generating circuit 30, when supplied with the internal write command signal IWRT and the timing signal TCCDT, receives the address signal ADD as a column address in response to the internal write command signal IWRT. .

Column decoder & timing signal generation circuit 30, in response to The internal write command signal IWRT, the timing signal TCCDT, and the column address are output, and the control signals of various columns are output. Specifically, the Y switch selection signal YS and the write enable signal WE are output in response to the internal write command signal IWRT and the column address.

In addition, the burst signal flag BSTFLGT is output in response to the timing signal TCCDT. Specifically, the burst signal signal BSTFLGT is generated by delaying the timing signal TCCDT for the fourth period.

Further, the column decoder & timing signal generating circuit 30 sets the input/output equalization control signal IOEQB in response to the internal write command signal IWRT, and in the fifth period, is inactive from the LOW level of the active level. The HIGH position of the position. On the other hand, the read enable signal RE and the main amplifier connection signal TGB are maintained at an inactive level, and the main amplifier equalization signal MAEQB is maintained at an active level.

At the memory cell array 40, a plurality of word lines WL and a plurality of bit lines BL are included, and a plurality of memory cells MC disposed at intersections of the respective word lines WL and bit lines BL.

In the sense amplifier 50, a plurality of sense amplification sections are included. The details of the sense amplifier 50 will be described later.

The amplification & buffer unit 60 includes a plurality of main input/output line equalization circuits MIOEQ (main input/output line equalization circuit, which corresponds to the above-described first equalization circuit), and a plurality of main amplifiers MA, and a plurality of writes. The buffer circuit WB and the main input/output equalization signal generating circuit MIOEQSC.

When the data input/output unit 70 is supplied with a write command from the outside, that is, when the write operation is performed, the write data supplied to the data terminal DQ is read and written via the read/write bus RWBUS. It is supplied to the amplification & buffer section 60. When a read command is supplied from the outside, that is, when the read operation is performed, the read data supplied from the enlargement & buffer unit 60 via the read/write bus bar RWBUS is supplied to the data terminal. DQ.

Next, a description will be given of a plurality of sense amplification sections included in the sense amplifier 50.

Figure 2 is a circuit diagram of the sense amplifier. In Fig. 2, a sense amplifying portion formed by a basic circuit of the same configuration of four groups is shown. In other words, the sense amplifying portion is composed of the transistor pairs SA1 and SA2, the equalization circuit BLEQ, and the Y switch circuit YS, and four groups are symmetrically arranged with the center of FIG. 2 as the center. Further, the sense amplifier unit is provided with an NMOS transistor MN6 that drives a drive line CSN that is commonly connected to the four transistor pairs SA1, and the drive is commonly connected to the two transistor pairs SA2. The PMOS transistor MP3 of the drive line CSP. Further, at the drive lines CSN and CSP, the sense amplifier activation signals CSN and CSP to which the same component symbols are added, which are described in FIG. 1, are respectively provided.

In addition, the bit line BL of FIG. 1 is shown as the bit line pair BLkT and BLkB (k=0 to 3) of FIG. Further, the input/output line MIO of Fig. 1 is hierarchically shown as a partial input/output line pair LIOkT, LIOkB (k = 0 to 3) of Fig. 2 . Balance of Figure 1 One of the signals EQ1 to EQk is assigned to the drive line ABLEQT of FIG. The Y switch selection signal YS of FIG. 1 is equivalent to the Y switch selection signal AYST of FIG.

Hereinafter, the component symbol will be added to only one of the above four groups and will be described. Regarding the other groups, since the circuit configuration is the same, only the component symbols of the bit line pair, the local input/output line pair, and the like which are the connection targets are different, and therefore the description thereof will be omitted. In addition, in the following description, the transistor pairs SA1 and SA2 are collectively referred to simply as a sense amplifier or a sense amplifier circuit. That is, the so-called sense amplifier or sense amplifier circuit here is included in the sense amplifier 50 described above and includes a plurality of them.

The transistor pair SA1 is provided with NMOS transistors MN1, MN2 having a drain and a gate connected to each other. The transistor pair SA2 is provided with PMOS transistors MP1 and MP2 for mutually connecting the drain and the gate. The drain of the NMOS transistor MN1 and the drain of the PMOS transistor MP1 are commonly connected to the bit line BL3B. The drain of the NMOS transistor MN2 and the drain of the PMOS transistor MP2 are commonly connected to the bit line BL3T. The bit line BL3T is a bit line pair with the bit line BL3B. The sources of the NMOS transistors MN1, MN2 are commonly connected to the drive line CSN. The sources of the PMOS transistors MP1, MP2 are commonly connected to the drive line CSP.

In the thus constructed sense amplifier (transistor pair SA1, SA2), a CMOS reverse circuit is formed by the NMOS transistor MN1 and the PMOS transistor MP1, and the NMOS transistor MN2 is used. And a PMOS transistor MP2 constitutes a CMOS inverter circuit. The sense amplifier functions as an amplifier composed of the above two CMOS inverter circuits that connect input and output to each other.

The equalization circuit BLEQ is provided with NMOS transistors MN3 to MN5. The NMOS transistor MN3 is connected between the bit line pairs (BL3T, BL3B). The NMOS transistor MN4 is connected between the bit line pair BL3B and the power source VBLP. The NMOS transistor MN5 is connected between the bit line pair BL3T and the power source VBLP. The gates of the NMOS transistors MN3 to MN5 are commonly connected to the drive line ABLEQT.

When the drive line ABLEQT is at the H level, all of the NMOS transistors MN3 to MN5 are turned ON, and the bit lines BL3T and BL3B are precharged to the potential of the power source VBLP.

The NMOS transistor MN6 connects the drain to the driving line CSN, and connects the source to the power source VSS, and receives a driving signal ASANT for activating the sense amplifier at the gate.

The PMOS transistor MP3 connects the drain electrode to the driving line CSP, and connects the source to the power source VARY, and receives a driving signal ASAPB for activating the sensing amplifier at the gate.

When the drive signal ASANT is at the H level and the drive signal ASAPB is at the L level, the NMOS transistor MN6 and the PMOS transistor MP3 are turned ON, and the sense amplifier is activated.

The Y switch circuit YS is provided with NMOS transistors MN7 and MN8. NMOS transistor MN7, is connected to the bit line Between BL2T and local input and output line LIO2T. The NMOS transistor MN8 is connected between the bit line BL3T and the local input/output line LIO3T. At the gates of the NMOS transistors MN7 and MN8, the Y switch selection signal AYST is commonly applied.

When the Y switch selects the signal AYST to the H level, the bit line BL2T and the local input and output line LIO2T and the bit line BL3T and the local input and output line LIO3T are respectively short-circuited, bit line pair and local. The input and output line pairs are set to the connected state.

In the above-described general configuration of the amplifying and amplifying portion, one group surrounded by the circle A is four groups of NMOS transistors MN1 to MN5, and an NMOS transistor which is commonly connected to the four groups. MN6 is configured to have the same threshold value Vt1. Here, the threshold value of the NMOS transistors MN7 and MN8 constituting the Y switch circuit YS is Vt2. Further, the threshold value of the NMOS transistor at the peripheral circuits such as the line control circuit, the column control circuit, the control logic circuit, the data input/output circuit, and the buffer (not shown) is Vt3. In this case, each transistor is configured to satisfy Vt1 < Vt2 < Vt3.

Here, the four groups of the NMOS transistors MN1 to MN5 surrounded by the circle A and the NMOS transistor MN6 connected in common with the four groups have the same threshold value Vt1. It can be formed in one P well region without providing an element separation region.

Next, speaking on the layout on the wafer of the sense amplifier Bright. Figure 3 is a diagram showing a schematic representation of the layout of the sense amplifier. In Fig. 3, the groups of the basic configurations having the same configuration of the four groups are arranged symmetrically with the center of Fig. 3 as the center, as explained in Fig. 2 . More specifically, the NMOS transistors MN1 to MN5 connected to the bit lines BL3T and BL3B shown in FIG. 2 are constituted by transistors arranged at the right side of FIG. Further, an NMOS transistor which is provided at a position symmetrical to the NMOS transistors MN1 to MN5 connected to the bit lines BL1T and BL1B shown in FIG. 2 is provided on the left side of FIG. The transistor at the column is formed. Further, the NMOS transistor MN6 is connected in parallel to two transistors in order to improve the driving ability.

The four groups of the NMOS transistors MN1 to MN5 and the NMOS transistor MN6 connected in common with the four groups are as described above, and are not provided with the element isolation region in one P well region P-Well. The ground is formed. Further, the PMOS transistors MP1 to MP3 are disposed in the N-well region N-Well disposed above the P-well region. Further, the NMOS transistors MN7 and MN8 are provided in other P well regions (not shown).

According to the above-described general configuration of the sense amplifier, four groups of the NMOS transistors MN1 to MN5 and the NMOS transistor MN6 connected in common with the four groups are in one P-well region. It is formed without providing a component separation region. Therefore, the area of the wafer to be connected to the sense amplifying portion can be reduced by omitting the element isolation region.

[Embodiment 2]

Fig. 4 is a block diagram showing the configuration of a drive circuit of the sense amplifying portion of the second embodiment. In FIG. 4, the semiconductor memory device is provided with decoding circuits DEC1, DEC2, level traverse circuits LS1, LS2, and buffer circuit BUF1 in addition to the NMOS transistors MN1 to MN6 described in the first embodiment. , BUF2. Further, the decoding circuits DEC1, DEC2, the level traverse circuits LS1, LS2, and the buffer circuits BUF1, BUF2 may be configured to be embedded in the row decoder & timing signal generating circuit 20 of FIG.

The decoding circuit DEC1 decodes the address signal ADD and the control signal CNTL and outputs it to the level traverse circuit LS1. The level traverse circuit LS1 converts the L level in the output signal of the decoding circuit DEC1 from the potential of the power source VSS to a potential Vneg lower than the potential of the power source VSS, and outputs it to the buffer circuit BUF1. The output of the buffer circuit BUF1 is connected to the gate of the NMOS transistor MN6 as a drive line ASANT to which the same component symbol as that of the drive signal ASNT illustrated in FIG. 2 is added.

The decoding circuit DEC2 decodes the address signal ADD and the control signal CNTL and outputs it to the level traverse circuit LS2. The level traverse circuit LS2 converts the L level in the output signal of the decoding circuit DEC2 from the potential of the power source VSS to a potential Vneg lower than the potential of the power source VSS, and outputs it to the buffer circuit BUF2. The output of the buffer circuit BUF2 is used as the driving line ABLEQT and the NMOS transistor MN3 The gate of ~MN5 is connected.

In the above-described general configuration, it is considered that the potential of the drive line ASANT is VSS, the NMOS transistor MN6 is OFF, and the NMOS transistors MN3 to MN5 are turned ON. In this case, since the threshold value Vt1 of the NMOS transistor MN6 is small, as shown in FIG. 5(A), the NMOS transistor MN6 in the OFF state flows from the driving line CSN toward the power source VSS. Off leak current Io1.

Further, it is considered that the potential of the drive line ABLEQT is VSS, the NMOS transistors MN3 to MN5 are turned off, and the NMOS transistor MN6 is turned ON. Further, it is assumed that the potential (VARY) of the bit line BLT is higher than the potential (VSS) of the bit line BLB. In this case, since the threshold value Vt1 of the NMOS transistors MN3 to MN5 is small, as shown in FIG. 5(B), the NMOS transistor MN3 in the OFF state is oriented from the bit line BLT. The bit line BLB flows offoff leak current Io2. Further, the off leak current Io3 flows from the bit line BLT toward the VBLP via the NMOS transistor MN5 in the OFF state. Further, the off leak current Io4 flows from the VBLP toward the bit line BLB via the NMOS transistor MN4 in the OFF state.

On the other hand, in the circuit shown in FIG. 4, the driving line ASANT and the driving line ABLEQT are driven at a potential Vneg lower than the potential of the power source VSS when the L level is used, and the NMOS transistors MN3 to MN6 are driven. They are each biased to depth. Therefore, the above off The leak current Io1~Io4 is extremely small, and the current consumption of the chip is reduced.

The disclosures of the above-mentioned patent documents and the like are incorporated herein by reference. Modifications and adjustments of the embodiments and the embodiments may be made within the scope of the disclosure of the invention (including the scope of the claims) and the basic technical idea of the invention. Further, within the scope of the entire disclosure of the present invention, a combination of various elements (including each element of each request item, each element of each embodiment, each element of each drawing, etc.) can be performed. Even choose. In other words, the present invention includes various modifications and corrections that can be made by the practitioner in accordance with the entire disclosure and technical idea contained in the scope of the patent application. In particular, the numerical ranges recited in the specification are to be construed as being Sexual record.

1‧‧‧Semiconductor memory device

10‧‧‧Control logic

20‧‧‧ row decoder & timing signal generation circuit

30‧‧‧ Column Decoder & Timing Signal Generation Circuit

40‧‧‧ memory cell array

50‧‧‧Sense Amplifier

60‧‧‧Amplification & Buffer Department

70‧‧‧Data input and output department

ADD‧‧‧ address signal

CK‧‧‧ clock signal

IACT‧‧‧ internal start command signal

TCCDT‧‧‧ timing signal

IWRT‧‧‧Internal write command signal

IRD‧‧‧ internal read command signal

BSTFLGT‧‧‧Congfa flag signal

IOEQB‧‧‧Input and output equalization control signals

WLS‧‧‧ character line selection signal

S1‧‧‧ switch control signal

EQ1~Eqk‧‧‧Equilibrium signal

CSP‧‧‧Sense Amplifier Activation Signal

CSN‧‧‧Sense Amplifier Activation Signal

WE‧‧‧Write enable signal

RE‧‧‧Read enable signal

TGB‧‧‧ main amplifier connection signal

MAEQB‧‧‧Main Amplifier Equalization Signal

WL‧‧‧ character line

BL‧‧‧ bit line

MC‧‧‧ memory cell

MIO‧‧‧Input and output lines

RWBUS‧‧‧reading bus

DQ0~n‧‧‧ data terminal

YS‧‧‧Y switch selection signal

Claims (8)

A semiconductor memory device characterized by comprising: a bit line pair; and a sensing amplifying circuit comprising two CMOS inverting circuits connected between the bit line pairs and connecting the input and output to each other And an equalization circuit connected between the pair of bit lines; and a driving transistor that drives one of the driving lines of the sensing amplifier circuit to form a transistor of one of the CMOS inverting circuits And the transistor group constituting the equalization circuit and the driving transistor are first conductivity type and have the same first threshold value. The semiconductor memory device according to the first aspect of the invention, wherein the transistor constituting one of the CMOS inverter circuits and the transistor group constituting the equalization circuit and the driving transistor are disposed in one In the well area of the second conductivity type. The semiconductor memory device according to the second aspect of the invention, wherein the one of the second conductivity type well regions has one of the equalization circuits and one of the sensing electrodes in one direction. a sequence of one of the two of the amplifier circuits, the drive transistor, and one of the other of the other sense amplifier circuits, and the other equalization circuit These are included in such a manner that no element separation region is provided between them. Such as the semiconductor memory device described in item 3 of the patent application scope The first direction is the direction in which the bit line pairs are arranged. The semiconductor memory device according to the first aspect of the invention, wherein the first threshold value is Vt1, and the input/output line pair is connected to the transistor for controlling the pair of bit lines. When the value is Vt2 and the threshold value of the transistor constituting the lanthan control circuit is Vt3, it is configured to satisfy Vt1 < Vt2 < Vt3. The semiconductor memory device according to claim 3, wherein the driving transistor is driven by a common driving line in the one of the sensing amplifier circuit and the other sensing amplifying circuit. The semiconductor memory device according to any one of claims 1, 2, 3, and 6, wherein the semiconductor memory device is provided with a potential lower than a potential of a source of the driving transistor. The first level traverse circuit of the first driving signal, wherein the gate of the driving transistor is driven by the first driving signal. The semiconductor memory device according to any one of claims 1, 2, 3, and 6, wherein the semiconductor memory device is provided with a potential lower than a potential of a source of the driving transistor. The second level traverse circuit of the second driving signal, the respective gates of the transistor group constituting the equalizing circuit are driven by the second driving signal.