TW201506601A - Smart automatic booting device - Google Patents

Abstract

This invention concerns a smart automatic booting device, which comprises a microcontroller; a south bridge chip connected to the microcontroller via a first signal circuit in order to transmit a software power control signal to the microcontroller; a power supply connected to the microcontroller via a second signal circuit in order to transmit a hardware power control signal to the microcontroller; and a Super I/O chip. When the second signal circuit bucks first and then the first signal circuit bucks, the microcontroller transmits a PWRBTN signal to the Super I/O chip when the power is restored. Then the Super I/O chip transmits a PS_ON# signal to the power supply, so that the power supply executes automatic booting procedure. As such, the system can thereby identify normal and abnormal power failure intelligently to enable constant automatic system reboot regardless the duration of power failure, such as accidental power failure.

Description

Intelligent automatic boot device

The invention relates to an intelligent automatic starting device of an ATX specification computer, in particular to a state in which the system can intelligently recognize the state of normal power failure and abnormal power failure, and the length of time of abnormal power failure (unexpected power failure) A smart automatic boot device that enables the system to automatically power on.

Press, the existing computer (such as ATX specification, Advanced Technology eXpanding) need to press the power switch to start the boot process. When a power failure occurs, the computer startup program still needs to press the manual switch (Power/hardware switch). In order to start the computer, if the computer is used for display or real-time monitoring, it will cause delay in display or monitoring, or when there are multiple computers in the computer room, the computer program needs to be manually operated one by one. The power switch of the computer is turned on, it cannot be turned on automatically, and it lacks convenience.

In response to this problem, the conventional technology has to determine whether the voltage of the computer is 0 to solve the automatic power-on after the power-off. If the voltage of the computer drops to 0, it means that the power is turned off, so that the computer automatically turns on when the power is restored; Please refer to FIG. 1A, which is a schematic diagram showing the theoretical change of voltage with time after the computer is powered off. As shown in the figure, when the computer maintains its normal operation of the output voltage V, and the voltage to the power-off point A, the voltage is Instantly reduce to V ₀ (that is, the voltage is reset to zero). If the voltage is set to zero (V ₀ ), the automatic power-on sequence will be started during the power-on, so that the power supply is turned on, but the power supply has a capacitor discharge phenomenon. Therefore, it does not actually have the ideal state of the voltage drop; and the voltage drop state after the actual power-off is as shown in FIG. 1B, when the computer maintains its normal operation of the output voltage V, and when it reaches the power-off point A, The voltage will gradually drop to V ₀ (ie, the voltage is reset to zero). If the voltage gradually returns to zero (V ₀ ), the time is t ₀ . Therefore, the above method is improved to set the elapsed time t ₀ and the voltage drop to zero. when (V _0), it initiates the startup procedure after power failure when automatic restoration, After the restoration of this solution off the computer automatically boot problems.

The foregoing prior art can adjust the discharge time of the power supply to solve the automatic power-on of the power-on after the power-off. However, there is still a defect, as shown in FIG. 1B, when the computer is powered off at the power-off point A, And re-energize at point A1, because its voltage has not completely returned to zero (V ₀ ), and its power-off time t ₁ <t ₀ , that is, the power-off time is too short (time difference δ _t ), at this time still can be detected Voltage, the system will be mistakenly judged as not being powered off, so in the case of a short time out of power and re-power, it will lead to misjudgment, can not make the power supply start the boot process, showing a non-ideal design. Of course, this can be improved by the power supply manufacturer, even if the power supply discharge time is shortened to solve the problem, but because the power supply has a lot of brand specifications, if all the power supply specifications of the brand are required to be improved, It is not easy to do, and it is not a better and more effective solution. Therefore, how to solve the problem of the lack of automatic power-on technology after the power-off of the conventional power-off is a key direction for the industry to develop and break through.

Therefore, the present inventors have in view of the fact that the use of the automatic power-on technology after the power-off of the computer is turned off, and the fact that the structural design is not ideal, the creator of the case started to develop and conceive its solution, hoping to develop A smart automatic boot device that is more convenient, simple, and correct in judgment, serves the public and promotes the development of the industry, and has the concept of the present invention.

The object of the present invention is to provide a smart automatic starting device which can intelligently recognize the state of normal power failure and abnormal power failure, and can make the system irrespective of the abnormal power failure (unexpected power failure). Automatically turn on, and achieve the excellent, correct and safe switching machine stability function, and actively improve the quality and efficiency of the product.

The technology used in the present invention to achieve the above object includes: a microcontroller; a south bridge chip connected to the microcontroller by a first signal line for transmitting a software power control signal to the microcontroller; a power supply connected to the microcontroller by a second signal line for transmitting a hardware power control signal to the microcontroller; a Super I/O chip coupled to the microcontroller The power supply is electrically connected; when the power is off, the microcontroller according to the received software power control signal and the hardware power control signal, if the hardware power control signal is stepped down earlier than the software power control signal, The microcontroller determines that it is not normal At this time, when the microcontroller is powered back, a PWRBTN signal will be transmitted to the Super I/O chip, and then the Super I/O chip will transmit a PS_ON# signal to the power supply to make the power supply. The device performs an automatic booting process; if the software power control signal is stepped earlier than the hardware power control signal, the microcontroller determines that the power is turned off normally, and the microcontroller will not transmit the PWRBTN signal to the Super I/O chip.

The microcontroller connects the Super I/O chip with a signal line for transmitting a PWRBTN signal to the Super I/O chip.

The Super I/O chip is connected to the power supply by a third signal line for transmitting a PS_ON# signal to the power supply.

The microcontroller and the Super I/O chip system are integrated into a second microcontroller, and the second microcontroller includes the microcontroller and the Super I/O chip.

The microcontroller in the second microcontroller is electrically connected to the Super I/O chip by a connecting circuit, so that the microcontroller can transmit a PWRBTN signal to the Super I/O chip by using the connecting circuit.

The software power control signal is an S3 signal, an S4 signal or an S5 signal.

The hardware power control signal is a PWROK signal.

The microcontroller is an 8-bit microcontroller such as the PIC12F675 microcontroller manufactured by Microchip Technology.

In order to give the reviewer a better understanding and understanding of the technical features of the present invention and the efficacies achieved, the following is a description of the preferred embodiment and a detailed description.

10‧‧‧Microcontroller

20‧‧‧Southbridge

30‧‧‧Power supply

21‧‧‧First signal line

31‧‧‧Second signal line

11‧‧‧ signal line

40‧‧‧Super I/O Chip

12‧‧‧ third signal line

Figure 1A: Schematic diagram of the voltage change with time after the computer is powered off.

Figure 1B: The actual schematic diagram of the voltage change with time after the computer is powered off.

Figure 2 is a schematic diagram of the architecture of the present invention.

Figure 3A: The hardware power control signal for the normal shutdown of the present invention ( The voltage of the PWROK signal is an example, and the graph changes with time.

Figure 3B is a diagram showing the voltage of the software power control signal (taking the S3 signal as an example) of the normal shutdown of the present invention as a function of time.

Figure 4A is a diagram showing the voltage of the hardware power control signal (using the PWROK signal as an example) of the abnormal shutdown of the present invention as a function of time.

Fig. 4B is a diagram showing the voltage of the software power supply control signal (using the S3 signal as an example) of the abnormal shutdown of the present invention as a function of time.

Referring to FIG. 2, the smart automatic boot device of the present invention includes a microcontroller 10 (such as a Microcontroller/MCU), a Southbridge 20 (Southbridge), a power supply 30 (Power Supply), and a Super I/O chip 40. The output of the microcontroller 10 is electrically connected to the power supply device 30. The electrical connection is configured such that the south bridge chip 20 is connected to the microcontroller 10 by a first signal line 21. The first signal line 21 is a software power control signal line for transmitting a software power control signal, and the transmission software power control signal includes a signal such as S3, S4 or S5; the power supply 30 is a second The signal line 31 is connected to the microcontroller 10. The second signal line 31 is a hardware power control signal line for transmitting a hardware power control signal. The hardware signal includes a PWROK signal, and the PWROK signal is a voltage. The normal digital signal is output. When the output voltage of the power supply 30 is stable, PWROK will send a positive 5 volt signal; the microcontroller 10 is connected to the Super I/O chip 40 by a signal line 11 for pass A PWRBTN (power-on button) is sent to the Super I/O chip 40. The Super I/O chip 40 is connected to the power supply 30 by a third signal line 12 for transmitting a PS_ON#. A signal (Power Supply ON signal) is sent to the power supply 30 to cause the power supply 30 to activate the switch.

The microcontroller 10 is an 8-bit microcontroller manufactured by Microchip Technology: PIC12F675; the Southbridge 20 Series includes peripherals, multimedia and communication interface functions such as PCI (Peripheral Components Interconnect) controllers. ATA controller for hard disk or CD player, USB interface controller, network controller interface, sound control The south bridge chip 20 can transmit the software power control signal (eg, S3, S4, or S5) signals to the microcontroller 10 through the first signal line 21, wherein, according to the advanced power management specification (ACPI, Advanced Configuration and Power Interface), the S3 signal is a standby (Suspend to RAM, abbreviated as STR) state signal, and the S3 state is to store the working state data before the system enters the STR into the memory. In the S3 state, the power supply continues to supply power to the most necessary devices such as memory to ensure that the data is not lost, while other devices are turned off; the S4 signal is a sleep (Suspend to Disk, abbreviated as STD) The status signal, when the system main power is off, but the hard disk is still powered and can be woken up; the S5 signal is a device all off signal, at which time its power consumption is zero. The power supply 30 can transmit the PWROK signal to the microcontroller 10 via the second signal line 31. The microcontroller 10 is connected to the Super I/O chip 40 by a signal line 11 for transmitting a PWRBTN signal to the Super I/O chip 40. The Super I/O chip 40 is connected to a third signal line 12. The power supply 30 is connected to transmit a PS_ON# signal to the power supply 30, so that the power supply 30 generates a booting operation.

The following describes the situation when the power is turned off normally. Please refer to the 3A and 3B diagrams together. The 3A is the voltage of the normal power-off control signal (using the PWROK signal as an example) of the normal shutdown of the present invention. The figure shows the voltage of the software power control signal (taking the S3 signal as an example) of the normal shutdown of the invention, and changes with time. When the system is normally shut down, the software starts the shutdown process. Please refer to the 3B figure and pass the computer software switch. Shutdown, the computer's software power control signal (such as S3, S4 or S5 signal, this picture takes S3 signal as an example) the voltage will drop to 0, as shown in Figure 3B, because the software shuts down at 0.2 seconds to make the S3 The voltage drop of the signal is 0, and the south bridge chip 20 outputs the software power control signal (for example, S3, S4 or S5 signals, for example, the S3 signal) to the microcontroller 10 via the first signal line 21. After that, the power supply 30 will be powered off to complete the shutdown process. When the power supply 30 is powered off, the voltage of the hardware power control signal (taking the PWROK signal as an example) will instantaneously drop to 0 (as shown in FIG. 3A). At the 0.3 second shown, the power of the PWROK signal The voltage drop is 0), and the power supply 30 will output a hardware power control signal (taking the PWROK signal as an example) to the microcontroller 10 via the second signal line 31; It can be seen that, in the case of normal shutdown, the voltage of the software power control signal is stepped down first, and then the voltage of the software power control signal is stepped down again. According to the present invention, the microcontroller 10 is controlled according to the received software power supply. The signal and the hardware power control signal, if the software power control signal is stepped earlier than the hardware power control signal, the microcontroller 10 determines that the power is off (non-unexpected power-off state), at this time the microcontroller 10 will not transmit the PWRBTN signal to the Super I/O chip 40, that is, keep the computer system turned off.

The following describes the situation when the power is turned off abnormally. Please refer to FIG. 4A and FIG. 4B together. FIG. 4A is a diagram showing the voltage of the hardware power control signal (taking the PWROK signal as an example) of the abnormal shutdown of the present invention as a function of time. FIG. 4B is a schematic diagram showing the voltage of the software power control signal (taking the S3 signal as an example) of the abnormal shutdown of the present invention as a function of time. When the power is turned off abnormally, for example, a sudden high voltage caused by a lightning strike causes a power failure, or a typhoon earthquake destroys the power supply line to cause a power failure, the power supply 30 is powered off, and when the power supply 30 is powered off, the hardware power supply is turned off. The voltage of the control signal (taking the PWROK signal as an example) is instantaneously reduced to 0 (as the 0.2 second shown in Figure 4A, the voltage drop of the PWROK signal is 0), and at the same time the power supply 30 will be The two signal lines 31 output a hardware power control signal (taking the PWROK signal as an example) to the microcontroller 10, and the software power control signal of the computer (for example, S3, S4 or S5 signals, this figure takes the S3 signal as an example) The voltage is reduced to 0. As shown in FIG. 4B, the voltage drop of the S3 signal is 0 at 0.3 seconds, and the south bridge chip 20 outputs the software power control signal (for example, S3, by the first signal line 21). S4 or S5 signal, this figure takes the S3 signal as an example) to the microcontroller 10; thus, it can be seen that in the case of abnormal shutdown, the voltage of the hardware power control signal will be stepped down first, then the hardware power control The voltage of the signal is stepped down again, and according to the present invention, the microcontroller 10 is based on Receiving the software power control signal and the hardware power control signal, if the hardware power control signal is stepped earlier than the software power control signal, the microcontroller 10 determines that the power is off (unexpected power off state), At this time, when the microcontroller 10 is powered back, a PWRBTN signal is transmitted to the Super I/O chip 40, and then the Super I/O chip 40 transmits a PS_ON# signal to the power supply 30 to enable the power supply. The supplier 30 executes an automatic boot process.

The aforementioned hardware power control signal (taking the PWROK signal as an example), the system is a number Bit signal, when the capacitance drop value is about 5% of the original capacitance, the voltage of the signal is directly reduced to 0. Therefore, it is very accurate to judge whether the computer is turned off by the voltage of the hardware power control signal. The conventional technology uses the voltage of the computer to determine whether the computer is turned off, and may be affected by the voltage of the residual value of the capacitor, and the discriminating is not accurate.

The microcontroller 10 and the Super I/O chip 40 can be integrated into a second microcontroller, and the second microcontroller includes the microcontroller 10 and the Super I/O wafer 40. The microcontroller 10 in the second microcontroller is electrically coupled to the Super I/O chip 40 by a communication circuit, so that the microcontroller 10 can transmit a PWRBTN signal to the Super I/O chip through the communication circuit. .

When the intelligent automatic booting device of the present invention operates, it detects the voltage of the hardware power control signal and the software power control signal, and transmits the voltage to the microcontroller 10 for judgment to determine the power failure of the computer system. The system is normally shut down (non-unexpected power-off state) or determined to be abnormally shut down (ie, it is an unexpected power-off), and then the microcontroller 10 is used to signal the power supply 30 to complete the automatic power-on operation.

According to the foregoing configuration, the intelligent automatic booting device can intelligently recognize the state of normal power failure and abnormal power off, and enable the system to be turned on when the power is turned on during the power-on, and shut down when the power is turned off, and The short time of normal power failure (unexpected power failure) can make the system automatically turn on when the power is restored, so as to achieve the stability and stability of the switch with excellent, correct and safe performance, and actively improve the quality of use of the product. And efficiency.

In summary, the present invention is indeed a rather excellent invention, and a patent application is filed according to law; however, the above description is only a preferred embodiment of the present invention, and is extended by the technical means of the present invention. Changes are intended to fall within the scope of the patent application of the present invention.

10‧‧‧Microcontroller

20‧‧‧Southbridge

30‧‧‧Power supply

21‧‧‧First signal line

31‧‧‧Second signal line

11‧‧‧ signal line

40‧‧‧Super I/O Chip

12‧‧‧ third signal line

Claims (10)

A smart automatic booting device includes: a microcontroller; a south bridge chip connected to the microcontroller by a first signal line for transmitting a software power control signal to the microcontroller; a supplier connected to the microcontroller by a second signal line for transmitting a hardware power control signal to the microcontroller; a Super I/O chip coupled to the microcontroller and the power supply Electrically connected; the microcontroller according to the received software power control signal and the hardware power control signal when the power is off, if the hardware power control signal is stepped earlier than the software power control signal, then the micro The controller determines that the shutdown is abnormal. At this time, the microcontroller will transmit a PWRBTN signal to the Super I/O chip upon power-on, and then the Super I/O chip transmits a PS_ON# signal to the power supply. The power supply is configured to perform an automatic power-on procedure; if the software power control signal is stepped earlier than the hardware power control signal, the microcontroller determines that the power is off, and the microcontroller will not pass PWRBTN signal to the Super I / O chip. The smart automatic boot device of claim 1, wherein the microcontroller connects the Super I/O chip with a signal line for transmitting a PWRBTN signal to the Super I/O chip. The smart automatic booting device of claim 1, wherein the Super I/O chip is connected to the power supply by a third signal line for transmitting a PS_ON# signal to the power supply. The smart automatic boot device of claim 1, wherein the microcontroller and the Super I/O chip system are integrated into a second microcontroller, the second microcontroller including the microcontroller and The Super I/O chip. The smart automatic booting device according to claim 4, wherein the microcontroller in the second microcontroller is electrically connected to the Super I/O chip by a connecting circuit, so that the microcontroller can borrow The connected circuit transmits a PWRBTN signal to the Super I/O chip. The smart automatic power-on device according to claim 1, wherein the software power control signal is an S3 signal. The smart automatic power-on device according to claim 1, wherein the software power control signal is an S4 signal. The smart automatic power-on device according to claim 1, wherein the software power control signal is an S5 signal. The smart automatic power-on device according to claim 1, wherein the hardware power control signal is a PWROK signal. The smart automatic boot device of claim 1, wherein the microcontroller is an 8-bit microcontroller.