TW201504067A - Transparent conductive multilayer film and method for producing same - Google Patents

Transparent conductive multilayer film and method for producing same Download PDF

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TW201504067A
TW201504067A TW103111652A TW103111652A TW201504067A TW 201504067 A TW201504067 A TW 201504067A TW 103111652 A TW103111652 A TW 103111652A TW 103111652 A TW103111652 A TW 103111652A TW 201504067 A TW201504067 A TW 201504067A
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transparent conductive
film
conductive film
transparent
tin oxide
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TW103111652A
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TWI617460B (en
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Shinya OMOTO
Takashi Kuchiyama
Takahisa Fujimoto
Kenji Yamamoto
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Kaneka Corp
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • C23C14/5806Thermal treatment
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08Oxides
    • C23C14/086Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth

Abstract

This transparent conductive multilayer film (100) sequentially comprises, on at least one surface of a film base (10), a transparent dielectric layer (21) and a transparent conductive film (24) that is provided in contact with the transparent dielectric layer (21), in this order. The transparent dielectric layer (21), which is in contact with the transparent conductive film (24), is a silicon oxide layer. The transparent conductive film (24) is a multilayer film that sequentially has, from the transparent film base (10) side, a first transparent conductive film (22) that is composed of an indium tin oxide layer that has a tin oxide content of 1% by weight of more but less than 6% by weight and a second transparent conductive film (23) that is composed of an indium tin oxide layer that has a tin oxide content of 6-20% by weight (inclusive). The film thickness (d1) of the first transparent conductive film (22) and the film thickness (d2) of the second transparent conductive film (23) satisfy the following relations (1)-(3): (1) d1 = 1-9 nm; (2) d1 + d2 = 15-37 nm; and (3) 2d1 < d2.

Description

透明導電層積膜及其製造方法 Transparent conductive laminated film and method of manufacturing same

本發明關於透明導電層積膜及其製造方法,該透明導電層積膜係在透明膜基材上包括透明介電層及透明導電層者。 The present invention relates to a transparent conductive laminated film which comprises a transparent dielectric layer and a transparent conductive layer on a transparent film substrate, and a method for producing the same.

在透明膜上形成有氧化銦錫(ITO)等導電性氧化物薄膜的透明導電性膜,係作為顯示器或發光元件、光電轉換元件等透明電極廣泛被使用。此種透明導電性膜,例如係藉由濺鍍法等乾製程,於透明膜基材上形成導電性氧化物薄膜層而製造。構成透明電極的導電性氧化物薄膜,係被要求在高溫高濕度環境下之電阻係數之可靠性等。為符合此種要求特性,透明導電性膜大多於導電性氧化物結晶化狀態下使用。 A transparent conductive film in which a conductive oxide film such as indium tin oxide (ITO) is formed on a transparent film is widely used as a transparent electrode such as a display, a light-emitting element, or a photoelectric conversion element. Such a transparent conductive film is produced by, for example, a dry process such as a sputtering method to form a conductive oxide thin film layer on a transparent film substrate. The conductive oxide film constituting the transparent electrode is required to have reliability of a resistivity in a high-temperature and high-humidity environment. In order to meet such a required characteristic, a transparent conductive film is often used in a state in which a conductive oxide is crystallized.

為了透明導電性膜之品質提升目的,而提案於將設於膜基材上的透明導電膜予以積層之構成。例如於專利文獻1揭示,在膜基材上形成具小粒徑結晶粒的第一透明導電膜,及較第一透明導電膜具有更大粒徑結晶粒的第二透明導電膜,依此而在維持透明性狀態下可以改善筆壓耐久性或捲曲特性等之技術。 For the purpose of improving the quality of the transparent conductive film, it is proposed to laminate a transparent conductive film provided on a film substrate. For example, Patent Document 1 discloses that a first transparent conductive film having a small particle size crystal grain and a second transparent conductive film having a larger particle size crystal grain than the first transparent conductive film are formed on the film substrate, and thus A technique that can improve the durability of the writing pressure, the curling property, and the like while maintaining the transparency.

專利文獻2揭示在膜基材上設置:由氧化錫(SnO2)含量小的(SnO2:3~8重量%)氧化銦錫構成的第一透明導 電膜,及由SnO2含量大的(SnO2:10~30重量%)氧化銦錫構成的第二透明導電膜,據以改善透明性之同時,達成低電阻化之技術。 Patent Document 2 discloses that a first transparent conductive film made of indium tin oxide having a small content of tin oxide (SnO 2 ) (SnO 2 : 3 to 8 wt%) and a large content of SnO 2 are provided on a film substrate ( SnO 2 : 10 to 30% by weight) A second transparent conductive film made of indium tin oxide has a technique of improving the transparency and reducing the resistance.

專利文獻3揭示在膜基材上設置:由SnO2含量小的(SnO2:2~6重量%)氧化銦錫構成的第一透明導電膜,及由SnO2含量大的(SnO2:6~20重量%)氧化銦錫構成的第二透明導電膜,並將兩者之膜厚比設於特定範圍,據以滿足觸控面板用的透明導電性膜之高溫高濕可靠性,或者使低溫熱處理之結晶化成為可能。 Patent Document 3 discloses a substrate disposed on the film: made of SnO 2 content is small: a first transparent conductive film (SnO 2 2 ~ 6 wt%) composed of indium tin oxide, and a large content of SnO 2 (SnO 2:. 6 ~20% by weight of a second transparent conductive film made of indium tin oxide, and the film thickness ratio of the two is set to a specific range, in order to satisfy the high temperature and high humidity reliability of the transparent conductive film for a touch panel, or Crystallization of low temperature heat treatment is possible.

上述專利文獻1~3之透明導電性膜,主要使用於電阻膜方式之觸控面板。但是近年來,可以多點觸控(multi touch)輸入或手勢(gesture)輸入的靜電容量方式之觸控面板急速普及,被使用於手機、平板電腦、筆電等。靜電容量方式觸控面板要求透明電極層之低電阻化,以便提升感測器之感度或響應速度。 The transparent conductive film of the above Patent Documents 1 to 3 is mainly used for a resistive film type touch panel. However, in recent years, the touch panel of the electrostatic capacity type which can be multi-touch input or gesture input has been rapidly popularized, and is used in mobile phones, tablet computers, notebooks, and the like. The capacitive touch panel requires low resistance of the transparent electrode layer to improve the sensitivity or response speed of the sensor.

另外,於透明導電性膜之製造工程中要求在短時間內進行導電性氧化物之結晶化。結晶化之方法通常為,在膜基材上形成非晶質之導電性氧化物薄膜之後,進行加熱的方法。就膜基材之耐熱性觀點而言,使用樹脂膜基材的透明導電性膜係難以加熱至高溫(例如200℃以上)。因此,須於較低溫之加熱下進行結晶化,會有結晶化時間變長之傾向。 Further, in the manufacturing process of the transparent conductive film, it is required to crystallize the conductive oxide in a short time. The method of crystallization is usually a method of heating after forming an amorphous conductive oxide film on a film substrate. From the viewpoint of heat resistance of the film substrate, it is difficult to heat the transparent conductive film using the resin film substrate to a high temperature (for example, 200 ° C or higher). Therefore, crystallization is required to be performed under heating at a lower temperature, and the crystallization time tends to be longer.

專利文獻4揭示藉由積層透明導電膜之構成,而可以兼顧低電阻化與短時間之結晶化。具體言之為,在透明導電性膜之表面側(遠離膜基材之側)設置SnO2含量小的ITO 層,在基材側設置SnO2含量大的ITO層之構成。依據該構成揭示之推測原理,係藉由在膜基材之不易受產生氣體之影響的表面側設置SnO2含量小的ITO層,來促進結晶核之形成縮短結晶化時間之同時,增大SnO2含量大的基材側之ITO層之膜厚,依此可使載子增加,達成電阻化。 Patent Document 4 discloses that the composition of the laminated transparent conductive film can achieve both low resistance and crystallization for a short period of time. Specifically, an ITO layer having a small SnO 2 content is provided on the surface side of the transparent conductive film (on the side away from the film substrate), and an ITO layer having a large SnO 2 content is provided on the substrate side. According to the presumed principle disclosed in the configuration, the ITO layer having a small SnO 2 content is provided on the surface side of the film substrate which is less susceptible to the gas generation, thereby promoting the formation of the crystal nucleus and shortening the crystallization time while increasing the SnO. 2 large content of the thickness of the ITO layer side of the substrate, so the carrier can increase the resistance to reach.

【先行技術文獻】 [First technical literature] 【專利文獻】 [Patent Literature]

【專利文獻1】日本特開2003-263925號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2003-263925

【專利文獻2】日本特開平10-49306號公報 [Patent Document 2] Japanese Patent Laid-Open No. Hei 10-49306

【專利文獻3】日本特開2006-244771號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2006-244771

【專利文獻4】日本特開2012-114070號公報 [Patent Document 4] Japanese Patent Laid-Open Publication No. 2012-114070

上述專利文獻3之揭示,係藉由積層透明導電膜之構成,除可提升透明性及高溫高濕環境下之可靠性以外,可以有效縮短結晶化時間。但是,專利文獻3,主要關於電阻膜方式之觸控面板所使用的透明導電性膜,表面電阻為較高的300Ω/□左右,並非可以兼顧低電阻化與結晶化時間之短縮者。 According to the disclosure of Patent Document 3, the crystallization time can be effectively shortened by the structure of the laminated transparent conductive film, in addition to improving the transparency and the reliability in a high-temperature and high-humidity environment. However, Patent Document 3 mainly relates to a transparent conductive film used in a resistive film type touch panel, and has a surface resistance of about 300 Ω/□, which is not limited to a reduction in resistance and crystallization time.

專利文獻4之揭示,係藉由積層透明導電膜之構成,來兼顧低電阻化與結晶化時間之短縮。但是,伴隨著觸控面板所搭載裝置之大畫面化(大面積化),為求響應速度之提升,而需要透明導電膜之更進一步低電阻化。另外,伴隨大面積化,亦需要提升面內之電阻係數之均一性。 According to the disclosure of Patent Document 4, the composition of the laminated transparent conductive film is used to achieve both the reduction in resistance and the shortening of the crystallization time. However, with the increase in the screen size (large area) of the device mounted on the touch panel, in order to improve the response speed, it is necessary to further reduce the resistance of the transparent conductive film. In addition, with the increase in area, it is also necessary to increase the uniformity of the resistivity in the plane.

本發明有鑑於該課題,目的在於提供可以維持透 明導電膜之透明性,以及高溫高濕環境下之可靠性之同時,可以實現結晶化時間之短縮、更進一步低電阻化,以及面內電阻係數之均一性提升的透明導電性膜。 The present invention has in view of the subject, and aims to provide a maintenance The transparency of the conductive film and the reliability in a high-temperature and high-humidity environment can simultaneously reduce the crystallization time, further reduce the resistance, and improve the uniformity of the in-plane resistivity.

為解決上述課題,發明人經由經由銳意檢討之結果發現,在透明膜基材上,隔著氧化矽層設置氧化錫含有比例小的氧化銦錫層,及氧化錫含有比例大的氧化銦錫層,而且將彼等之膜厚設於特定範圍,可以使透明導電性膜於短時間達成結晶化,另外,結晶後之電阻係數亦低,面內電阻係數之均一性亦佳。 In order to solve the above-mentioned problems, the inventors have found that an indium tin oxide layer having a small tin oxide content and an indium tin oxide layer having a large tin oxide content are provided on the transparent film substrate via a ruthenium oxide layer. Further, by setting the film thicknesses of the films to a specific range, the transparent conductive film can be crystallized in a short time, and the resistivity after crystallization is also low, and the uniformity of the in-plane resistivity is also good.

本發明關於透明導電層積膜及其製造方法,該透明導電層積膜,係在透明膜基材之至少一面,依序包括至少1層透明介電層,及和上述透明介電層相接而設的透明導電膜。 The present invention relates to a transparent conductive laminated film which is formed on at least one side of a transparent film substrate, and includes at least one transparent dielectric layer in sequence, and is in contact with the transparent dielectric layer. A transparent conductive film is provided.

本發明之透明導電層積膜中,和透明導電膜相接的透明介電層為氧化矽層。氧化矽層之膜厚較好是2nm以上60nm以下。透明導電膜為層積膜,係由透明膜基材側起依序具有:由氧化錫之含有比例在1重量%以上小於6重量%之氧化銦錫層構成的第一透明導電膜;及由氧化錫含有比例在6重量%以上20重量%以下之氧化銦錫層構成的第二透明導電膜。 In the transparent conductive laminated film of the present invention, the transparent dielectric layer that is in contact with the transparent conductive film is a ruthenium oxide layer. The film thickness of the ruthenium oxide layer is preferably 2 nm or more and 60 nm or less. The transparent conductive film is a laminated film which has, in order from the side of the transparent film substrate, a first transparent conductive film composed of an indium tin oxide layer having a tin oxide content of 1% by weight or more and less than 6% by weight; The tin oxide contains a second transparent conductive film composed of an indium tin oxide layer in a proportion of 6 wt% or more and 20 wt% or less.

第一透明導電膜之膜厚d1與第二透明導電膜之膜厚d2,滿係足以下之(1)~(3)之關係。 The film thickness d 1 of the first transparent conductive film and the film thickness d 2 of the second transparent conductive film are sufficient to be in the relationship of (1) to (3).

(1)d1=1~9nm;(2)d1+d2=15~37nm;(3)2d1<d2 (1) d 1 = 1 to 9 nm; (2) d 1 + d 2 = 15 to 37 nm; (3) 2d 1 < d 2

本發明之透明導電層積膜之一形態中,透明導電膜為結晶率30%以下之非晶質膜。該非晶質膜,較好是1um2平均具有90個以上之結晶粒。另外,非晶質膜於150℃加熱時,較好是2小時以內電阻係數成為3.7×10-4Ωcm以下。 In one embodiment of the transparent conductive laminated film of the present invention, the transparent conductive film is an amorphous film having a crystallinity of 30% or less. The amorphous film preferably has an average of 90 or more crystal grains of 1 um 2 . Further, when the amorphous film is heated at 150 ° C, the resistivity is preferably 3.7 × 10 -4 Ωcm or less within 2 hours.

本發明之透明導電層積膜之一形態中,第一透明導電膜及第二透明導電膜均為結晶質。結晶質之透明導電膜,較好是電阻係數在3.7×10-4Ωcm以下。 In one embodiment of the transparent conductive laminated film of the present invention, the first transparent conductive film and the second transparent conductive film are both crystalline. The crystalline transparent conductive film preferably has a resistivity of 3.7 × 10 -4 Ωcm or less.

本發明之透明導電層積膜的製造方法,係具有:於透明膜基材上形成透明介電層的工程(透明介電層形成工程);及於透明介電層上依序形成第一透明導電膜及第二透明導電膜的工程(透明導電膜形成工程);該第一透明導電膜係由氧化錫之含有比例在1重量%以上小於6重量%之氧化銦錫層構成,該第二透明導電膜係由氧化錫之含有比例在6重量%以上20重量%以下之氧化銦錫層構成。 The method for producing a transparent conductive laminated film of the present invention comprises: forming a transparent dielectric layer on a transparent film substrate (transparent dielectric layer forming process); and sequentially forming a first transparent layer on the transparent dielectric layer a conductive film and a second transparent conductive film (transparent conductive film forming process); the first transparent conductive film is composed of an indium tin oxide layer having a tin oxide content of 1% by weight or more and less than 6% by weight, the second The transparent conductive film is composed of an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less.

於透明介電層形成工程,氧化矽層較好是藉由濺鍍法形成。透明導電膜形成工程中,係於氧化矽層上直接製作第一透明導電膜,於其上製作第二透明導電膜。第一透明導電膜及第二透明導電膜,較好是均藉由濺鍍法形成。 In the transparent dielectric layer formation process, the hafnium oxide layer is preferably formed by sputtering. In the transparent conductive film forming process, a first transparent conductive film is directly formed on the ruthenium oxide layer, and a second transparent conductive film is formed thereon. The first transparent conductive film and the second transparent conductive film are preferably formed by sputtering.

本發明的製造方法之一形態中,係另具有:於透明導電膜形成工程之後,藉由加熱處理使透明導電膜結晶化的工程(結晶化工程)。 In one aspect of the production method of the present invention, there is another process (crystallization process) of crystallizing the transparent conductive film by heat treatment after the transparent conductive film formation process.

依據本發明,藉由短時間之熱處理可以提供電阻係數小,而且面內電阻均一的透明導電層積膜。本發明之透明 導電層積膜,適合使用於靜電容量方式之觸控面板用之電極。 According to the present invention, a transparent conductive laminated film having a small resistivity and uniform in-plane resistance can be provided by heat treatment for a short period of time. Transparent of the invention The conductive laminated film is suitable for use in an electrode for a touch panel of an electrostatic capacitance type.

10‧‧‧透明膜基材 10‧‧‧Transparent film substrate

21‧‧‧透明介電層(氧化矽層) 21‧‧‧Transparent dielectric layer (yttria layer)

22‧‧‧第一透明導電膜 22‧‧‧First transparent conductive film

23‧‧‧第二透明導電膜 23‧‧‧Second transparent conductive film

24‧‧‧積層透明導電膜 24‧‧‧Laminated transparent conductive film

100‧‧‧透明導電層積膜 100‧‧‧Transparent conductive laminated film

第1圖表示本發明之一實施形態的透明導電層積膜(透明導電性膜)之剖面模式圖。 Fig. 1 is a schematic cross-sectional view showing a transparent conductive laminated film (transparent conductive film) according to an embodiment of the present invention.

第2圖表示將非晶質成分蝕刻後之透明導電層積體之SEM觀察影像。 Fig. 2 shows an SEM observation image of a transparent conductive laminate obtained by etching an amorphous component.

第1圖表示透明導電層積膜100之模式剖面圖,該透明導電層積膜100,係於透明膜基材10上具有透明介電層21;及第一透明導電膜22與第二透明導電膜23之積層透明導電膜24。以下,參照圖面說明透明導電層積膜之實施形態,係以使用捲繞式濺鍍裝置,藉由捲輪式薄膜輸送(Roll-to-roll)法,於透明膜基材10上製作透明介電層21、第一透明導電膜22及第二透明導電膜23為中心加以說明。 1 is a schematic cross-sectional view showing a transparent conductive laminated film 100 having a transparent dielectric layer 21 on a transparent film substrate 10; and a first transparent conductive film 22 and a second transparent conductive film The transparent conductive film 24 is laminated on the film 23. Hereinafter, an embodiment of a transparent conductive laminated film will be described with reference to the drawings, and a transparent sputtering substrate is used to form a transparent film substrate 10 by a roll-to-roll method. The dielectric layer 21, the first transparent conductive film 22, and the second transparent conductive film 23 will be described as a center.

<透明膜基材> <Transparent film substrate>

透明膜基材10較好是至少在可見光區域為無色透明者。透明膜基材之材料可為聚對苯二甲酸乙二醇酯(PET)、聚對苯二甲酸丁二酯(PBT)或聚萘二甲酸乙二醇酯(PEN)等聚酯樹脂,環烯系樹脂,聚碳酸酯樹脂,聚醯亞胺樹脂,纖維素系樹脂等。透明膜基材10之厚度未特別限定,10um~400um為較好,25um~200um更好。透明膜基材10之厚度在上述範圍,可以具有耐久性與適度之柔軟性。因此,可以使用捲繞式濺鍍製作裝置,藉由捲輪式薄膜輸送方式,於透明膜基材上以 較高生產效率製作透明介電層21及透明導電膜24。透明膜基材10,可於單面或兩面形成硬塗層等機能層(未圖示)。 The transparent film substrate 10 is preferably one which is colorless and transparent at least in the visible light region. The material of the transparent film substrate may be a polyester resin such as polyethylene terephthalate (PET), polybutylene terephthalate (PBT) or polyethylene naphthalate (PEN). An olefin resin, a polycarbonate resin, a polyimide resin, a cellulose resin, or the like. The thickness of the transparent film substrate 10 is not particularly limited, and is preferably 10 um to 400 um, more preferably 25 um to 200 um. The thickness of the transparent film substrate 10 is in the above range, and it can have durability and moderate flexibility. Therefore, it is possible to use a roll-to-roll sputtering apparatus by means of a roll-to-roll film transport method on a transparent film substrate. The transparent dielectric layer 21 and the transparent conductive film 24 are formed with higher production efficiency. The transparent film substrate 10 can form a functional layer (not shown) such as a hard coat layer on one or both sides.

為提升密接性可於該透明高分子膜基材上,事先於表面實施電漿處理或電暈放電,火焰,紫外線照射,電子線照射粗面化等表面處理。 In order to improve the adhesion, a surface treatment such as plasma treatment or corona discharge, flame, ultraviolet irradiation, and electron beam irradiation roughening may be performed on the transparent polymer film substrate in advance.

<介電層> <dielectric layer>

於透明膜基材10上形成至少1層之透明介電層21。透明介電層之作用,係在其上形成透明導電膜24時,作為抑制來自透明膜基材10之水分或有機物質之揮發的氣體阻障層,或減低對透明膜基材之電漿損傷的保護層。 At least one transparent dielectric layer 21 is formed on the transparent film substrate 10. The transparent dielectric layer functions as a gas barrier layer for suppressing volatilization of moisture or organic substances from the transparent film substrate 10 or to reduce plasma damage to the transparent film substrate when the transparent conductive film 24 is formed thereon. Protective layer.

透明介電層21之材料,可以使用聚合物等有機樹脂材料、或金屬氧化物等無機材料、有機-無機混合材料等。氧化物,較好是在可見光區域為無色透明,電阻係數為10Ω‧cm以上者。例如較好是使用Si、Ge、Sn、Al、Ga、In、V、Nb、Ta、Ti、Zr、Zn、Hf等金屬或半金屬之氧化物。 As the material of the transparent dielectric layer 21, an organic resin material such as a polymer, an inorganic material such as a metal oxide, an organic-inorganic hybrid material, or the like can be used. The oxide is preferably colorless and transparent in the visible light region, and has a resistivity of 10 Ω ‧ cm or more. For example, a metal such as Si, Ge, Sn, Al, Ga, In, V, Nb, Ta, Ti, Zr, Zn, Hf or an oxide of a semimetal is preferably used.

透明介電層21,可為僅由1層構成者,或由複數層積層者。本發明中,透明介電層21中,和透明導電膜24相接的介電層為氧化矽層。氧化矽層,可為僅由氧化矽構成者,或含有摻雜質等者。氧化矽層中之氧原子與矽原子之含量之合計較好是80重量%以上,更好是90重量%以上,再更好是95重量%以上。 The transparent dielectric layer 21 may be composed of only one layer or a plurality of layers. In the present invention, in the transparent dielectric layer 21, the dielectric layer that is in contact with the transparent conductive film 24 is a ruthenium oxide layer. The ruthenium oxide layer may be composed only of ruthenium oxide or may contain dopants or the like. The total of the content of the oxygen atom and the ruthenium atom in the ruthenium oxide layer is preferably 80% by weight or more, more preferably 90% by weight or more, still more preferably 95% by weight or more.

透明介電層之最表面層為氧化矽時,發揮作為形成於其上的透明導電膜24之膜成長之底層作用,促使透明導電膜24於短時間均勻結晶化之同時,結晶後之透明導電膜具 有低電阻化之傾向。另外,氧化矽層,亦發揮提升透明導電膜之高溫高濕可靠性之作用。 When the outermost layer of the transparent dielectric layer is yttrium oxide, it functions as a bottom layer of the film which is formed as the transparent conductive film 24 formed thereon, and promotes the transparent conductive film 24 to be uniformly crystallized in a short time, and the transparent conductive after crystallization. Membrane There is a tendency to reduce resistance. In addition, the ruthenium oxide layer also serves to enhance the high temperature and high humidity reliability of the transparent conductive film.

透明介電層21於透明膜基材10上之形成方法,並未特別限定,只要能夠形成均勻的薄膜之方法即可。製作方法可為濺鍍法、蒸鍍法、各種CVD法等之乾塗布法,或旋轉塗布法、輥塗布法、噴塗或浸漬塗布等濕塗布法。就奈米級薄膜之容易形成觀點而言,於上述之中,和透明導電膜24相接的氧化矽層較好是使用乾塗布法來形成。特別是,就以數奈米單位進行膜厚之控制,調整硬度或光學特性之觀點而言,較好是濺鍍法。另外,就形成於氧化矽上的透明導電膜24之結晶化時間之短縮或低電阻化之觀點而言,氧化矽層以乾塗布法,其中以濺鍍法來製作為較好。和以濕塗布製作者比較,以乾塗布法製作的氧化矽層,因為膜中之水分等雜質濃度低,雜質對形成於其上之透明導電膜的混入可以被抑制,有助於低電阻化及結晶化時間之短縮。 The method of forming the transparent dielectric layer 21 on the transparent film substrate 10 is not particularly limited as long as a uniform film can be formed. The production method may be a dry coating method such as a sputtering method, a vapor deposition method, or various CVD methods, or a wet coating method such as a spin coating method, a roll coating method, spray coating, or dip coating. In view of the ease of formation of the nano-scale film, among the above, the ruthenium oxide layer which is in contact with the transparent conductive film 24 is preferably formed by a dry coating method. In particular, the sputtering method is preferred from the viewpoint of controlling the film thickness in units of nanometers and adjusting the hardness or optical characteristics. Further, from the viewpoint of shortening or lowering the crystallization time of the transparent conductive film 24 formed on the ruthenium oxide, the ruthenium oxide layer is preferably formed by a dry coating method using a sputtering method. Compared with the wet coating manufacturer, the yttrium oxide layer produced by the dry coating method has a low impurity concentration such as moisture in the film, and impurities can be suppressed from being mixed into the transparent conductive film formed thereon, contributing to low resistance. And the shortening of the crystallization time.

藉由濺鍍法製作和上述透明導電膜相接的介電層時,靶材可以使用矽、氧化矽、炭化矽等。電源可以使用DC、RF、MF電源等。就生產性之觀點而言MF電源較好。製膜時之電力密度,可於不對透明膜基材造成多餘之熱,而且在不損及生產性範圍內進行調整。電力密度之適當值,會受平板型或圓筒型等陰極之形狀或大小影響,平板型陰極時較好是0.5W/cm2~10W/cm2左右,更好是0.7W/cm2~4W/cm2,再更好是1W/cm2~3W/cm2。特別是氧化矽層以3W/cm2以下之低電力密度製膜時,製作於其上的透明導電膜容易成為低電 阻化。 When a dielectric layer that is in contact with the transparent conductive film is formed by a sputtering method, germanium, cerium oxide, tantalum carbide or the like can be used as the target. The power supply can use DC, RF, MF power, and the like. The MF power supply is better from the viewpoint of productivity. The power density at the time of film formation can be adjusted without causing excessive heat to the transparent film substrate and without impairing the productivity. The appropriate value of the power density may be affected by the shape or size of the cathode such as a flat plate type or a cylindrical type, and the flat type cathode is preferably about 0.5 W/cm 2 to 10 W/cm 2 , more preferably 0.7 W/cm 2 ~ 4 W/cm 2 , more preferably 1 W/cm 2 to 3 W/cm 2 . In particular, when the ruthenium oxide layer is formed at a low power density of 3 W/cm 2 or less, the transparent conductive film formed thereon is likely to have a low resistance.

濺鍍製膜,係於製膜室內導入含氬或氮等惰性氣體及氧氣體之載子氣體來進行。導入氣體較好是氬與氧之混合氣體。 The sputtering film formation is carried out by introducing a carrier gas containing an inert gas such as argon or nitrogen and an oxygen gas into the film forming chamber. The introduction gas is preferably a mixed gas of argon and oxygen.

介電層製膜時之製膜室內之壓力(全壓)較好是5.0×10-3Pa~4.0×10-1Pa,更好是1.0×10-2Pa~1.0×10-1Pa。介電層之製膜壓力過高時,會因形態(微細構造)之變化致使製膜於其上的透明導電膜之表面粗度變大,電阻係數有增大之傾向。 The pressure (total pressure) in the film forming chamber at the time of film formation of the dielectric layer is preferably 5.0 × 10 -3 Pa to 4.0 × 10 -1 Pa, more preferably 1.0 × 10 -2 Pa to 1.0 × 10 -1 Pa. When the film formation pressure of the dielectric layer is too high, the surface roughness of the transparent conductive film formed thereon is increased by the change in the morphology (fine structure), and the resistivity tends to increase.

氧化矽層製膜時之基板溫度,只要在透明膜基材具有耐熱性之範圍內即可,例如較好是60℃以下。基板溫度更好是在-20℃~40℃,再更好是-10℃~20℃。藉由設定基板溫度為上述範圍,可以抑制透明膜基材之脆化或尺寸變化,因此可形成良質之薄膜。 The substrate temperature at the time of film formation of the cerium oxide layer may be within the range of heat resistance of the transparent film substrate, and is preferably, for example, 60 ° C or lower. The substrate temperature is preferably from -20 ° C to 40 ° C, and more preferably from -10 ° C to 20 ° C. By setting the substrate temperature to the above range, embrittlement or dimensional change of the transparent film substrate can be suppressed, so that a favorable film can be formed.

氧化矽層之膜厚較好是2~60nm,更好是10~50nm,再更好是20~40nm。藉由設定透明導電膜正下方的氧化矽層之膜厚為2nm以上,可以發揮透明導電膜製膜時之底層效果,實現透明導電膜之結晶化時間之短縮及低電阻化。藉由增大氧化矽層之膜厚,可以提高透明導電膜製膜時來自膜基材之排氣之阻障機能,此舉亦有助於結晶化時間之短縮化及低電阻化。另外,氧化矽層之膜厚過大時,因為界面反射之多重干涉致使可見光之反射變大,有可能造成辨識性之降低。 The film thickness of the ruthenium oxide layer is preferably from 2 to 60 nm, more preferably from 10 to 50 nm, even more preferably from 20 to 40 nm. By setting the film thickness of the ruthenium oxide layer directly under the transparent conductive film to 2 nm or more, the underlayer effect at the time of film formation of the transparent conductive film can be exhibited, and the crystallization time of the transparent conductive film can be shortened and the resistance can be reduced. By increasing the film thickness of the ruthenium oxide layer, the barrier function of the exhaust gas from the film substrate at the time of film formation of the transparent conductive film can be improved, which contributes to shortening of the crystallization time and reduction in resistance. Further, when the film thickness of the ruthenium oxide layer is too large, the multiple reflection of the interface reflection causes the reflection of visible light to become large, which may cause a decrease in the visibility.

<透明導電膜> <Transparent Conductive Film>

於最表面層為氧化矽的透明介電層21上形成透明導電膜 24。透明導電膜24至少由2層構成。和透明介電層21相接的第一透明導電膜22,係由氧化錫之含有比例:SnO2/(SnO2+In2O3)為1重量%以上小於6重量%之氧化銦錫層構成。第一透明導電膜之氧化錫之含有比例,較好是2重量%以上小於6重量%,更好是3~5重量%。形成於第一透明導電膜22上的第二透明導電膜23,係由氧化錫含有比例:SnO2/(SnO2+In2O3)為6重量%以上20重量%以下之氧化銦錫層構成。第二透明導電膜之氧化錫之含有比例較好是10~15重量%。 The transparent conductive film 24 is formed on the transparent dielectric layer 21 whose outermost layer is yttrium oxide. The transparent conductive film 24 is composed of at least two layers. The first transparent conductive film 22 that is in contact with the transparent dielectric layer 21 is composed of a tin oxide containing ratio of SnO 2 /(SnO 2 +In 2 O 3 ) of 1% by weight or more and less than 6% by weight. Composition. The content of tin oxide in the first transparent conductive film is preferably 2% by weight or more and less than 6% by weight, more preferably 3 to 5% by weight. The second transparent conductive film 23 formed on the first transparent conductive film 22 is an indium tin oxide layer having a tin oxide content ratio of SnO 2 /(SnO 2 +In 2 O 3 ) of 6 wt% or more and 20 wt% or less. Composition. The content of tin oxide in the second transparent conductive film is preferably from 10 to 15% by weight.

和透明導電膜相接的透明介電層21為氧化矽層,而且第一及第二透明導電膜之SnO2含有比例在上述範圍時,低溫短時間之熱處理可達成結晶化,而且可以獲得結晶後之電阻係數小,電阻值之面內均一性良好的透明導電層積體。 The transparent dielectric layer 21 connected to the transparent conductive film is a ruthenium oxide layer, and when the SnO 2 content of the first and second transparent conductive films is in the above range, heat treatment at a low temperature for a short time can be achieved, and crystallization can be obtained. A transparent conductive layered body having a small resistivity and a good in-plane uniformity of the resistance value.

第一透明導電膜之SnO2之含有比例小於2重量%時,高溫高濕度環境下之可靠性有降低的傾向,第二透明導電膜之SnO2之含有比例小於6重量%時,結晶後之電阻係數有變高傾向。另外,第一透明導電膜之SnO2之含有比例在6重量%以上時,或第二透明導電膜之SnO2之含有比例大於20重量%時,結晶化需要較長時間,或者電阻值之面內均一性降低(誤差變大)之傾向存在。 When the content ratio of SnO 2 in the first transparent conductive film is less than 2% by weight, the reliability in a high-temperature and high-humidity environment tends to decrease, and when the content ratio of SnO 2 in the second transparent conductive film is less than 6% by weight, the crystal is formed. The resistivity tends to become higher. Further, when the content ratio of SnO 2 of the first transparent conductive film is 6% by weight or more, or when the content ratio of SnO 2 of the second transparent conductive film is more than 20% by weight, crystallization requires a long time, or the surface of the resistance value There is a tendency for the internal homogeneity to decrease (the error becomes larger).

欲於短時間達結晶化,而且設為低電阻之積層透明導電膜時,第一及第二透明導電膜之膜厚需要設為特定範圍。第一透明導電膜之膜厚d1為1~9nm,較好為3~7nm。第一透明導電膜之膜厚d1與第二透明導電膜之膜厚d2之合計d1+d2為15~37nm,較好為17~33nm,更好為19~30nm。透 明導電膜之合計膜厚小時,會有結晶化時間變長,電阻係數變大之傾向。另外,欲減小透明導電膜之表面電阻時,亦須設定透明導電膜之合計膜厚成為15nm以上。合計膜厚變大時,透明導電膜造成之光吸收變大。 When it is desired to crystallize in a short time and to form a laminated conductive film having a low electrical resistance, the film thicknesses of the first and second transparent conductive films need to be in a specific range. The film thickness d 1 of the first transparent conductive film is 1 to 9 nm, preferably 3 to 7 nm. The total thickness d 1 + d 2 of the film thickness d 1 of the first transparent conductive film and the film thickness d 2 of the second transparent conductive film is 15 to 37 nm, preferably 17 to 33 nm, more preferably 19 to 30 nm. When the total thickness of the transparent conductive film is small, the crystallization time becomes long and the electric resistance coefficient tends to increase. Further, when the surface resistance of the transparent conductive film is to be reduced, the total thickness of the transparent conductive film must be set to 15 nm or more. When the total film thickness is increased, the light absorption by the transparent conductive film is increased.

第二透明導電膜之膜厚d2係較第一透明導電膜之膜厚d1之2倍更大,亦即2d1<d2。第二透明導電膜之膜厚d2為第一透明導電膜之膜厚d1之2.5倍以上為更好,3倍以上為再更好,3.5倍以上特別好。另外,氧化錫含有比例小的第一透明導電膜之膜厚比率小時,結晶化難以進行之同時,電阻之面內分布有變大傾向。因此,第二透明導電膜之膜厚d2在第一透明導電膜之膜厚d1之15倍以下為較好,10倍以下為更好,6倍以下為再更好。 The film thickness d 2 of the second transparent conductive film is greater than twice the film thickness d 1 of the first transparent conductive film, that is, 2d 1 <d 2 . The film thickness d 2 of the second transparent conductive film is preferably 2.5 times or more the film thickness d 1 of the first transparent conductive film, more preferably 3 times or more, and even more preferably 3.5 times or more. Further, when the ratio of the film thickness of the first transparent conductive film having a small content of tin oxide is small, crystallization is difficult to proceed, and the in-plane distribution of the electric resistance tends to increase. Therefore, the film thickness d 2 of the second transparent conductive film is preferably 15 times or less the film thickness d 1 of the first transparent conductive film, more preferably 10 times or less, and still more preferably 6 times or less.

藉由將氧化錫含有比例小的第一透明導電膜之膜厚d1設為相對小,將氧化錫含有比例大的第二透明導電膜之膜厚d2設為相對大,可以提升膜中載子濃度,實現低電阻化。另外,於和氧化矽層相接的第一透明導電膜22中,有由氧化矽層側進行結晶化之傾向,因此藉由將其膜厚d1設為9nm以下之較小,則亦有促進第二透明導電膜23之結晶化,可於短時間達成結晶化。另外,藉由設定合計膜厚d1+d2成為15nm以上,可以減低表面電阻,藉由設定d1+d2為37nm以下,可以抑制可見光之吸收,可以獲得高透過率之透明導電層積膜。 When the film thickness d 1 of the first transparent conductive film having a small tin oxide content ratio is relatively small, the film thickness d 2 of the second transparent conductive film having a large tin oxide content ratio is relatively large, and the film thickness can be raised. The carrier concentration is low resistance. Further, in the first transparent conductive film 22 that is in contact with the ruthenium oxide layer, crystallization tends to proceed from the ruthenium oxide layer side. Therefore, when the film thickness d 1 is set to be smaller than 9 nm, The crystallization of the second transparent conductive film 23 is promoted, and crystallization can be achieved in a short time. In addition, by setting the total film thickness d 1 +d 2 to 15 nm or more, the surface resistance can be reduced, and by setting d 1 +d 2 to 37 nm or less, absorption of visible light can be suppressed, and transparent conductive layering with high transmittance can be obtained. membrane.

又,於上述之專利文獻3(日本特開2006-244771號公報)揭示,當膜基材側之透明導電膜之膜厚小於10nm時,高溫高濕可靠性會降低。相對於此,本發明中,和第一透明導 電膜22相接的透明介電層21之氧化矽層,係發揮第一透明導電膜22之製作底層之作用,因此推斷高溫高濕度可靠性亦佳,而且可以獲得可於短時間達成均勻之結晶化的透明導電層積體。 Further, in the above-mentioned Patent Document 3 (JP-A-2006-244771), when the film thickness of the transparent conductive film on the film substrate side is less than 10 nm, the high-temperature and high-humidity reliability is lowered. In contrast, in the present invention, and the first transparent guide The ruthenium oxide layer of the transparent dielectric layer 21 to which the electric film 22 is connected functions as the bottom layer of the first transparent conductive film 22, so that high temperature and high humidity reliability is also estimated, and uniformity can be obtained in a short time. A crystallized transparent conductive laminate.

於上述之專利文獻4(日本特開2012-114070號公報),考慮到最接近膜基材的透明導電膜受膜基材之產生氣體之影響而難以結晶化,在最遠離膜基材的位置(最表面側)設置氧化錫含有比例小的ITO。相對於此,於本發明中,和第一透明導電膜22相接的透明介電層21之氧化矽層,係發揮對基材之產生氣體的阻障層之作用之同時,亦發揮結晶化促進層之作用。因此,藉由減少和氧化矽層相接的第一透明導電膜22之氧化錫含有比例,可以達成結晶化時間之短縮之同時,達成更進一步之低電阻化。 In the above-mentioned Patent Document 4 (JP-A-2012-114070), it is considered that the transparent conductive film closest to the film substrate is hardly crystallized by the influence of the gas generated by the film substrate, and is located farthest from the film substrate. The (most surface side) is provided with tin oxide containing a small proportion of ITO. On the other hand, in the present invention, the ruthenium oxide layer of the transparent dielectric layer 21 which is in contact with the first transparent conductive film 22 functions as a barrier layer for generating a gas to the substrate, and also exhibits crystallization. Promote the role of the layer. Therefore, by reducing the tin oxide content ratio of the first transparent conductive film 22 that is in contact with the ruthenium oxide layer, it is possible to achieve a reduction in crystallization time and achieve further reduction in resistance.

實際上,以掃描型電子顯微鏡(SEM)觀察製作透明導電膜後(as deposited)之透明導電層積膜,結果確認和在氧化矽上製作氧化錫含有比例大的ITO比較,,在氧化矽層上製作氧化錫含有比例小的ITO時可以產生多數之結晶粒。另外,觀察透明導電層積膜之剖面,結果確認在氧化矽層之界面附近出現多數之結晶粒,由此亦可推測藉由在氧化矽層上製作氧化錫含有比例小的ITO,可以促進結晶化進行。另外,可以推測於製膜後之階段,因為面內存在多數之結晶粒,而可以提高結晶後之透明導電膜之電阻之面內均一性。 In fact, a transparent conductive laminated film which was deposited as a transparent conductive film was observed by a scanning electron microscope (SEM), and as a result, it was confirmed that a cerium oxide layer was formed in comparison with ITO having a large proportion of tin oxide on cerium oxide. When a tin oxide is produced with a small proportion of ITO, a large number of crystal grains can be produced. Further, when the cross section of the transparent conductive laminated film was observed, it was confirmed that a large number of crystal grains appeared in the vicinity of the interface of the ruthenium oxide layer, and it was also presumed that crystallization can be promoted by making ITO having a small proportion of tin oxide on the ruthenium oxide layer. Governing. Further, it can be presumed that the in-plane uniformity of the electric resistance of the transparent conductive film after crystallization can be improved because a large number of crystal grains exist in the surface at the stage after film formation.

透明導電膜24,製膜後為非晶質膜,結晶率(結晶粒佔有之面積比率)在30%以下。非晶質之透明導電膜可藉 由加熱成為結晶化。製膜後之透明導電膜,1um2平均之結晶粒之數較好是90個以上,更好是100個以上,再更好是110個以上。製膜後之透明導電膜越是含有多數之結晶粒,結晶化所要之時間越短。但是,製膜後之透明導電膜含有多數之結晶粒時,若氧化矽層不存在時結晶化亦傾向需要長時間。如上述說明,藉由使用濺鍍來製作氧化錫含有比例小的ITO,可使結晶粒之數變多。亦即本發明中,藉由形成氧化錫含有比例小的ITO層作為透明膜基材10側之第一透明導電膜22,則製膜後存在多數之結晶粒之同時,因為透明介電層21之氧化矽層之作用,可以促進其結晶化,結果可以同時滿足短時間之結晶化、低電阻化及電阻值之面內均一性。 The transparent conductive film 24 is an amorphous film after film formation, and the crystallization ratio (area ratio of crystal grains occupied) is 30% or less. The amorphous transparent conductive film can be crystallized by heating. In the transparent conductive film after film formation, the number of crystal grains of 1 um 2 average is preferably 90 or more, more preferably 100 or more, still more preferably 110 or more. The more the transparent conductive film after film formation contains a large number of crystal grains, the shorter the time required for crystallization. However, when the transparent conductive film after film formation contains a large number of crystal grains, it takes a long time to crystallize if the ruthenium oxide layer is not present. As described above, by using sputtering to form ITO having a small tin oxide content, the number of crystal grains can be increased. In the present invention, by forming the ITO layer having a small tin oxide content as the first transparent conductive film 22 on the side of the transparent film substrate 10, a large number of crystal grains are present after the film formation, because the transparent dielectric layer 21 The action of the ruthenium oxide layer promotes crystallization, and as a result, it is possible to simultaneously satisfy the in-plane uniformity of crystallization, low resistance, and resistance value in a short period of time.

透明導電膜24,其結晶後之電阻係數在3.7×10-4Ω‧cm以下為較好。透明導電膜之結晶化詳如後述說明。 The transparent conductive film 24 preferably has a resistivity after crystallization of 3.7 × 10 -4 Ω ‧ cm or less. The crystallization of the transparent conductive film will be described later in detail.

第一透明導電膜22及第二透明導電膜23,較好是均藉由濺鍍法製作。藉由捲繞式濺鍍裝置進行製膜時,可以連續製作第一透明導電膜22與第二透明導電膜23。於透明膜基材10上,可以連續製作透明介電層21、第一透明導電膜22及第二透明導電膜23。另外,可於第二透明導電膜上進一步製作其他導電膜等。 The first transparent conductive film 22 and the second transparent conductive film 23 are preferably produced by sputtering. When the film formation is performed by the roll-type sputtering apparatus, the first transparent conductive film 22 and the second transparent conductive film 23 can be continuously formed. On the transparent film substrate 10, the transparent dielectric layer 21, the first transparent conductive film 22, and the second transparent conductive film 23 can be continuously formed. Further, another conductive film or the like can be further formed on the second transparent conductive film.

透明導電膜之製膜時之基板溫度或電力密度並未特別限制,例如透明介電層之製作可於上述之基板溫度或電力密度之範圍。第一透明導電膜及第二透明導電膜之製膜時之導入氣體,較好是氬與氧之混合氣體。相對於全部導入氣體量,製膜室內之氧導入量較好是設為0.1体積%~2.0体積%,更 好是設為0.4体積%~1.5体積%。透明導電膜之製膜時之製膜室內之壓力(全壓)較好是設為0.1Pa~1.0Pa,更好是設為0.2Pa~0.8Pa。另外,製膜室內之氧分壓較好是設為1×10-3Pa~2×10-1Pa,更好是設為3×10-3Pa~1×10-2Pa。藉由設定製膜壓力及導入氣體量於上述範圍,可以提升透明導電膜之透明性及導電性。在不損及本發明機能範圍內,導入氣體可含氧或氬以外之氣體。 The substrate temperature or power density at the time of film formation of the transparent conductive film is not particularly limited. For example, the production of the transparent dielectric layer may be in the range of the above substrate temperature or power density. The gas to be introduced at the time of film formation of the first transparent conductive film and the second transparent conductive film is preferably a mixed gas of argon and oxygen. The oxygen introduction amount in the film forming chamber is preferably from 0.1% by volume to 2.0% by volume, more preferably from 0.4% by volume to 1.5% by volume, based on the total amount of introduced gas. The pressure (full pressure) in the film forming chamber at the time of film formation of the transparent conductive film is preferably 0.1 Pa to 1.0 Pa, more preferably 0.2 Pa to 0.8 Pa. Further, the oxygen partial pressure in the film forming chamber is preferably from 1 × 10 -3 Pa to 2 × 10 -1 Pa, more preferably from 3 × 10 -3 Pa to 1 × 10 -2 Pa. By setting the film forming pressure and the amount of the introduced gas in the above range, the transparency and conductivity of the transparent conductive film can be improved. The introduction gas may contain a gas other than oxygen or argon within a range not impairing the function of the present invention.

<透明導電膜之結晶化> <Crystalization of Transparent Conductive Film>

ITO等金屬氧化物構成的透明導電膜,通常於濺鍍製膜後為非晶質。本發明之透明導電層積膜,於供作為觸控面板之形成等之實用時,基於透過率提升或低電阻化等目的,較好是進行透明導電膜之結晶化。結晶化,係藉由針對在透明膜基材10上隔著透明介電層21被形成的透明導電膜24實施加熱來進行。 A transparent conductive film made of a metal oxide such as ITO is usually amorphous after being formed by sputtering. When the transparent conductive laminated film of the present invention is used as a touch panel, it is preferable to crystallize the transparent conductive film for the purpose of improving transmittance or reducing resistance. The crystallization is performed by heating the transparent conductive film 24 formed on the transparent film substrate 10 via the transparent dielectric layer 21.

熱處理溫度係設為膜基材具有耐熱性之範圍,一般為小於200℃。本發明之透明導電層積膜,於150℃進行加熱處理時,可於2小時以內之短時間成為良好的結晶膜。 The heat treatment temperature is a range in which the film substrate has heat resistance, and is generally less than 200 °C. When the transparent conductive laminated film of the present invention is heat-treated at 150 ° C, it can be a good crystal film in a short time of 2 hours.

結晶後的透明導電膜24之電阻係數較好是在3.7×10-4Ω‧cm以下,更好是在3.2×10-4Ω‧cm以下,再更好是在3.0×10-4Ω‧cm以下,2.8×10-4Ω‧cm以下為特別好。電阻係數越低越好,但通常為2.0Ω‧cm以上。結晶後之透明導電膜24之表面電阻較好為200Ω/□以下,更好是在150Ω/□以下,再更好為120Ω/□以下,100Ω/□以下為特別好。透明導電膜之電阻係數及表面電阻在上述範圍時,透明導電層積膜 作為大面積之靜電容量方式觸控面板用之透明電極使用時,亦可以實現高的響應速度。 The resistivity of the transparent conductive film 24 after crystallization is preferably 3.7 × 10 -4 Ω ‧ cm or less, more preferably 3.2 × 10 -4 Ω ‧ cm or less, and even more preferably 3.0 × 10 -4 Ω ‧ Below cm, 2.8 × 10 -4 Ω ‧ cm or less is particularly good. The lower the resistivity, the better, but it is usually 2.0 Ω ‧ cm or more. The surface resistance of the transparent conductive film 24 after crystallization is preferably 200 Ω/□ or less, more preferably 150 Ω/□ or less, still more preferably 120 Ω/□ or less, and particularly preferably 100 Ω/□ or less. When the resistivity and surface resistance of the transparent conductive film are in the above range, the transparent conductive laminated film can also achieve a high response speed when used as a transparent electrode for a large-area electrostatic capacitance type touch panel.

【實施例】 [Examples]

以下依據實施例更具體說明本發明,但本發明不限定於彼等實施例。 The invention will be more specifically described below based on examples, but the invention is not limited to the examples.

〔量測方法〕 [Measurement method] <膜厚> <film thickness>

各層之膜厚,係進行光譜橢圓偏振(Spectroscopic Ellipsometry)量測,以柯西模型(cauchy model)及Tauc-Lorentz模型進行調整來求得。 The film thickness of each layer was measured by Spectroscopic Ellipsometry and adjusted by the Cauchy model and the Tauc-Lorentz model.

<表面電阻及電阻係數> <surface resistance and resistivity>

表面電阻係使用低電阻係數計Loresta-GP(MCP-T710,三菱化學社製)藉由四探針壓接量測進行量測。電阻係數係由上述表面電阻之值與透明導電膜之膜厚之積算出。又,透明導電性膜之電阻係數受溫度而變化乃習知者。因此,針對結晶化後之樣本,係由烤爐取出結晶化終了之樣本,冷卻至室溫之後進行上述之量測。 The surface resistance was measured by a four-probe crimp measurement using a low resistivity meter Loresta-GP (MCP-T710, manufactured by Mitsubishi Chemical Corporation). The resistivity is calculated from the product of the value of the surface resistance and the film thickness of the transparent conductive film. Further, it is known that the resistivity of the transparent conductive film changes depending on the temperature. Therefore, for the crystallization sample, the crystallization finished sample was taken out from the oven, and after cooling to room temperature, the above measurement was performed.

<結晶粒之數及結晶率> <Number of crystal grains and crystallization rate>

將結晶化前之透明導電層積體置於1.7%之鹽酸浸漬90秒,使非晶質成分完全蝕刻之後,進行流水洗淨。使用掃描型電子顯微鏡(SEM)以倍率100000倍觀察該樣本之表面,在1um×1um之視野範圍內,以清晰可見之點之數設為結晶粒之數。另外,對SEM影像實施畫像處理使成為黑白二值化,將清晰可見部分(白部分)之面積率設為結晶率。 The transparent conductive laminate before crystallization was immersed in 1.7% hydrochloric acid for 90 seconds, and the amorphous component was completely etched, followed by running water washing. The surface of the sample was observed at a magnification of 100,000 times using a scanning electron microscope (SEM), and the number of clearly visible dots was set as the number of crystal grains in the field of view of 1 μm × 1 μm. Further, the SEM image is subjected to image processing to be black-and-white binarized, and the area ratio of the clearly visible portion (white portion) is set to the crystallization ratio.

<面內電阻分布> <In-Plane Resistance Distribution>

將透明導電層積體切成A3尺寸,於150℃之烤爐進行特定時間加熱後予以取出,將長邊方向7等分,短邊方向5等分,切割成合計35個試料,藉由上述裝置對各試料之表面電阻進行量測。由各試料之表面電阻與35個試料之表面電阻之平均值,算出|試料之電阻係數-平均電阻係數|÷平均電阻係數×100,將其最大值設為面內電阻分布。 The transparent conductive laminate was cut into an A3 size, and was taken out in an oven at 150 ° C for a specific period of time, and then taken out, and the longitudinal direction was equally divided into 7, and the short side direction was equally divided into 5, and cut into a total of 35 samples. The device measures the surface resistance of each sample. From the average of the surface resistance of each sample and the surface resistance of 35 samples, the resistivity of the sample - the average resistivity | ÷ average resistivity × 100, and the maximum value was defined as the in-plane resistance distribution.

<電阻變化率> <resistance change rate>

將透明導電層積體置於150℃之烤爐進行120分鐘鐘加熱使ITO結晶化。進行表面電阻量測後,於85℃85%之環境下靜置500小時,冷卻至室溫後再度量測表面電阻,求出試驗後之表面電阻(R)對試驗前之表面電阻(R0)的變化率R/R0The transparent conductive laminate was placed in an oven at 150 ° C for 120 minutes to crystallize the ITO. After the surface resistance measurement, it was allowed to stand at 85 ° C for 85% in an environment of 85 ° C. After cooling to room temperature, the surface resistance was measured, and the surface resistance (R) after the test was determined for the surface resistance before the test (R 0 The rate of change of R/R 0 .

〔實施例1〕 [Example 1] (介電層之製膜) (film formation of dielectric layer)

透明膜基材,係使用在兩面包括由尿烷系樹脂構成的硬塗層,厚度為125um之二軸延伸PET膜使用的。於該PET膜之一面上,使用摻雜硼的矽靶材,將氧(流量:3.0sccm)與氬(流量:20.0sccm)之混合氣體導入裝置內之同時,於製膜室內壓力:5.0×10-2Pa、電力密度:1.5W/cm2之條件下進行濺鍍製膜,形成由氧化矽構成的介電層。獲得的介電層之膜厚為25nm。 The transparent film substrate was used for a biaxially stretched PET film having a thickness of 125 μm including a hard coat layer made of a urethane resin on both sides. On one side of the PET film, a boron-doped ruthenium target was used, and a mixed gas of oxygen (flow rate: 3.0 sccm) and argon (flow rate: 20.0 sccm) was introduced into the apparatus, and the pressure in the film forming chamber was 5.0×. A dielectric layer composed of yttrium oxide was formed by sputtering under the conditions of 10 -2 Pa and power density: 1.5 W/cm 2 . The film thickness of the obtained dielectric layer was 25 nm.

(第一透明導電膜之製膜) (film formation of the first transparent conductive film)

於上述透明介電層上,形成氧化錫含有比例為5重量%之 氧化銦錫(ITO)薄膜作為第一透明導電膜層。使用酸化銦與氧化錫之混合燒結靶材(氧化錫含量5重量%),將氧(流量:3.0sccm)與氬(流量:500sccm)之混合氣體導入裝置內之同時,於製膜室內壓力:0.4Pa,電力密度:0.8W/cm2之條件下進行濺鍍製膜。獲得的透明導電膜之膜厚為5nm。 On the transparent dielectric layer, an indium tin oxide (ITO) film containing tin oxide in a proportion of 5% by weight was formed as the first transparent conductive film layer. The target was sintered using a mixture of indium acid and tin oxide (tin oxide content: 5% by weight), and a mixed gas of oxygen (flow rate: 3.0 sccm) and argon (flow rate: 500 sccm) was introduced into the apparatus, and pressure in the film forming chamber was: 0.4 Pa, power density: 0.8 W/cm 2 was sputter-coated to form a film. The film thickness of the obtained transparent conductive film was 5 nm.

(第二透明導電膜之製膜) (film formation of the second transparent conductive film)

於上述第一透明導電膜上,形成氧化錫含有比例為10重量%之ITO薄膜作為第二透明導電膜層。使用酸化銦與氧化錫之混合燒結靶材(氧化錫含量10重量%),將氧(流量:4.0sccm)與氬(流量:500sccm)之混合氣體導入裝置內之同時,於製膜室內壓力:0.4Pa,電力密度:1.5W/cm2之條件下進行濺鍍製膜。獲得的透明導電膜之膜厚為25nm。 On the first transparent conductive film, an ITO film containing tin oxide in an amount of 10% by weight was formed as the second transparent conductive film layer. The target was sintered using a mixture of indium acid and tin oxide (tin oxide content: 10% by weight), and a mixed gas of oxygen (flow rate: 4.0 sccm) and argon (flow rate: 500 sccm) was introduced into the apparatus while the pressure in the film forming chamber was: 0.4 Pa, power density: 1.5 W/cm 2 was sputter coated. The film thickness of the obtained transparent conductive film was 25 nm.

〔實施例2~4〕 [Examples 2 to 4]

除將第一透明導電膜及第二透明導電膜之膜厚變更為表1所示以外,均和實施例1同樣,於二軸延伸PET膜上製作包括氧化矽膜及2層透明導電膜的透明導電層積膜。 In the same manner as in Example 1, except that the film thicknesses of the first transparent conductive film and the second transparent conductive film were changed to those shown in Table 1, a ruthenium oxide film and a two-layer transparent conductive film were formed on the biaxially stretched PET film. Transparent conductive laminated film.

〔比較例1〕 [Comparative Example 1]

於比較例1,第一透明導電膜(氧化錫含有比例10重量%)與第二透明導電膜(氧化錫含有比例5重量%)之配置,係和實施例1相反。 In Comparative Example 1, the arrangement of the first transparent conductive film (the content of the tin oxide is 10% by weight) and the second transparent conductive film (the content of the tin oxide is 5% by weight) are opposite to those of the first embodiment.

首先,和實施例1同樣,於二軸延伸PET膜上,藉由濺鍍製作膜厚25nm之氧化矽膜作為介電層。於其上使用氧化錫含有比例10重量%之靶材,藉由濺鍍製作膜厚25nm之ITO透明導電膜,於其上使用氧化錫含量5重量%之靶材,藉由濺鍍 製作膜厚5nm之ITO透明導電膜。 First, in the same manner as in Example 1, a ruthenium oxide film having a thickness of 25 nm was formed as a dielectric layer by sputtering on a biaxially stretched PET film. A target having a proportion of 10% by weight of tin oxide was used thereon, and an ITO transparent conductive film having a thickness of 25 nm was formed by sputtering, and a target having a tin oxide content of 5% by weight was used thereon by sputtering. An ITO transparent conductive film having a film thickness of 5 nm was formed.

〔比較例2〕 [Comparative Example 2]

於比較例2未形成介電層。具體言之為,於二軸延伸PET膜上,直接藉由濺鍍製作第一透明導電膜(氧化錫含有比例5重量%、膜厚25nm)及第二透明導電膜(氧化錫含有比例10重量%、膜厚5nm)。 No dielectric layer was formed in Comparative Example 2. Specifically, the first transparent conductive film (the tin oxide content: 5% by weight, the film thickness: 25 nm) and the second transparent conductive film (the tin oxide content ratio of 10 parts by weight) are directly formed on the biaxially stretched PET film by sputtering. %, film thickness 5 nm).

〔比較例3〕 [Comparative Example 3]

於比較例3,除將第一透明導電膜及第二透明導電膜之膜厚變更為表1所示以外,均和比較例2同樣,於二軸延伸PET膜上,製作不存在介電層而包括2層透明導電膜的透明導電層積膜。 In Comparative Example 3, except that the film thicknesses of the first transparent conductive film and the second transparent conductive film were changed to those shown in Table 1, a dielectric layer was formed on the biaxially stretched PET film in the same manner as in Comparative Example 2. A transparent conductive laminated film comprising two transparent conductive films.

〔比較例4〕 [Comparative Example 4]

於比較例4,係於介電層上僅形成氧化錫含有比例10重量之ITO透明導電膜。具體言之為,於二軸延伸PET膜上,藉由濺鍍製作膜厚25nm之氧化矽膜作為介電層,於其上使用氧化錫含量10重量%之靶材,藉由濺鍍製作膜厚30nm之透明導電膜。 In Comparative Example 4, only ITO transparent conductive film containing 10% by weight of tin oxide was formed on the dielectric layer. Specifically, on the biaxially stretched PET film, a hafnium oxide film having a thickness of 25 nm was formed as a dielectric layer by sputtering, and a target having a tin oxide content of 10% by weight was used thereon to form a film by sputtering. A transparent conductive film having a thickness of 30 nm.

〔比較例5〕 [Comparative Example 5]

於比較例5,除減低第一透明導電膜之膜厚以外,均和實施例1同樣製作透明導電層積膜。具體言之為,於氧化矽膜上,藉由濺鍍製作0.5nm膜厚之第一透明導電膜(氧化錫含有比例10重量%),於其上藉由濺鍍製作29.5nm膜厚之第二透明導電膜(氧化錫含有比例5重量%)。 In Comparative Example 5, a transparent conductive laminated film was produced in the same manner as in Example 1 except that the film thickness of the first transparent conductive film was reduced. Specifically, a first transparent conductive film (10% by weight of tin oxide) having a film thickness of 0.5 nm is formed on the ruthenium oxide film by sputtering, and a film thickness of 29.5 nm is formed thereon by sputtering. Two transparent conductive films (tin oxide content of 5% by weight).

〔比較例6〕 [Comparative Example 6]

比較例6係增大第一透明導電膜之膜厚。具體言之為,於透明介電層上,藉由濺鍍製作8nm膜厚之第一透明導電膜(氧化錫含有比例10重量%),於其上藉由濺鍍製作10nm膜厚之第二透明導電膜(氧化錫含有比例5重量%)。 Comparative Example 6 increases the film thickness of the first transparent conductive film. Specifically, a first transparent conductive film (10% by weight of tin oxide) having a film thickness of 8 nm is formed on the transparent dielectric layer by sputtering, and a film thickness of 10 nm is formed thereon by sputtering. A transparent conductive film (tin oxide contains 5% by weight).

〔評估結果〕 〔evaluation result〕

上述實施例及比較例之透明導電層積膜之積層構成、製膜後之SEM觀察結果(結晶量之數及結晶率)、於150℃進行90分鐘或120分鐘加熱後之電阻值之量測結果及電阻變化率(R/R0),係如表1所示。另外,非晶質成分蝕刻後之各實施例及比較例之透明導電層積體之SEM觀察影像係如第2圖所示。 The laminated structure of the transparent conductive laminated film of the above Examples and Comparative Examples, the SEM observation result after the film formation (the number of crystals and the crystallinity), and the measurement of the resistance value after heating at 150 ° C for 90 minutes or 120 minutes The results and the rate of change in resistance (R/R 0 ) are shown in Table 1. Further, the SEM observation image of the transparent conductive laminate of each of the examples and the comparative examples after the etching of the amorphous component is as shown in Fig. 2 .

由表1可知,任一比較例在150℃進行120分鐘加熱後之電阻係數為3.8Ω‧cm以上,相對於此,實施例1~4則為3.1Ω‧cm以下,而且電阻值之面內誤差小。 As is clear from Table 1, the resistivity of any of the comparative examples after heating at 150 ° C for 120 minutes was 3.8 Ω ‧ cm or more, whereas in Examples 1 to 4, it was 3.1 Ω ‧ cm or less, and the resistance value was in the surface The error is small.

於不透過透明介電層而形成透明導電膜的比較例 2、3,經由耐濕熱試驗後電阻大幅降低。此乃因為,除了透明導電膜之耐濕熱性低以外,於150℃ 120分鐘之加熱處理中結晶化不充分而引起的。又,如表1之結晶粒數及第2圖之SEM影像所示,和其他比較例比較,於比較例2、3,透明導電膜製作後之結晶粒之數或結晶率變大。但不受影響,因為結晶加速度小,因此氧化矽層發揮作為ITO之製膜底層作用而促進結晶粒之形成之同時,在進行加熱結晶化時,亦具有促進結晶化之作用。 Comparative Example of Forming Transparent Conductive Film Without Transmitting Transparent Dielectric Layer 2, 3, the resistance is greatly reduced after the heat and humidity resistance test. This is because, in addition to the low heat and humidity resistance of the transparent conductive film, crystallization is insufficient in the heat treatment at 150 ° C for 120 minutes. Further, as shown in the number of crystal grains in Table 1 and the SEM image in FIG. 2, in Comparative Examples 2 and 3, the number of crystal grains or the crystallinity after the production of the transparent conductive film was increased as compared with the other comparative examples. However, since the crystallization efficiency is small, the ruthenium oxide layer functions as a film underlayer of ITO to promote the formation of crystal grains, and also has an effect of promoting crystallization when heated and crystallized.

於氧化矽層上形成氧化錫之含有比例大的ITO膜,於其上形成氧化錫含有比例小的ITO膜之比較例1,在進行150℃ 120分鐘之加熱結晶化之後電阻係數亦變高。 In Comparative Example 1 in which an ITO film having a large proportion of tin oxide was formed on the ruthenium oxide layer and an ITO film having a small tin oxide content was formed thereon, the resistivity was also increased after heating and crystallization at 150 ° C for 120 minutes.

氧化錫含有比例小的第一透明導電膜之膜厚為較小的0.5um之比較例5,製膜後之結晶粒之數變少,結晶後之電阻係數亦變高。另外,第一透明導電膜之膜厚為較大的8um,d2/d1=1.25之比較例6,製膜後之結晶粒數多,但是結晶後之透明導電膜之電阻係數變高。此乃因為氧化錫含有比例大的第二透明導電膜之膜厚小,載子密度低而造成的。 In Comparative Example 5 in which the film thickness of the first transparent conductive film having a small tin oxide content was as small as 0.5 μm, the number of crystal grains after film formation was small, and the electric resistance after crystallization was also high. Further, in Comparative Example 6 in which the film thickness of the first transparent conductive film was 8 μm and d 2 /d 1 = 1.25, the number of crystal grains after film formation was large, but the resistivity of the transparent conductive film after crystallization became high. This is because the second transparent conductive film having a large proportion of tin oxide has a small film thickness and a low carrier density.

相較於d2/d1=12.5之實施例2,d2/d1=5之實施例1的電阻值之面內誤差變小。另外,由比較例2與比較例3之對比亦可知,d2/d1小者,電阻值之面內誤差亦變小。和其他實施例比較,d2/d1=2.33之實施例4,其結晶後之電阻係數變高,由此亦可知透明導電膜之膜厚比就低電阻化及電阻值之面內誤差之減低而言係重要者。又,實施例1與實施例3,雖d1與d2之比相同,但是實施例1之電阻係數小、而且電阻 值之面內誤差亦小。此可推此為,實施例1之透明導電膜之合計膜厚d1+d2較大所造成。由上述說明可知,藉由設定第一透明導電膜與第二透明導電膜之膜厚之比及合計膜厚成為特定範圍,可以獲得低電阻、而且電阻之面內誤差小的透明導電層積膜。 Compared with Example 2 in which d 2 /d 1 = 12.5, the in-plane error of the resistance value of Example 1 of d 2 /d 1 = 5 became small. Further, from the comparison between Comparative Example 2 and Comparative Example 3, it is also known that the in-plane error of the resistance value also becomes small when d 2 /d 1 is small. Compared with the other examples, in Example 4, where d 2 /d 1 =2.33, the resistivity after crystallization becomes high, and it is also known that the film thickness ratio of the transparent conductive film is low resistance and the in-plane error of the resistance value. It is important to reduce it. Further, in the first embodiment and the third embodiment, although the ratio of d 1 to d 2 is the same, the resistivity of the first embodiment is small, and the in-plane error of the resistance value is also small. This is because the total thickness d 1 +d 2 of the transparent conductive film of Example 1 is large. As described above, by setting the ratio of the film thicknesses of the first transparent conductive film to the second transparent conductive film and the total film thickness to a specific range, it is possible to obtain a transparent conductive laminated film having low electric resistance and small in-plane error of electric resistance. .

10‧‧‧透明膜基材 10‧‧‧Transparent film substrate

21‧‧‧透明介電層(氧化矽層) 21‧‧‧Transparent dielectric layer (yttria layer)

22‧‧‧第一透明導電膜 22‧‧‧First transparent conductive film

23‧‧‧第二透明導電膜 23‧‧‧Second transparent conductive film

24‧‧‧積層透明導電膜 24‧‧‧Laminated transparent conductive film

100‧‧‧透明導電層積膜 100‧‧‧Transparent conductive laminated film

Claims (10)

一種透明導電層積膜,係在透明膜基材之至少一面,依序包括至少1層透明介電層,及和上述透明介電層相接而設的透明導電膜者;和上述透明導電膜相接的上述透明介電層為氧化矽層;上述透明導電膜為層積膜,係由上述透明膜基材側起依序具有:由氧化錫之含有比例在1重量%以上小於6重量%之氧化銦錫層構成的第一透明導電膜;及由氧化錫含有比例在6重量%以上20重量%以下之氧化銦錫層構成的第二透明導電膜;上述第一透明導電膜之膜厚d1與第二透明導電膜之膜厚d2,係滿足以下(1)~(3)之關係:(1)d1=1~9nm;(2)d1+d2=15~37nm;(3)2d1<d2上述透明導電膜之結晶後的電阻係數在3.7×10-4Ω‧cm以下。 A transparent conductive laminated film comprising at least one transparent dielectric layer on at least one side of a transparent film substrate, and a transparent conductive film provided in contact with the transparent dielectric layer; and the transparent conductive film The transparent dielectric layer that is in contact with each other is a ruthenium oxide layer, and the transparent conductive film is a laminated film which is sequentially provided from the side of the transparent film substrate: the content of the tin oxide is 1% by weight or more and less than 6% by weight. a first transparent conductive film made of an indium tin oxide layer; and a second transparent conductive film made of an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less; a film thickness of the first transparent conductive film The film thickness d 2 of d 1 and the second transparent conductive film satisfies the following relationship (1) to (3): (1) d 1 = 1 to 9 nm; (2) d 1 + d 2 = 15 to 37 nm; (3) 2d 1 <d 2 The resistivity after crystallization of the above transparent conductive film is 3.7 × 10 -4 Ω ‧ cm or less. 如申請專利範圍第1項之透明導電層積膜,其中上述氧化矽層之膜厚在2nm以上60nm以下。 The transparent conductive laminated film according to claim 1, wherein the ruthenium oxide layer has a film thickness of 2 nm or more and 60 nm or less. 如申請專利範圍第1或2項之透明導電層積膜,其中上述透明導電膜,係結晶率在30%以下的非晶質膜,1um2平均具有90個以上之結晶粒。 The transparent conductive laminated film according to claim 1 or 2, wherein the transparent conductive film is an amorphous film having a crystallinity of 30% or less, and has an average of 90 or more crystal grains per 1 um 2 . 如申請專利範圍第1或2項之透明導電層積膜,其中上述透明導電膜,係結晶率在30%以下的非晶質膜,於150℃ 加熱時,2小時以內電阻係數成為3.7×10-4Ω‧cm以下。 The transparent conductive laminated film according to claim 1 or 2, wherein the transparent conductive film is an amorphous film having a crystallinity of 30% or less, and when heated at 150 ° C, the resistivity within 2 hours is 3.7 × 10 -4 Ω‧cm or less. 如申請專利範圍第1或2項之透明導電層積膜,其中上述第一透明導電膜與上述第二透明導電膜均為結晶質。 The transparent conductive laminated film according to claim 1 or 2, wherein the first transparent conductive film and the second transparent conductive film are both crystalline. 一種透明導電層積膜的製造方法,係用來製造透明導電層積膜的方法,該透明導電層積膜,係在透明膜基材之至少一面,依序包括至少1層透明介電層,及和上述透明介電層相接而設的透明導電膜者;其具有:於透明膜基材上形成透明介電層的透明介電層形成工程;及於上述透明介電層上依序形成第一透明導電膜及第二透明導電膜的透明導電膜形成工程,該第一透明導電膜係由氧化錫之含有比例在1重量%以上小於6重量%之氧化銦錫層構成,該第二透明導電膜係由氧化錫之含有比例在6重量%以上20重量%以下之氧化銦錫層構成;和上述透明導電膜相接的上述透明介電層,係氧化矽層;於上述透明導電膜形成工程,係於上述氧化矽層上直接以1~9nm之膜厚d1製作上述第一透明導電膜,於其上以比d1之2倍大的膜厚d2製作上述第二透明導電膜;上述第一透明導電膜之膜厚d1與上述第二透明導電膜之膜厚d2之合計d1+d2在15~37nm。 A method for producing a transparent conductive laminated film, which is a method for producing a transparent conductive laminated film, which is provided on at least one side of a transparent film substrate, and sequentially includes at least one transparent dielectric layer. And a transparent conductive film provided in contact with the transparent dielectric layer; the transparent dielectric layer forming a transparent dielectric layer on the transparent film substrate; and sequentially forming on the transparent dielectric layer Forming a transparent conductive film of the first transparent conductive film and the second transparent conductive film, the first transparent conductive film being composed of an indium tin oxide layer having a tin oxide content of 1% by weight or more and less than 6% by weight, the second The transparent conductive film is composed of an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less; the transparent dielectric layer in contact with the transparent conductive film is a hafnium oxide layer; and the transparent conductive film In the forming process, the first transparent conductive film is directly formed on the yttrium oxide layer by a film thickness d 1 of 1 to 9 nm, and the second transparent conductive film is formed thereon by a film thickness d 2 which is twice larger than d 1 Film; the first transparent conductive film The total thickness d 1 +d 2 of the film thickness d 1 and the film thickness d2 of the second transparent conductive film is 15 to 37 nm. 如申請專利範圍第6項之透明導電層積膜的製造方法,其中於上述透明介電層形成工程,上述氧化矽層係藉由濺鍍法形成。 The method for producing a transparent conductive laminated film according to claim 6, wherein the ruthenium oxide layer is formed by a sputtering method in the transparent dielectric layer forming process. 如申請專利範圍第6或7項之透明導電層積膜的製造方法,其中於上述透明導電膜形成工程,上述第一透明導電膜及上述第二透明導電膜均藉由濺鍍法形成。 The method for producing a transparent conductive laminated film according to claim 6 or 7, wherein the first transparent conductive film and the second transparent conductive film are formed by sputtering. 如申請專利範圍第6或7項之透明導電層積膜的製造方法,其中進一步具有:於上述透明導電膜形成工程之後,藉由加熱處理使上述透明導電膜結晶化的結晶化工程。 The method for producing a transparent conductive laminated film according to claim 6 or 7, further comprising: a crystallization process for crystallizing the transparent conductive film by heat treatment after the transparent conductive film forming process. 如申請專利範圍第9項之透明導電層積膜的製造方法,其中結晶化工程後的上述透明導電膜之電阻係數在3.7×10-4Ω‧cm以下。 The method for producing a transparent conductive laminated film according to claim 9, wherein the transparent conductive film after the crystallization process has a resistivity of 3.7 × 10 -4 Ω‧ cm or less.
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