JPWO2014157312A1 - Transparent conductive laminated film and method for producing the same - Google Patents

Transparent conductive laminated film and method for producing the same Download PDF

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JPWO2014157312A1
JPWO2014157312A1 JP2015508579A JP2015508579A JPWO2014157312A1 JP WO2014157312 A1 JPWO2014157312 A1 JP WO2014157312A1 JP 2015508579 A JP2015508579 A JP 2015508579A JP 2015508579 A JP2015508579 A JP 2015508579A JP WO2014157312 A1 JPWO2014157312 A1 JP WO2014157312A1
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慎也 大本
慎也 大本
崇 口山
崇 口山
貴久 藤本
貴久 藤本
山本 憲治
憲治 山本
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/086Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth

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Abstract

透明導電積層体フィルム(100)は、フィルム基材(10)の少なくとも一方の面に、透明誘電体層(21)、および透明誘電体層(21)に接して設けられた透明導電膜(24)をこの順に備える。透明導電膜(24)に接する透明誘電体層(21)は、酸化珪素層である。透明導電膜(24)は、透明フィルム基材(10)側から順に、酸化スズの含有割合が1重量%以上6重量%未満の酸化インジウムスズ層からなる第一の透明導電膜(22)と;酸化スズ含有割合が6重量%以上20重量%以下の酸化インジウムスズ層からなる第二の透明導電膜(23)とを有する積層膜である。第一の透明導電膜(22)の膜厚d1と第二の透明導電膜(23)の膜厚d2は、以下の(1)〜(3)の関係を満たす:(1)d1=1〜9nm;(2)d1+d2=15〜37nm;(3)2d1<d2。The transparent conductive laminate film (100) includes a transparent dielectric layer (21) and a transparent conductive film (24) provided on and in contact with the transparent dielectric layer (21) on at least one surface of the film substrate (10). ) In this order. The transparent dielectric layer (21) in contact with the transparent conductive film (24) is a silicon oxide layer. The transparent conductive film (24) includes, in order from the transparent film substrate (10) side, a first transparent conductive film (22) composed of an indium tin oxide layer having a tin oxide content of 1 wt% or more and less than 6 wt%. A laminated film having a second transparent conductive film (23) composed of an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less. The film thickness d1 of the first transparent conductive film (22) and the film thickness d2 of the second transparent conductive film (23) satisfy the following relationships (1) to (3): (1) d1 = 1 to 9 nm; (2) d1 + d2 = 15-37 nm; (3) 2d1 <d2.

Description

本発明は、透明フィルム基材上に、透明誘電体層と透明導電体層とを備える透明導電積層フィルム、およびその製造方法に関する。   The present invention relates to a transparent conductive laminated film comprising a transparent dielectric layer and a transparent conductor layer on a transparent film substrate, and a method for producing the same.

透明フィルム上に酸化インジウムスズ(ITO)等の導電性酸化物薄膜が形成された透明導電性フィルムは、ディスプレイや発光素子、光電変換素子等の透明電極として広く用いられている。このような透明導電性フィルムは、例えば、透明フィルム基材上に、スパッタリング法等のドライプロセスにより、導電性酸化物薄膜層を形成することにより製造される。透明電極を構成する導電性酸化物薄膜には、高温高湿度環境下での抵抗率の信頼性等が要求される。このような要求特性に応えるため、透明導電性フィルムは、導電性酸化物を結晶化させて用いる場合が多い。   A transparent conductive film in which a conductive oxide thin film such as indium tin oxide (ITO) is formed on a transparent film is widely used as a transparent electrode for displays, light emitting elements, photoelectric conversion elements and the like. Such a transparent conductive film is manufactured, for example, by forming a conductive oxide thin film layer on a transparent film substrate by a dry process such as a sputtering method. The conductive oxide thin film that constitutes the transparent electrode is required to have a reliability of resistivity in a high temperature and high humidity environment. In order to meet such required characteristics, the transparent conductive film is often used by crystallizing a conductive oxide.

透明導電性フィルムの品質向上を目的として、フィルム基材上に設ける透明導電膜を積層構成とすることが提案されている。例えば、特許文献1には、フィルム基材上に粒径の小さい結晶粒を有する第一の透明導電膜と、第一の透明導電膜よりも粒径の大きい結晶粒を有する第二の透明導電膜とを形成することで、透明性を維持したままペン圧耐久性やカール特性等を改善する技術が記載されている。   For the purpose of improving the quality of the transparent conductive film, it has been proposed that the transparent conductive film provided on the film substrate has a laminated structure. For example, Patent Document 1 discloses that a first transparent conductive film having crystal grains having a small particle diameter on a film substrate and a second transparent conductive film having crystal grains having a larger particle diameter than the first transparent conductive film. A technique for improving pen pressure durability and curling characteristics while maintaining transparency by forming a film is described.

特許文献2には、フィルム基材上に、酸化スズ(SnO)含有量の小さい(SnO:3〜8重量%)酸化インジウムスズからなる第一の透明導電膜と、SnO含有量の大きい(SnO:10〜30重量%)酸化インジウムスズからなる第二の透明導電膜とを設けて、透明性を改善するとともに、低抵抗化する技術が記載されている。Patent Document 2 discloses a first transparent conductive film made of indium tin oxide having a small tin oxide (SnO 2 ) content (SnO 2 : 3 to 8% by weight) on a film substrate, and a SnO 2 content. A technique is described in which a large (SnO 2 : 10 to 30 wt%) second transparent conductive film made of indium tin oxide is provided to improve transparency and reduce resistance.

特許文献3には、フィルム基材上に、SnO含有量の小さい(SnO:2〜6重量%)酸化インジウムスズからなる第一の透明導電膜と、SnO含有量の大きい(SnO:6〜20重量%)酸化インジウムスズからなる第二の透明導電膜とを設け、両者の膜厚比を所定範囲とすることにより、タッチパネル用の透明導電性フィルムとしての高温高湿信頼性を満足できることや、低温の熱処理による結晶化が可能であることが記載されている。Patent Document 3 discloses a first transparent conductive film made of indium tin oxide having a small SnO 2 content (SnO 2 : 2 to 6% by weight) on a film substrate and a large SnO 2 content (SnO 2). : 6 to 20% by weight) By providing a second transparent conductive film made of indium tin oxide, and setting the film thickness ratio of both to a predetermined range, high temperature and high humidity reliability as a transparent conductive film for a touch panel is achieved. It describes that it is satisfactory and that crystallization is possible by low-temperature heat treatment.

上記特許文献1〜3の透明導電性フィルムは、主に抵抗膜方式のタッチパネルに用いられるものである。一方、近年、マルチタッチ入力やジェスチャー入力が可能である静電容量方式のタッチパネルが急速に普及しており、スマートフォン、タブレットパソコン、ノートパソコン等に用いられている。静電容量方式タッチパネルでは、センサの感度や応答速度を高めるために、透明電極層が低抵抗であることが求められる。   The transparent conductive films of Patent Documents 1 to 3 are mainly used for resistive touch panels. On the other hand, in recent years, capacitive touch panels capable of multi-touch input and gesture input are rapidly spreading and are used in smartphones, tablet computers, notebook computers, and the like. In the capacitive touch panel, the transparent electrode layer is required to have a low resistance in order to increase the sensitivity and response speed of the sensor.

また、透明導電性フィルムの製造工程においては、導電性酸化物の結晶化を短時間で行うことが求められる。結晶化の方法としては、フィルム基材上に非晶質の導電性酸化物薄膜を形成した後に、加熱を行なう方法が一般的である。樹脂フィルム基材を用いた透明導電性フィルムでは、フィルム基材の耐熱性の観点から、高温(例えば200℃以上)に加熱することは困難である。そのため、比較的低温の加熱で結晶化を行う必要があり、結晶化時間が長くなる傾向がある。   Moreover, in the manufacturing process of a transparent conductive film, it is calculated | required to crystallize a conductive oxide in a short time. As a crystallization method, a method of heating after forming an amorphous conductive oxide thin film on a film substrate is generally used. In the transparent conductive film using a resin film base material, it is difficult to heat to high temperature (for example, 200 degreeC or more) from a heat resistant viewpoint of a film base material. Therefore, it is necessary to perform crystallization by heating at a relatively low temperature, and the crystallization time tends to be long.

特許文献4では、透明導電膜を積層構成とすることにより、低抵抗化と短時間での結晶化を両立し得ることが開示されている。具体的には、透明導電性フィルムの表面側(フィルム基材から離れている側)にSnO含有量の小さいITO層を設け、基材側にSnO含有量の大きいITO層を設ける構成が開示されている。この構成によれば、フィルム基材からの発生ガスの影響を受け難い表面側にSnO含有量の小さいITO層を設けることで、結晶核の形成を促進して結晶化時間を短縮すると共に、SnO含有量の大きい基材側のITO層の膜厚を大きくすることで、キャリアが増加するために抵抗化が図られる、との推定原理が記載されている。Patent Document 4 discloses that a transparent conductive film having a laminated structure can achieve both low resistance and crystallization in a short time. Specifically, a configuration in which an ITO layer having a small SnO 2 content is provided on the surface side of the transparent conductive film (side away from the film substrate) and an ITO layer having a large SnO 2 content is provided on the substrate side. It is disclosed. According to this configuration, by providing an ITO layer with a small SnO 2 content on the surface side that is not easily affected by the gas generated from the film substrate, the formation of crystal nuclei is promoted and the crystallization time is shortened. The estimation principle is described that resistance is increased because the carrier is increased by increasing the film thickness of the ITO layer on the substrate side having a large SnO 2 content.

特開2003−263925号公報JP 2003-263925 A 特開平10−49306号公報Japanese Patent Laid-Open No. 10-49306 特開2006−244771号公報JP 2006-244771 A 特開2012−114070号公報JP 2012-1114070 A

上記特許文献3では、透明導電膜を積層構成とすることにより、透明性および高温高湿環境下における信頼性の向上に加えて、結晶化時間の短縮に効果的であることが記載されている。しかしながら、特許文献3は、主に抵抗膜方式のタッチパネルに用いられる透明導電性フィルムに関し、表面抵抗が300Ω/□程度と高く、低抵抗化と結晶化時間の短縮とを両立し得るものではない。   Patent Document 3 describes that a transparent conductive film having a laminated structure is effective in reducing crystallization time in addition to improving transparency and reliability in a high temperature and high humidity environment. . However, Patent Document 3 relates to a transparent conductive film mainly used for a resistive film type touch panel, and the surface resistance is as high as about 300Ω / □, and it is not possible to achieve both low resistance and shortening of crystallization time. .

特許文献4では、透明導電膜を積層構成とすることにより、低抵抗化と結晶化時間の短縮とを両立し得ることが記載されている。しかしながら、タッチパネルが搭載されるデバイスの大画面化(大面積化)に伴い、応答速度向上のために、透明導電膜のさらなる低抵抗化が求められるようになっている。また、大面積化に伴って、面内の抵抗率の均一性の向上も求められるようになっている。   Patent Document 4 describes that a transparent conductive film having a laminated structure can achieve both a reduction in resistance and a reduction in crystallization time. However, with an increase in screen size (increase in area) of a device on which a touch panel is mounted, further reduction in resistance of the transparent conductive film is required for improving response speed. In addition, as the area increases, the uniformity of the in-plane resistivity is also required.

本発明はこのような課題に鑑み、透明導電膜の透明性、および高温高湿環境下における信頼性を維持しつつ、結晶化時間の短縮、さらなる低抵抗化、および面内抵抗率の均一性向上を実現可能な透明導電性フィルムを提供することを目的とする。   In view of such problems, the present invention maintains the transparency of the transparent conductive film and the reliability in a high-temperature and high-humidity environment, while shortening the crystallization time, further reducing the resistance, and uniformity of the in-plane resistivity. It aims at providing the transparent conductive film which can implement | achieve improvement.

上記課題を解決するため、発明者らが鋭意検討の結果、透明フィルム基材上に、酸化珪素層を介して、酸化スズ含有割合の小さい酸化インジウムスズ層と、酸化スズ含有割合の大きい酸化インジウムスズ層とを設け、かつこれらの膜厚を所定範囲とすることにより、透明導電性フィルムを短時間で結晶化することが可能であり、さらには結晶化後の抵抗率が低く、面内抵抗率の均一性にも優れることを見出した。   In order to solve the above problems, the inventors have intensively studied, and as a result, on the transparent film substrate, an indium tin oxide layer having a small tin oxide content and an indium oxide having a large tin oxide content are interposed via a silicon oxide layer. It is possible to crystallize a transparent conductive film in a short time by providing a tin layer and making these film thicknesses within a predetermined range, and furthermore, the resistivity after crystallization is low and the in-plane resistance is reduced. It was found that the uniformity of rate is also excellent.

本発明は、透明フィルム基材の少なくとも一方の面に、少なくとも1層の透明誘電体層、および前記透明誘電体層に接して設けられた透明導電膜をこの順に備える透明導電積層フィルム、ならびにその製造方法に関する。   The present invention provides a transparent conductive laminated film comprising, in this order, at least one transparent dielectric layer on at least one surface of a transparent film substrate, and a transparent conductive film provided in contact with the transparent dielectric layer, and It relates to a manufacturing method.

本発明の透明導電積層フィルムにおいて、透明導電膜に接する透明誘電体層は、酸化珪素層である。酸化珪素層の膜厚は、2nm以上60nm以下であることが好ましい。透明導電膜は、透明フィルム基材側から順に、酸化スズの含有割合が1重量%以上6重量%未満の酸化インジウムスズ層からなる第一の透明導電膜と、酸化スズ含有割合が6重量%以上20重量%以下の酸化インジウムスズ層からなる第二の透明導電膜とを有する積層膜である。   In the transparent conductive laminated film of the present invention, the transparent dielectric layer in contact with the transparent conductive film is a silicon oxide layer. The thickness of the silicon oxide layer is preferably 2 nm or more and 60 nm or less. The transparent conductive film includes, in order from the transparent film substrate side, a first transparent conductive film composed of an indium tin oxide layer having a tin oxide content of 1 wt% or more and less than 6 wt%, and a tin oxide content of 6 wt%. A laminated film having a second transparent conductive film composed of an indium tin oxide layer of 20 wt% or less.

第一の透明導電膜の膜厚dと第二の透明導電膜の膜厚dは、以下の(1)〜(3)の関係を満たす。
(1)d=1〜9nm;
(2)d+d=15〜37nm;
(3)2d<d
And the thickness d 1 of the first transparent conductive film thickness d 2 of the second transparent conductive film satisfies a relation of the following (1) to (3).
(1) d 1 = 1 to 9 nm;
(2) d 1 + d 2 = 15 to 37 nm;
(3) 2d 1 <d 2

本発明の透明導電積層フィルムは、一形態において、透明導電膜が、結晶化率30%以下の非晶質膜である。この非晶質膜は、1μmあたり90個以上の結晶粒を有することが好ましい。また、非晶質膜は、150℃で加熱した場合に、2時間以内に抵抗率が3.7×10−4Ωcm以下となることが好ましい。In one embodiment, the transparent conductive laminated film of the present invention is an amorphous film having a crystallization rate of 30% or less. This amorphous film preferably has 90 or more crystal grains per 1 μm 2 . The amorphous film preferably has a resistivity of 3.7 × 10 −4 Ωcm or less within 2 hours when heated at 150 ° C.

本発明の透明導電積層フィルムは、一形態において、第一の透明導電膜および第二の透明導電膜がいずれも結晶質である。結晶質の透明導電膜は、抵抗率が3.7×10−4Ωcm以下であることが好ましい。In the transparent conductive laminated film of the present invention, in one form, both the first transparent conductive film and the second transparent conductive film are crystalline. The crystalline transparent conductive film preferably has a resistivity of 3.7 × 10 −4 Ωcm or less.

本発明の透明導電積層フィルムの製造方法は、透明フィルム基材上に透明誘電体層が形成される工程(透明誘電体層形成工程);および透明誘電体層上に、酸化スズの含有割合が1重量%以上6重量%未満の酸化インジウムスズ層からなる第一の透明導電膜と、酸化スズの含有割合が6重量%以上20重量%以下の酸化インジウムスズ層からなる第二の透明導電膜とがこの順に形成される工程(透明導電膜形成工程)、を有する。   In the method for producing a transparent conductive laminated film of the present invention, the step of forming a transparent dielectric layer on a transparent film substrate (transparent dielectric layer forming step); and the content ratio of tin oxide on the transparent dielectric layer A first transparent conductive film comprising an indium tin oxide layer of 1 wt% or more and less than 6 wt%, and a second transparent conductive film comprising an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less And a step of forming in this order (transparent conductive film forming step).

透明誘電体層形成工程では、酸化珪素層がスパッタリング法により形成されることが好ましい。透明導電膜形成工程では、酸化珪素層上に直接、第一の透明導電膜が製膜され、その上に第二の透明導電膜が製膜される。第一の透明導電膜および第二の透明導電膜は、いずれもスパッタリング法により形成されることが好ましい。   In the transparent dielectric layer forming step, the silicon oxide layer is preferably formed by a sputtering method. In the transparent conductive film forming step, the first transparent conductive film is formed directly on the silicon oxide layer, and the second transparent conductive film is formed thereon. Both the first transparent conductive film and the second transparent conductive film are preferably formed by sputtering.

本発明の製造方法の一形態では、透明導電膜形成工程の後に、加熱処理により透明導電膜が結晶化される工程(結晶化工程)をさらに有する。   In one form of the manufacturing method of this invention, it has further the process (crystallization process) in which a transparent conductive film is crystallized by heat processing after a transparent conductive film formation process.

本発明によれば、短時間の熱処理により抵抗率が小さく、かつ面内抵抗が均一な透明導電積層フィルムが提供される。本発明の透明導電積層フィルムは、静電容量方式のタッチパネル用の電極として好適に用いることができる。   According to the present invention, there is provided a transparent conductive laminated film having a low resistivity and a uniform in-plane resistance by a short heat treatment. The transparent conductive laminated film of the present invention can be suitably used as an electrode for a capacitive touch panel.

本発明の実施の一形態に係る透明導電積層フィルム(透明導電性フィルム)を示す断面模式図である。It is a cross-sectional schematic diagram which shows the transparent conductive laminated film (transparent conductive film) which concerns on one Embodiment of this invention. アモルファス成分をエッチング後の透明導電積層体のSEM観察像である。It is a SEM observation image of the transparent conductive laminated body after etching an amorphous component.

図1は、透明フィルム基材10上に、透明誘電体層21、および第一の透明導電膜22と第二の透明導電膜23との積層透明導電膜24、を有する透明導電積層フィルム100の模式断面図である。以下、図面を参照しながら、透明フィルム基材10上に、透明誘電体層21、第一の透明導電膜22、および第二の透明導電膜23を、巻取式スパッタリング装置を用いて、ロール・トゥー・ロール法により製膜する方法を中心に、透明導電積層フィルムの実施形態について説明する。   FIG. 1 shows a transparent conductive laminated film 100 having a transparent dielectric layer 21 and a laminated transparent conductive film 24 of a first transparent conductive film 22 and a second transparent conductive film 23 on a transparent film substrate 10. It is a schematic cross section. Hereinafter, with reference to the drawings, the transparent dielectric layer 21, the first transparent conductive film 22, and the second transparent conductive film 23 are rolled onto the transparent film substrate 10 using a winding type sputtering apparatus. -Embodiment of a transparent conductive laminated film is demonstrated centering on the method of forming into a film by a two-roll method.

<透明フィルム基材>
透明フィルム基材10は、少なくとも可視光領域で無色透明であるものが好ましい。透明フィルム基材の材料としては、ポリエチレンテレフタレート(PET)、ポリブチレンテレフテレート(PBT)やポリエチレンナフタレート(PEN)等のポリエステル樹脂、シクロオレフィン系樹脂、ポリカーボネート樹脂、ポリイミド樹脂、セルロース系樹脂等が挙げられる。透明フィルム基材10の厚みは特に限定されないが、10μm〜400μmが好ましく、25μm〜200μmがより好ましい。透明フィルム基材10の厚みが上記範囲であれば、耐久性と適度な柔軟性とを有し得る。そのため、透明フィルム基材上に、透明誘電体層21および透明導電膜24を、巻取式スパッタリング製膜装置を用いたロール・トゥー・ロール方式により、生産性高く製膜することが可能である。透明フィルム基材10は、片面又は両面にハードコート層等の機能性層(不図示)が形成されたものでもよい。
<Transparent film substrate>
The transparent film substrate 10 is preferably transparent and colorless at least in the visible light region. Examples of the transparent film base material include polyester resins such as polyethylene terephthalate (PET), polybutylene terephthalate (PBT), and polyethylene naphthalate (PEN), cycloolefin resins, polycarbonate resins, polyimide resins, and cellulose resins. Is mentioned. Although the thickness of the transparent film base material 10 is not specifically limited, 10 micrometers-400 micrometers are preferable and 25 micrometers-200 micrometers are more preferable. If the thickness of the transparent film base material 10 is the said range, it may have durability and moderate softness | flexibility. Therefore, it is possible to form the transparent dielectric layer 21 and the transparent conductive film 24 on the transparent film substrate with high productivity by a roll-to-roll method using a winding type sputtering film forming apparatus. . The transparent film substrate 10 may have a functional layer (not shown) such as a hard coat layer formed on one side or both sides.

この透明高分子フィルム基材上に密着性向上のため、予め表面にプラズマ処理やコロナ放電、火炎、紫外線照射、電子線照射粗面化等の表面処理をしてもよい。   In order to improve adhesion on the transparent polymer film substrate, the surface may be previously subjected to surface treatment such as plasma treatment, corona discharge, flame, ultraviolet ray irradiation, electron beam irradiation roughening or the like.

<誘電体層>
透明フィルム基材10上には、少なくとも1層の透明誘電体層21が形成される。透明誘電体層は、その上に透明導電膜24が形成される際に、透明フィルム基材10からの水分や有機物質の揮発を抑制するガスバリア層や、透明フィルム基材に対するプラズマダメージを低減する保護層として作用し得る。
<Dielectric layer>
On the transparent film substrate 10, at least one transparent dielectric layer 21 is formed. The transparent dielectric layer reduces plasma damage to the gas barrier layer that suppresses volatilization of moisture and organic substances from the transparent film substrate 10 and the transparent film substrate when the transparent conductive film 24 is formed thereon. Can act as a protective layer.

透明誘電体層21の材料としては、ポリマー等の有機樹脂材料や、金属酸化物等の無機材料、有機−無機ハイブリッド材料等が用いられる。酸化物としては、可視光領域で無色透明であり、抵抗率が10Ω・cm以上であるものが好ましい。例えば、Si,Ge,Sn,Al,Ga,In,V,Nb,Ta,Ti,Zr,Zn,Hf等の金属又は半金属の酸化物が好ましく用いられる。   As a material of the transparent dielectric layer 21, an organic resin material such as a polymer, an inorganic material such as a metal oxide, an organic-inorganic hybrid material, or the like is used. As the oxide, an oxide that is colorless and transparent in the visible light region and has a resistivity of 10 Ω · cm or more is preferable. For example, a metal or semi-metal oxide such as Si, Ge, Sn, Al, Ga, In, V, Nb, Ta, Ti, Zr, Zn, and Hf is preferably used.

透明誘電体層21は、1層のみからなるものでもよく、複数の層が積層されたものでもよい。本発明において、透明誘電体層21は、透明導電膜24に接する誘電体層は酸化珪素層である。酸化珪素層は、酸化珪素のみからなるものでもよく、ドーパント等を含有するものでもよい。酸化珪素層中の酸素原子と珪素原子の含有量の合計は、80重量%以上が好ましく、90重量%以上がより好ましく、95重量%以上がさらに好ましい。   The transparent dielectric layer 21 may be composed of only one layer, or may be a laminate of a plurality of layers. In the present invention, the dielectric layer 21 in contact with the transparent conductive film 24 is a silicon oxide layer. The silicon oxide layer may be composed only of silicon oxide or may contain a dopant or the like. The total content of oxygen atoms and silicon atoms in the silicon oxide layer is preferably 80% by weight or more, more preferably 90% by weight or more, and still more preferably 95% by weight or more.

透明誘電体層の最表面層が酸化珪素である場合、その上に形成される透明導電膜24の膜成長の下地層として作用し、透明導電膜24を短時間で均一に結晶化することを促すとともに、結晶化後の透明導電膜が低抵抗化する傾向がある。また、酸化珪素層は、透明導電膜の高温高湿信頼性を向上する作用も有する。   When the outermost surface layer of the transparent dielectric layer is silicon oxide, it acts as a base layer for film growth of the transparent conductive film 24 formed thereon, and crystallizes the transparent conductive film 24 uniformly in a short time. In addition, the transparent conductive film after crystallization tends to have a low resistance. The silicon oxide layer also has an effect of improving the high temperature and high humidity reliability of the transparent conductive film.

透明フィルム基材10上への透明誘電体層21の形成方法は、均一な薄膜が形成される方法であれば特に限定されない。製膜方法としては、スパッタリングリング法、蒸着法、各種CVD法等のドライコーティング法や、スピンコート法、ロールコート法、スプレー塗布やディッピング塗布等のウェットコーティング法が挙げられる。上記の中でも透明導電膜24に接する酸化珪素層は、ナノメートルレベルの薄膜を形成しやすいという観点からドライコーティング法を用いて形成されることが好ましい。特に、数ナノメートル単位で膜厚を制御し、硬度や光学特性を調整する観点から、スパッタリング法が好ましい。また、酸化珪素上に形成される透明導電膜24の結晶化時間の短縮や低抵抗化の観点からも、酸化珪素層はドライコーティング法、中でもスパッタリング法により製膜されることが好ましい。ドライコーティング法により製膜された酸化珪素層は、ウェットコーティングにより製膜されたものに比べて、膜中の水分等の不純物濃度が低いために、その上に形成される透明導電膜への不純物の混入が抑制されることが、低抵抗化および結晶化時間の短縮に寄与すると考えられる。   The formation method of the transparent dielectric material layer 21 on the transparent film base material 10 will not be specifically limited if it is a method in which a uniform thin film is formed. Examples of the film forming method include dry coating methods such as sputtering ring method, vapor deposition method and various CVD methods, and wet coating methods such as spin coating method, roll coating method, spray coating and dipping coating. Among the above, the silicon oxide layer in contact with the transparent conductive film 24 is preferably formed using a dry coating method from the viewpoint of easily forming a nanometer-level thin film. In particular, the sputtering method is preferable from the viewpoint of controlling the film thickness in units of several nanometers and adjusting the hardness and optical characteristics. Further, from the viewpoint of shortening the crystallization time and lowering the resistance of the transparent conductive film 24 formed on the silicon oxide, the silicon oxide layer is preferably formed by a dry coating method, particularly a sputtering method. The silicon oxide layer formed by the dry coating method has a lower impurity concentration such as moisture in the film than that formed by the wet coating. It is considered that the suppression of the mixing of the element contributes to lowering the resistance and shortening the crystallization time.

前記透明導電膜に接する誘電体層がスパッタリング法により製膜される場合、ターゲットとしてはシリコン、酸化シリコン、炭化シリコン等を用いることができる。電源としては、DC,RF,MF電源等が使用できる。生産性の観点からはMF電源が好ましい。製膜時のパワー密度は、透明フィルム基材に過剰な熱を与えず、かつ生産性を損なわない範囲で調整され得る。パワー密度の適正値は、平板型や円筒型などのカソードの形状や大きさに依存するが、平板型カソードの場合には、0.5W/cm〜10W/cm程度が好ましく、0.7W/cm〜4W/cmがより好ましく、1W/cm〜3W/cmがさらに好ましい。特に、酸化珪素層が3W/cm以下の低パワー密度で製膜された場合、その上に製膜される透明導電膜が低抵抗化されやすくなる傾向がある。When the dielectric layer in contact with the transparent conductive film is formed by sputtering, silicon, silicon oxide, silicon carbide, or the like can be used as the target. As the power source, a DC, RF, MF power source or the like can be used. From the viewpoint of productivity, an MF power source is preferable. The power density during film formation can be adjusted within a range that does not give excessive heat to the transparent film substrate and does not impair productivity. Proper value of the power density is dependent on the cathode of the shape and size of such flat plate type or a cylindrical type, in the case of a flat type cathode, 0.5W / cm 2 ~10W / cm 2 of about preferably, 0. more preferably 7W / cm 2 ~4W / cm 2 , more preferably 1W / cm 2 ~3W / cm 2 . In particular, when the silicon oxide layer is formed at a low power density of 3 W / cm 2 or less, the transparent conductive film formed thereon tends to have a low resistance.

スパッタリング製膜は、製膜室内に、アルゴンや窒素等の不活性ガスおよび酸素ガスを含むキャリアガスが導入されながら行われる。導入ガスは、アルゴンと酸素の混合ガスが好ましい。   Sputtering is performed while a carrier gas containing an inert gas such as argon or nitrogen and an oxygen gas is introduced into the film forming chamber. The introduced gas is preferably a mixed gas of argon and oxygen.

誘電体層製膜時の製膜室内の圧力(全圧)は、5.0×10−3Pa〜4.0×10−1Paが好ましく、1.0×10−2Pa〜1.0×10−1Paがより好ましい。誘電体層の製膜圧力が過度に高いと、モルフォロジー(微細構造)の変化により、その上に製膜される透明導電膜の表面粗さが大きくなり、抵抗率が増大する傾向がある。The pressure (total pressure) in the film forming chamber at the time of forming the dielectric layer is preferably 5.0 × 10 −3 Pa to 4.0 × 10 −1 Pa, and 1.0 × 10 −2 Pa to 1.0. × 10 −1 Pa is more preferable. When the film forming pressure of the dielectric layer is excessively high, the surface roughness of the transparent conductive film formed thereon increases due to a change in morphology (fine structure), and the resistivity tends to increase.

酸化珪素層製膜時の基板温度は、透明フィルム基材が耐熱性を有する範囲であればよく、例えば、60℃以下が好ましい。基板温度は、−20℃〜40℃がより好ましく、−10℃〜20℃がさらに好ましい。基板温度を上記範囲とすることで、透明フィルム基材の脆化や寸法変化が抑制されるため、良質の薄膜を形成することができる。   The substrate temperature at the time of forming the silicon oxide layer may be in a range in which the transparent film substrate has heat resistance, and is preferably 60 ° C. or less, for example. The substrate temperature is more preferably −20 ° C. to 40 ° C., and further preferably −10 ° C. to 20 ° C. By setting the substrate temperature within the above range, embrittlement and dimensional change of the transparent film substrate are suppressed, so that a high-quality thin film can be formed.

酸化珪素層の膜厚は2〜60nmが好ましく、10〜50nmがより好ましく、20〜40nmがさらに好ましい。透明導電膜直下の酸化珪素層の膜厚を2nm以上とすることにより、透明導電膜製膜時の下地効果が発揮され、透明導電膜の結晶化時間の短縮および低抵抗化が図られる。また、酸化珪素層の膜厚を大きくすることにより、透明導電膜製膜時のフィルム基材からのアウトガスのバリア機能が高められることも、結晶化時間の短縮化および低抵抗化に寄与すると考えられる。一方、酸化珪素層の膜厚が過度に大きいと、界面反射の多重干渉による可視光の反射が大きくなり、視認性の低下を招く場合がある。   The thickness of the silicon oxide layer is preferably 2 to 60 nm, more preferably 10 to 50 nm, and still more preferably 20 to 40 nm. By setting the film thickness of the silicon oxide layer immediately below the transparent conductive film to 2 nm or more, the base effect at the time of forming the transparent conductive film is exhibited, and the crystallization time of the transparent conductive film is shortened and the resistance is reduced. In addition, increasing the film thickness of the silicon oxide layer increases the barrier function of outgas from the film substrate when forming a transparent conductive film, which also contributes to shortening the crystallization time and reducing resistance. It is done. On the other hand, when the film thickness of the silicon oxide layer is excessively large, reflection of visible light due to multiple interference of interface reflection increases, and visibility may be reduced.

<透明導電膜>
最表面層が酸化珪素である透明誘電体層21上に、透明導電膜24が形成される。透明導電膜24は少なくとも2層からなる。透明誘電体層21に接する第一の透明導電膜22は、酸化スズの含有割合:SnO/(SnO+In)が、1重量%以上6重量%未満の酸化インジウムスズ層からなる。第一の透明導電膜の酸化スズの含有割合は、2重量%以上、6重量%未満が好ましく、3〜5重量%がより好ましい。第一の透明導電膜22上に形成される第二の透明導電膜23は、酸化スズ含有割合:SnO/(SnO+In)が、6重量%以上20重量%以下の酸化インジウムスズ層からなる。第二の透明導電膜の酸化スズの含有割合は、10〜15重量%が好ましい。
<Transparent conductive film>
A transparent conductive film 24 is formed on the transparent dielectric layer 21 whose outermost layer is silicon oxide. The transparent conductive film 24 consists of at least two layers. The first transparent conductive film 22 in contact with the transparent dielectric layer 21 is composed of an indium tin oxide layer having a tin oxide content ratio: SnO 2 / (SnO 2 + In 2 O 3 ) of 1 wt% or more and less than 6 wt%. . The content of tin oxide in the first transparent conductive film is preferably 2% by weight or more and less than 6% by weight, and more preferably 3 to 5% by weight. The second transparent conductive film 23 formed on the first transparent conductive film 22 has a tin oxide content ratio: SnO 2 / (SnO 2 + In 2 O 3 ) of 6% by weight or more and 20% by weight or less of indium oxide. It consists of a tin layer. The content ratio of tin oxide in the second transparent conductive film is preferably 10 to 15% by weight.

透明導電膜に接する透明誘電体層21が酸化珪素層であり、かつ、第一および第二の透明導電膜のSnO含有割合が上記範囲である場合に、低温短時間の熱処理による結晶化が可能であり、かつ結晶化後の抵抗率が小さく、抵抗値の面内均一性に優れる透明導電積層体が得られる。When the transparent dielectric layer 21 in contact with the transparent conductive film is a silicon oxide layer and the SnO 2 content ratio of the first and second transparent conductive films is in the above range, crystallization by heat treatment at low temperature and short time is performed. It is possible to obtain a transparent conductive laminate having a low resistivity after crystallization and excellent in-plane uniformity of resistance value.

第一の透明導電膜のSnOの含有割合が2重量%未満の場合は、高温高湿度環境での信頼性が低下する傾向があり、第二の透明導電膜のSnOの含有割合が6重量%未満の場合は、結晶化後の抵抗率が高くなる傾向がある。また、第一の透明導電膜のSnOの含有割合が6重量%以上の場合や、第二の透明導電膜のSnOの含有割合が20重量%を超える場合は、結晶化に長時間を要したり、抵抗値の面内均一性が低下する(バラツキが大きくなる)傾向がある。When the content ratio of SnO 2 in the first transparent conductive film is less than 2% by weight, the reliability in a high-temperature and high-humidity environment tends to decrease, and the content ratio of SnO 2 in the second transparent conductive film is 6 When the content is less than% by weight, the resistivity after crystallization tends to increase. Also, when the content ratio 6% by weight or more of SnO 2 of and the first transparent conductive film, if the content of SnO 2 in the second transparent conductive film is more than 20% by weight, a long time crystallization Or the in-plane uniformity of the resistance value tends to decrease (increase variation).

また、短時間で結晶化が可能で、かつ低抵抗の積層透明導電膜とするためには、第一および第二の透明導電膜の膜厚を所定範囲とする必要がある。第一の透明導電膜の膜厚dは、1〜9nmであり、好ましくは3〜7nmである。また、第一の透明導電膜の膜厚dと、第二の透明導電膜の膜厚dの合計d+dは、15〜37nmであり、好ましくは17〜33nmであり、より好ましくは19〜30nmである。透明導電膜の合計膜厚が小さいと、結晶化時間が長くなり、抵抗率が大きくなる傾向がある。また、透明導電膜の表面抵抗を小さくするためにも、透明導電膜の合計膜厚は、15nm以上とする必要がある。一方、合計膜厚が大きくなると、透明導電膜による光吸収が大きくなる。Further, in order to obtain a laminated transparent conductive film that can be crystallized in a short time and has a low resistance, it is necessary to set the film thicknesses of the first and second transparent conductive films within a predetermined range. The film thickness d1 of the first transparent conductive film is 1 to 9 nm, preferably 3 to 7 nm. The total d 1 + d 2 of the film thickness d 1 of the first transparent conductive film and the film thickness d 2 of the second transparent conductive film is 15 to 37 nm, preferably 17 to 33 nm, and more preferably. Is 19-30 nm. When the total film thickness of the transparent conductive film is small, the crystallization time tends to be long and the resistivity tends to increase. In order to reduce the surface resistance of the transparent conductive film, the total film thickness of the transparent conductive film needs to be 15 nm or more. On the other hand, when the total film thickness increases, light absorption by the transparent conductive film increases.

第二の透明導電膜の膜厚dは、第一の透明導電膜の膜厚dの2倍よりも大きい、すなわち、2d<dである。第二の透明導電膜の膜厚dは、第一の透明導電膜の膜厚dの2.5倍以上であることがより好ましく、3倍以上であることがさらに好ましく、3.5倍以上であることが特に好ましい。一方、酸化スズ含有割合の小さい第一の透明導電膜の膜厚比率が小さいと、結晶化が進行し難くなるとともに、抵抗の面内分布が大きくなる傾向がある。そのため、第二の透明導電膜の膜厚dは、第一の透明導電膜の膜厚dの15倍以下が好ましく、10倍以下がより好ましく、6倍以下がさらに好ましい。Thickness d 2 of the second transparent conductive film is larger than twice the thickness d 1 of the first transparent conductive film, that is, 2d 1 <d 2. The film thickness d2 of the second transparent conductive film is more preferably 2.5 times or more of the film thickness d1 of the first transparent conductive film, more preferably 3 times or more, and 3.5 It is particularly preferable that the number is twice or more. On the other hand, when the film thickness ratio of the first transparent conductive film having a small tin oxide content ratio is small, crystallization hardly proceeds and the in-plane distribution of resistance tends to increase. Therefore, the film thickness d2 of the second transparent conductive film is preferably 15 times or less, more preferably 10 times or less, and still more preferably 6 times or less the film thickness d1 of the first transparent conductive film.

酸化スズ含有割合の小さい第一の透明導電膜の膜厚dを相対的に小さく、酸化スズ含有割合の大きい第二の透明導電膜の膜厚dを相対的に大きくすることにより、膜中キャリア濃度が高められ、低抵抗化が可能となる。また、酸化珪素層に接する第一の透明導電膜22では、酸化珪素層側から結晶化が進行する傾向があるため、その膜厚dを9nm以下と小さくすることにより、第二の透明導電膜23の結晶化も促進され、短時間での結晶化が可能となる。さらに、合計膜厚d+dを15nm以上とすることにより、表面抵抗を小さくすることができ、d+dを37nm以下とすることにより、可視光の吸収が抑制され、高透過率の透明導電積層フィルムが得られる。The film thickness d 1 of the first transparent conductive film with a small tin oxide content ratio is relatively small, and the film thickness d 2 of the second transparent conductive film with a large tin oxide content ratio is relatively large, The medium carrier concentration is increased and the resistance can be reduced. Further, the first transparent conductive film 22 in contact with the silicon oxide layer, since there is a tendency that crystallization proceeds from the silicon oxide layer side, by reducing the thickness d 1 and 9nm or less, the second transparent conductive Crystallization of the film 23 is also promoted, and crystallization can be performed in a short time. Furthermore, by setting the total film thickness d 1 + d 2 to 15 nm or more, the surface resistance can be reduced, and by setting d 1 + d 2 to 37 nm or less, absorption of visible light is suppressed, and high transmittance is achieved. A transparent conductive laminated film is obtained.

なお、上述の特許文献3(特開2006−244771号公報)では、フィルム基材側の透明導電膜の膜厚が10nm未満の場合は、高温高湿信頼性が低下することが記載されている。これに対して、本発明においては、第一の透明導電膜22に接する透明誘電体層21の酸化珪素層が、第一の透明導電膜22の製膜下地として作用することにより、高温高湿度信頼性にも優れ、かつ、短時間で均一な結晶化が可能な透明導電積層体が得られると推定される。   In addition, in the above-mentioned patent document 3 (Unexamined-Japanese-Patent No. 2006-244771), when the film thickness of the transparent conductive film by the side of a film base material is less than 10 nm, it describes that high temperature, high humidity reliability falls. . On the other hand, in the present invention, the silicon oxide layer of the transparent dielectric layer 21 in contact with the first transparent conductive film 22 acts as a film formation base of the first transparent conductive film 22, thereby increasing the temperature and humidity. It is presumed that a transparent conductive laminate having excellent reliability and capable of uniform crystallization in a short time can be obtained.

上述の特許文献4(特開2012−114070号公報)では、フィルム基材に近い透明導電膜がフィルム基材からの発生ガスの影響により結晶化し難いことを考慮して、フィルム基材から最も遠い位置(最表面側)に、酸化スズ含有割合の小さいITOが設けられている。これに対して、本発明においては、第一の透明導電膜22に接する透明誘電体層21の酸化珪素層が、基材からの発生ガスに対するバリア層として作用するとともに、結晶化促進層として作用すると考えられる。そのため、酸化珪素層に接する第一の透明導電膜22の酸化スズ含有割合を小さくすることにより、結晶化時間が短縮されるとともに、さらなる低抵抗化が可能である。   In the above-mentioned Patent Document 4 (Japanese Patent Application Laid-Open No. 2012-1114070), considering that the transparent conductive film close to the film base is difficult to crystallize due to the influence of the gas generated from the film base, it is farthest from the film base. ITO with a small tin oxide content ratio is provided at the position (outermost surface side). On the other hand, in the present invention, the silicon oxide layer of the transparent dielectric layer 21 in contact with the first transparent conductive film 22 functions as a barrier layer against the gas generated from the substrate and also functions as a crystallization promoting layer. I think that. Therefore, by reducing the tin oxide content ratio of the first transparent conductive film 22 in contact with the silicon oxide layer, the crystallization time can be shortened and the resistance can be further reduced.

実際、透明導電膜を製膜直後(as deposited)の透明導電積層フィルムを走査型電子顕微鏡(SEM)で観察したところ、酸化珪素層上に酸化スズ含有割合の小さいITOを製膜した場合の方が、酸化珪素上に酸化スズ含有割合の大きいITOを製膜した場合よりも、多数の結晶粒が発生していることが確認されている。また、透明導電積層フィルムの断面を観察したところ、酸化珪素層との界面付近に多数の結晶粒が確認されたことからも、酸化珪素層上に酸化スズ含有割合の小さいITOが製膜されることにより、結晶化が促進されると考えられる。また、製膜直後の段階で、面内に多数の結晶粒が存在することにより、結晶化後の透明導電膜の抵抗の面内均一性が高められると考えられる。   Actually, when a transparent conductive laminated film was deposited with a scanning electron microscope (SEM) as soon as the transparent conductive film was deposited, an ITO film with a small tin oxide content was formed on the silicon oxide layer. However, it has been confirmed that a larger number of crystal grains are generated than when ITO having a large tin oxide content is formed on silicon oxide. Moreover, when the cross section of the transparent conductive laminated film was observed, many crystal grains were observed near the interface with the silicon oxide layer, so that ITO having a small tin oxide content was formed on the silicon oxide layer. This is thought to promote crystallization. Further, it is considered that the in-plane uniformity of resistance of the transparent conductive film after crystallization is enhanced by the presence of a large number of crystal grains in the plane immediately after the film formation.

透明導電膜24は、製膜直後は非晶質膜であり、結晶化率(結晶粒が占める面積比率)は30%以下である。非晶質の透明導電膜は、加熱により結晶化することができる。製膜直後の透明導電膜は、1μmあたりの結晶粒の数が、90個以上であることが好ましく、100個以上であることがより好ましく、110個以上であることがさらに好ましい。製膜直後の透明導電膜が多数の結晶粒を含むほど、結晶化時間に要する時間が短くなる傾向がある。ただし、製膜直後の透明導電膜が多数の結晶粒を含む場合でも、酸化珪素層が存在しない場合は結晶化に長時間を要する傾向がある。上述のように、酸化スズ含有割合の小さいITOがスパッタリング製膜されることで、結晶粒の数が多くなる傾向がある。すなわち、本発明では、透明フィルム基材10側の第一の透明導電膜22として酸化スズ含有割合の小さいITO層が形成されることにより、製膜直後から多数の結晶粒を存在させるとともに、透明誘電体層21の酸化珪素層の作用により、その結晶化を促進させることで、短時間の結晶化、低抵抗化、および抵抗値の面内均一性を同時に満足させることができると考えられる。The transparent conductive film 24 is an amorphous film immediately after film formation, and the crystallization rate (area ratio occupied by crystal grains) is 30% or less. The amorphous transparent conductive film can be crystallized by heating. In the transparent conductive film immediately after film formation, the number of crystal grains per 1 μm 2 is preferably 90 or more, more preferably 100 or more, and even more preferably 110 or more. As the transparent conductive film immediately after film formation contains more crystal grains, the time required for the crystallization time tends to be shorter. However, even when the transparent conductive film immediately after film formation contains a large number of crystal grains, if there is no silicon oxide layer, crystallization tends to take a long time. As described above, ITO having a small tin oxide content ratio is formed by sputtering, so that the number of crystal grains tends to increase. That is, in the present invention, an ITO layer having a small tin oxide content is formed as the first transparent conductive film 22 on the transparent film substrate 10 side, so that a large number of crystal grains are present immediately after film formation and transparent. By promoting the crystallization by the action of the silicon oxide layer of the dielectric layer 21, it is considered that short-time crystallization, low resistance, and in-plane uniformity of resistance value can be satisfied at the same time.

透明導電膜24は、結晶化後の抵抗率が、3.7×10−4Ω・cm以下であることが好ましい。透明導電膜の結晶化については、後に詳述する。The transparent conductive film 24 preferably has a resistivity after crystallization of 3.7 × 10 −4 Ω · cm or less. The crystallization of the transparent conductive film will be described in detail later.

第一の透明導電膜22および第二の透明導電膜23は、いずれもスパッタリング法により製膜されることが好ましい。巻取式スパッタリング装置により製膜が行われる場合、第一の透明導電膜22と第二の透明導電膜23とを連続製膜してもよい。透明フィルム基材10上に、透明誘電体層21、第一の透明導電膜22、および第二の透明導電膜23を連続製膜することもできる。また、第二の透明導電膜上に、さらに別の導電膜等を製膜することもできる。   Both the first transparent conductive film 22 and the second transparent conductive film 23 are preferably formed by sputtering. When film formation is performed by a winding type sputtering apparatus, the first transparent conductive film 22 and the second transparent conductive film 23 may be continuously formed. The transparent dielectric layer 21, the first transparent conductive film 22, and the second transparent conductive film 23 can be continuously formed on the transparent film substrate 10. Further, another conductive film or the like can be formed on the second transparent conductive film.

透明導電膜の製膜時の基板温度やパワー密度は特に制限されず、例えば、透明誘電体層の製膜に関して上述した基板温度やパワー密度の範囲であってもよい。第一の透明導電膜および第二の透明導電膜の製膜時の導入ガスは、アルゴンと酸素の混合ガスが好ましい。製膜室への酸素導入量は、全導入ガス量に対して、0.1体積%〜2.0体積%が好ましく、0.4体積%〜1.5体積%がより好ましい。透明導電膜の製膜時の製膜室内の圧力(全圧)は、0.1Pa〜1.0Paが好ましく、0.2Pa〜0.8Paがより好ましい。また、製膜室内の酸素分圧は、1×10−3Pa〜2×10−1Paが好ましく、3×10−3Pa〜1×10−2Paがより好ましい。製膜圧力および導入ガス量を上記範囲とすることで、透明導電膜の透明性および導電性を向上させることができる。導入ガスには、本発明の機能を損なわない限りにおいて、酸素やアルゴン以外のガスが含まれていてもよい。The substrate temperature and power density at the time of forming the transparent conductive film are not particularly limited, and may be, for example, the range of the substrate temperature and power density described above for the formation of the transparent dielectric layer. The gas introduced during the formation of the first transparent conductive film and the second transparent conductive film is preferably a mixed gas of argon and oxygen. The amount of oxygen introduced into the film forming chamber is preferably 0.1% by volume to 2.0% by volume, and more preferably 0.4% by volume to 1.5% by volume with respect to the total amount of introduced gas. The pressure (total pressure) in the film-forming chamber when forming the transparent conductive film is preferably 0.1 Pa to 1.0 Pa, and more preferably 0.2 Pa to 0.8 Pa. The oxygen partial pressure in the deposition chamber is, 1 × 10 -3 Pa~2 × 10 -1 Pa , and more preferably 3 × 10 -3 Pa~1 × 10 -2 Pa. By setting the film forming pressure and the amount of introduced gas in the above ranges, the transparency and conductivity of the transparent conductive film can be improved. The introduced gas may contain a gas other than oxygen or argon as long as the function of the present invention is not impaired.

<透明導電膜の結晶化>
ITO等の金属酸化物からなる透明導電膜は、一般に、スパッタリング製膜直後は非晶質である。本発明の透明導電積層フィルムは、タッチパネルの形成等の実用に供する際には、透過率向上や低抵抗化等の目的で、透明導電膜の結晶化が行われることが好ましい。結晶化は、透明フィルム基材10上に透明誘電体層21を介して形成された透明導電膜24を加熱することにより行われる。
<Crystalization of transparent conductive film>
A transparent conductive film made of a metal oxide such as ITO is generally amorphous immediately after sputtering film formation. When the transparent conductive laminated film of the present invention is put to practical use such as formation of a touch panel, the transparent conductive film is preferably crystallized for the purpose of improving transmittance and reducing resistance. Crystallization is performed by heating the transparent conductive film 24 formed on the transparent film substrate 10 via the transparent dielectric layer 21.

熱処理温度は、フィルム基材が耐熱性を有する範囲に設定され、一般には200℃未満である。本発明の透明導電積層フィルムは、150℃で加熱処理を行う場合、2時間以内の短時間で良好な結晶膜とすることが可能である。   The heat treatment temperature is set in a range in which the film substrate has heat resistance, and is generally less than 200 ° C. The transparent conductive laminated film of the present invention can be formed into a good crystal film in a short time within 2 hours when heat treatment is performed at 150 ° C.

結晶化後の透明導電膜24の抵抗率は、3.7×10−4Ω・cm以下が好ましく、3.2×10−4Ω・cm以下がより好ましく、3.0×10−4Ω・cm以下がさらに好ましく、2.8×10−4Ω・cm以下が特に好ましい。抵抗率は低いほどよいが、一般には、2.0Ω・cm以上である。結晶化後の透明導電膜24の表面抵抗は、200Ω/□以下が好ましく、150Ω/□以下がより好ましく、120Ω/□以下がさらに好ましく、100Ω/□以下が特に好ましい。透明導電膜の抵抗率および表面抵抗が上記範囲であれば、透明導電積層フィルムが、大面積の静電容量方式タッチパネル用の透明電極として用いられた場合でも、高い応答速度を実現することができる。The resistivity of the transparent conductive film 24 after crystallization is preferably 3.7 × 10 −4 Ω · cm or less, more preferably 3.2 × 10 −4 Ω · cm or less, and 3.0 × 10 −4 Ω. More preferably, it is not more than cm, and particularly preferably not more than 2.8 × 10 −4 Ω · cm. The lower the resistivity, the better, but generally it is 2.0 Ω · cm or more. The surface resistance of the transparent conductive film 24 after crystallization is preferably 200Ω / □ or less, more preferably 150Ω / □ or less, still more preferably 120Ω / □ or less, and particularly preferably 100Ω / □ or less. When the resistivity and surface resistance of the transparent conductive film are in the above ranges, a high response speed can be realized even when the transparent conductive laminated film is used as a transparent electrode for a large-area capacitive touch panel. .

以下に、実施例を挙げて本発明をより具体的に説明するが、本発明はこれらの実施例に限定されるものではない。   Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to these examples.

[測定方法]
<膜厚>
各層の膜厚は、分光エリプソメトリー測定を行い、cauchyモデル及びtauc‐lorentzモデルでフィッティングを行うことにより求めた。
[Measuring method]
<Film thickness>
The film thickness of each layer was determined by performing spectroscopic ellipsometry measurement and fitting using a cauchy model and a tauc-lorentz model.

<表面抵抗および抵抗率>
表面抵抗は、低抵抗率計ロレスタGP(MCP‐T710、三菱化学社製)を用いて四探針圧接測定により測定した。抵抗率は、前記表面抵抗の値と透明導電膜の膜厚との積により算出した。なお、透明導電性フィルムは温度によって抵抗率が変化することが知られている。そのため、結晶化後のサンプルについては、結晶化が終了したサンプルをオーブンから取り出し、室温まで冷却した後に上記の測定を行った。
<Surface resistance and resistivity>
The surface resistance was measured by four-probe pressure welding measurement using a low resistivity meter Loresta GP (MCP-T710, manufactured by Mitsubishi Chemical Corporation). The resistivity was calculated by the product of the value of the surface resistance and the film thickness of the transparent conductive film. In addition, it is known that the resistivity of a transparent conductive film changes with temperature. Therefore, for the sample after crystallization, the sample after crystallization was taken out of the oven and cooled to room temperature, and then the above measurement was performed.

<結晶粒の数および結晶化率>
結晶化前の透明導電積層体を、1.7%の塩酸に90秒浸漬することにより、アモルファス成分を完全にエッチングした後、流水洗浄を行った。このサンプルの表面を走査型電子顕微鏡(SEM)により、倍率100000倍で観察し、1μm×1μmの視野の範囲で、明るく見える点の数を、結晶粒の数とした。また、SEM像を画像処理により白黒二値化し、明るく見える部分(白部分)の面積率を結晶化率とした。
<Number of crystal grains and crystallization rate>
The transparent conductive laminate before crystallization was immersed in 1.7% hydrochloric acid for 90 seconds to completely etch the amorphous component, and then washed with running water. The surface of this sample was observed with a scanning electron microscope (SEM) at a magnification of 100,000, and the number of points that appeared bright in the range of 1 μm × 1 μm field of view was taken as the number of crystal grains. In addition, the SEM image was binarized by image processing, and the area ratio of the brightly visible part (white part) was defined as the crystallization ratio.

<面内抵抗分布>
透明導電積層体をA3サイズに切り出し、150℃のオーブンで所定時間加熱後に取出し、長辺方向に7等分、短辺方向に5等分して、計35個の試料に切り分け、上記装置により、各試料の表面抵抗を測定した。各試料の表面抵抗と、35個の試料の表面抵抗の平均値から、|試料の抵抗率−平均抵抗率|÷平均抵抗率×100を求め、その最大値を面内抵抗分布とした。
<In-plane resistance distribution>
Cut the transparent conductive laminate into A3 size, take out after heating for a predetermined time in an oven at 150 ° C, divide into 7 equal parts in the long side direction and 5 equal parts in the short side direction, cut into 35 samples in total, using the above equipment The surface resistance of each sample was measured. From the surface resistance of each sample and the average value of the surface resistances of 35 samples, | sample resistivity−average resistivity | ÷ average resistivity × 100 was obtained, and the maximum value was defined as the in-plane resistance distribution.

<抵抗変化率>
透明導電積層体を150℃のオーブンで120分加熱しITOを結晶化した。表面抵抗を測定後に、85℃85%の環境下に500時間静置し、室温まで冷却後に表面抵抗を再度測定し、試験前の表面抵抗(R)に対する試験後の表面抵抗(R)の変化率R/Rを求めた。
<Rate of change in resistance>
The transparent conductive laminate was heated in an oven at 150 ° C. for 120 minutes to crystallize ITO. The surface resistance after the measurement, allowed to stand for 500 hours under 85 ° C. 85% of the environment, again measuring the surface resistance after cooling to room temperature, the surface resistivity after the test with respect to the surface resistance before the test (R 0) of (R) The rate of change R / R 0 was determined.

[実施例1]
(誘電体層の製膜)
透明フィルム基材として、ウレタン系樹脂からなるハードコート層を両面に備える厚み125μmの二軸延伸PETフィルムを用いた。このPETフィルムの一方の面上に、ホウ素がドープされたシリコンターゲットを用い、酸素(流量:3.0sccm)とアルゴン(流量:20.0sccm)の混合ガスを装置内に導入しながら、製膜室内圧力:5.0×10−2Pa、パワー密度:1.5W/cmの条件でスパッタリング製膜を行ない、酸化シリコンからなる誘電体層を形成した。得られた誘電体層の膜厚は25nmであった。
[Example 1]
(Dielectric layer deposition)
As the transparent film substrate, a biaxially stretched PET film having a thickness of 125 μm and having hard coat layers made of urethane resin on both surfaces was used. Using a silicon target doped with boron on one surface of this PET film, a mixed gas of oxygen (flow rate: 3.0 sccm) and argon (flow rate: 20.0 sccm) is introduced into the apparatus while forming a film. Sputtering was performed under the conditions of room pressure: 5.0 × 10 −2 Pa and power density: 1.5 W / cm 2 to form a dielectric layer made of silicon oxide. The film thickness of the obtained dielectric layer was 25 nm.

(第一の透明導電膜の製膜)
上記の透明誘電体層上に、第一の透明導電膜層として、酸化スズ含有割合が5重量%の酸化インジウムスズ(ITO)薄膜を形成した。酸化インジウムと酸化スズの混合焼結ターゲット(酸化スズ含有量5重量%)を用い、酸素(流量:3.0sccm)とアルゴン(流量:500sccm)の混合ガスを装置内に導入しながら、製膜室内圧力:0.4Pa、パワー密度:0.8W/cmの条件で、スパッタリング製膜を行なった。得られた透明導電膜の膜厚は5nmであった。
(Film formation of the first transparent conductive film)
On the transparent dielectric layer, an indium tin oxide (ITO) thin film having a tin oxide content of 5% by weight was formed as the first transparent conductive film layer. Using a mixed sintered target of indium oxide and tin oxide (tin oxide content 5% by weight), a mixed gas of oxygen (flow rate: 3.0 sccm) and argon (flow rate: 500 sccm) is introduced into the apparatus while forming a film. Sputtering film formation was performed under conditions of room pressure: 0.4 Pa and power density: 0.8 W / cm 2 . The film thickness of the obtained transparent conductive film was 5 nm.

(第二の透明導電膜の製膜)
上記の第一の透明導電膜上に、第二の透明導電膜層として酸化スズ含有割合が10重量%のITO薄膜を形成した。酸化インジウムと酸化スズの混合焼結ターゲット(酸化スズ含有量10重量%)を用い、酸素(流量:4.0sccm)とアルゴン(流量:500sccm)の混合ガスを装置内に導入しながら、製膜室内圧力:0.4Pa、パワー密度:1.5W/cmの条件で、スパッタリング製膜を行なった。得られた透明導電膜の膜厚は25nmであった。
(Formation of second transparent conductive film)
On the first transparent conductive film, an ITO thin film having a tin oxide content of 10% by weight was formed as a second transparent conductive film layer. Using a mixed sintered target of indium oxide and tin oxide (tin oxide content 10% by weight), a mixed gas of oxygen (flow rate: 4.0 sccm) and argon (flow rate: 500 sccm) is introduced into the apparatus while forming a film. Sputtering film formation was performed under conditions of indoor pressure: 0.4 Pa and power density: 1.5 W / cm 2 . The film thickness of the obtained transparent conductive film was 25 nm.

[実施例2〜4]
第一の透明導電膜および第二の透明導電膜の膜厚が表1に示すように変更されたこと以外は、実施例1と同様にして、二軸延伸PETフィルム上に、酸化シリコン膜および2層の透明導電膜を備える透明導電積層フィルムを作製した。
[Examples 2 to 4]
A silicon oxide film and a biaxially stretched PET film were formed on the biaxially stretched PET film in the same manner as in Example 1 except that the film thicknesses of the first transparent conductive film and the second transparent conductive film were changed as shown in Table 1. A transparent conductive laminated film provided with a two-layer transparent conductive film was produced.

[比較例1]
比較例1では、第一の透明導電膜(酸化スズ含有割合10重量%)と第二の透明導電膜(酸化スズ含有割合5重量%)の配置が、実施例1と逆であった。
まず、実施例1と同様に、二軸延伸PETフィルム上に、誘電体層として膜厚25nmの酸化シリコン膜をスパッタリング製膜した。その上に、酸化スズ含有割合10重量%のターゲットを用いて、膜厚25nmのITO透明導電膜をスパッタリング製膜し、その上に、酸化スズ含有量5重量%のターゲットを用いて、膜厚5nmのITO透明導電膜をスパッタリング製膜した。
[Comparative Example 1]
In Comparative Example 1, the arrangement of the first transparent conductive film (tin oxide content 10% by weight) and the second transparent conductive film (tin oxide content 5% by weight) was opposite to that in Example 1.
First, in the same manner as in Example 1, a 25 nm-thickness silicon oxide film as a dielectric layer was formed by sputtering on a biaxially stretched PET film. On top of that, an ITO transparent conductive film having a film thickness of 25 nm was formed by sputtering using a target having a tin oxide content ratio of 10% by weight, and a film thickness was formed thereon by using a target having a tin oxide content of 5% by weight. A 5 nm ITO transparent conductive film was formed by sputtering.

[比較例2]
比較例2では、誘電体層が形成されなかった。具体的には、二軸延伸PETフィルム上に、直接、第一の透明導電膜(酸化スズ含有割合5重量%、膜厚25nm)および第二の透明導電膜(酸化スズ含有割合10重量%、膜厚5nm)をスパッタリング製膜した。
[Comparative Example 2]
In Comparative Example 2, no dielectric layer was formed. Specifically, on the biaxially stretched PET film, the first transparent conductive film (tin oxide content 5 wt%, film thickness 25 nm) and the second transparent conductive film (tin oxide content 10 wt%, A film thickness of 5 nm) was formed by sputtering.

[比較例3]
比較例3では、第一の透明導電膜および第二の透明導電膜の膜厚が表1に示すように変更されたこと以外は、比較例2と同様にして、二軸延伸PETフィルム上に、誘電体層を介さずに2層の透明導電膜を備える透明導電積層フィルムを作製した。
[Comparative Example 3]
In Comparative Example 3, on the biaxially stretched PET film in the same manner as in Comparative Example 2, except that the film thicknesses of the first transparent conductive film and the second transparent conductive film were changed as shown in Table 1. A transparent conductive laminated film including two transparent conductive films without using a dielectric layer was produced.

[比較例4]
比較例4では、誘電体層上に、酸化スズ含有割合10重量のITO透明導電膜のみを形成した。具体的には、二軸延伸PETフィルム上に、誘電体層として膜厚25nmの酸化シリコン膜をスパッタリング製膜し、その上に、酸化スズ含有量10重量%のターゲットを用いて、膜厚が30nmの透明導電膜をスパッタリング製膜した。
[Comparative Example 4]
In Comparative Example 4, only an ITO transparent conductive film having a tin oxide content of 10% was formed on the dielectric layer. Specifically, on a biaxially stretched PET film, a silicon oxide film having a film thickness of 25 nm is formed as a dielectric layer by sputtering, and a film having a film thickness of A 30 nm transparent conductive film was formed by sputtering.

[比較例5]
比較例5では、第一の透明導電膜の膜厚を小さくしたこと以外は、実施例1と同様にして透明導電積層フィルムを作製した。具体的には、酸化シリコン膜上に、第一の透明導電膜(酸化スズ含有割合10重量%)を0.5nmの膜厚でスパッタリング製膜し、その上に第二の透明導電膜(酸化スズ含有割合5重量%)を29.5nmの膜厚でスパッタリング製膜した。
[Comparative Example 5]
In Comparative Example 5, a transparent conductive laminated film was produced in the same manner as in Example 1 except that the film thickness of the first transparent conductive film was reduced. Specifically, a first transparent conductive film (tin oxide content 10% by weight) is formed on a silicon oxide film by sputtering to a thickness of 0.5 nm, and a second transparent conductive film (oxidized) is formed thereon. Sputtering was performed at a film thickness of 29.5 nm.

[比較例6]
比較例6では、第一の透明導電膜の膜厚を大きくした。具体的には、透明誘電体層上に、第一の透明導電膜(酸化スズ含有割合10重量%)を8nmの膜厚でスパッタリング製膜し、その上に第二の透明導電膜(酸化スズ含有割合5重量%)を10nmの膜厚でスパッタリング製膜した。
[Comparative Example 6]
In Comparative Example 6, the film thickness of the first transparent conductive film was increased. Specifically, on the transparent dielectric layer, a first transparent conductive film (tin oxide content 10% by weight) is formed by sputtering with a film thickness of 8 nm, and a second transparent conductive film (tin oxide) is formed thereon. Sputtering was performed at a film thickness of 10 nm.

[評価結果]
上記の実施例および比較例の透明導電積層フィルムの積層構成、製膜直後のSEM観察結果(結晶量の数および結晶化率)、150℃で90分あるいは120分加熱後の抵抗値の測定結果、ならびに抵抗変化率(R/R)を、表1に示す。また、アモルファス成分をエッチング後の各実施例および比較例の透明導電積層体のSEM観察像を図2に示す。
[Evaluation results]
Laminated structure of transparent conductive laminated films of the above examples and comparative examples, SEM observation results (number of crystals and crystallization rate) immediately after film formation, measurement results of resistance value after heating at 150 ° C. for 90 minutes or 120 minutes Table 1 shows the resistance change rate (R / R 0 ). Moreover, the SEM observation image of the transparent conductive laminated body of each Example after etching an amorphous component and a comparative example is shown in FIG.

表1からも明らかなように、いずれの比較例も、150℃で120分加熱後の抵抗率が3.8Ω・cm以上であるのに対して、実施例1〜4では、3.1Ω・cm以下であり、かつ抵抗値の面内バラツキが小さいことが分かる。   As is clear from Table 1, in each of the comparative examples, the resistivity after heating at 150 ° C. for 120 minutes is 3.8 Ω · cm or more, whereas in Examples 1 to 4, 3.1 Ω · It can be seen that it is not more than cm and the in-plane variation in resistance value is small.

透明誘電体層を介さずに透明導電膜が形成された比較例2,3では、耐湿熱試験後に抵抗が大幅に低下していた。これは、透明導電膜の耐湿熱性が低いことに加えて、150℃120分の加熱処理では結晶化が不十分であったことに起因している。なお、表1の結晶粒数および図2のSEM像に示されるように、比較例2,3では、他の比較例に比して、透明導電膜を製膜後の結晶粒の数や結晶化率が大きいことが分かる。にも関わらず結晶加速度が小さいことから、酸化珪素層は、ITOの製膜下地として結晶粒の形成を促進するするとともに、加熱による結晶化の際にも、結晶化を促進する作用を有すると考えられる。   In Comparative Examples 2 and 3 in which the transparent conductive film was formed without using the transparent dielectric layer, the resistance was greatly reduced after the wet heat resistance test. This is due to the fact that the heat treatment at 150 ° C. for 120 minutes was insufficient for crystallization in addition to the low wet heat resistance of the transparent conductive film. In addition, as shown in the number of crystal grains in Table 1 and the SEM image in FIG. 2, in Comparative Examples 2 and 3, the number of crystal grains and crystals after forming the transparent conductive film compared to other Comparative Examples. It can be seen that the conversion rate is large. Nevertheless, since the crystal acceleration is small, the silicon oxide layer promotes the formation of crystal grains as the ITO film formation base, and also has the action of promoting crystallization during crystallization by heating. Conceivable.

酸化珪素層上に、酸化スズの含有割合が大きいITO膜が形成され、その上に酸化スズ含有割合が小さいITO膜が形成された比較例1では、150℃120分の加熱により結晶化した後も抵抗率が高かった。   In Comparative Example 1 in which an ITO film having a large tin oxide content was formed on a silicon oxide layer and an ITO film having a small tin oxide content was formed thereon, after crystallization by heating at 150 ° C. for 120 minutes The resistivity was also high.

酸化スズ含有割合が小さい第一の透明導電膜の膜厚が0.5μmと小さい比較例5では、製膜直後の結晶粒の数が少なく、結晶化後の抵抗率も高くなっていた。また、第一の透明導電膜の膜厚が8μmと大きく、d/d=1.25である比較例6では、製膜直後の結晶粒数は多いものの、結晶化後の透明導電膜の抵抗率が高くなっていた。これは、酸化スズ含有割合が大きい第二の透明導電膜の膜厚が小さいために、キャリア密度が低いことに起因していると考えられる。In Comparative Example 5 in which the film thickness of the first transparent conductive film having a small tin oxide content ratio was as small as 0.5 μm, the number of crystal grains immediately after film formation was small, and the resistivity after crystallization was also high. In Comparative Example 6 where the thickness of the first transparent conductive film is as large as 8 μm and d 2 / d 1 = 1.25, the number of crystal grains immediately after film formation is large, but the transparent conductive film after crystallization The resistivity was high. This is considered to be due to the low carrier density because the film thickness of the second transparent conductive film having a large tin oxide content ratio is small.

/d=5の実施例1は、d/d=12.5の実施例2よりも抵抗値の面内バラツキが小さくなっている。また、比較例2と比較例3の対比からも、d/dが小さい方が、抵抗値の面内バラツキが小さいことがわかる。d/d=2.33である実施例4が、他の実施例に比して結晶化後の抵抗率が高いことからも、透明導電膜の膜厚比が低抵抗化および抵抗値の面内バラツキの低減に重要であることがわかる。なお、実施例1と実施例3は、dとdの比が同じであるが、実施例1の方が、抵抗率が小さくかつ抵抗値の面内バラツキも小さくなっている。これは、実施例1の方が透明導電膜の合計膜厚d+dが大きいことに起因していると考えられる。このように、第一の透明導電膜と第二の透明導電膜の膜厚の比および合計膜厚を所定範囲とすることにより、低抵抗で、かつ抵抗の面内バラツキが小さい透明導電積層フィルムが得られることが分かる。In Example 1 where d 2 / d 1 = 5, the in-plane variation of the resistance value is smaller than that in Example 2 where d 2 / d 1 = 12.5. Further, from the comparison between Comparative Example 2 and Comparative Example 3, it can be seen that the smaller the d 2 / d 1 , the smaller the in-plane variation of the resistance value. Since Example 4 where d 2 / d 1 = 2.33 has a higher resistivity after crystallization than other examples, the film thickness ratio of the transparent conductive film is reduced in resistance and resistance value. It can be seen that this is important for reducing the in-plane variation. In Example 1 and Example 3, the ratio of d 1 and d 2 is the same, but Example 1 has a smaller resistivity and smaller in-plane variation in resistance value. This is considered to be due to the fact that Example 1 has a larger total film thickness d 1 + d 2 of the transparent conductive film. Thus, by setting the ratio of the film thickness of the first transparent conductive film to the second transparent conductive film and the total film thickness within a predetermined range, the transparent conductive laminated film has low resistance and small in-plane variation in resistance. It can be seen that

100 透明導電積層フィルム
10 透明フィルム基材
21 透明誘電体層(酸化珪素層)
22 第一の透明導電膜
23 第二の透明導電膜
24 積層透明導電膜
DESCRIPTION OF SYMBOLS 100 Transparent conductive laminated film 10 Transparent film base material 21 Transparent dielectric material layer (silicon oxide layer)
22 First transparent conductive film 23 Second transparent conductive film 24 Laminated transparent conductive film

Claims (10)

透明フィルム基材の少なくとも一方の面に、少なくとも1層の透明誘電体層、および前記透明誘電体層に接して設けられた透明導電膜をこの順に備える透明導電積層フィルムであって、
前記透明導電膜に接する前記透明誘電体層は、酸化珪素層であり、
前記透明導電膜は、前記透明フィルム基材側から順に、酸化スズの含有割合が1重量%以上6重量%未満の酸化インジウムスズ層からなる第一の透明導電膜と;酸化スズ含有割合が6重量%以上20重量%以下の酸化インジウムスズ層からなる第二の透明導電膜と;を有する積層膜であり、
前記第一の透明導電膜の膜厚dと第二の透明導電膜の膜厚dとが、以下の(1)〜(3)の関係を満たし:
(1)d=1〜9nm;
(2)d+d=15〜37nm;
(3)2d<d
前記透明導電膜の結晶化後の抵抗率が、3.7×10−4Ω・cm以下である、透明導電積層フィルム。
A transparent conductive laminated film comprising, in this order, at least one transparent dielectric layer on at least one surface of the transparent film substrate, and a transparent conductive film provided in contact with the transparent dielectric layer,
The transparent dielectric layer in contact with the transparent conductive film is a silicon oxide layer;
The transparent conductive film includes, in order from the transparent film substrate side, a first transparent conductive film composed of an indium tin oxide layer having a tin oxide content of 1 wt% or more and less than 6 wt%; and a tin oxide content of 6 A laminated film comprising: a second transparent conductive film comprising an indium tin oxide layer having a weight percent of 20% by weight or less;
And the thickness d 1 of the first transparent conductive film and the film thickness d 2 of the second transparent conductive film satisfies a relation of the following (1) to (3):
(1) d 1 = 1 to 9 nm;
(2) d 1 + d 2 = 15 to 37 nm;
(3) 2d 1 <d 2
The transparent conductive laminated film whose resistivity after crystallization of the said transparent conductive film is 3.7 * 10 <-4> ohm * cm or less.
前記酸化珪素層の膜厚が2nm以上60nm以下である、請求項1に記載の透明導電積層フィルム。   The transparent conductive laminated film according to claim 1, wherein the silicon oxide layer has a thickness of 2 nm to 60 nm. 前記透明導電膜は、結晶化率が30%以下の非晶質膜であり、1μmあたり90個以上の結晶粒を有する、請求項1または2に記載の透明導電積層フィルム。The transparent conductive laminated film according to claim 1, wherein the transparent conductive film is an amorphous film having a crystallization rate of 30% or less, and has 90 or more crystal grains per 1 μm 2 . 前記透明導電膜は、結晶化率が30%以下の非晶質膜であり、150℃で加熱した場合に、2時間以内に抵抗率が3.7×10−4Ω・cm以下となる、請求項1〜3のいずれか1項に記載の透明導電積層フィルム。The transparent conductive film is an amorphous film having a crystallization rate of 30% or less, and when heated at 150 ° C., the resistivity becomes 3.7 × 10 −4 Ω · cm or less within 2 hours. The transparent conductive laminated film of any one of Claims 1-3. 前記第一の透明導電膜および前記第二の透明導電膜がいずれも結晶質である、請求項1または2に記載の透明導電積層フィルム。   The transparent conductive laminated film according to claim 1 or 2, wherein both the first transparent conductive film and the second transparent conductive film are crystalline. 透明フィルム基材の少なくとも一方の面に、少なくとも1層の透明誘電体層、および前記透明誘電体層に接して設けられた透明導電膜をこの順に備える透明導電積層フィルムを製造する方法であって、
透明フィルム基材上に、透明誘電体層が形成される透明誘電体層形成工程;および
前記透明誘電体層上に、酸化スズの含有割合が1重量%以上6重量%未満の酸化インジウムスズ層からなる第一の透明導電膜と、酸化スズの含有割合が6重量%以上20重量%以下の酸化インジウムスズ層からなる第二の透明導電膜とがこの順に形成される透明導電膜形成工程、を有し、
前記透明導電膜に接する前記透明誘電体層は、酸化珪素層であり、
前記透明導電膜形成工程において、前記酸化珪素層上に直接、前記第一の透明導電膜が1〜9nmの膜厚dで製膜され、その上に前記第二の透明導電膜が、dの2倍より大きい膜厚dで製膜され、
前記第一の透明導電膜の膜厚dと前記第二の透明導電膜の膜厚dの合計d+dが15〜37nmである、透明導電積層フィルムの製造方法。
A method of producing a transparent conductive laminated film comprising at least one transparent dielectric layer on at least one surface of a transparent film substrate and a transparent conductive film provided in contact with the transparent dielectric layer in this order. ,
A transparent dielectric layer forming step in which a transparent dielectric layer is formed on the transparent film substrate; and an indium tin oxide layer having a tin oxide content of 1 wt% to less than 6 wt% on the transparent dielectric layer; A transparent conductive film forming step in which a first transparent conductive film made of and a second transparent conductive film made of an indium tin oxide layer having a tin oxide content of 6 wt% or more and 20 wt% or less are formed in this order; Have
The transparent dielectric layer in contact with the transparent conductive film is a silicon oxide layer;
In the transparent conductive film forming step, the first transparent conductive film is directly formed on the silicon oxide layer with a film thickness d 1 of 1 to 9 nm, and the second transparent conductive film is is a film 1 of 2 times greater than the thickness d 2,
It said first sum d 1 + d 2 of the film thickness d 2 of the film thickness d 1 of the transparent conductive film second transparent conductive film is 15~37Nm, method for producing a transparent conductive laminated film.
前記透明誘電体層形成工程において、前記酸化珪素層がスパッタリング法により形成される、請求項6に記載の透明導電積層フィルムの製造方法。   The method for producing a transparent conductive laminated film according to claim 6, wherein in the transparent dielectric layer forming step, the silicon oxide layer is formed by a sputtering method. 前記透明導電膜形成工程において、前記第一の透明導電膜および前記第二の透明導電膜がいずれもスパッタリング法により形成される、請求項6または7に記載の透明導電積層フィルムの製造方法。   The method for producing a transparent conductive laminated film according to claim 6 or 7, wherein, in the transparent conductive film forming step, the first transparent conductive film and the second transparent conductive film are both formed by a sputtering method. 前記透明導電膜形成工程の後に、加熱処理により前記透明導電膜が結晶化される結晶化工程をさらに有する、請求項6〜8のいずれか1項に記載の透明導電積層フィルムの製造方法。   The manufacturing method of the transparent conductive laminated film of any one of Claims 6-8 which further has the crystallization process in which the said transparent conductive film is crystallized by heat processing after the said transparent conductive film formation process. 結晶化工程後における前記透明導電膜の抵抗率が、3.7×10−4Ω・cm以下である、請求項9に記載の透明導電積層フィルムの製造方法。The manufacturing method of the transparent conductive laminated film of Claim 9 whose resistivity of the said transparent conductive film after a crystallization process is 3.7 * 10 <-4> ohm * cm or less.
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