TW201503410A - Light-emitting device - Google Patents

Light-emitting device Download PDF

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Publication number
TW201503410A
TW201503410A TW103122964A TW103122964A TW201503410A TW 201503410 A TW201503410 A TW 201503410A TW 103122964 A TW103122964 A TW 103122964A TW 103122964 A TW103122964 A TW 103122964A TW 201503410 A TW201503410 A TW 201503410A
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TW
Taiwan
Prior art keywords
layer
light
top surface
emitting element
height difference
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TW103122964A
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Chinese (zh)
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TWI610462B (en
Inventor
De-Shan Kuo
Chun-Hsiang Tu
Po-Shun Chiu
Chun-Teng Ko
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Epistar Corp
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Priority claimed from US13/934,049 external-priority patent/US8928022B2/en
Application filed by Epistar Corp filed Critical Epistar Corp
Publication of TW201503410A publication Critical patent/TW201503410A/en
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Publication of TWI610462B publication Critical patent/TWI610462B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

A light-emitting device, comprises: a semiconductor contact layer comprising a rough top surface comprising any two adjacent first crests and a first trough, wherein the crests each comprises a first highest point respectively and the first trough comprises a first lowest point between the two first adjacent crests, and two first oblique lines are formed by connecting the first highest points and the first lowest point, and a first angle is formed between the two first oblique lines; and a transparent current spreading layer comprising a top surface on the semiconductor contact layer and comprising any two second adjacent crests and a second trough, wherein the two second adjacent crests each comprises a second highest point respectively and the second trough comprises a second lowest point between the two second adjacent crests, and two second oblique lines are formed by connecting the second highest points and the second lowest point, and a second angle is formed between the two second oblique lines; wherein the rough top surface of the semiconductor contact layer is substantially directly under the top surface of the transparent current spreading layer and a difference between the first angle and the second angle is not greater than 10 degrees.

Description

發光元件 Light-emitting element

本發明揭示一種發光元件,特別是關於一種光取出效率高的發光二極體元件。 The present invention discloses a light-emitting element, and more particularly to a light-emitting diode element having high light extraction efficiency.

發光二極體之應用頗為廣泛,例如,可應用於光學顯示裝置、交通號誌、資料儲存裝置、通訊裝置、照明裝置、以及醫療裝置。目前技術人員重要課題之一為提高發光二極體之亮度。 Light-emitting diodes are widely used, for example, in optical display devices, traffic signs, data storage devices, communication devices, lighting devices, and medical devices. One of the important topics of the current technicians is to increase the brightness of the light-emitting diode.

現有技術的發光二極體,其具有的半導體層因具有粗化表面,可提高光取出效率。然而,粗化表面會降低橫向電流的傳導以及擴散,因此提高起始電壓。 The light-emitting diode of the prior art has a semiconductor layer which has a roughened surface and can improve light extraction efficiency. However, roughening the surface reduces the conduction and diffusion of lateral currents, thus increasing the starting voltage.

本發明提供一發光元件,包含:一半導體接觸層,其包含一粗糙頂面,粗糙頂面包含兩相鄰的第一頂峰以及一第一波谷,各第一頂峰包含一第一最高點,第一波谷包含一位於兩相鄰的第一頂峰之間的第一最低點,兩個第一最高點與第一最低點連接形成兩條第一斜線,且一第一角度位於兩條第一斜線之間;以及一透明電流擴散層,其包含一位於半導體接觸層之上的頂面,且透明電流擴散層的頂面包含兩相鄰的第二頂峰以及一第二波谷,各第二頂峰包含一第二最高點,第二波谷包含一位於兩相鄰的第二頂峰之間的第二最低點,頂面的該兩個第二最高點與第二最低點連接形成兩條第二斜線,一第二角度位於兩條第二斜線之間;其中半導體接觸層的粗糙頂面大致位於透明電流擴散層的頂面的正下方,且第一角度與第二角度的差異不大於10度。 The present invention provides a light emitting device comprising: a semiconductor contact layer comprising a rough top surface, the rough top surface comprising two adjacent first peaks and a first trough, each first peak comprising a first highest point, A wave valley includes a first lowest point between two adjacent first peaks, two first highest points are connected to the first lowest point to form two first oblique lines, and a first angle is located at two first oblique lines And a transparent current diffusion layer comprising a top surface over the semiconductor contact layer, and the top surface of the transparent current diffusion layer includes two adjacent second peaks and a second valley, each second peak comprising a second highest point, the second trough comprising a second lowest point between two adjacent second peaks, the two second highest points of the top surface being joined to the second lowest point to form two second oblique lines, A second angle is between the two second oblique lines; wherein the rough top surface of the semiconductor contact layer is substantially directly below the top surface of the transparent current diffusion layer, and the first angle is different from the second angle by no more than 10 degrees.

底下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

10、300、40‧‧‧導電基板 10, 300, 40‧‧‧ conductive substrate

101、201‧‧‧第一表面 101, 201‧‧‧ first surface

102‧‧‧第二表面 102‧‧‧ second surface

20、1210、50‧‧‧基板 20, 1210, 50‧‧‧ substrates

12、22、32、42‧‧‧發光疊層 12, 22, 32, 42‧‧‧Lighting laminates

124、224、324、424、524、1220‧‧‧第一導電型半導體層 124, 224, 324, 424, 524, 1220‧‧‧ first conductive semiconductor layer

122、222、322、422、522、1230‧‧‧主動層 122, 222, 322, 422, 522, 1230‧‧ ‧ active layer

120、220、1240、320、420、520‧‧‧第二導電型半導體層 120, 220, 1240, 320, 420, 520‧‧‧ second conductive semiconductor layer

13‧‧‧第一平坦層 13‧‧‧First flat layer

1201、2201、2241‧‧‧上表面 1201, 2201, 2241‧‧‧ upper surface

131、231、331、431、534‧‧‧第二平坦層 131, 231, 331, 431, 534‧‧‧ second flat layer

291‧‧‧第四平坦層 291‧‧‧fourth flat layer

14、24‧‧‧第一透明導電氧化物層 14, 24‧‧‧ first transparent conductive oxide layer

141、241、281、341、441、541‧‧‧第一部分 First part of 141, 241, 281, 341, 441, 541‧‧

142、242、282、342、442、542‧‧‧第二部分 142, 242, 282, 342, 442, 542‧‧‧ second part

1421、2421、2821、3421、4421、5421‧‧‧第一多孔穴群 1421, 2421, 2821, 3421, 4421, 5421‧‧‧ first porous pocket group

1422、2422、2822、3422、4422、5422‧‧‧第二多孔穴群 1422, 2422, 2822, 3422, 4422, 5422‧‧‧ second porous pocket group

28、48、58‧‧‧第二透明導電氧化物層 28, 48, 58‧‧‧ second transparent conductive oxide layer

15、25、35、45、55‧‧‧第一電極 15, 25, 35, 45, 55‧‧‧ first electrode

16、26、36、46、56‧‧‧第二電極 16, 26, 36, 46, 56‧‧‧ second electrode

17、27‧‧‧第一金屬反射層 17, 27‧‧‧ first metal reflective layer

30‧‧‧第二金屬反射層 30‧‧‧Second metal reflective layer

38‧‧‧布拉格反射層 38‧‧‧ Prague reflection layer

41、51‧‧‧金屬鍵合層 41, 51‧‧‧ metal bonding layer

49、59‧‧‧反射層 49, 59‧‧‧reflective layer

151、251‧‧‧第一分支 151, ‧‧‧ first branch

1411、2411‧‧‧第二分支 1411, 2411‧‧‧ second branch

1412、2412‧‧‧第三分支 1412, 2412‧‧‧ third branch

1200‧‧‧發光元件 1200‧‧‧Lighting elements

1250‧‧‧發光結構 1250‧‧‧Lighting structure

1260‧‧‧半導體接觸層 1260‧‧‧Semiconductor contact layer

1270‧‧‧透明電流擴散層 1270‧‧‧Transparent current diffusion layer

1310‧‧‧粗糙頂面 1310‧‧‧Rough top

A1、A2‧‧‧第一最高點 A 1 , A 2 ‧ ‧ first highest point

B1‧‧‧第一最低點 B 1 ‧‧‧first lowest point

1320‧‧‧頂面 1320‧‧‧ top surface

A3、A4‧‧‧第二最高點 A 3 , A 4 ‧ ‧ second highest point

B2‧‧‧第二最低點 B 2 ‧‧‧ second lowest point

L2、L4‧‧‧第一斜線 L 2 , L 4 ‧‧‧ first slash

θ1‧‧‧第一角度 θ 1 ‧‧‧first angle

L1、L3‧‧‧第二斜線 L 1 , L 3 ‧‧‧ second diagonal

θ2‧‧‧第二角度 θ 2 ‧‧‧second angle

H1‧‧‧第一高度差 H 1 ‧‧‧First height difference

H2‧‧‧第二高度差 H 2 ‧‧‧second height difference

H3‧‧‧第三高度差 H 3 ‧‧‧third height difference

C1‧‧‧第一平整區域 C 1 ‧‧‧First leveling area

C2‧‧‧第二平整區域 C 2 ‧‧‧Second leveling area

800‧‧‧光電裝置 800‧‧‧Optoelectronic devices

900‧‧‧光電元件模組 900‧‧‧Photoelectric module

902‧‧‧次載體 902‧‧‧ times carrier

904、906、908、910、1122‧‧‧透鏡 904, 906, 908, 910, 1122‧‧ lens

912‧‧‧電源供應端子 912‧‧‧Power supply terminal

903‧‧‧頂部子單元 903‧‧‧Top subunit

901‧‧‧底部子單元 901‧‧‧ bottom subunit

915‧‧‧穿孔 915‧‧‧Perforation

921‧‧‧封裝材料 921‧‧‧Encapsulation materials

919‧‧‧反射層 919‧‧‧reflective layer

917‧‧‧金屬層 917‧‧‧metal layer

1000‧‧‧照明裝置 1000‧‧‧Lighting device

1040‧‧‧燈罩 1040‧‧‧shade

1100‧‧‧燈泡 1100‧‧‧ bulb

1121‧‧‧燈殼 1121‧‧‧ lamp housing

1124‧‧‧照明模組 1124‧‧‧Lighting module

1125‧‧‧燈座 1125‧‧‧ lamp holder

1126‧‧‧散熱槽 1126‧‧‧heat sink

1127‧‧‧連結部 1127‧‧‧Links

1128‧‧‧電連結器 1128‧‧‧Electrical connector

1123‧‧‧載體 1123‧‧‧ Carrier

第1A圖至第1F圖係顯示本發明第一實施例之一種發光元件之製造流程圖;第1G圖係顯示本發明第一實施例之第二導電型半導體層之上視示意圖;第1H圖係顯示本發明第一實施例中之發光元件表面之氧化銦錫層之電子顯微鏡圖;第2A-2D圖係顯示本發明中第二實施例中之水平式發光元件實施例之剖面示意圖;第3圖係顯示本發明第三實施例中發光元件之剖面示意圖;第4圖係顯示本發明第四實施例中發光元件之剖面示意圖;第5圖係顯示本發明第五實施例中發光元件之剖面示意圖;第6A-6B圖係顯示本發明第一實施例之第二導電型半導體層之上視示意圖;第7A-7B圖係顯示本發明第二實施例之第二導電型半導體層之上視示意圖;第8A圖係顯示本發明其中一實施例之發光元件之剖面示意圖;第8B圖係顯示本發明其中一實施例之發光元件之部分區域的剖面放大示意圖;第8C圖係顯示本發明其中一實施例之發光元件之部分區域的剖面放大示意圖;第9A圖係顯示本發明之發光元件應用於發光二極體模組之外觀示意圖;第9B圖係顯示本發明之光電元件模組之剖面示意圖;第9C圖係第9B圖中E區之剖面放大示意圖;第10A至10B圖係顯示本發明之其中一實施例之照明裝置之示意圖;以及第11圖係本發明發光元件應用於燈泡之分解圖。 1A to 1F are views showing a manufacturing process of a light-emitting element according to a first embodiment of the present invention; and FIG. 1G is a top view showing a second conductive type semiconductor layer according to the first embodiment of the present invention; An electron micrograph showing an indium tin oxide layer on the surface of the light-emitting element in the first embodiment of the present invention; and a second A-2D view showing a schematic cross-sectional view of the horizontal light-emitting element in the second embodiment of the present invention; 3 is a schematic cross-sectional view showing a light-emitting element in a third embodiment of the present invention; FIG. 4 is a cross-sectional view showing a light-emitting element in a fourth embodiment of the present invention; and FIG. 5 is a view showing a light-emitting element in a fifth embodiment of the present invention. FIG. 6A-6B is a top view showing the second conductive semiconductor layer of the first embodiment of the present invention; and FIGS. 7A-7B are diagrams showing the second conductive semiconductor layer of the second embodiment of the present invention. Figure 8A is a schematic cross-sectional view showing a light-emitting element of one embodiment of the present invention; and Figure 8B is a cross-sectional enlarged view showing a portion of a light-emitting element of one embodiment of the present invention; Figure C is a cross-sectional enlarged view showing a portion of a light-emitting element of one embodiment of the present invention; Figure 9A is a schematic view showing the appearance of a light-emitting element of the present invention applied to a light-emitting diode module; and Figure 9B is a view showing the present invention. FIG. 9C is a cross-sectional enlarged view of the E region in FIG. 9B; FIG. 10A to FIG. 10B are schematic views showing a lighting device according to an embodiment of the present invention; and FIG. 11 is a schematic view The inventive light-emitting element is applied to an exploded view of a bulb.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。在圖式或說明中,相似或相同之部份係使用相同之標號,並且在圖式中,元件之形狀或厚度可擴大或縮小。需特別注意的是,圖中未繪示或描述之元件,可以是熟習此技藝之人士所知之形式。 The above described features and advantages of the invention will be apparent from the following description. In the drawings or the description, the same or similar parts are given the same reference numerals, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the figures may be in a form known to those skilled in the art.

為了使本發明之敘述更加詳盡與完備,請參照下列描述並配合第1圖至第7圖之圖示。第1A圖至第1F圖係顯示本發明第一實施例之發光元件之製造流程圖:第1A圖顯示一發光元件包含一具有一第一表面101以及一第二表面102的導電基板10、一發光疊層12形成於導電基板10之上,且發光疊層12包含一第一導電型半導體層124、一主動層122及一第二導電型半導體層120,依序形成於導電基板10之第一表面101之上。其中第二導電型半導體層120之上表面1201為一粗化表面且包含一第一多孔穴群1421,形成的方式可包含磊晶、蝕刻或兩者混合之方式為之。在本實施例中,發光疊層12之材料包含鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)、矽(Si)或上述元素之組合。常用之材料例如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列等。主動層122之結構可為單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井(multi-quantum well;MQW)。再者,調整量子井之對數亦可以改變發光波長。 In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the diagrams of FIGS. 1 to 7. 1A to 1F are views showing a manufacturing process of a light-emitting element according to a first embodiment of the present invention: FIG. 1A shows a light-emitting element including a conductive substrate 10 having a first surface 101 and a second surface 102, The light emitting layer 12 is formed on the conductive substrate 10, and the light emitting layer 12 includes a first conductive semiconductor layer 124, an active layer 122 and a second conductive semiconductor layer 120, which are sequentially formed on the conductive substrate 10. Above a surface 101. The upper surface 1201 of the second conductive semiconductor layer 120 is a roughened surface and includes a first porous pocket group 1421, which may be formed by epitaxy, etching or a mixture of the two. In this embodiment, the material of the light-emitting layer 12 comprises gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), cerium (Si) or the above elements. The combination. Commonly used materials such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series and the like. The structure of the active layer 122 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum multi-quantum. Well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

如第1B圖所示,一第一平坦層13形成在第二導電型半導體層120之上表面1201上,覆蓋並填滿為粗化表面之上表面1201。此第一平坦層13可以旋轉塗佈(Spin Coating)方式形成。在一實施例中,第一平坦層13採用旋轉塗佈玻璃(SOG,spin on glass coating)之方式形成。在一實施例中,旋轉塗佈玻璃材料可為懸浮在溶液中的氧化矽(SiO2)和摻雜物混合之介電材料,其中摻雜物可為硼或磷。旋轉塗佈玻璃材料亦可為BCB(benzocyclobutene)、HSQ(hydrogen silsesquioxane)和MSQ(methylsequioxane)等聚合物(polymer)。 As shown in FIG. 1B, a first planarization layer 13 is formed on the upper surface 1201 of the second conductive semiconductor layer 120, covering and filling the roughened surface upper surface 1201. This first flat layer 13 can be formed by spin coating. In one embodiment, the first planar layer 13 is formed by spin-on glass coating (SOG). In one embodiment, the spin-on glass material can be a cerium oxide (SiO 2 ) suspended in solution and a dopant mixed dielectric material, wherein the dopant can be boron or phosphorus. The spin-coated glass material may also be a polymer such as BCB (benzocyclobutene), HSQ (hydrogen silsesquioxane), and MSQ (methylsequioxane).

如第1C圖所示,將上述第一平坦層13圖形化及硬化後,以蝕刻及曝光微影製程形成一第二平坦層131,以暴露出第二導電型半導體 層120之部分的上表面1201,即部分的上表面1201並未被第二平坦層131覆蓋。第二平坦層131之位置並不限定,可形成於第二導電型半導體層120的上表面1201之中間或邊緣。 As shown in FIG. 1C, after the first flat layer 13 is patterned and cured, a second flat layer 131 is formed by etching and exposure lithography to expose the second conductive semiconductor. The upper surface 1201 of the portion of the layer 120, that is, the portion of the upper surface 1201 is not covered by the second planar layer 131. The position of the second flat layer 131 is not limited and may be formed in the middle or the edge of the upper surface 1201 of the second conductive type semiconductor layer 120.

如第1D圖所示,一第一透明導電氧化物層14形成並覆蓋整個第二平坦層131及第二導電型半導體層120之部分的上表面1201。第一透明導電氧化物層14包含第一部分141與第二部分142,其中第一部分141大致為平坦且與整個第二平坦層131接觸,第二部分142形成於第二導電型半導體層120的上表面1201之上且包含一第二多孔穴群1422,第二導電型半導體層120之第一多孔穴群1421接觸第一透明導電氧化物層14,第二多孔穴群1422形成在第二部分142之上表面之上且與第一多孔穴群1421相對。第一多孔穴群1421之形狀可為圓錐形或多角錐形(如第1G-1H圖所示之形狀)。第一多孔穴群1421可於第二導電型半導體層120之部分的上表面1201以例如磊晶、蝕刻或兩者混合之方式形成。第二多孔穴群1422中各孔穴之形狀可以蝕刻方式形成為圓錐形或多角錐形並朝向第一多孔穴群1421之方向延伸,較佳的,延伸方向與導電基板10之第一表面101大致垂直。 As shown in FIG. 1D, a first transparent conductive oxide layer 14 is formed and covers the entire upper surface 1201 of portions of the second planarization layer 131 and the second conductive semiconductor layer 120. The first transparent conductive oxide layer 14 includes a first portion 141 and a second portion 142, wherein the first portion 141 is substantially flat and is in contact with the entire second planar layer 131, and the second portion 142 is formed on the second conductive semiconductor layer 120. Above the surface 1201 and including a second porous pocket group 1422, the first porous pocket group 1421 of the second conductive semiconductor layer 120 contacts the first transparent conductive oxide layer 14, and the second porous pocket group 1422 is formed in the first The upper surface of the two portions 142 is above and opposite the first porous pocket group 1421. The shape of the first porous pocket group 1421 may be conical or polygonal (as shown in the shape of the first G-1H). The first porous pocket group 1421 may be formed on the upper surface 1201 of a portion of the second conductive type semiconductor layer 120 by, for example, epitaxy, etching, or a mixture of both. The shape of each of the holes in the second porous pocket group 1422 can be formed into a conical or polygonal shape in an etching manner and extending toward the first porous pocket group 1421. Preferably, the extending direction is opposite to the first surface of the conductive substrate 10. 101 is roughly vertical.

如第1E圖所示,一第一電極15形成在第一透明導電氧化物層14之第一部分141之上;一第二電極16形成在導電基板10的第二表面102之上。上述第一電極15與第二電極16之材料可包含鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、或銀(Ag)等金屬材料或其等之合金。 As shown in FIG. 1E, a first electrode 15 is formed over the first portion 141 of the first transparent conductive oxide layer 14; a second electrode 16 is formed over the second surface 102 of the conductive substrate 10. The material of the first electrode 15 and the second electrode 16 may include chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or A metal material such as silver (Ag) or an alloy thereof.

如第1F圖所示,於本發明之另一實施例中,一第一金屬反射層17可形成在第一透明導電氧化物層14之第一部分141與第一電極15之間以增進發光效率。 As shown in FIG. 1F, in another embodiment of the present invention, a first metal reflective layer 17 may be formed between the first portion 141 of the first transparent conductive oxide layer 14 and the first electrode 15 to improve luminous efficiency. .

如本發明之第一實施例所示,藉由形成第二平坦層131在第二導電型半導體層120之部分的上表面1201之上,可使第一透明導電氧化物層14、第一電極15及第一金屬反射層17形成在大致平坦的表面上,進而減少發光元件的阻抗及正向電壓且增加電流側向傳導、電流分散能力及出光效率。 As shown in the first embodiment of the present invention, the first transparent conductive oxide layer 14 and the first electrode can be formed by forming the second planar layer 131 over the upper surface 1201 of the portion of the second conductive semiconductor layer 120. 15 and the first metal reflective layer 17 are formed on a substantially flat surface, thereby reducing the impedance and forward voltage of the light-emitting element and increasing current lateral conduction, current dispersion capability, and light extraction efficiency.

此外,由於第一多孔穴群1421自第二導電型半導體層120 之上表面1201向下延伸,使第一透明氧化物層14可依上表面1201之輪廓形成在第二導電型半導體層120之上,使第一透明氧化物層14之第二部分142的上表面形成第二多孔穴群1422。而由於第一多孔穴群1421,可增加第一金屬反射層17及第一透明氧化物層14之間的黏接強度。根據本發明第一實施例之發光元件及第一透明氧化物層表面不具孔穴結構之習知發光元件所進行的剝離測試(peeling test)之結果顯示,所有依本發明第一實施例形成之發光元件可通過測試,但80%之習知發光元件無法通過測試。由上述結果可得知,藉由第一透明氧化物層同時包含大致為平坦的第一部分以及包含多孔穴群的第二部分之設計,可改善出光效率低與剝離問題。 In addition, since the first porous pocket group 1421 is from the second conductive type semiconductor layer 120 The upper surface 1201 extends downwardly such that the first transparent oxide layer 14 can be formed over the second conductive semiconductor layer 120 in accordance with the contour of the upper surface 1201 such that the second portion 142 of the first transparent oxide layer 14 is over. The surface forms a second porous pocket group 1422. Due to the first porous pocket group 1421, the bonding strength between the first metal reflective layer 17 and the first transparent oxide layer 14 can be increased. The result of the peeling test performed by the light-emitting element according to the first embodiment of the present invention and the conventional light-emitting element having no hole structure on the surface of the first transparent oxide layer shows that all the light rays formed according to the first embodiment of the present invention Components can pass the test, but 80% of the conventional light-emitting components cannot pass the test. From the above results, it can be seen that the low light extraction efficiency and the peeling problem can be improved by the design that the first transparent oxide layer simultaneously includes the substantially flat first portion and the second portion including the porous pocket group.

第2A-2D圖係顯示本發明第二實施例中之水平式發光元件之剖面示意圖。第2A圖顯示一發光元件包含一基板20、一發光疊層22包含一第一導電型半導體層224、一主動層222及一第二導電型半導體層220依序形成於基板20之第一表面201之上。其中第二導電型半導體層220之上表面2201為一粗化表面且包含一第一多孔穴群2421,形成的方式可包含磊晶、蝕刻或兩者混合之方式為之。接著,蝕刻發光疊層22,並暴露出部分的第一導電型半導體層224以形成一水平式發光元件。 2A-2D is a schematic cross-sectional view showing a horizontal type light-emitting element in a second embodiment of the present invention. 2A shows a light-emitting device comprising a substrate 20, a light-emitting layer 22 comprising a first conductive semiconductor layer 224, an active layer 222 and a second conductive semiconductor layer 220 sequentially formed on the first surface of the substrate 20. Above 201. The upper surface 2201 of the second conductive semiconductor layer 220 is a roughened surface and includes a first porous pocket group 2421, which may be formed by epitaxy, etching or a mixture of the two. Next, the light emitting laminate 22 is etched, and a portion of the first conductive type semiconductor layer 224 is exposed to form a horizontal light emitting element.

在本實施例中,發光疊層22之材料包含鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)、矽(Si)或上述元素之組合。常用之材料例如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列等。主動層222之結構可為單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井結構(multi-quantum well;MQW)。再者,調整量子井之對數亦可以改變發光波長。 In this embodiment, the material of the light-emitting layer 22 comprises gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), antimony (Si) or the above elements. The combination. Commonly used materials such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series and the like. The structure of the active layer 222 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well structure (multi- Quantum well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

接著,以類似本發明第一實施例的製程,形成一第一平坦層(圖未示)在第二導電型半導體層220之上表面2201上,並覆蓋且填滿粗化表面之上表面2201。此第一平坦層可以旋轉塗佈(Spin Coating)方式形成。在一實施例中,第一平坦層採用旋轉塗佈玻璃(SOG,spin on glass coating)之方式形成。在一實施例中,旋轉塗佈玻璃材料可為懸浮在溶液中的氧化矽(SiO2)和摻雜物混合之介電材料,其中摻雜物可為硼或磷。旋轉塗佈玻璃材料亦可為BCB(benzocyclobutene)、HSQ(hydrogen silsesquioxane)和 MSQ(methylsequioxane)等聚合物(polymer)。 Next, in a process similar to the first embodiment of the present invention, a first planar layer (not shown) is formed on the upper surface 2201 of the second conductive semiconductor layer 220, and covers and fills the surface 2201 of the roughened surface. . This first flat layer can be formed by spin coating. In one embodiment, the first planar layer is formed by spin on glass coating (SOG). In one embodiment, the spin-on glass material can be a cerium oxide (SiO 2 ) suspended in solution and a dopant mixed dielectric material, wherein the dopant can be boron or phosphorus. The spin-coated glass material may also be a polymer such as BCB (benzocyclobutene), HSQ (hydrogen silsesquioxane), and MSQ (methylsequioxane).

接著,將上述第一平坦層(圖未示)圖形化及硬化後,以蝕刻及曝光微影製程形成一第二平坦層231,以暴露出第二導電型半導體層220之部分的上表面2201,即部分的上表面2201並未被第二平坦層231覆蓋。第二平坦層231之位置並不限定,可形成於第二導電型半導體層220的上表面2201之中間或邊緣。 Next, after patterning and hardening the first planar layer (not shown), forming a second planar layer 231 by etching and exposing the lithography process to expose the upper surface 2201 of the portion of the second conductive semiconductor layer 220 That is, the portion of the upper surface 2201 is not covered by the second flat layer 231. The position of the second flat layer 231 is not limited and may be formed in the middle or the edge of the upper surface 2201 of the second conductive type semiconductor layer 220.

接著,一第一透明導電氧化物層24形成並覆蓋整個第二平坦層231及第二導電型半導體層220之部分的上表面2201。第一透明導電氧化物層24包含第一部分241與第二部分242,其中第一部分241大致為平坦且與整個第二平坦層231接觸,第二部分242形成於第二導電型半導體層220上表面2201之上且包含一第二多孔穴群2422,第二導電型半導體層220之第一多孔穴群2421接觸第一透明導電氧化物層24,第二多孔穴群2422形成在第二部分242之上表面之上且與第一多孔穴群2421相對。第一多孔穴群2421中各孔穴之形狀可為圓錐形或多角錐形。第一多孔穴群1421可於第二導電型半導體層220之部分的上表面2201以例如磊晶、蝕刻或兩者混合之方式形成。第二多孔穴群2422中各孔穴之形狀可以蝕刻方式形成為圓錐形或多角錐形並朝向第一多孔穴群2421之方向延伸,較佳的,延伸方向與導電基板20之第一表面201大致垂直。 Next, a first transparent conductive oxide layer 24 is formed and covers the entire upper surface 2201 of the portions of the second planarization layer 231 and the second conductive semiconductor layer 220. The first transparent conductive oxide layer 24 includes a first portion 241 and a second portion 242, wherein the first portion 241 is substantially flat and is in contact with the entire second planar layer 231, and the second portion 242 is formed on the upper surface of the second conductive semiconductor layer 220. Above the 2201 and including a second porous pocket group 2422, the first porous pocket group 2421 of the second conductive semiconductor layer 220 contacts the first transparent conductive oxide layer 24, and the second porous pocket group 2422 is formed in the second The upper portion of the portion 242 is above and opposite the first porous pocket group 2421. The shape of each of the holes in the first porous pocket group 2421 may be conical or polygonal. The first porous pocket group 1421 may be formed on the upper surface 2201 of a portion of the second conductive type semiconductor layer 220 by, for example, epitaxy, etching, or a mixture of both. The shape of each of the holes in the second porous pocket group 2422 can be formed into a conical or polygonal shape in an etching manner and extending toward the first porous pocket group 2421. Preferably, the extending direction is opposite to the first surface of the conductive substrate 20. 201 is substantially vertical.

最後,一第一電極25形成在第一透明導電氧化物層24之第一部分241之上;一第二電極26形成在暴露出的第一導電型半導體層224之上。上述第一電極25與第二電極26之材料可包含鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、或銀(Ag)等金屬材料或其等之合金。藉由第一透明氧化物層同時包含大致為平坦的第一部分以及包含多孔穴群的第二部分之設計,可改善出光效率低的問題。 Finally, a first electrode 25 is formed over the first portion 241 of the first transparent conductive oxide layer 24; a second electrode 26 is formed over the exposed first conductive semiconductor layer 224. The material of the first electrode 25 and the second electrode 26 may include chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or A metal material such as silver (Ag) or an alloy thereof. By the design of the first transparent oxide layer containing both the substantially flat first portion and the second portion including the porous pocket group, the problem of low light extraction efficiency can be improved.

如第2B圖所示,於本發明之另一實施例中,一第一金屬反射層27可形成在第一透明導電氧化物層24之第一部分與第一電極25之間以增進發光效率。 As shown in FIG. 2B, in another embodiment of the present invention, a first metal reflective layer 27 may be formed between the first portion of the first transparent conductive oxide layer 24 and the first electrode 25 to enhance luminous efficiency.

此外,由於第一多孔穴群2421自第二導電型半導體層220之上表面2201向下延伸使第一透明氧化物層24的第二部分242之上表面可依上表面2201之輪廓形成在第二導電型半導體層220之上,故第二部分242 相對第二導電型半導體層220之上表面2201的上表面包含第二多孔穴群2422。藉由第一多孔穴群2421,可增加第一金屬反射層27及第一透明氧化物層24之間的黏接強度。根據本發明第二實施例之發光元件及第一透明氧化物層表面不具孔穴結構之習知發光元件所進行的剝離測試(peeling test)之結果顯示,所有依本發明第二實施例之發光元件可通過測試,但80%之習知發光元件無法通過測試。由上述結果可得知,藉由第一透明氧化物層同時包含大致為平坦的第一部分以及包含多孔穴群的第二部分之設計,可改善低效率與剝離之問題。 In addition, since the first porous pocket group 2421 extends downward from the upper surface 2201 of the second conductive type semiconductor layer 220, the upper surface of the second portion 242 of the first transparent oxide layer 24 may be formed according to the contour of the upper surface 2201. Above the second conductive semiconductor layer 220, the second portion 242 The upper surface of the upper surface 2201 of the second conductive semiconductor layer 220 includes a second porous pocket group 2422. By the first porous pocket group 2421, the bonding strength between the first metal reflective layer 27 and the first transparent oxide layer 24 can be increased. The result of the peeling test performed by the light-emitting element according to the second embodiment of the present invention and the conventional light-emitting element having no hole structure on the surface of the first transparent oxide layer shows that all of the light-emitting elements according to the second embodiment of the present invention Can pass the test, but 80% of the known light-emitting components can not pass the test. From the above results, it is understood that the problem of low efficiency and peeling can be improved by the design that the first transparent oxide layer simultaneously includes the substantially flat first portion and the second portion including the porous pocket group.

如第2C圖顯示本發明之另一實施例,第2C圖之實施例與第2A圖之差異在於第一導電型半導體層224之表面經蝕刻為一粗化的上表面2241且包含一第一多孔穴群2821。接著,以類似本發明第一實施例的製程,一第三平坦層(圖未示)形成在第一導電型半導體層224之上表面2241上,並覆蓋且填滿上述之為粗化表面的上表面2241。此第三平坦層可以旋轉塗佈(Spin Coating)方式形成。在一實施例中,第三平坦層採用旋轉塗佈玻璃(SOG,spin on glass coating)之方式形成,材料可為BCB(Benzocyclobutene)等。接著,將上述第三平坦層圖形化及硬化後並以蝕刻及曝光微影製程形成一第四平坦層291,以暴露出部分的第一導電型半導體層224之上表面2241。第四平坦層291之位置並不被限定,可形成於第一導電型半導體層224上表面2241之中間或邊緣。 Another embodiment of the present invention is shown in FIG. 2C. The difference between the embodiment of FIG. 2C and FIG. 2A is that the surface of the first conductive semiconductor layer 224 is etched into a roughened upper surface 2241 and includes a first Porous cavity group 2821. Next, in a process similar to the first embodiment of the present invention, a third planar layer (not shown) is formed on the upper surface 2241 of the first conductive type semiconductor layer 224, and covers and fills the above-mentioned roughened surface. Upper surface 2241. This third flat layer can be formed by spin coating. In one embodiment, the third flat layer is formed by spin-on glass coating (SOG), and the material may be BCB (Benzocyclobutene) or the like. Next, the third flat layer is patterned and hardened, and a fourth flat layer 291 is formed by etching and exposure lithography to expose a portion of the upper surface 1241 of the first conductive semiconductor layer 224. The position of the fourth flat layer 291 is not limited and may be formed in the middle or the edge of the upper surface 2241 of the first conductive type semiconductor layer 224.

接著,一第二透明導電氧化物層28形成並覆蓋整個第四平坦層291及第一導電型半導體層224之部分的上表面2241。第二透明導電氧化物層28包含第一部分281與第二部分282,其中第一部分281大致為平坦且與整個第四平坦層291接觸,第二部分282形成於第一導電型半導體層224上表面2241之上且包含一第二多孔穴群2822,第一導電型半導體層224之第一多孔穴群2821接觸第二透明導電氧化物層28,第二多孔穴群2822形成在第二部分282之上表面之上且與第一多孔穴群2821相對。第一多孔穴群2821中各孔穴之形狀可為圓錐形或多角錐形。第一多孔穴群2821可於第一導電型半導體層224之部分的上表面2241以例如磊晶、蝕刻或兩者方式混和而形成。第二多孔穴群2822中各孔穴之形狀可以蝕刻方式形成為圓錐形或多角錐形並朝向第一多孔穴群2821之方向延伸,較佳的,延伸方向 與基板20之第一表面201大致垂直。 Next, a second transparent conductive oxide layer 28 is formed and covers the entire upper surface 2241 of the fourth planarization layer 291 and a portion of the first conductive semiconductor layer 224. The second transparent conductive oxide layer 28 includes a first portion 281 and a second portion 282, wherein the first portion 281 is substantially flat and is in contact with the entire fourth planar layer 291, and the second portion 282 is formed on the upper surface of the first conductive semiconductor layer 224. Above the 2241 and comprising a second porous pocket group 2822, the first porous pocket group 2821 of the first conductive semiconductor layer 224 contacts the second transparent conductive oxide layer 28, and the second porous pocket group 2822 is formed in the second The upper portion of the portion 282 is above and opposite the first porous pocket group 2821. The shape of each of the holes in the first porous pocket group 2821 may be conical or polygonal. The first porous pocket group 2821 may be formed by, for example, epitaxy, etching, or both, on the upper surface 2241 of a portion of the first conductive type semiconductor layer 224. The shape of each of the holes in the second porous pocket group 2822 can be formed into a conical shape or a polygonal pyramid shape in an etching manner and extending toward the first porous pocket group 2821. Preferably, the extending direction It is substantially perpendicular to the first surface 201 of the substrate 20.

最後,一第一電極25形成在第一透明導電氧化物層24之第一部分241之上;一第二電極26形成在第二透明導電氧化物層28之第一部分281之上。上述第一電極25與第二電極26之材料可包含鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、或銀(Ag)等金屬材料或其等之合金。藉由第二透明氧化物層同時包含大致為平坦的第一部分以及包含多孔穴群的第二部分之設計,可改善出光效率低的問題。 Finally, a first electrode 25 is formed over the first portion 241 of the first transparent conductive oxide layer 24; a second electrode 26 is formed over the first portion 281 of the second transparent conductive oxide layer 28. The material of the first electrode 25 and the second electrode 26 may include chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or A metal material such as silver (Ag) or an alloy thereof. The problem of low light extraction efficiency can be improved by the design of the second transparent oxide layer containing both the substantially flat first portion and the second portion including the porous pocket group.

如第2D圖所示,本發明之另一實施例中,除了第一金屬反射層3027可形成在第一透明導電氧化物層24之第一部分241與第一電極25之間,發光元件更包含一第二金屬反射層30形成在第二透明導電氧化物層28之第一部分281與第二電極26之間,以更增進發光效率。 As shown in FIG. 2D, in another embodiment of the present invention, in addition to the first metal reflective layer 3027 being formed between the first portion 241 of the first transparent conductive oxide layer 24 and the first electrode 25, the light emitting element further includes A second metal reflective layer 30 is formed between the first portion 281 of the second transparent conductive oxide layer 28 and the second electrode 26 to further enhance luminous efficiency.

第3圖係顯示本發明第三實施例之發光元件之剖面示意圖,第三實施例中與第一實施例的差異在於一布拉格反射(Distributed Bragg Reflector,DBR)層38形成於導電基板30與第一導電型半導體層324之間。 3 is a schematic cross-sectional view showing a light-emitting element according to a third embodiment of the present invention. The third embodiment differs from the first embodiment in that a Bragg Reflector (DBR) layer 38 is formed on the conductive substrate 30 and Between a conductive semiconductor layer 324.

第4圖係顯示本發明第四實施例之發光元件之剖面示意圖,第四實施例與第一實施例的差異在於一金屬鍵合層41、一反射層49以及一第二透明導電氧化層48係形成於導電基板40與第一導電型半導體層424之間。 4 is a cross-sectional view showing a light-emitting element according to a fourth embodiment of the present invention. The fourth embodiment differs from the first embodiment in a metal bonding layer 41, a reflective layer 49, and a second transparent conductive oxide layer 48. It is formed between the conductive substrate 40 and the first conductive type semiconductor layer 424.

第5圖係顯示本發明第五實施例之發光元件之剖面示意圖,第五實施例與第一實施例的差異在於一金屬鍵合層51、一反射層59以及一第二透明導電氧化層58係形成於基板50與第一導電型半導體層524之間,且第二電極56係形成於第二透明導電氧化層58之上。 5 is a schematic cross-sectional view showing a light-emitting element according to a fifth embodiment of the present invention. The fifth embodiment differs from the first embodiment in a metal bonding layer 51, a reflective layer 59, and a second transparent conductive oxide layer 58. The second electrode 56 is formed on the second transparent conductive oxide layer 58 between the substrate 50 and the first conductive semiconductor layer 524.

第6A-6B圖係顯示本發明第一實施例之第二導電型半導體層之上視示意圖;第6A圖係顯示第二導電型半導體層120之上視圖,如前所述,第二平坦層(未繪示)係形成在第二導電型半導體層之部分的上表面1201之上。形成第二平坦層之後,第一透明導電氧化物層14形成在部分的第二平坦層之上且包含第一部分141以及第二部分142,第一部分141係大致平坦並接觸整個第二平坦層,第二部分142形成在第二導電型半導體層120之上且包含粗化表面。第一電極15係形成在第一透明導電氧化物層14之第一部分141上。於本實施例中,部分的第一透明導電氧化物層14並 未被第一電極15覆蓋,且第一電極15可如指狀向發光元件的邊緣延伸以分散電流。 6A-6B are top views showing the second conductive semiconductor layer of the first embodiment of the present invention; and FIG. 6A is a top view showing the second conductive semiconductor layer 120, as described above, the second flat layer (not shown) is formed over the upper surface 1201 of a portion of the second conductive type semiconductor layer. After forming the second planarization layer, the first transparent conductive oxide layer 14 is formed over a portion of the second planar layer and includes a first portion 141 and a second portion 142, the first portion 141 being substantially flat and contacting the entire second planar layer, The second portion 142 is formed over the second conductive type semiconductor layer 120 and includes a roughened surface. The first electrode 15 is formed on the first portion 141 of the first transparent conductive oxide layer 14. In this embodiment, a portion of the first transparent conductive oxide layer 14 is The first electrode 15 is not covered by the first electrode 15, and the first electrode 15 may extend toward the edge of the light emitting element as a finger to disperse current.

具體的,如第6B圖所示,於另一實施例中,第一電極15包含一具有手指狀(finger-like)圖案且向發光元件的邊緣延伸的第一分支151,以達到更佳的電流分散效果。第一透明導電氧化物層14可進一步包含一第二分支1411以及一第三分支1412,第二分支1411具有手指狀(finger-like)圖案且向發光元件的邊緣延伸,第三分支1412為透明且如指狀,並自第二分支1411之側邊向發光元件的邊緣延伸,以進一步增進電流分散效率。在本實施例中,第一透明導電氧化物層14之部分的第二分支1411以及第三分支1412並未被第一電極15的第一分支151覆蓋。因為第一透明導電氧化物層14之第二分支1411與第三分支1412係形成於第二平坦層(圖未示)之上,因此第二分支1411與第三分支1412包含一大致平坦之表面,進而具有更好的電流分散效果。 Specifically, as shown in FIG. 6B, in another embodiment, the first electrode 15 includes a first branch 151 having a finger-like pattern and extending toward an edge of the light emitting element to achieve better. Current dispersion effect. The first transparent conductive oxide layer 14 may further include a second branch 1411 and a third branch 1412. The second branch 1411 has a finger-like pattern and extends toward the edge of the light emitting element, and the third branch 1412 is transparent. And as a finger, and extending from the side of the second branch 1411 toward the edge of the light-emitting element to further enhance the current dispersion efficiency. In the present embodiment, the second branch 1411 and the third branch 1412 of the portion of the first transparent conductive oxide layer 14 are not covered by the first branch 151 of the first electrode 15. Because the second branch 1411 and the third branch 1412 of the first transparent conductive oxide layer 14 are formed on the second flat layer (not shown), the second branch 1411 and the third branch 1412 comprise a substantially flat surface. , in turn, has a better current dispersion effect.

第7A-7B圖係顯示本發明第二實施例之第二導電型半導體層之上視示意圖;第7A圖係顯示第二導電型半導體層之上視圖。如前所述,第二平坦層(圖未示)可形成在第二導電型半導體層之部分的上表面2201之上。形成第二平坦層之後,第一透明導電氧化物層24形成在部分的第二平坦層之上且包含第一部分241以及第二部分242,第一部分241係大致平坦並接觸整個第二平坦層,第二部分242形成在第二導電型半導體層220之上且包含粗化表面。接著,第一電極25係形成在第一透明導電氧化物層24之第一部分241上。於本實施例中,部分的第一透明導電氧化物層24並未被第一電極25覆蓋,且第一電極25可如指狀向發光元件的邊緣延伸以分散電流。 7A-7B are top views showing the second conductive type semiconductor layer of the second embodiment of the present invention; and Fig. 7A is a top view showing the second conductive type semiconductor layer. As described above, a second flat layer (not shown) may be formed over the upper surface 2201 of a portion of the second conductive type semiconductor layer. After forming the second planarization layer, the first transparent conductive oxide layer 24 is formed over a portion of the second planar layer and includes a first portion 241 and a second portion 242 that is substantially flat and contacts the entire second planar layer, The second portion 242 is formed over the second conductive type semiconductor layer 220 and includes a roughened surface. Next, the first electrode 25 is formed on the first portion 241 of the first transparent conductive oxide layer 24. In the present embodiment, a portion of the first transparent conductive oxide layer 24 is not covered by the first electrode 25, and the first electrode 25 may extend toward the edge of the light emitting element as a finger to disperse current.

如第7B圖所示,於另一實施例中,第一電極25包含一向發光元件的邊緣延伸的第一分支251,以達到更佳的電流分散效果。第一透明導電氧化物層24可進一步包含一第二分支2411以及一第三分支2412,第二分支2411具有手指狀(finger-like)圖案且向發光元件的邊緣延伸,第三分支2412為透明且如指狀,並自第二分支2411之側邊向發光元件的邊緣延伸,以更增進電流分散效率。在本實施例中,第一透明導電氧化物層24之部分的第二分支2411以及第三分支2412並未被第一電極25的第一分支 251覆蓋。由於第一透明導電氧化物層24之第二分支2411與第三分支2412係形成於第二平坦層(圖未示)之上,因此第二分支2411與第三分支2412包含一大致平坦之表面,進而具有更好的電流分散效果。 As shown in FIG. 7B, in another embodiment, the first electrode 25 includes a first branch 251 extending toward the edge of the light-emitting element for better current dispersion. The first transparent conductive oxide layer 24 may further include a second branch 2411 and a third branch 2412. The second branch 2411 has a finger-like pattern and extends toward the edge of the light-emitting element, and the third branch 2412 is transparent. And as a finger, and extending from the side of the second branch 2411 toward the edge of the light-emitting element to further enhance the current dispersion efficiency. In the present embodiment, the second branch 2411 and the third branch 2412 of the portion of the first transparent conductive oxide layer 24 are not the first branch of the first electrode 25. 251 coverage. Since the second branch 2411 and the third branch 2412 of the first transparent conductive oxide layer 24 are formed on the second flat layer (not shown), the second branch 2411 and the third branch 2412 comprise a substantially flat surface. , in turn, has a better current dispersion effect.

第8A至8C圖為本發明其中一實施例之發光元件1200之剖面示意圖。第8A圖顯示之發光元件1200包含一基板1210;一發光結構1250形成於基板1210上;一位於發光結構1250之上的半導體接觸層1260,其包含一粗糙頂面;以及一透明電流擴散層1270,其包含一位於半導體接觸層1260之上的頂面。發光結構1250包含一第一導電型半導體層1220、一主動層1230及一第二導電型半導體層1240。半導體接觸層1260的粗糙頂面大致位於透明電流擴散層1270的頂面的正下方。基板1210是一成長基底或是承載基底。半導體接觸層1260之材料包含鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)、矽(Si)或上述元素之組合。透明電流擴散層1270之材料包含金屬氧化物或金屬氮化物。 8A to 8C are schematic cross-sectional views showing a light-emitting element 1200 according to an embodiment of the present invention. 8A shows a light-emitting element 1200 comprising a substrate 1210; a light-emitting structure 1250 formed on the substrate 1210; a semiconductor contact layer 1260 over the light-emitting structure 1250, comprising a rough top surface; and a transparent current diffusion layer 1270 It includes a top surface over the semiconductor contact layer 1260. The light emitting structure 1250 includes a first conductive semiconductor layer 1220, an active layer 1230, and a second conductive semiconductor layer 1240. The rough top surface of the semiconductor contact layer 1260 is located substantially directly below the top surface of the transparent current spreading layer 1270. The substrate 1210 is a growth substrate or a carrier substrate. The material of the semiconductor contact layer 1260 includes gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), cerium (Si), or a combination of the above. The material of the transparent current diffusion layer 1270 contains a metal oxide or a metal nitride.

第8B圖係顯示本發明其中一實施例之發光元件中部分區域的半導體接觸層1260以及透明電流擴散層1270之剖面放大示意圖。半導體接觸層1260之粗糙頂面1310包含兩相鄰的第一頂峰以及一第一波谷,各第一頂峰分別包含一第一最高點A1、A2,第一波谷包含一位於兩相鄰的第一頂峰之間的第一最低點B1。透明電流擴散層1270的頂面1320包含兩相鄰的第二頂峰以及一第二波谷,各第二頂峰分別包含一第二最高點A3、A4,第二波谷包含一位於兩相鄰的第二頂峰之間的第二最低點B2。半導體接觸層1260的粗糙頂面1310的兩個第一最高點A1、A2與第一最低點B1連接形成兩條第一斜線L2、L4,一第一角度θ1位於兩條第一斜線L2、L4之間。透明電流擴散層1270的頂面1320的兩個第二最高點A3,A4與第二最低點B2連接形成兩條第二斜線L1、L3,一第二角度θ2位於兩條第二斜線L1、L3之間。第一角度θ1與第二角度θ2的差異不大於10度。於另一實施例中,第一角度θ1大致等於第二角度θ2。透明電流擴散層1270的頂面1320的第二波谷之第二最低點B2與半導體接觸層1260之粗糙頂面1310的第一波谷的第一最低點B1之間的第一高度差H1大於0。透明電流擴散層1270的頂面1320的其中一第二頂峰之第二最高點A3與半導體接觸層1260之粗糙頂面1310的其中一第一頂峰之第一最高點A1之間的第二高度差H2大於0。透明電流 擴散層1270的頂面1320的其中一第二頂峰之第二最高點A4與半導體接觸層1260之粗糙頂面1310的其中一第一頂峰之第一最高點A2之間的第三高度差H3大於0。第二高度差H2相等或相異於第三高度差H3。第一高度差H1與第二高度差H2的比例為0.1至10之間。第一高度差H1與第三高度差H3的比例為0.1至10之間。於另一實施例中,半導體接觸層1260之頂部形成有圓錐形或多角錐形之孔穴,且孔穴自半導體接觸層1260之頂部向下延伸以形成粗糙頂面1310。 Fig. 8B is a schematic enlarged cross-sectional view showing the semiconductor contact layer 1260 and the transparent current diffusion layer 1270 in a partial region of the light-emitting element of one embodiment of the present invention. The rough top surface 1310 of the semiconductor contact layer 1260 includes two adjacent first peaks and a first trough, each of the first peaks respectively includes a first highest point A 1 , A 2 , and the first trough includes one adjacent to the two The first lowest point B 1 between the first peaks. The top surface 1320 of the transparent current diffusion layer 1270 includes two adjacent second peaks and a second valley, each of the second peaks respectively includes a second highest point A 3 , A 4 , and the second valley includes one adjacent to the two The second lowest point B 2 between the second peaks. The two first highest points A 1 , A 2 of the rough top surface 1310 of the semiconductor contact layer 1260 are connected to the first lowest point B 1 to form two first oblique lines L 2 , L 4 , and a first angle θ 1 is located at two The first oblique line is between L 2 and L 4 . The two second highest points A 3 , A 4 of the top surface 1320 of the transparent current diffusion layer 1270 are connected to the second lowest point B 2 to form two second oblique lines L 1 , L 3 , and a second angle θ 2 is located at two Between the second oblique lines L 1 and L 3 . The difference between the first angle θ 1 and the second angle θ 2 is not more than 10 degrees. In another embodiment, the first angle θ 1 is substantially equal to the second angle θ 2 . A first height difference H 1 between a second lowest point B 2 of the second trough of the top surface 1320 of the transparent current spreading layer 1270 and a first lowest point B 1 of the first trough of the rough top surface 1310 of the semiconductor contact layer 1260 Greater than 0. a second highest point A 3 of one of the second peaks of the top surface 1320 of the transparent current diffusion layer 1270 and a second highest point A 1 of one of the first peaks of the rough top surface 1310 of the semiconductor contact layer 1260 The height difference H 2 is greater than zero. a third between the second highest point A 4 of one of the second peaks of the top surface 1320 of the transparent current diffusion layer 1270 and the first highest point A 2 of one of the first peaks of the rough top surface 1310 of the semiconductor contact layer 1260 The height difference H 3 is greater than zero. The second height difference H 2 is equal or different from the third height difference H 3 . The ratio of the first height difference H 1 to the second height difference H 2 is between 0.1 and 10. The ratio of the first height difference H 1 to the third height difference H 3 is between 0.1 and 10. In another embodiment, the top of the semiconductor contact layer 1260 is formed with conical or polygonal conical holes, and the holes extend downward from the top of the semiconductor contact layer 1260 to form a rough top surface 1310.

第8C圖係顯示本發明其中一實施例之發光元件之發光元件中部分區域的半導體接觸層1260以及透明電流擴散層1270之剖面放大示意圖。位於半導體接觸層1260之粗糙頂面1310的第一波谷包含一第一平整區域C1,且第一最低點(未標示)係位於第一平整區域C1;位於透明電流擴散層1270的頂面1320的第二波谷包含一第二平整區域C2,且第二最低點(未標示)係位於第二平整區域C2。第一平整區域C1與第二平整區域C2之間的第一高度差H1大於0。 Fig. 8C is a schematic enlarged cross-sectional view showing the semiconductor contact layer 1260 and the transparent current diffusion layer 1270 in a partial region of the light-emitting element of the light-emitting element of one embodiment of the present invention. The first trough of the rough top surface 1310 of the semiconductor contact layer 1260 includes a first flat region C 1 , and the first lowest point (not labeled) is located in the first flat region C 1 ; the top surface of the transparent current diffusion layer 1270 The second trough of 1320 includes a second flat region C 2 and the second lowest point (not labeled) is located at the second flat region C 2 . The first height difference H 1 between the first flat region C 1 and the second flat region C 2 is greater than zero.

第9A至9C圖顯示本發明之發光元件應用於發光二極體模組之示意圖。第9A圖顯示一光電元件模組900包含一次載體902,一光電裝置(圖未示),複數透鏡904、906、908、910,以及兩個電源供應端子912(另一圖未示)。光電元件模組900可與一燈罩連接以形成一照明裝置連接,後續會詳細說明。 9A to 9C are schematic views showing the application of the light-emitting element of the present invention to a light-emitting diode module. Fig. 9A shows a photovoltaic element module 900 comprising a primary carrier 902, a photovoltaic device (not shown), a plurality of lenses 904, 906, 908, 910, and two power supply terminals 912 (another one not shown). The optoelectronic component module 900 can be coupled to a lampshade to form a lighting device connection, as will be described in detail later.

第9B圖係顯示本發明之光電元件模組900之剖面示意圖,第9C圖係第9B圖中E區之剖面放大示意圖。如第9B圖所示,次載體902包含一頂部子單元903以及一底部子單元901,其中底部子單元901至少有一表面係與頂部子單元903接觸。透鏡904、908係形成於頂部子單元903之上。如第9C圖所示,至少一穿孔915係穿透頂部子單元903,且至少一光電裝置800係位於穿孔915內且與底部子單元901接觸。此外,光電裝置800係使用一封裝材料921封裝,且透鏡908係位於封裝材料921之上,封裝材料921包含矽樹脂(silicone resin)或環氧樹脂等(epoxy resin)。於一實施例中,一反射層919係形成於頂部子單元903環繞穿孔915之側壁上,藉以增加發光效率。一金屬層917可行於底部子單元901之下表面上以提高散熱效果。 Fig. 9B is a schematic cross-sectional view showing a photovoltaic element module 900 of the present invention, and Fig. 9C is an enlarged cross-sectional view showing an E region in Fig. 9B. As shown in FIG. 9B, the secondary carrier 902 includes a top subunit 903 and a bottom subunit 901, wherein the bottom subunit 901 has at least one surface system in contact with the top subunit 903. Lenses 904, 908 are formed over top sub-unit 903. As shown in FIG. 9C, at least one through hole 915 penetrates the top subunit 903, and at least one optoelectronic device 800 is located within the through hole 915 and is in contact with the bottom subunit 901. In addition, the optoelectronic device 800 is packaged using a package material 921, and the lens 908 is disposed over the encapsulation material 921, which includes a silicone resin or an epoxy resin. In one embodiment, a reflective layer 919 is formed on the sidewall of the top sub-unit 903 surrounding the via 915 to increase luminous efficiency. A metal layer 917 can be applied to the lower surface of the bottom sub-unit 901 to improve the heat dissipation effect.

第10A至10B圖係顯示本發明之其中一實施例之照明裝置之示意圖。照明裝置1000包含一光電元件模組900,一燈罩1040,一提供光電元件模組900電流的電源供應電路(圖未示),以及一控制電源供應電路的控制單元(圖未示)。照明裝置1000可以是路燈、車頭燈、室內照明光源、交通號誌或是顯示器的背光模組。 10A to 10B are schematic views showing a lighting device of one embodiment of the present invention. The illuminating device 1000 comprises a photoelectric component module 900, a lampshade 1040, a power supply circuit (not shown) for supplying current of the photovoltaic device module 900, and a control unit (not shown) for controlling the power supply circuit. The lighting device 1000 can be a street lamp, a headlight, an indoor lighting source, a traffic sign, or a backlight module of the display.

第11圖係本發明發光元件應用於燈泡之分解圖,一燈泡1100具有一燈殼1121;一透鏡1122,置於燈罩1121之中;一照明模組1124,位於透鏡62之下;一燈座1125,具有一散熱槽1126,用以承載照明模組1124;一連結部1127;以及一電連結器1128,其中連結部1127連結燈座1125與電連接器1128。照明模組1124具有一載體1123;以及複數個前述任一實施例之位於載體1123上的光電裝置800。 Figure 11 is an exploded view of the light-emitting element of the present invention, a bulb 1100 having a lamp housing 1121; a lens 1122 disposed in the lamp housing 1121; a lighting module 1124 located below the lens 62; a lamp holder 1125, having a heat sink 1126 for carrying the lighting module 1124; a connecting portion 1127; and an electrical connector 1128, wherein the connecting portion 1127 is coupled to the socket 1125 and the electrical connector 1128. The illumination module 1124 has a carrier 1123; and a plurality of optoelectronic devices 800 on the carrier 1123 of any of the foregoing embodiments.

具體的,光電裝置包含前述任一實施例之發光元件、光電二極管、光敏電阻(photo resister)、雷射二極體、紅外線發射器、有機發光二極體以及太陽能電池。導電基板10、300、40和/或基板20、1210、50、80可為成長或承載基底,基板20、1210、50、80包含導電基板、絕緣基板、透明基板或透光基板。導電基板之材料可包含金屬、氧化物、氮化物、磷化物或矽化物,其中金屬例如可包含鍺(Ge)或砷化鎵(GaAs),氧化物例如可包含鋁酸鋰(LiAlO2)或氧化鋅(ZnO),氮化物例如可包含氮化鎵(GaN)或氮化鋁(AlN),磷化物例如可包含磷化銦(InP),矽化物例如可包含矽或碳化矽(SiC)。透明基板之材料可包含氧化鋁(Al2O3)、鋁酸鋰(LiAlO2)、氧化鋅(ZnO)氮化鎵(GaN)、氮化鋁(AlN)、玻璃、鑽石、合成鑽石(CVD diamond)、類鑽碳(diamond-like carbon,DLC)、尖晶石(MgAl2O3)、氧化矽(SiOx)或鎵酸鋰(LiGaO2)。 Specifically, the photovoltaic device comprises the light-emitting element, the photodiode, the photo resister, the laser diode, the infrared emitter, the organic light-emitting diode, and the solar cell of any of the foregoing embodiments. The conductive substrates 10, 300, 40 and/or the substrates 20, 1210, 50, 80 may be growth or carrier substrates, and the substrates 20, 1210, 50, 80 comprise a conductive substrate, an insulating substrate, a transparent substrate or a light transmissive substrate. The material of the conductive substrate may comprise a metal, an oxide, a nitride, a phosphide or a germanide, wherein the metal may, for example, comprise germanium (Ge) or gallium arsenide (GaAs), and the oxide may, for example, comprise lithium aluminate (LiAlO 2 ) or Zinc oxide (ZnO), the nitride may, for example, comprise gallium nitride (GaN) or aluminum nitride (AlN), and the phosphide may, for example, comprise indium phosphide (InP), which may, for example, comprise niobium or tantalum carbide (SiC). The material of the transparent substrate may include aluminum oxide (Al 2 O 3 ), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO) gallium nitride (GaN), aluminum nitride (AlN), glass, diamond, synthetic diamond (CVD). Diamond), diamond-like carbon (DLC), spinel (MgAl 2 O 3 ), yttrium oxide (SiO x ) or lithium gallate (LiGaO 2 ).

第一導電型半導體層124、224、324、424、524、1220和第二導電型半導體層120、220、1240、320、420、520之電性、極性或摻雜物相異,或者包含用以提供電子或電洞的半導體材料,半導體材料可為單層或多層。電性選擇可以為p型、n型、及i型中至少任意二者之組合。主動層122、222、322、422、522、1230係分別位於第一導電型半導體層124、224、324、424、524、1220和第二導電型半導體層120、220、1240、320、420、520之間,主動層為電能與光能可能發生轉換或被誘發轉換之區域。 電能可能發生轉換或被誘發轉換為光能之裝置可以是發光二極體、液晶顯示器或是有機發光二極體。光能可能發生轉換或被誘發轉換為電能之裝置可以是太陽能電池或光電二極體。第一導電型半導體層124、224、324、424、524、1220、主動層122、222、322、422、522、1230、第二導電型半導體層120、220、1240、320、420、520之材料包含鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)、矽(Si)或上述元素之組合。 The first conductive type semiconductor layers 124, 224, 324, 424, 524, and 1220 and the second conductive type semiconductor layers 120, 220, 1240, 320, 420, and 520 have different electrical properties, polarities, or dopants, or include To provide a semiconductor material for electrons or holes, the semiconductor material can be a single layer or multiple layers. The electrical selection can be a combination of at least any of p-type, n-type, and i-type. The active layers 122, 222, 322, 422, 522, and 1230 are respectively located on the first conductive type semiconductor layers 124, 224, 324, 424, 524, and 1220 and the second conductive type semiconductor layers 120, 220, 1240, 320, and 420. Between 520, the active layer is an area where electrical energy and light energy may be converted or induced to be converted. The means by which electrical energy may be converted or induced to be converted into light energy may be a light emitting diode, a liquid crystal display or an organic light emitting diode. The means by which light energy may be converted or induced to be converted into electrical energy may be a solar cell or a photodiode. First conductive semiconductor layers 124, 224, 324, 424, 524, 1220, active layers 122, 222, 322, 422, 522, 1230, second conductive semiconductor layers 120, 220, 1240, 320, 420, 520 The material comprises gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), cerium (Si) or a combination of the above.

於一實施例中,光電裝置包含之發光元件,其發光頻譜可以藉由改變單層半導體材料層或多層半導體材料層之物理或化學要素進行調整。常用之單層半導體材料層之材料或多層半導體材料層包含鋁(Al)、鎵(Ga)、銦(In)、磷(P)、氮(N)、鋅(Zn)、氧(O)或上述元素之組合。主動層(未顯示)之結構例如:單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井結構(multi-quantum well;MQW)。再者,調整量子井之對數亦可以改變發光波長。 In one embodiment, the optoelectronic device includes a light-emitting element whose illumination spectrum can be adjusted by changing the physical or chemical elements of the single-layer semiconductor material layer or the multi-layer semiconductor material layer. A commonly used single layer semiconductor material layer or a multilayer semiconductor material layer comprising aluminum (Al), gallium (Ga), indium (In), phosphorus (P), nitrogen (N), zinc (Zn), oxygen (O) or A combination of the above elements. The structure of the active layer (not shown) is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multilayer quantum well structure. (multi-quantum well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

於一實施例中,第一導電型半導體層124、224、324、424、524、1220和基板20、1210、50、導電基板10、300、40之間可選擇性的設置一緩衝層(圖未示)。此緩衝層係介於二種材料系統之間,使基板20、1210、50、導電基板10、300、40之材料系統”過渡”至第一導電型半導體層124、224、324、424、524、1220之材料系統。對發光二極體之結構而言,緩衝層係用以降低二種材料間晶格不匹配之材料層。另一方面,緩衝層亦可以是包含二種材料或二個分離結構之單層、多層或一結構,其可選用之材料係包含有機材料、無機材料、金屬、或半導體等;其可選用之結構係包含:反射層、導熱層、導電層、歐姆接觸層、抗形變層、應力釋放(stress release)層、接合(bonding)層、波長轉換層、及機械固定構造等。在一實施例中,此緩衝層之材料可包含氮化鋁(AlN)或氮化鎵(GaN),且形成方法可包含濺鍍(sputter)或原子層沉積(atomic layer deposition,ALD)。 In an embodiment, a buffer layer may be selectively disposed between the first conductive semiconductor layers 124, 224, 324, 424, 524, and 1220 and the substrates 20, 1210, and 50 and the conductive substrates 10, 300, and 40. Not shown). The buffer layer is interposed between the two material systems to "transition" the material systems of the substrates 20, 1210, 50, and the conductive substrates 10, 300, 40 to the first conductive semiconductor layers 124, 224, 324, 424, 524. , 1220 material system. For the structure of the light-emitting diode, the buffer layer is used to reduce the material layer of the lattice mismatch between the two materials. In another aspect, the buffer layer may also be a single layer, a plurality of layers or a structure comprising two materials or two separate structures, and the materials selectable include organic materials, inorganic materials, metals, or semiconductors; The structure includes: a reflective layer, a thermally conductive layer, a conductive layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a bonding layer, a wavelength conversion layer, and a mechanical fixing structure. In an embodiment, the material of the buffer layer may include aluminum nitride (AlN) or gallium nitride (GaN), and the forming method may include sputtering or atomic layer deposition (ALD).

於前述之實施例中,第一透明導電氧化物層14、24以及第二透明導電氧化物層28、48、58之材料包含銦錫氧化物(indium tin oxide,ITO)、鎘錫氧化物(cadmium tin oxide,CTO)、銻氧化錫(antimony tin oxide)、氧化銦鋅(zinc indium oxide)、氧化鋅鋁(aluminum zinc oxide)、鋅 錫氧化物(zinc antimony oxide)、或其等之組合,且形成方法可包含電子束蒸鍍、離子濺鍍、熱蒸鍍或其等之組合。以第一透明導電氧化物層14、24以及第二透明導電氧化物層28、48、58包含銦錫氧化物為例,第一透明導電氧化物層14、24之厚度以及第二透明導電氧化物層28、48、58之厚度係為1微米至150之間,且在波長為300微米至700微米之間的範圍內,透光率係大於50%。 In the foregoing embodiments, the materials of the first transparent conductive oxide layers 14, 24 and the second transparent conductive oxide layer 28, 48, 58 comprise indium tin oxide (ITO), cadmium tin oxide ( Cadmium tin oxide, CTO), antimony tin oxide, zinc indium oxide, aluminum zinc oxide, zinc A zinc antimony oxide, or a combination thereof, and the formation method may include electron beam evaporation, ion sputtering, thermal evaporation, or the like. Taking the first transparent conductive oxide layers 14, 24 and the second transparent conductive oxide layers 28, 48, 58 comprising indium tin oxide as an example, the thickness of the first transparent conductive oxide layers 14, 24 and the second transparent conductive oxidation The thickness of the layer 28, 48, 58 is between 1 micrometer and 150, and the light transmittance is greater than 50% in the range of wavelengths between 300 micrometers and 700 micrometers.

於前述之實施例中,金屬鍵合層41、51之材料包含銦、錫、金-錫(AuSn)或是其等之合金。 In the foregoing embodiments, the material of the metal bonding layers 41, 51 comprises indium, tin, gold-tin (AuSn) or an alloy thereof.

布拉格反射層38係包含半導體疊層。反射層49、59係包含銦、錫、鋁、金、鉑、鋅、銀、鈦、鉛、鈀、鍺、銅、鈹金、鍺金、鎳、鉛錫合金、金鋅合金或其等之合金。第一和第二金屬反射層17、27、30之材料包含鋁或銀。 The Bragg reflector layer 38 comprises a semiconductor stack. The reflective layers 49 and 59 comprise indium, tin, aluminum, gold, platinum, zinc, silver, titanium, lead, palladium, iridium, copper, ruthenium, ruthenium, nickel, lead-tin alloy, gold-zinc alloy or the like. alloy. The material of the first and second metal reflective layers 17, 27, 30 comprises aluminum or silver.

以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。 The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required.

雖然本發明已說明如上,然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更,皆不脫本發明之精神與範圍。 Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

1200‧‧‧發光元件 1200‧‧‧Lighting elements

1250‧‧‧發光結構 1250‧‧‧Lighting structure

1260‧‧‧半導體接觸層 1260‧‧‧Semiconductor contact layer

1270‧‧‧透明電流擴散層 1270‧‧‧Transparent current diffusion layer

1210‧‧‧基板 1210‧‧‧Substrate

1220‧‧‧第一導電型半導體層 1220‧‧‧First Conductive Semiconductor Layer

1230‧‧‧主動層 1230‧‧‧Active layer

1240‧‧‧第二導電型半導體層 1240‧‧‧Second conductive semiconductor layer

Claims (10)

一種發光元件,其包含:一半導體接觸層,其包含一粗糙頂面,該粗糙頂面包含兩相鄰的第一頂峰以及一第一波谷,各第一頂峰包含一第一最高點,該第一波谷包含一位於該兩相鄰的第一頂峰之間的第一最低點,該兩個第一最高點與該第一最低點連接形成兩條第一斜線,且一第一角度位於該兩條第一斜線之間;以及一透明電流擴散層,其包含一位於該半導體接觸層之上的頂面,且該透明電流擴散層的該頂面包含兩相鄰的第二頂峰以及一第二波谷,各第二頂峰包含一第二最高點,該第二波谷包含一位於該兩相鄰的第二頂峰之間的第二最低點,該頂面的該兩個第二最高點與該第二最低點連接形成兩條第二斜線,一第二角度位於該兩條第二斜線之間;其中該半導體接觸層的該粗糙頂面大致位於該透明電流擴散層的該頂面的正下方,該第一角度與該第二角度的差異不大於10度。 A light emitting device comprising: a semiconductor contact layer comprising a rough top surface, the rough top surface comprising two adjacent first peaks and a first trough, each first peak comprising a first highest point, the first a wave valley includes a first lowest point between the two adjacent first peaks, the two first highest points are connected to the first lowest point to form two first oblique lines, and a first angle is located at the two a first oblique line between the strips; and a transparent current diffusion layer comprising a top surface over the semiconductor contact layer, and the top surface of the transparent current diffusion layer includes two adjacent second peaks and a second a trough, each second peak comprising a second highest point, the second trough comprising a second lowest point between the two adjacent second peaks, the two second highest points of the top surface and the first The second lowest point is connected to form two second oblique lines, and a second angle is located between the two second oblique lines; wherein the rough top surface of the semiconductor contact layer is substantially directly below the top surface of the transparent current diffusion layer, The first angle and the second angle The difference is not greater than 10 degrees. 如申請專利範圍第1項所述之發光元件,其更包括一位於該第一最低點與該第二最低點之間的第一高度差,該第一高度差大於0。 The illuminating element of claim 1, further comprising a first height difference between the first lowest point and the second lowest point, the first height difference being greater than zero. 如申請專利範圍第2項所述之發光元件,其更包括一第二高度差以及一第三高度差,該第二高度差位於兩相鄰的第一頂峰與第二頂峰之間且大於0,該第三高度差位於另兩相鄰的第一頂峰與第二頂峰之間且大於0。 The illuminating element of claim 2, further comprising a second height difference and a third height difference, the second height difference being between the two adjacent first peaks and the second peak and greater than 0 The third height difference is located between the other two adjacent first peaks and the second peak and is greater than zero. 如申請專利範圍第3項所述之發光元件,該第一高度差與該第二高度差的比例為0.1至10之間。 The light-emitting element according to claim 3, wherein the ratio of the first height difference to the second height difference is between 0.1 and 10. 如申請專利範圍第3項所述之發光元件,該第一高度差與該第三高度差的比例為0.1至10之間。 The light-emitting element according to claim 3, wherein the ratio of the first height difference to the third height difference is between 0.1 and 10. 如申請專利範圍第1項所述之發光元件,其中該第一波谷包含一第一平整區域。 The illuminating element of claim 1, wherein the first trough comprises a first flat area. 如申請專利範圍第6項所述之發光元件,其中該第二波谷包含 一第二平整區域。 The illuminating element of claim 6, wherein the second trough comprises A second flat area. 如申請專利範圍第1項所述之發光元件,其中該半導體接觸層之頂部形成有複數孔穴,且該等孔穴自半導體接觸層之頂部向下延伸以形成該粗糙頂面。 The light-emitting element of claim 1, wherein a plurality of holes are formed in a top portion of the semiconductor contact layer, and the holes extend downward from a top of the semiconductor contact layer to form the rough top surface. 如申請專利範圍第1項所述之發光元件,該第一角度大致等於該第二角度。 The light-emitting element of claim 1, wherein the first angle is substantially equal to the second angle. 如申請專利範圍第1項所述之發光元件,其中透明電流擴散層之材料包含金屬氧化物或金屬氮化物。 The light-emitting element according to claim 1, wherein the material of the transparent current diffusion layer comprises a metal oxide or a metal nitride.
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