TW201503293A - Semiconductor assembly structure and semiconductor process - Google Patents

Abstract

The present invention relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. The interconnection elements connect the first substrate and the second substrate. The encapsulation material covers the interconnection elements, wherein the adhesion force between the encapsulation material and the first substrate is substantially the same with that between the encapsulation material and the second substrate. Whereby, the second substrate will not warp during the reflow process.

Description

Semiconductor composite structure and semiconductor process

The present invention relates to a semiconductor composite structure and a semiconductor process. In particular, the present invention relates to a semiconductor composite structure and a semiconductor process including a vertical bonded wafer.

The manufacturing method of the semiconductor composite structure including the vertical bonding wafer is to bond a vertical wafer to a substrate, wherein the first surface of the vertical wafer is perpendicular to a first surface of the substrate, and the vertical wafer is The first surface has a wafer pad, and one of the first surfaces of the substrate has a substrate pad. The wafer pads are perpendicular to the substrate pads and are in close proximity. Then, the solder pad and the substrate pad are simultaneously contacted by a solder to electrically connect the die pad and the substrate pad. The disadvantage of this method is that the reliability is low because the position of the wafer pad must be very close to the lower edge of the vertical wafer so that the solder can simultaneously contact the wafer pad and the substrate pad. In addition, the wafer pads are in a vertical direction, and when the solder is at a high temperature, it is in a flowable state, which is not easily attached to the wafer pads. In order to improve the above problems, a solution has been proposed.

One aspect of the disclosure relates to a semiconductor package structure. In one embodiment, the semiconductor package structure includes a first substrate, a second substrate, a die, a plurality of interconnecting components, and a cladding material. The first substrate has an upper surface and a plurality of first substrates Upper conductive pad. The second substrate has a lower surface and a plurality of second substrate lower conductive pads, wherein the upper surface of the first substrate faces the lower surface of the second substrate. The die is electrically connected to an upper surface of the first substrate. The inner connecting elements connect the conductive pads on the first substrate and the second substrate lower conductive pads. The covering material is disposed between the upper surface of the first substrate and the lower surface of the second substrate, and covers the die and the inner connecting components, wherein the covering material is respectively adhered to the first substrate The surface and the lower surface of the second substrate, and the adhesion between the cladding material and the upper surface of the first substrate is substantially the same as the adhesion between the cladding material and the lower surface of the second substrate.

Another aspect of the disclosure relates to a semiconductor package structure. In one embodiment, the semiconductor package structure includes a first substrate, a second substrate, a die, a plurality of interconnecting components, and a cladding material. The first substrate has an upper surface and a plurality of conductive pads on the first substrate. The second substrate has a lower surface and a plurality of second substrate lower conductive pads, wherein the upper surface of the first substrate faces the lower surface of the second substrate. The die is electrically connected to an upper surface of the first substrate. The inner connecting elements connect the conductive pads on the first substrate and the second substrate lower conductive pads. The covering material is located between the upper surface of the first substrate and the lower surface of the second substrate, and covers the die and the inner connecting components, wherein the covering material has a plurality of receiving slots to accommodate the The inner connecting members are, and the shapes of the receiving grooves are defined by the inner connecting members.

Another aspect of the disclosure is directed to a semiconductor process. In one embodiment, the semiconductor process includes the steps of: (a) electrically connecting a die to an upper surface of a first substrate, wherein the first substrate further comprises a plurality of conductive pads on the first substrate, a surface of the first substrate; (b) forming a plurality of first conductive portions on the conductive pads on the first substrate; (c) applying a cladding material on the upper surface of the first substrate to cover the crystal And the first conductive portion, wherein the covering material is a B-stage adhesive; (d) forming a plurality of openings in the covering material to expose the first conductive portions; (e) Pressing a second substrate on the covering material such that a lower surface of the second substrate adheres to the covering material The second substrate further includes a plurality of second substrate lower conductive pads and a plurality of second conductive portions, wherein at least one of the first conductive portion and the second conductive portion includes a solder under the second substrate The conductive pads are exposed on the lower surface of the second substrate, the second conductive portions are located on the lower conductive pads of the second substrate, and the solder contacts the first conductive portions and the second conductive portions; f) performing a heating step such that the solder melts to form a plurality of interconnecting elements, and the cladding material solidifies into a C stage.

In this embodiment, since the lower surface of the second substrate is adhered to the covering material, the second substrate and the covering material are not displaced during the movement of the entire package structure. In addition, during reflow, the second substrate does not warp, and the product yield can be improved.

W ₁ ‧‧‧first width

W ₂ ‧‧‧second width

W ₃ ‧‧‧ third width

W _m ‧‧‧max width

1‧‧‧An embodiment of the semiconductor package structure of the present invention

1a‧‧‧Another embodiment of the semiconductor package structure of the present invention

1b‧‧‧Another embodiment of the semiconductor package structure of the present invention

10‧‧‧First substrate

12‧‧‧second substrate

14‧‧‧ grain

15‧‧‧First Conductive Department

16‧‧‧Interconnecting components

16a‧‧‧Interconnecting components

18‧‧‧Covering materials

20‧‧‧Bottom solder balls

30‧‧‧ solder

101‧‧‧Top surface of the first substrate

102‧‧‧The lower surface of the first substrate

103‧‧‧Electrical mat on the first substrate

104‧‧‧First substrate under conductive pad

105‧‧‧First upper dielectric layer

106‧‧‧First lower dielectric layer

107‧‧‧First copper column

121‧‧‧Top surface of the second substrate

122‧‧‧The lower surface of the second substrate

123‧‧‧Electrical mat on the second substrate

124‧‧‧Second substrate under conductive pad

126‧‧‧Second upper dielectric layer

127‧‧‧Second lower dielectric layer

128‧‧‧second copper pillar

161‧‧‧necked neck

181‧‧‧ accommodating slot

182‧‧‧filled particles

183‧‧‧ openings

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an embodiment of a semiconductor composite structure of the present invention. .

2 is a top plan view showing the conductor and the first electrical connection in the semiconductor composite structure of FIG. 1.

Fig. 3 is an enlarged schematic view showing a region A in Fig. 1.

4 is a partially enlarged schematic view showing the first wafer and the bump in FIG. 1.

5 through 14 are schematic views showing an embodiment of a semiconductor process of the present invention.

Referring to Figure 1, there is shown a cross-sectional schematic view of one embodiment of a semiconductor composite structure of the present invention. The semiconductor composite structure 1 includes a substrate 10, at least one conductor 12, a retaining wall portion 14, a first wafer 16, an underfill 18, a second wafer 20, at least a third wafer 24, and a plurality of strips. The first wire 22, the plurality of second wires 26, and a glue material 28.

The substrate 10 has an upper surface 101, a lower surface 102, a first electrical connection 103, and a second electrical connection 104, wherein the upper surface 101 is opposite to the lower surface 102, and the first electrical The connection 103 and the second electrical connection 104 are located in the upper table On the face 101. In this embodiment, the first electrical connection 103 and the second electrical connection 104 are conductive fingers.

The conductor 12 is located on the first electrical connection 103. The conductor 12 is made of a conductive material such as gold or copper.

The retaining wall portion 14 is adjacent to the substrate 10 and is configured to abut the conductor 12. In this embodiment, the retaining wall portion 14 is located on the electrical connection 103 and further covers the upper surface 101 of the substrate 10. The material of the retaining wall portion 14 is a non-conductive rubber material, such as polyimide (PI), epoxy resin (Epoxy) or benzocyclobutene (BCB).

The first wafer 16 has a first surface 161 , a second surface 162 , a third surface 163 , and at least one bump 17 . The first surface 161 is opposite to the second surface 162 , and the third surface 163 is adjacent to the first surface 161 and the second surface 162 . The first surface 161 of the first wafer 16 is substantially perpendicular to the upper surface 101 of the substrate 10, and the third surface 163 of the first wafer 16 is substantially parallel to the upper surface 101 of the substrate 10. That is, the first wafer 16 is a vertical bonded wafer.

The bumps 17 are located on the first surface 161 of the first wafer 16, and the number and position correspond to the conductors 12 such that the bumps 17 contact the conductors 12. In this embodiment, the number of the conductors 12 is six, which are respectively located on the six first electrical connections 103. Therefore, the first wafer 16 has six bumps 17, wherein each bump 17 Each conductor 12 is contacted. The material of the bump 17 is different from the material of the conductor 12. In this embodiment, the material of the bump 17 is tin. It is to be noted that the bump 17 in Fig. 1 is not a sphere since it has undergone a heating step, and the melt collapses and adheres to the conductor 12.

The primer 18 covers the bumps 17. In this embodiment, the third surface 163 of the first wafer 16 has a gap with the upper surface 101 of the substrate 10 such that the primer 18 can pass through the second surface 162 of the first wafer 16. A slit is applied to the first surface 161 of the first wafer 16 to cover the bump 17. The primer 18 is different from the material of the retaining wall portion 14 . Further, the viscous coefficient of the retaining wall portion 14 is greater than the viscous coefficient of the primer 18. The second wafer 20 is attached to the substrate 10 and electrically connected to the substrate 10. In the embodiment, the second wafer 20 is adhered to the upper surface 101 of the substrate 10 by using an adhesive layer 21, and is utilized. The first wires 22 are electrically connected to the second electrical connection 104 on the substrate 10 .

The third wafer 24 is attached to the second wafer 20 and electrically connected to the second wafer 20. In this embodiment, the third wafer 24 is adhered to the second wafer 20 by an adhesive layer 25, and is electrically connected to the second wafer 20 by the second wires 26. Preferably, the second wafer 20 is an Application Specific Integrated Circuit (ASIC) chip, and the third chip 24 is a sensor.

The encapsulant 28 is located on the upper surface 101 of the substrate 10 and covers the first wafer 16, the primer 18, the second wafer 20, the third wafer 24, the first wires 22, and the Wait for the second wire 26. Further, the sealing material 28 is in direct contact with the retaining wall portion 14 and the primer 18.

Referring to FIG. 2, a top plan view of the conductor and the first electrical connection in the semiconductor composite structure of FIG. 1 is shown. In this embodiment, the first electrical connection 103 has a length L of 60 μm and a width W of 30 μm. The maximum width D of the conductor 12 is 20 μm.

Referring to Figure 3, an enlarged schematic view of area A of Figure 1 is shown. In the present embodiment, the conductor 12 is spherical or columnar having a maximum height H of 15 to 30 μm. The retaining wall portion 14 is in contact with the conductor 12 to form a contact surface 121. The highest point 1211 of the contact surface 121 is lower than the highest point 123 of the conductor 12 itself. That is, the retaining wall portion 14 does not cover the highest point 123 of the conductor 12. Therefore, the thickness T of the retaining wall portion 14 is smaller than the maximum height H of the conductor 12, and the contact surface 121 is smaller than one half of the outer surface of the conductor 12. Thereby, the retaining wall portion 14 does not affect the connection between the bump 17 and the conductor 12. Preferably, the thickness T of the retaining wall portion 14 is about 1/3 to 2/3 of the maximum height H of the conductor 12.

The bump 17 is in contact with the conductor 12 not covered by the retaining wall portion 14 to form a contact Face 122, the contact surface 122 will extend beyond the highest point 123 of the conductor 12. That is, the contact surface 122 is larger than one half or more of the outer surface of the conductor 12. The retaining wall portion 14 has a blocking function to prevent the bumps 17 from being completely attached to the conductor 12 and overflowing to the substrate 10 after the heating step is subjected to the heating step, so that the bumps 17 are separated from the first wafer 16, thereby causing electrical properties. Poor performance. Therefore, the bonding reliability between the bump 17 and the conductor 12 can be improved, and the electrical connection between the bump 17 and the first electrical connection 103 is ensured, and the first wafer 16 and the substrate 10 are ensured. Electrical connection between the two.

Referring to FIG. 4, a partial enlarged view of the first wafer 16 and the bump 17 in FIG. 1 is shown. In this embodiment, the first wafer 16 further has a protective layer 164, a pad 165 and a sub-ball metal layer (UBM) 166. The material of the pad 165 is gold. The surface of the protective layer 164 is the first surface 161 of the first wafer 16. The protective layer 164 has an opening 1641 to expose a portion of the pad 165. The under-ball metal layer (UBM) 166 is located on the protective layer 164 and in the opening 1641 to contact the pad 165. The bump 17 is located on the under-ball metal layer (UBM) 166.

The under-ball metal layer (UBM) 166 sequentially includes a first metal layer 1661, a second metal layer 1662, and a third metal layer 1663. The first metal layer 1661 is in contact with the pad 165, and the bump 17 is located on the third metal layer 1663. In this embodiment, the material of the first metal layer 1661 is titanium, chromium, tungsten or zinc, and the material of the second metal layer 1662 is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the third metal layer The material of 1663 is copper. In another embodiment, the material of the first metal layer 1661 is palladium or cobalt, and the material of the second metal layer 1662 is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the material of the third metal layer 1663 It is made of copper. In another embodiment, the under-ball metal layer (UBM) 166 sequentially includes a first metal layer and a second metal layer. The first metal layer contacts the pad 165, and the bump 17 is located. On the second metal layer. The material of the first metal layer is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the material of the second metal layer is copper. The material of the under-ball metal layer (UBM) 166 can strengthen the bump 17 and the under-ball metal layer (UBM) 166. The bonding force allows the bump 17 to be firmly bonded to the under-ball metal layer (UBM) 166 even after multiple reflows (e.g., more than 10 times).

Referring to Figures 5 through 14, a schematic diagram of one embodiment of a semiconductor process of the present invention is shown. Referring to Figure 5, a substrate 10 is provided. The substrate 10 has an upper surface 101, a lower surface 102, a first electrical connection 103, and a second electrical connection 104, wherein the upper surface 101 is opposite to the lower surface 102, and the first electrical The connection 103 and the second electrical connection 104 are located on the upper surface 101. In this embodiment, the first electrical connection 103 and the second electrical connection 104 are conductive fingers.

Next, at least one conductor 12 is formed on the first electrical connection 103. The conductor 12 is made of a conductive material such as gold or copper.

Referring to FIG. 6, a barrier portion 14 is formed adjacent to the substrate 10 to abut the conductor 12. In this embodiment, the retaining wall portion 14 is located on the electrical connection 103 and further covers the upper surface 101 of the substrate 10. The material of the retaining wall portion 14 is a non-conductive adhesive material, such as polyimide (PI), epoxy resin (Epoxy) or benzocyclobutene (BCB), and it must have a high viscosity. . The retaining wall portion 14 is in contact with the conductor 12 to form a contact surface 121. The highest point 1211 of the contact surface 121 is lower than the highest point 123 of the conductor 12 itself. That is, the retaining wall portion 14 does not cover the highest point 123 of the conductor 12. Therefore, the thickness T of the retaining wall portion 14 is smaller than the maximum height H of the conductor 12, and the contact surface 121 is smaller than one half of the outer surface of the conductor 12. Thereby, the retaining wall portion 14 does not affect the subsequent electrical connection. Preferably, the thickness T of the retaining wall portion 14 is about 1/3 to 2/3 of the maximum height H of the conductor 12. Next, the retaining wall portion 14 is cured.

Referring to Figure 7, a first wafer 16 is provided. The first wafer 16 has a first surface 161 , a second surface 162 , a third surface 163 , and at least one bump 17 . The first surface 161 is opposite to the second surface 162 , and the third surface 163 is adjacent to the first surface 161 and the second surface 162 . The bumps 17 are located on the first surface 161 of the first wafer 16, and the number and position correspond to the conductors 12. Between the bottom of the bump 17 and the third surface 163 The distance d is substantially equal to the sum of the thickness of the electrical connection 103 and the maximum height H of the conductor 12.

Referring to FIG. 8, a partial enlarged view of the first wafer and the bump in FIG. 7 is shown. In this embodiment, the first wafer 16 further has a protective layer 164, a pad 165 and a sub-ball metal layer (UBM) 166. The material of the bump 17 is different from the material of the conductor 12. In this embodiment, the material of the bump 17 is tin. It should be noted that the bump 17 in this figure is a sphere. The material of the pad 165 is gold. The surface of the protective layer 164 is the first surface 161 of the first wafer 16. The protective layer 164 has an opening 1641 to expose a portion of the pad 165. The under-ball metal layer (UBM) 166 is located on the protective layer 164 and in the opening 1641 to contact the pad 165. The bump 17 is located on the under-ball metal layer (UBM) 166.

The under-ball metal layer (UBM) 166 sequentially includes a first metal layer 1661, a second metal layer 1662, and a third metal layer 1663. The first metal layer 1661 is in contact with the pad 165, and the bump 17 is located on the third metal layer 1663. In this embodiment, the material of the first metal layer 1661 is titanium, chromium, tungsten or zinc, and the material of the second metal layer 1662 is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the third metal layer The material of 1663 is copper. In another embodiment, the material of the first metal layer 1661 is palladium or cobalt, and the material of the second metal layer 1662 is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the material of the third metal layer 1663 It is made of copper. In another embodiment, the under-ball metal layer (UBM) 166 sequentially includes a first metal layer and a second metal layer. The first metal layer contacts the pad 165, and the bump 17 is located. On the second metal layer. The material of the first metal layer is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the material of the second metal layer is copper. The material of the under-ball metal layer (UBM) 166 can strengthen the bonding force between the bump 17 and the under-ball metal layer (UBM) 166, so that the bump 17 remains even after multiple reflows (for example, 10 times or more). It can be firmly bonded to the under-ball metal layer (UBM) 166.

Referring to FIG. 9, the first wafer 16 is bonded to the substrate 10. The first of the first wafer 16 A surface 161 is substantially perpendicular to the upper surface 101 of the substrate 10, and the third surface 163 of the first wafer 16 is substantially parallel to the upper surface 101 of the substrate 10. That is, the first wafer 16 is a vertical bonded wafer. At this time, the bump 17 contacts the conductor 12, both of which are in point contact. In this embodiment, the third surface 163 of the first wafer 16 has a gap with the upper surface 101 of the substrate 10.

Referring to FIG. 10, reflow heating is performed such that the bump 17 is melted and collapsed to adhere to the conductor 12 not covered by the retaining wall portion 14. The bump 17 is in contact with the conductor 12 to form a contact surface 122 (FIG. 3) that extends beyond the highest point 123 of the conductor 12. That is, the contact surface 122 is larger than one half or more of the outer surface of the conductor 12. Therefore, the bonding reliability between the bump 17 and the conductor 12 can be improved, and the electrical connection between the bump 17 and the first electrical connection 103 is ensured, and the first wafer 16 and the substrate 10 are ensured. Electrical connection between the two.

Next, a primer 18 is formed to cover the bumps 17. In the present embodiment, the primer 18 may cover the bump 17 from the second surface 162 of the first wafer 16 through the slit to the first surface 161 of the first wafer 16. Next, the primer 18 is cured.

Referring to Figure 11, a second wafer 20 is attached to the substrate 10. In this embodiment, an adhesive layer 21 is formed on the upper surface 101 of the substrate 10, and then the second wafer 20 is placed on the adhesive layer 21. Thereafter, the adhesive layer 21 is dried. In this embodiment, the second wafer 20 is an Application Specific Integrated Circuit (ASIC) chip.

Referring to FIG. 12, at least one third wafer 24 is attached to the second wafer 20. In this embodiment, an adhesive layer 25 is first adhered to the second wafer 20. Next, the third wafer 24 is placed on the adhesive layer 25. Thereafter, the adhesive layer 25 is dried. In this embodiment, the third wafer 24 is a sensor.

Referring to FIG. 13 , the second wafer 20 is electrically connected to the substrate 10 , and the third wafer 24 is electrically connected to the second wafer 20 . In this embodiment, a plurality of first wires 22 are utilized The second wafer 20 is electrically connected to the second electrical connection 104 on the substrate 10, and the third wafer 24 is electrically connected to the second wafer 20 by a plurality of second wires 26.

Referring to FIG. 14, a bonding material 28 is formed on the upper surface 101 of the substrate 10 to cover the first wafer 16, the primer 18, the second wafer 20, the third wafer 24, and the first wires. 22 and the second conductors 26. Next, the sealant material 28 is cured. Next, a dicing step is performed to form a plurality of semiconductor composite structures 1.

However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1‧‧‧An embodiment of the semiconductor package structure of the present invention

10‧‧‧First substrate

12‧‧‧second substrate

14‧‧‧ grain

16‧‧‧Interconnecting components

18‧‧‧Covering materials

20‧‧‧Bottom solder balls

101‧‧‧Top surface of the first substrate

102‧‧‧The lower surface of the first substrate

103‧‧‧Electrical mat on the first substrate

104‧‧‧First substrate under conductive pad

121‧‧‧Top surface of the second substrate

122‧‧‧The lower surface of the second substrate

123‧‧‧Electrical mat on the second substrate

124‧‧‧Second substrate under conductive pad

161‧‧‧necked neck

181‧‧‧ accommodating slot

182‧‧‧filled particles

Claims (20)

A semiconductor composite structure comprising: a substrate having an upper surface and at least one electrical connection, the electrical connection being located on the upper surface; at least one conductor located at the electrical connection; and a retaining wall portion Adjacent to the substrate and for abutting the conductor; and a first wafer having a first surface and at least one bump, the bump being located on the first surface of the first wafer, the first wafer The first surface is substantially perpendicular to the upper surface of the substrate, the bump contacts the conductor, and the material of the bump is different from the material of the conductor. The semiconductor composite structure of claim 1, wherein the electrical connection is a conductive finger, and the retaining wall portion is located at the electrical connection. The semiconductor composite structure of claim 1, wherein the material of the retaining wall portion is a non-conductive rubber material. The semiconductor composite structure of claim 1, wherein the retaining wall portion is in contact with the conductor to form a contact surface, the highest point of the contact surface being lower than the highest point of the conductor itself. The semiconductor package structure of claim 1, wherein the first wafer further has a protective layer, a pad and a sub-metal layer, the protective layer has an opening to expose a portion of the pad, the under-metal layer is located The protective layer and the opening thereof are in contact with the pad, and the bump is located on the under-metal layer of the ball, wherein the material of the pad is gold. The semiconductor composite structure of claim 5, wherein the under-metal layer comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer contacting the pad, the first The material of the metal layer is titanium, chromium, tungsten or zinc, and the material of the second metal layer is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the third metal layer The material is copper. The semiconductor assembly structure of claim 1, further comprising a primer and a glue material, the primer coating the bump, the sealing material being located on the upper surface of the substrate and covering the first wafer, The primer and the retaining wall portion. A semiconductor composite structure comprising: a substrate having an upper surface and at least one electrical connection; at least one conductor located on the electrical connection; a retaining wall portion adjacent to the substrate and adapted to abut And a first wafer having a first surface, at least one bump, a protective layer, a pad and a sub-metal layer, wherein one surface of the protective layer is the first surface, and the protective layer has An opening is formed to expose a portion of the bonding pad, the underlying metal layer is located on the protective layer and the opening thereof to contact the pad, the pad is made of gold, and the bump is located on the underlying metal layer The first surface of the first wafer is substantially perpendicular to the upper surface of the substrate, and the bump contacts the conductor. The semiconductor composite structure of claim 8, wherein the electrical connection is a conductive finger, and the retaining wall portion is located at the electrical connection. The semiconductor composite structure of claim 8, wherein the conductive system is spherical or columnar having a maximum height of 15 to 30 μm. The semiconductor composite structure of claim 8, wherein the material of the retaining wall portion is a non-conductive rubber material. The semiconductor composite structure of claim 8, wherein the retaining wall portion is in contact with the conductor to form a contact surface, the highest point of the contact surface being lower than the highest point of the conductor itself. The semiconductor composite structure of claim 8, wherein the under-metal layer comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer contacting the pad, the first The material of the metal layer is titanium, chromium, tungsten or zinc, and the material of the second metal layer is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the third metal layer The material is copper. The semiconductor composite structure of claim 8, wherein the under-metal layer (UBM) sequentially comprises a first metal layer and a second metal layer, the first metal layer contacting the pad, the first metal layer The material is nickel, nickel vanadium alloy or nickel phosphorus alloy, and the material of the second metal layer is copper. The semiconductor assembly structure of claim 8, further comprising a primer and a glue material, the primer coating the bump, the sealant material is located on the upper surface of the substrate and covering the first wafer, the bottom Glue and the retaining wall. A semiconductor process comprising the steps of: (a) providing a substrate having an upper surface and at least one electrical connection; (b) forming at least one conductor on the electrical connection; and (c) forming a first stop a wall portion adjacent to the substrate to abut the conductor; (d) providing a first wafer, the first wafer having a first surface and at least one bump, the bump being located on the first surface of the first wafer And the material of the bump is different from the material of the conductor; (e) bonding the first wafer to the substrate, wherein the first surface of the first wafer is substantially perpendicular to the upper surface of the substrate, the bump Contacting the conductor; and (f) heating such that the bump melts and collapses to adhere to the conductor. The semiconductor process of claim 16, wherein in step (c), the retaining wall portion contacts the conductor to form a contact surface, the highest point of the contact surface being lower than the highest point of the conductor itself. The semiconductor process of claim 16, wherein in the step (d), the first wafer further has a third surface, the third surface is substantially perpendicular to the first surface, and the bottom of the bump is between the bottom surface and the third surface The distance is approximately equal to the sum of the thickness of the electrical connection and the height of the conductor. The semiconductor process of claim 16, wherein in the step (d), the first wafer further has a protective layer, a pad and a ball under metal layer, the protective layer has an opening to expose a portion of the pad, the underlying metal layer is located on the protective layer and in the opening to contact the pad, the protrusion The block is located on the under-metal layer of the ball, wherein the material of the pad is gold. The semiconductor process of claim 16, wherein the step (f) further comprises: (g) forming a primer to coat the bump; (h) attaching a second wafer to the substrate; (i) attaching at least one a third wafer to the second wafer; (j) electrically connecting the second wafer to the substrate, and electrically connecting the third wafer to the second wafer; (k) forming a glue material on the substrate Surface coating the first wafer, the second wafer, and the third wafer; and (1) performing a dicing step to form a plurality of semiconductor composite structures.