JP2003031763A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003031763A5 JP2003031763A5 JP2002163925A JP2002163925A JP2003031763A5 JP 2003031763 A5 JP2003031763 A5 JP 2003031763A5 JP 2002163925 A JP2002163925 A JP 2002163925A JP 2002163925 A JP2002163925 A JP 2002163925A JP 2003031763 A5 JP2003031763 A5 JP 2003031763A5
- Authority
- JP
- Japan
- Prior art keywords
- lsi chip
- chip
- semiconductor device
- wiring substrate
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Description
【００１４】
【課題を解決するための手段】
前記従来の課題を解決するために、本発明の半導体装置は、第１のＬＳＩチップと配線基板とが突起電極を介してフリップチップ接続され、前記第１のＬＳＩチップの回路形成されていない面と、第２のＬＳＩチップの回路形成されていない面とが接着され、前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続された半導体装置において、前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にあり、前記第１のＬＳＩチップの少なくとも一辺と前記第２のＬＳＩチップの少なくとも一辺とは近接している。0014.
[Means for solving problems]
In order to solve the above-mentioned conventional problems, in the semiconductor device of the present invention, the first LSI chip and the wiring board are flip-chip connected via the protrusion electrodes, and the circuit of the first LSI chip is not formed. And the surface of the second LSI chip on which the circuit is not formed are adhered to each other, and the electrode formed on the second LSI chip and the wiring formed on the wiring board are electrically connected by a thin metal wire. In a semiconductor device , the protruding electrode and the electrode formed on the second LSI chip are located at different positions in the vertical direction with the surface of the wiring substrate facing the first LSI chip as the horizontal direction. At least one side of the first LSI chip and at least one side of the second LSI chip are close to each other .
【００１６】
また、第１のＬＳＩチップと配線基板とが突起電極を介してフリップチップ接続され、前記第１のＬＳＩチップの回路形成されていない面と、第２のＬＳＩチップの回路形成されていない面とが接着され、前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続された半導体装置において、前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にあり、前記突起電極の接続部断面径は数十μ m 以下である。0016.
Further, the first LSI chip and the wiring board are flip-chip connected via the projection electrodes, and the surface of the first LSI chip where the circuit is not formed and the surface of the second LSI chip where the circuit is not formed are formed. In a semiconductor device in which an electrode formed on the second LSI chip and a wiring formed on the wiring board are electrically connected by a thin metal wire, the wiring facing the first LSI chip With the surface of the substrate in the horizontal direction , the protruding electrode and the electrode formed on the second LSI chip are located at different positions in the vertical direction, and the cross-sectional diameter of the connecting portion of the protruding electrode is several tens of μm or less. ..
【００２３】
このように、突起電極と配線基板に形成された電極とが直接接続する場合は、ＬＳＩチップの電極が狭ピッチであっても、接合剤による電気的ショートを防止することができる。
また、前記第１のＬＳＩチップと前記第２のＬＳＩチップの厚みは３００μｍ以下である半導体装置である。
また、本発明の半導体装置の製造方法は、第１のＬＳＩチップと配線基板とが突起電極を介してフリップチップ接続され前記第１のＬＳＩチップの回路形成されていない面と、前記第１のＬＳＩチップと等しいまたは小さい第２のＬＳＩチップの回路形成されていない面とが接着され、前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続されており、前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にある半導体装置の製造方法であって、前記第１のＬＳＩチップと前記配線基板との間に封止樹脂を注入したのち、前記金属細線をワイヤボンドにより電気的に接続する半導体装置の製造方法である。 [0023]
In this way, when the protruding electrode and the electrode formed on the wiring board are directly connected, it is possible to prevent an electrical short circuit due to the joining agent even if the electrodes of the LSI chip have a narrow pitch.
Further, the thickness of the first LSI chip and the second LSI chip is 300 μm or less, which is a semiconductor device.
Further, in the method for manufacturing a semiconductor device of the present invention, a surface in which a first LSI chip and a wiring board are flip-chip connected via a protrusion electrode and a circuit of the first LSI chip is not formed, and the first LSI chip. The non-circuit-formed surface of the second LSI chip, which is equal to or smaller than the LSI chip, is adhered, and the electrode formed on the second LSI chip and the wiring formed on the wiring board are electrically formed by a thin metal wire. A semiconductor in which the protruding electrode and the electrode formed on the second LSI chip are located at different positions in the vertical direction with the surface of the wiring board facing the first LSI chip as the horizontal direction. It is a method of manufacturing a semiconductor device, which is a method of manufacturing a semiconductor device in which a sealing resin is injected between the first LSI chip and the wiring substrate, and then the fine metal wires are electrically connected by wire bonding.
Claims (7)
前記第１のＬＳＩチップの回路形成されていない面と、第２のＬＳＩチップの回路形成されていない面とが接着され、
前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続された半導体装置において、
前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にあり、
前記第１のＬＳＩチップの少なくとも一辺と前記第２のＬＳＩチップの少なくとも一辺とは近接していることを特徴とする半導体装置。 The first LSI chip and the wiring substrate are flip chip connected through the bump electrodes,
Wherein a surface which is not the circuit formation of the first LSI chip, and a surface which is not the circuit formation of the second LSI chip is bonded,
In the semi-conductor device and the second LSI chip formed with an electrode formed on the wiring board in the wiring is electrically connected by metal wires,
With the surface of the wiring substrate facing the first LSI chip as the horizontal direction, the bump electrodes and the electrodes formed on the second LSI chip are at different positions in the vertical direction,
At least one side of the first LSI chip and at least one side of the second LSI chip are close to each other .
前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続された半導体装置において、
前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にあり、
前記突起電極の接続部断面径は数十μ m 以下であることを特徴とする半導体装置。 The first LSI chip and the wiring substrate are flip-chip connected via the protruding electrodes, and the non-circuit-formed surface of the first LSI chip and the non-circuit-formed surface of the second LSI chip are bonded And
In a semiconductor device in which an electrode formed on the second LSI chip and a wiring formed on the wiring substrate are electrically connected by a metal thin wire,
Said opposing surfaces of said wiring board to the first LSI chip as a horizontal direction, Ri position near differing in the protruding electrode and the second LSI chip electrodes formed on and in the vertical direction,
Wherein a said connecting portion the cross-sectional diameter of the bump electrode is less than several tens of mu m.
前記第２のＬＳＩチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続されており、
前記第１のＬＳＩチップに対向した前記配線基板の表面を水平方向として、前記突起電極と前記第２のＬＳＩチップに形成された電極とが鉛直方向において異なる位置にある半導体装置の製造方法であって、
前記第１のＬＳＩチップと前記配線基板との間に封止樹脂を注入したのち、
前記金属細線をワイヤボンドにより電気的に接続することを特徴とする半導体装置の製造方法。 The first LSI chip and the wiring substrate are flip-chip connected via the protruding electrodes, and a second LSI chip which is equal to or smaller than the surface of the first LSI chip on which the circuit is not formed and the first LSI chip. The circuit of the circuit is not formed with the
The electrodes formed on the second LSI chip and the wirings formed on the wiring substrate are electrically connected by metal thin wires,
A method of manufacturing a semiconductor device, wherein the protruding electrodes and the electrodes formed on the second LSI chip are at different positions in the vertical direction, with the surface of the wiring substrate facing the first LSI chip as the horizontal direction. ,
After injecting a sealing resin between the first LSI chip and the wiring substrate,
A method of manufacturing a semiconductor device, comprising electrically connecting the thin metal wires by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002163925A JP3558070B2 (en) | 2002-06-05 | 2002-06-05 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002163925A JP3558070B2 (en) | 2002-06-05 | 2002-06-05 | Semiconductor device and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000271113A Division JP3581086B2 (en) | 2000-09-07 | 2000-09-07 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004115273A Division JP2004207760A (en) | 2004-04-09 | 2004-04-09 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003031763A JP2003031763A (en) | 2003-01-31 |
| JP3558070B2 JP3558070B2 (en) | 2004-08-25 |
| JP2003031763A5 true JP2003031763A5 (en) | 2004-12-16 |
Family
ID=19195013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002163925A Expired - Fee Related JP3558070B2 (en) | 2002-06-05 | 2002-06-05 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3558070B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3718205B2 (en) * | 2003-07-04 | 2005-11-24 | 松下電器産業株式会社 | Chip stacked semiconductor device and manufacturing method thereof |
| JP4538830B2 (en) * | 2004-03-30 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2002
- 2002-06-05 JP JP2002163925A patent/JP3558070B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4998268B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7871865B2 (en) | Stress free package and laminate-based isolator package | |
| US7420814B2 (en) | Package stack and manufacturing method thereof | |
| CN101345199B (en) | Packaging structure and its forming method | |
| JP2015523743A (en) | BVA interposer | |
| US7504728B2 (en) | Integrated circuit having bond pad with improved thermal and mechanical properties | |
| CN103137582B (en) | Projection wire direct coupled structure in packaging part | |
| US20130334684A1 (en) | Substrate structure and package structure | |
| JP4492233B2 (en) | Semiconductor chip mounting structure and semiconductor chip mounting method | |
| US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
| JP2003007902A (en) | Electronic component mounting substrate and mounting structure | |
| US6979591B2 (en) | Connection of integrated circuits | |
| US9508670B2 (en) | Semiconductor device including semiconductor chips stacked via relay substrate | |
| JP2000277649A (en) | Semiconductor and manufacture of the same | |
| KR100533847B1 (en) | Stacked flip chip package using carrier tape | |
| JP2000208675A (en) | Semiconductor device and its manufacture | |
| JP2003031763A5 (en) | ||
| JP3824545B2 (en) | Wiring board, semiconductor device using the same, and manufacturing method thereof | |
| JP2001177049A (en) | Semiconductor device and ic card | |
| KR20100002870A (en) | Method for fabricating semiconductor package | |
| JP2004363319A (en) | Mount substrate and semiconductor device | |
| JPH0786340A (en) | Connection of semiconductor element | |
| JP4696712B2 (en) | Semiconductor device | |
| JP4090906B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2007059430A (en) | Semiconductor device |