TW201448467A - Integrated circuit and method with digital power gating - Google Patents

Abstract

A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digtial control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Description

Integrated circuit with digital power gate control system and control method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a power supply gating, and more particularly to a gating control voltage for digitally controlling a circuit, the circuit comprising rapidly and gently lowering a supply voltage, the regulated supply voltage being sufficient to maintain the circuit It is in its own state and reduces leakage current, and increases the supply voltage quickly and gently under recovery operation.

Complementary MOS (COMS) circuits consume less power and are more dense than other types of integrated circuits, so CMOS technology becomes the dominant type of digital circuits. A CMOS circuit has a combination of an N-channel device (NMOS) and a P-channel device (PMOS) or a complex transistor. Between the gate and the source of each transistor, depending on the design, size, material, and process. Has a corresponding threshold voltage. The design and manufacturing techniques of integrated circuits reduce operating voltage and device size. When the device size and voltage level are reduced, the channel length and oxide thickness of each device are reduced. During the manufacturing process, if the gate material is changed, the threshold voltage can be lowered, but the leakage current is increased. Leakage current refers to the current flowing between the drain and the source when the voltage between the gate and the source is less than the threshold voltage of the CMOS device. In the conventional dynamic environment architecture, leakage current causes 15% to 30% of the total power loss.

During a specific time period and/or under certain circumstances, A partial circuit of a CMOS circuit or a CMOS circuit may not be required to operate normally and thus be idle. Since the flowing leakage current consumes valuable power, it is wasteful and inefficient to maintain a full power supply to idle circuitry. For CMOS technology, leakage current can be reduced by reducing the bulk voltage of the CMOS device or the voltage of the body connection. However, for the current 40nm and 28nm CMOS technologies, the conventional method cannot effectively reduce the leakage current.

The invention provides a digital power gate system for controlling a supply voltage of a functional circuit for reducing the supply voltage of the functional circuit to a state retention level for reducing leakage current while maintaining a digital state of the functional circuit . The functional circuit can be of any type, such as a microprocessor core...etc. An integrated circuit has a non-gated (or integrated) supply bus and a gated supply bus. The gated control busbar provides a gated supply voltage. The digital power brake system has multiple gate control devices and a power gate control system. Each gate control device has a current terminal pair and a control terminal. The current terminal pair is coupled to the integrated supply bus bar and the gate control supply bus bar. Each control terminal is controlled by at least one bit of a digital control value. Each control bit controls a corresponding portion of one of the gate devices. The power gating control system continuously adjusts the digital control value and performs power gating control to reduce the voltage of the gating control supply bus to the state retention voltage level, and the state retention voltage level can retain a digital state of the functional circuit, To reduce leakage current.

In a possible embodiment, one bit of the digital control value controls a number of gate devices, while the other bits are binary weighted. The power gating system may include a digital adjuster. The digital adjuster integrates a digital adjustment value and a digital control value in each continuity adjustment cycle to reduce the gate control supply. The voltage of the busbar until the voltage of the gated supply busbar is equal to the state reserve voltage level. Under power gating, the digital adjustment value maintains a fixed gain. For example, the digital adjustment value is a displacement result of the digital adjustment value, and the digital adjustment value is then integrated into the current digital control value to update the digital control value.

Under power gating, adjust the digital adjustment value to update the gain, such as when the digital control value reaches a certain preset value or when the voltage of the gating supply bus bar reaches a certain voltage threshold. A voltage compensator compares the voltage of the gated supply busbar to at least one threshold voltage level. The threshold voltage level includes a state retention voltage level.

Under power gating, adjust the adjustment rate, such as when the digital control value reaches a certain value or when the voltage of the gating control bus bar reaches a certain level. For example, when the voltage of the gated supply busbar reaches a final voltage level, the adjustment rate may be lowered.

A clock signal can be used to control the adjustment rate. A clock controller generates a clock signal and changes the period of the clock signal to control the adjustment rate. For example, the period of the clock signal starts at a lower value (to increase the adjustment rate), and then the period of the clock signal is increased to slow down the change of the voltage of the gate control supply bus under the power gating. speed. The period of the clock signal is adjusted based on a number of coefficients or thresholds. In a possible embodiment, the period of the clock signal is adjusted based on the digital control value itself. For example, under power gating, the digital control value is reduced. For certain preset conditions or programmable digital control values, the period of the clock signal is increased. The period of the clock signal is adjusted according to the voltage threshold of the voltage supplied to the bus bar by the gate. For example, when the gate is supplied When the voltage of the bus bar reaches a certain voltage critical level, the period of the clock signal (such as an increase period) is adjusted to control the rate of change of the voltage of the gate control supply bus, and the specific voltage threshold level is greater than the state reserve voltage level.

Many control factors may be stylized. The number of threshold voltages can be any value, and any number of threshold voltages can be used depending on the particular architecture. At least one comparator compares the gated supply voltage (eg, VDD1) with any number of threshold voltages for adjustment operations, such as adjusting gain (to control the amount of adjustment) and/or adjusting the clock period (to control the regulation rate) ). Programmable fuses or scan values...etc. can be used to adjust the corresponding operating factors and values to control the power gating function. For example, a difference value and/or a total value can be adjusted for digital control values (ie, gain) under power gating or recovery operations. It is possible to program additional clock shift values to adjust the clock cycle under power gating.

In one embodiment, an integrated circuit has at least one functional block, each block having a voltage supply input and a digital power gate system. Each voltage supply input is coupled to a corresponding gate supply bus. Each digital power brake system controls the supply voltage of the gate supply bus. Each of the gate devices can be implemented in a suitable manner, such as a PMOS or NMOS transistor, and the like. The integrated circuit may include a power supply controller. The power controller causes a function block to perform an idle mode, and turns off a clock signal of the function block, and triggers a gate control signal for enabling the power gating system to reduce the voltage supplied to the function block by the gate control supply busbar to A state retains the voltage level.

In another possible embodiment, a method is provided for power gating a supply voltage, the supply voltage being provided to a functional block. this method The invention provides a digital control value for controlling a plurality of current devices between a non-gate controlled supply bus and a gate control supply bus; triggering a digital control value for controlling a part of the current device for full power supply In the mode, the voltage of the gate control supply bus is clamped into the voltage of the non-gate controlled supply bus; and according to a gate control signal, the power control is performed by periodically adjusting the value of the digital control value until The voltage of the gate control supply busbar reaches a state retention voltage level, and the leakage current can be reduced while maintaining a digital state of the function block.

The above method includes binaryarily weighting a portion of the bits of the digital control value. The above method includes comparing the voltage of the gated supply busbar with a plurality of threshold voltages. The above method may include periodically integrating the digital control value with a digital adjustment value. The above method may include providing a digital control value as a displacement result of the digital control value. The method may include comparing a voltage of the gate control supply bus and at least one threshold voltage; selecting one of the plurality of displacement results of the digital control value as the first digit adjustment value; and when the voltage of the gate control supply bus bar reaches at least At a threshold voltage, another different displacement result of the digital control value is selected. The above method may include selecting another different displacement result of the digital control value when the digital control value reaches a predetermined value.

The method includes comparing the voltage of the gated supply bus and the at least one threshold voltage. The above method includes providing a clock signal for controlling the adjustment of the digital control value. The method includes causing the clock signal to have an initial period, and changing the period of the clock signal when the voltage of the gate control supply bus reaches each threshold voltage, or changing when the digital control value reaches each preset value The period of the clock signal. The above method includes converting a partial bit of a digital control value into a complex number The period adjusts the value and changes the period of the clock signal when the period adjustment value becomes a specific level.

Full power gating can be used if needed. In order to restore the voltage from full power gating operation to normal operation, a recovery operation can be used. Many of the recovery functions can be programmed, such as recovery gain, recovery completion, recovery clock cycle control, and more. For example, in the recovery clock cycle, a fixed recovery clock is selected.

Under the power gating operation, the displacement non-gate control supply voltage is supplied to complete the integrated voltage displacement compensation. The level of the non-gate controlled full supply voltage may cause an unknown final state to retain the voltage level. An integrated control adjuster receives at least one signal to indicate the amount of change in the integrated voltage and adjusts the digital control value to avoid an unknown gate voltage.

100‧‧‧Microprocessor

101~104‧‧‧ core

105~108‧‧‧Power Gate System

109‧‧‧Integrated supply bus

110‧‧‧Power Controller

112‧‧‧ mode adjustment block

114‧‧‧Fuse array

116‧‧‧ memory

201‧‧‧Power Gate Control System

206‧‧‧Gate control supply bus

301‧‧‧ side square

401, 403‧‧‧ gate block

EESDCLK‧‧‧ clock signal

PGATE1‧‧‧Power gating signal

FSB<3:0>‧‧‧ front-end busbar values

PG_KILL_CORE1‧‧‧ signal

PGOOD1‧‧‧Power Ready Signal

PGATE<1:4>‧‧‧Control signal group

701‧‧‧Recovery logic

703‧‧‧OR logic

705‧‧‧Voltage comparison group

707‧‧‧ Clock Generator

709‧‧‧Delephone

711‧‧‧ clock selection box

712‧‧‧Time Decoder

713‧‧‧Power Gate Controller

PG16‧‧ bits

CMP1~CMPN‧‧‧ comparison results

PG_TIME<19:0> ‧ ‧ time value

CB<15:0>‧‧‧ Reversed phase clear value

S<15:0>‧‧‧Setting values

D<15:0>‧‧‧ data values

CB‧‧‧Inverted clear input

S‧‧‧Setting input

D‧‧‧ data input

CK‧‧‧ clock input

801‧‧‧Incremental Control Character Adjuster

803‧‧‧Integrated Control Character Adjuster

805‧‧‧storage group

807‧‧‧Control character logic

901‧‧‧ Current limit

913, 1005‧‧ ‧ adder

905‧‧‧Subtractor

911‧‧‧Valued Decoder

1001, 1109‧‧‧Latch group

1017‧‧‧V_DOWN decoder

1201‧‧‧Single hotspot decoder

1203‧‧‧clock shifter

1205‧‧‧Preset clock selection circuit

1209‧‧‧clock cycle selector

1207‧‧‧Fixed recovery clock selection circuit

PGATE1~PGATE4‧‧‧Power Gate Control Signal

VDD, VSS, VDD0, VSS0, VDD1‧‧‧ voltage

PG_VREF<1:N>‧‧‧reference voltage group

V_DOWN<4:0>, PG_KILL_CORE<1:4>‧‧‧Signal group

PWR_GOOD, PGOOD<1:4>, PG_FU_X, HIER, HIERB, HIGH, RESUME, KILLB, GATE, GATEB, HIGHB‧‧‧ signals

PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204, PG_GATE_BOTTOM205‧‧‧ gate control circuit

PG_CNTRL<16:0>, PG<15:0>‧‧‧ control characters

VDD1_FB, I<16:0>, IN, I<12:0>, I<16:13>, 1, S, 0‧‧‧ input

PG_FU_ADD_GN, PG_FU_SUB_GN, PG_FU_CONST_RES_CLK, PG_FU_RESUME_STOP, PG_FU_HIERB, OPB<15:0>, PGTWO, PGTHREE, PGFOUR, PGFIVE and PGSIX, <*6>VSS0, PG<15:7>, PGSIX, <*5>VSS0, PG<15:5>, SUB<15:0>, FSUB<15:0>, <*2>VSS0:PG<15:3>: PGTWO, <*3>VSS0: PG<15:4>: PGTHREE, <*4>VSS0: PG<15:5>: PGFOUR, <*5>VSS0 :PG<15:6>: PGFIVE, DOP<15:0>, VOP<14:0>: VDD0, DOP<14:0>: VDD0, VOP<13:0>: <*2> VDD0, DOP< 13:0>:<*2>VDD0,<*4>VSS0:<*12>GATEB, VOP<15:0>, OOPB<15:0>, VSS0:VOP<15:1>, <*3> VSS0: PGT<15:0>: VSS0, <*2> VSS0: PGT<15:0>: <*2> VSS0, DTIME<19:0>, PG2T<19:0>~PG8T<19:0> , <*13> VDD0: PGTIMEB<6:3>: <*3> VDD0, SHIFTVAL1~SHIFTVAL4‧‧‧ Value

PG_FU_ENT<10:5>, PG_FU_RESUME_GN<1:0>, PG_FU_RES_PER<1:0>‧‧‧value group

PG_CNTRLA<16:0>, PG_CNTRLB<16:0>‧‧‧ buffer results

O<16:0>, OUT, O<12:0>, O<16:13>‧‧‧ output

I<16>~I<0>‧‧‧Control buffer results

501‧‧‧Buffer group

O<16>~O<0>‧‧‧buffer output control level

502, 504, 506, 508, 602‧‧‧ PMOS transistor group

501‧‧‧buffer

503, 505, 507, 601, 909, 1015, 1003, 1101, 812, 1111, 1113, 1121, 1211, 1301, 1303, 1501, 1503 ‧ ‧ Inverter group

CLK20, C20NS, C40NC, C2.6MS‧‧‧ clock signals

903, 907, 915, 1007, 1009, 1011, 1107, 1413, 1601, 1603, 1605, 1607, 1609, 1611, 1613, 1615, 1617, 1701, 1703 ‧ ‧ multiplexer

917, 1119, 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616‧‧‧ AND gate

1115, 1313, 1315, 1317, 1505, 1507, 1509, 1511, 1409, 1411‧‧‧ NAND gate

919, 1013, 1103, 1105, 1117, 1123, 1305, 1307, 1309, 1311, 1319, 1321, 1323, 1325, 1327, 1329, 1401, 1403, 1405, 1407‧‧‧NOR gate

Figure 1 is a possible embodiment of one of the multi-core microprocessors of the present invention.

Figure 2 is a possible embodiment of one of the core and corresponding power gate systems of Figure 1 of the present invention.

Figure 3 is a possible embodiment of the gate control circuit of the present invention.

Figure 4 is a possible embodiment of one side block of Figure 3 of the present invention.

Figure 5 is a diagram showing one possible embodiment of the gate block of the high-order portion of the process control character of Figure 4 of the present invention.

Figure 6 is a diagram showing one possible embodiment of the gate block of the lower bit portion of the process control character of Figure 4 of the present invention.

7A and 7B are diagrams showing one possible implementation of the power gating control system of Fig. 2 of the present invention example.

Figure 8 is a diagram showing one possible embodiment of the power gate controller of Figures 7A and 7B of the present invention.

9A and 9B are diagrams showing one possible embodiment of the incremental control character adjuster of Fig. 8 of the present invention.

10A and 10B are diagrams showing one possible embodiment of the integrated control character adjuster of Fig. 8 of the present invention.

Figure 11 is a diagram showing one possible embodiment of the control character logic of Figure 8 of the present invention.

Figure 12 is a possible embodiment of a time decoder of Figure 7B of the present invention.

Figure 13 is a view showing one possible embodiment of the clock shifter of Fig. 12 of the present invention.

Figure 14 is a diagram showing one possible embodiment of the preset clock selection circuit of Fig. 12 of the present invention.

Figure 15 is a diagram showing one possible embodiment of the fixed recovery clock selection circuit of Figure 12 of the present invention.

16A and 16B are diagrams showing one possible embodiment of the clock cycle selector of Fig. 12 of the present invention.

Figure 17 is a possible embodiment of the invention for additionally adjusting the gain according to the threshold voltage, wherein the threshold voltage is represented by a comparison signal.

The conventional system uses analog technology for power gating. In the case of full power gating, conventional power gating completely removes the source voltage, thereby losing data and logic states stored by the circuit, such as data stored in the memory or registers of the circuit. In many circuit architectures, it is necessary to preserve the state or data of the circuit for later recovery operations.

In order to maintain the state of the circuit under full power gating, the data or information stored in the circuit can be copied to another storage device or memory, which can maintain data when the circuit enters the power gating. Reference herein to "state" refers to any information or material stored by a circuit having static or dynamic means such as a register, a flip-flop, a latch, a dynamic memory device, and the like. At power-on, the previously stored data is stored back into the circuit before the recovery operation. The above described storage actions are used to store data, such as caches on the wafer, etc., but the power of the storage device or the data stored therein must be removed when the power source is removed. In order to store information before entering the power gating and recovering information under the recovery operation, it takes a lot of time, so from the perspective of execution, the cost of storing and restoring information is quite high. Under the large-scale circuit, such as a microprocessor core, a processor of a system chip, etc., the price of conventional power gating is particularly expensive.

The present invention is not suitable for understanding conventional power gating techniques. Therefore, a digital power control technique has been proposed which has a state recovery function and reduces the supply voltage of a circuit to a final level, which is still sufficient to retain the state and reduce leakage current. A new control system and method for utilizing a digital method under power gating to cause the level of the distributed supply voltage to be equal to a final voltage level. Under the power gate control, the digital control system combines the integrated voltage displacement to temporarily increase the voltage of the gate control supply bus according to the variation of the voltage of the gate supply busbar to avoid the low voltage of the gate control supply busbar. The voltage level is reserved in one state. Under recovery operations, such as in accordance with a recovery indication, the digital control system and method more gradually restores the supply voltage level to its own normal operating voltage level. Additionally, digital control systems and methods may include at least one programmable parameter The number is used to control the operation under power gating and recovery operations. In this embodiment, since the information system is stored in a dynamic device, such as a register, a flip-flop, a latch, a dynamic memory device, etc., the power source is stored and can be restored to the power source. The state before the gate control. Full power gating can also be achieved. The full power gating operation may have at least one stylized parameter.

Figure 1 is a possible embodiment of a multi-core microprocessor of the present invention. Microprocessor 100 includes quad cores 101-104. The cores 101-104 are each coupled to a corresponding power brake system, such as 105-108. Although FIG. 1 only presents cores 101-104, in other embodiments, the number of cores may be greater or less than four. In this implementation, each core may be a microprocessor core, but is not intended to limit the invention. Although the microprocessor core is taken as an example here, it can be understood that any other circuit type or function that requires power gating can use the power gate system. The microprocessor 100 is integrated in an integrated circuit (IC), semiconductor wafer, etc., and may have other circuits (not shown).

The power gate systems 105-108 receive a power gate control signal, such as PGATE1, PGATE2, PGATE3, and PGATE4, wherein the power gate control signals PGATE1, PGATE2, PGATE3, and PGATE4 are collectively referred to as power gate control signal groups PGATE<1:4>. Each power gate control signal independently powers one of the cores 104-104. In a possible embodiment, the cores 101-104 can be powered on at the same time. For example, the power gate control signals PGATE1, PGATE2, PGATE3, and PGATE4 may be replaced or controlled by a single overall control signal. The microprocessor 100 receives an external power supply voltage that is between the source voltages VDD and VSS, wherein the source voltage VSS is a suitable reference voltage level, such as ground. Source voltage VDD and VSS as phase Corresponding integrated supply voltages VDD0 and VSS0. The power gate systems 105-108 receive voltages VDD0 and VSS0. The cores 101 to 104 receive the voltage VSS0. The voltage VDD0 is supplied to a conductive plate or a conductor group, and the conductor group constitutes an integrated supply bus 109.

As shown, the power gate system 105 converts the supply voltage VDD0 into a first gate supply voltage VDD1. The core 101 receives the first gate supply voltage VDD1. The power gate system 106 converts the supply voltage VDD0 into a second gate supply voltage VDD2. The core 102 receives the second gate supply voltage VDD3. The power gate system 107 converts the supply voltage VDD0 into a third gate supply voltage VDD3. The core 103 receives the third gate supply voltage VDD3. The power gate system 108 converts the supply voltage VDD0 into a fourth gate supply voltage VDD4. The core 104 receives the fourth gate supply voltage VDD4.

When the cores 101~104 are operated in a full power mode, the corresponding power gate control signals PGATE1~PGATE4 will be invalidated, and the corresponding power gate systems 105~108 are turned on or enable a preset full power amount. P-type or P-channel components, referred to herein as power gate devices. The preset full power supply is sufficient to effectively clamp the corresponding gate supply voltages VDD1~VDD4 to VDD0 to minimize the impedance path between the voltage VDD0 and the corresponding gate supply voltage, which helps to provide voltage The core of choice.

In a possible embodiment, the P-type power gate device comprises a PMOS transistor, etc. Further, the digital power gating operation is to turn off the selected PMOS transistor for a period of time to reduce the voltage supplied to the core. In another embodiment, an NMOS transistor, etc., may be used as a power gating device and disposed in the power gate systems 105-108 and coupled to the cores 101-104. Between the reference voltage VSS0 and the corresponding local voltage, such as VSS1 to VSS4 (not shown), the local voltages VSS1 to VSS4 are supplied to the cores 101 to 104.

It is well known in the art that in full power mode, large leakage currents will occur in each microprocessor core. Although there are techniques to reduce leakage current, it will cause power loss, such as 15% or more of the total power consumption. It can be known that the cores 101~104 are not started at the same time. Therefore, when at least one of the cores 101-104 performs a power gating operation, it can operate in a low power mode to reduce power loss. In fact, all cores of the multiprocessor architecture in microprocessor 100 are not activated at the same time. Therefore, under normal operation, at least one of the cores 101-104 is subjected to a power gating operation to reduce the overall power consumption of the microprocessor 100.

If the state information is not required to be stored, at least one of the cores 101-104 can be fully powered-backed by a digital power gate system and method to turn off at least one of the cores 101-104. When at least one of the cores 101-104 does not need to operate and does not need to store information, a full power gating operation can be used. However, under power gating operation, even if the core enters the idle mode, the core state needs to be retained for later recovery operations. In a conventional power gating configuration, all states of a core are stored in a memory built into the chip or other similar component (not shown) having a power source. Then, by not supplying the voltage VDD or VSS to the core, the power supply to the core can be effectively stopped. When the core is needed, the power is re-powered to the core, and the state stored in the memory is retrieved and then resumed.

The level used by conventional power gating directly affects overall performance. In particular, since more clock cycles are required, all conversions can be completed, and status information is stored and retrieved in a separate memory. A large delay. Therefore, when power-down and power-up, a large delay will result. If you want to improve the overall effect of the core 101~104, you must reduce the delay.

In the microprocessor 100 of FIG. 1, each of the power supply gate systems 105-108 performs a digital power supply according to the corresponding power gate control signals PGATE1 to PGATE4 (ie, the power gate control signal group PGATE<1:4>). Gate control. When power gating is required for a particular core of cores 101-104, the core will enter an idle mode and the core internal clock will be turned off. Even in an idle state, there is still leakage current, which causes severe power loss. Full power gating will lose the data or information stored in the core. However, according to the trigger condition of the power gate control signals PGATE1~PGATE4, the corresponding PMOS device is turned off to reduce the gate supply voltage supplied to the core for a predetermined time. The final gated supply voltage is less than the full power supply voltage, but maintains core state information and reduces power consumption and leakage current.

If a particular core is to be returned from power gating operation to full power operation, a recovery procedure or operation is required. In particular, the power gate system turns on the PMOS device to increase the supply voltage and supply the increased supply voltage to the core according to the ineffective condition of the power gate control signals PGATE1~PGATE4, which can be programmed by the core. Adjust the length of a specific period. When the core receives the full supply voltage again, it leaves the idle mode and may restart the action.

Both the power-down and power-off power gating times are less than the time required to store and restore core states. Therefore, the time to enter and leave the power gating mode can be minimized, greatly improving overall efficiency.

In a possible embodiment, the supply voltage VDD0 is approximately 1V or 1.05V in the full power mode. It can be understood that the supply voltage VDD0 may vary between 0.95V and 1.15V in a specific power mode. In power gating mode, the gating supply voltage (such as at least one of voltages VDD1 to VDD4) is reduced to 450mV to reduce or minimize leakage current while the core is being retained. It will be appreciated that for different semiconductor technologies, there may be different specific voltage levels, and these particular voltage levels are merely exemplary. The invention can be applied in different voltage level techniques to reduce or minimize leakage current while maintaining the logic state of the circuit (e.g., microprocessor core, etc.).

In a possible embodiment, the microprocessor 100 includes a power controller 110 for providing a plurality of control signals to control the power state and to control the power gating functions of the cores 101-104. If at least one of the cores 101-104 is to be power-gated, the power controller 110 causes at least one of the cores 101-104 to enter an idle mode and turn off the internal clock signal of the corresponding core. Next, the power controller 100 triggers the corresponding power gate control signals PGATE1~PGATE4 (as shown by PGATE<1:4>) for power gating of the corresponding core.

If the core of the power gating is to be restored, the power controller 110 disables the corresponding power gate control signal in the power gate control signal group PGATE<1:4> and waits for a while until the gate supply voltage returns to normal. Operation level and completion of recovery procedures. When any of the power gate systems 105-108 triggers a corresponding power-good signal in the power-good signal group PGOOD<1:4>, the power controller 110 is in accordance with the trigger state of the power-good signal group PGOOD<1:4> It is known that the recovery procedure has been completed, and the gate supply voltage has stabilized at the level of the voltage VDD0. Then, the power controller 110 re-enables the clock signal inside the core, because Therefore, the core may be re-run.

The power controller 110 may further provide a reference voltage group PG_VREF<1:N> for controlling the power gating process performed by the power gate systems 105-108. The reference voltage group PG_VREF<1:N> may have at least one reference voltage. . For a particular structure or device, N can be any number. When N is 1, it means that only a single reference voltage is provided. For example, as long as the digital state of the core can be preserved, when N is 1, the single reference voltage is the final voltage level of the gated supply voltages VDD1 VDD VDD4 to reduce leakage current. In another possible embodiment, when N is 2, it means that two reference voltages, such as PG_VREF_L and PG_VREF_H, are provided. The reference voltage PG_VREF_L indicates the final voltage level of the gate supply voltages VDD1 to VDD4 at the time of power supply gating. The reference voltage PG_VREF_H represents a small voltage level slightly higher than the final voltage level represented by the reference voltage PG_VREF_L.

In other embodiments, a plurality of additional reference voltages may be defined or provided as intermediate control voltage levels and a plurality of final voltages. Additionally, the reference voltage of the reference voltage group PG_VREF<1:N> can be replaced with at least one programmable voltage level. In some embodiments, the reference voltage of the reference voltage group PG_VREF<1:N> is provided by an external source.

The power controller 110 may also provide signal groups V_DOWN<4:0> to the power gate systems 105-108 for adjustment during power gating, as will be described in more detail below. The supply voltage VDD0 is throttled down under some or the following specific operating conditions. Before the level of the supply voltage VDD0 changes, the power controller 110 triggers a signal of the signal group V_DOWN<4:0>, wherein the triggered signal represents the magnitude of the decrease in the supply voltage VDD0. When the power is being controlled, when the gate is powered When at least one of the voltages VDD1 VDD VDD4 falls to a state reserved level, an additional decrease in the voltage VDD0 may cause at least one of the gated supply voltages (eg, VDD1) to drop and fall below a final voltage level. For example, if the final voltage level maintains core state information, the reduction in voltage VDD0 may cause the gated supply voltage to be less than the final voltage level without further correction, thereby preventing core state information from being retained. The signal in signal group V_DOWN<4:0> is used as a one-time adjustment to enable power gate systems 105-108 and to adjust power gating operations. Therefore, it is possible to prevent the gate supply voltage from being lower than the final voltage level.

For example, when it is necessary to turn off the core or does not need to store the state information of the core, the power controller 110 enables a signal corresponding to one of the signal groups PG_KILL_CORE<1:4> for initializing the power supply to a corresponding core. The gate control supply voltage is reduced to zero (or close to zero).

The signal PWR_GOOD is used to indicate that the integrated supply voltage VDD0 has stabilized at its normal operating voltage level. In Fig. 1, the signal PWR_GOOD is generated by the power controller 110, but the signal PWR_GOOD may also be provided externally (e.g., a motherboard...etc.) to indicate that the supply voltage VDD0 is stable and valid. The signal PWR_GOOD may be used to initialize the power controller 110 and the power gating signal before powering up or resetting and before enabling the enable.

Many other programmable control signals PG_FU_X are used to control the mode of power gating operation and operation. The value represented by the symbol FU is defined by a fuse or scan value, etc., for adjusting the corresponding operational parameters and values of the microprocessor 100. The scan value may be data or a scratchpad value that has been written during the test phase of the IC, such as JTAG boundary scan...etc. The described structure provides a number of static and dynamic levels of programmable operation. Under manufacturing or specific equipment, Test operations may be performed empirically and define the corresponding operational parameters. A fuse may then be used to statically program the operating parameters for best results. Scan inputs and fuses may be wire-ORs for enhanced testing and static programming. The power controller 110 may provide a signal PG_FU_X or enable other control signals to control the power gating process.

In this embodiment, mode adjustment block 112 may provide signal PG_FU_X for controlling or adjusting the mode of operation under the power gating function. The mode adjustment block 112 has a fuse array 114 and a memory 116. Either fuse array 114 or memory 116 or integration of fuse array 114 and memory 116 may be used to program at least one of signals PG_FU_X. The fuse array 114 includes a plurality of fuses that may be programmed to statically set at least one of the signals PG_FU_X. For example, the stylization of the fuse can be performed by address selection or by directly coupling a particular fuse to an external pin (not shown), applying sufficient high voltage to blow the fuse. When the fuse is blown, an electrical short can be provided to perform a first mode or a preset mode of operation. When the fuse is not blown, an open circuit characteristic is provided for operation in a second mode or a stylized mode. The memory can set at least one of the signals PG_FU_X statically or dynamically. For example, stylized static memory, such as read only memory (ROM), etc., is used to set at least one of the signals PG_FU_X. Stylized dynamic memory, such as random access memory (RAM), scratchpad, etc., for setting at least one of signals PG_FU_X during operation (such as electrical and/or boundary scan, etc.).

2 is a schematic diagram of the core 101 and power gate system 105 of the present invention. Between each core in Figure 1 and the corresponding power gate system The relationship is the same, so the relationship between the core 101 and the power gate system 105 shown in Fig. 2 can also represent the relationship between the other cores in Fig. 1 and the corresponding power gate system. In the present embodiment, the power gate system 105 includes a power gate system 201 and a plurality of gate control circuits, which are respectively displayed as PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204, and PG_GATE_BOTTOM205. The gate control circuits PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204, and PG_GATE_BOTTOM205 are located above, to the left, to the right, and below the core 101, respectively. Each gate control circuit includes a number of power gating devices. A power gating device is disposed around the core 101. In another embodiment, the power gating device may act as a power gating array and be integrated into the core 101. For at least one of the cores 101 to 104, internal and external gate control devices can be provided.

Core 101 is referenced to voltage VSS0 and includes a gated supply bus 206. The gated supply busbar 206 provides a gated supply voltage VDD1 to the core 101. It is well known in the art that the core 101 has a plurality of PMOS transistors, NMOS transistors, and other circuit components (none of which are shown) for performing processing functions. The CMOS device of the core 101 has a large leakage current under full power conditions. In the present embodiment, the power gating system 201 provides a 17-bit control character PG_CNTRL<16:0>. During power gating, the control word PG_CNTRL<16:0> controls the level of the voltage VDD1, and the level of the voltage VDD1 is related to the voltage VDD0. The voltage VDD1 is fed back to the power gating system 201 via the input terminal VDD1_FB.

The power gating system 201 receives the voltage VDD0. Therefore, when the core 101 performs power gating, the power gating system 201 is still in a power-on state for dimensioning. Power gating and operation. The power gating system 201 receives a clock signal EESDCLK and a 4-bit front-end bus bar value FSB<3:0>. The front-end bus bar value FSB<3:0> indicates the frequency of a bus clock. The clock signal EESDCLK and the front-end bus bar value FSB<3:0> are used to set and adjust the period of at least one internal clock signal (such as PG_CLK). The cycle time of the internal clock signal PG_CLK is the time at which the power gating is performed. The power gating system 201 receives the signal PWR_GOOD. The signal PWR_GOOD is triggered by the power controller 110 to indicate that the supply voltage VDD0 has returned to the normal operating voltage level. When the signal PWR_GOOD is not triggered, the power gating system 201 is reset or initialized. At power-on or reset, the level of voltage VDD1 follows the voltage VDD0 level.

The power gating system 201 receives the signal PG_KILL_CORE1. The signal PG_KILL_CORE1 is one of the signal groups PG_KILL_CORE<1:4>. The power controller 110 provides a signal PG_KILL_CORE1 to the core 101. If the core 101 is to be turned off or the state information of the core 101 is not stored in a low power mode, the power controller 110 triggers a signal PG_KILL_CORE1 for initializing the full power gating of the core 101. At this time, the voltage VDD1 drops. To (or close to) 0V. At power-on, if the signal PWR_GOOD has not been triggered, the signal PG_KILL_CORE1 is ignored.

The power gating system 201 receives a power gating signal PGATE1. The power gating signal PGATE1 is one of the signal groups PGATE<1:4>. The signal group PGATE<1:4> is provided by the power controller 110 to indicate whether the power gating operation of the core 101 is to be woken up or released. When the signal PGATE1 is triggered, it is used to perform power gating initialization on the core 101. When the signal PGATE1 is deactivated, the core 101 leaves the power gating operation and returns to the normal mode.

The power gating system 201 receives the reference voltage group PG_VREF<1:N>. By comparing at least one reference voltage of the reference voltage group PG_VREF<1:N> with the voltage VDD1 (through the input terminal VDD1_FB), it is possible to monitor the progress of the power gating operation and/or return to the normal mode. For example, in a possible embodiment, the power gating system 201 compares the level of the voltage VDD1 with at least one reference voltage to enter and/or exit the power gating operation depending on whether the voltage VDD1 reaches a certain threshold. The invention does not limit the number of reference voltages used to control the power gating.

The power gating system 201 receives the signal group V_DOWN<4:0> for making a one-time adjustment of the control character PG_CNTRL<16:0> (or simply PG_CNTRL) under certain conditions. The power controller 110 may trigger a specific signal of the signal group V_DOWN<4:0> to reduce the level of the voltage VDD0 in a low power state. In some embodiments, an external or internal decoupling capacitor may be present in the core 101 and receive the gated supply voltage VDD1. If there is no decoupling capacitor, the signal group V_DOWN<4:0> is not needed, or the signal group V_DOWN<4:0> is ignored. However, if there is a decoupling capacitor, or if the core has a large capacitance value, the large capacitance value will affect the resistance-capacitance (RC) time coefficient, especially if the voltage VDD0 is also reduced, in this case. The voltage VDD1 can be adjusted by the control character PG_CNTRL. C in the RC time coefficient refers to the total capacitance in the core 101, and R refers to the total impedance of the power gating device coupled between the voltages VDD0 and VDD1. When the power gating device is turned on or off, it will affect the total impedance, which in turn affects the RC time factor.

The power gating system 201 detects the trigger condition of the signal group V_DOWN<4:0>, and adjusts the control character and the voltage VDD1 according to the RC time coefficient. To compensate for the RC time factor, to ensure immediate response, and to avoid the level of voltage VDD1 at an unknown level. This prevents the level of the voltage VDD1 from being lower than a predetermined minimum level (such as the final voltage level capable of storing the state), and avoids losing state information stored in the core 101.

When the voltage VDD1 is at the normal operating level, the power gating system 201 triggers a power-good signal PGOOD1 and provides a power-good signal PGOOD1 to the power controller 110. The power-good signal PGOOD1 is one of the above-mentioned signal groups PGOOD<1:4>. In an embodiment, when the power gating operation is performed, the most significant bit (MSB) of the control character PG_CNTRL<16:0>, that is, the control bit PG_CNTRL<16> is turned off or not triggered, Turn off the corresponding complex PMOS device. When the most significant bit or the control bit PG_CNTRL<16> is triggered, the recovery process is performed. The signal PGOOD1 or the direct trigger signal PGOOD1 can be derived by controlling the bit PG_CNTRL<16:0>.

The power gating system 201 receives the signal PG_FU_X for adjusting the corresponding operating parameters and values, and the like. These parameters can be programmed and can be set by means of fuses, scans, etc. The signal with the symbol GN is used to adjust the gain of the corresponding operating parameter or value. For example, the value PG_FU_ADD_GN adjusts a total value for increasing the control character PG_CNTRL (eg, in the power gating mode, the static retention voltage level), and the value PG_FU_SUB_GN adjusts a difference value to reduce the control character PG_CNTRL (as in power gating mode). Under voltage modulation, the sum total value and the difference value are dynamic gains.

Under power gating operation, if voltage VDD1 reaches a certain threshold For voltage, use the value PG_FU_HIERB to adjust the time base or adjustment period. In one embodiment, when the voltage VDD1 drops to a critical level, the binary signal HIER (which will be described later) is triggered, the critical level is higher than a final voltage level, and the final voltage level can retain the core data or state. It is represented by a low critical level (HIGH). When the signal HIER is triggered, the period of the clock signal PG_CLK is increased to reduce the adjustment speed, and the period of the clock signal PG_CLK is related to the length of the above adjustment time. In the case where the value PG_FU_HIERB is not supplied or is not triggered, the adjustment time is a preset value. Further, the value PG_FU_HIERB is used to change the period size of the clock signal PG_CLK.

In the power gating operation, the clock signal PG_CLK can be adjusted using the fuse or scan value. For example, each value of the value group PG_FU_ENT<10:5> is set by the fuse to change the period of the clock signal PG_CLK. In a possible embodiment, the period of the clock signal PG_CLK can be adjusted by different parameters of a particular architecture. In an embodiment, the capacitance of a particular core may increase due to external capacitance, etc., and thus the RC time coefficient will increase under power gating operation. The extra value may increase the RC time factor, thus slowing down the response speed of the adjustment action. The value group PG_FU_ENT<10:5> has a programmable function to compensate for additional capacitance values under power gating operation.

When a signal RESUME is triggered, a number of fuses or scanning parameters can be used to enter the recovery operation and leave the power gating operation. The signal RESUME is typically triggered according to the signal PGATE1 or _PG_KILL_CORE1. The signal RESUME is invalidated during some or all of the time of the power gating operation. In the recovery process, an adjustment value is added to the control character PG_CNTRL. The value group PG_FU_RESUME_GN<1:0> is used to select different sum total values. To adjust the recovery gain, the value group PG_FU_RESUME_GN<1:0> has two values, and the period of the clock signal PG_CLK is adjusted by a fuse or a scanning method. For example, the value PG_FU_CONST_RES_CLK is used to select a predetermined fixed period of the clock signal PG_CLK in the recovery process. The value group PG_FU_RES_PER<1:0> is a programmable 2-bit value that may be used to adjust the period of the clock signal PG_CLK to a fixed value. The preset period must be long enough to return to normal operation without interrupting the operation of the surrounding core or other circuitry. The value PG_FU_RESUME_STOP is a binary value used to indicate that under normal operation, the adjustment of the control character is stopped and the control character is restored to the starting level.

The gate control circuits 202-205 operate in the same principle, and have at least one input terminal and at least one output terminal. The input terminal is configured to receive the integrated supply voltage VDD0, and the output terminal is configured to be coupled to the gate control supply bus bar 206. The gate control supply bus 206 transmits the gate supply voltage VDD1. In the present embodiment, the power gating system 201 generates control characters PG_CNTRL<16:0> for controlling the level of the voltage VDD1 in the power gating operation described above, and the level of the voltage VDD1 is relative to the voltage VDD0. The input terminals I<16:0> of the gate control circuits 202 and 203 receive control characters PG_CNTRL<16:0>. After the gate control circuit 202 buffers the control characters PG_CNTRL<16:0>, the buffered result PG_CNTRLA<16:0> is output to the corresponding input terminal I<16 of the gate control circuit 204 through the output terminal O<16:0>: 0>. Similarly, after the gate control circuit 203 buffers the control characters PG_CNTRL<16:0>, the buffered result PG_CNTRLB<16:0> is output to the corresponding input terminal I of the gate control circuit 205 through the output terminal O<16:0>. <16:0>.

Symbols I and O represent the input and output control characters CNTRL, respectively. After the gate control circuits 202 and 203 buffer the control character CNTRL, the buffer results CNTRLA and CNTRLB are generated, respectively. The operation principle of the gate control circuits 204 and 205 is the same as that of the gate control circuits 202 and 203, even if the buffering results generated by the gate control circuits 204 and 205 are not displayed. Here, the control character PG_CNTRL<16:0> may also be referred to as PG_CNTRL unless a 16-bit element of the control character PG_CNTRL<16:0> is used.

The gate control circuit (e.g., 202-205) shown in Figure 2 is disposed in a discrete manner around a large circuit (e.g., core 101), but is not intended to limit the invention. For example, the same or different gating circuits may be fully integrated into the circuit or core, or some of the gating circuits may be integrated into the circuit while another portion is placed around the circuit. Regardless of the structure of the gate control circuit, each gate control circuit has a partial distribution circuit for transmitting each bit of the control character PG_CNTRL<16:0> to the corresponding control terminal of the power gating device. The distribution circuit typically has a number of buffers or transmitters, etc., to maintain the signal correctness of each bit of the control character.

Fig. 3 is a simplified schematic diagram of the gate control circuit PG_GATE_TOP202 of the present invention, and the operation principle of the gate control circuit PG_GATE_TOP202~205 is the same. The gate control circuit PG_GATE_TOP 202 has four independent and substantially identical side blocks 301. The side block 301 is daisy chained together by the control character PG_CNTRL (as between PG_CNTRL<16:0> and PG_CNTRLA<16:0>). Each side block 301 receives the control character PG_CNTRL or a buffered result through the corresponding input terminal I<16:0>, and outputs the buffering result through the output terminal O<16:0>.

Each side block 301 further includes an input terminal IN and an output terminal OUT. The input terminal IN is coupled to the integrated supply bus 109 for receiving the voltage VDD0. Output The OUT is coupled to the gate supply bus 206 for generating a voltage VDD1. In general, each bit of the control character PG_CNTRL<16:0> is coupled to a device between VDD0 and VDD1, and can know the capacitance or impedance value between the supply voltages. When many devices (or all devices) are turned on, the capacitance is at a maximum and the impedance is minimized, and therefore, the voltage VDD1 is effectively clamped to the voltage VDD0, assuming that the voltage VDD1 is approximately equal to the voltage VDD0. At some or all of the time of the power gating operation, all devices are turned off, and therefore, the level of the voltage VDD1 falls with respect to the voltage VDD0.

Figure 4 is a possible embodiment of a side block 301 of the present invention. Side block 301 has two separate and identical gate blocks 401. The gate block 401 is daisy-chained together by the buffering result of the high-order portion PG_CNTRL<16:13> of the control character or the high-order portion PG_CNTRL<16:13>. Each gate block 401 includes a control character input I<16:13> and a control word output O<16:13>. Side block 301 has other gate blocks 403. The gate block 403 receives the low-order portion PG_CNTRL<12:0> of the control character through the input terminal I<12:0>, and outputs the buffer result of the low-order portion PG_CNTRL<12:0> through the output terminal O<12:0>. . Each of the gate blocks 401 and 403 has an input terminal IN and an output terminal OUT. The input terminal IN is coupled to the integrated supply bus 109 for receiving the voltage VDD0. The output terminal OUT is coupled to the gate supply bus bar 206 for providing the voltage VDD1.

Figure 5 is a possible embodiment of a gate block 401 for processing the high bit portion of the control character. The highest control bit PG_CNTRL<16> of the control character controls the buffer result I<16>. The highest control bit PG_CNTRL<16> is processed by the buffer group 501 (such as 8 serial buffers), and a The buffer output control level is O<16>. The plurality of PMOS transistor groups 502 are connected in parallel, and the gate of each PMOS transistor group 502 is coupled to the output of a corresponding buffer 501 for receiving a corresponding buffering result (the highest control bit PG_CNTRL< 16> buffering results). The source of the PMOS transistor group 502 receives the voltage VDD0, and its drain provides the voltage VDD1. In the present embodiment, when the highest control bit PG_CNTRL<16> is triggered to the low level, the PMOS transistor group 502 is turned on to provide a corresponding current path between the voltages VDD0 and VDD1. When the highest control bit PG_CNTRL<16> is triggered to a high level (or an invalid level), the PMOS transistor group 502 is not turned on.

In one embodiment, each PMOS transistor group 502 has 768 parallel PMOS transistors. Each gate block 401 has eight PMOS transistor groups 502, each side block 301 has two gate blocks 401, and each of the gate control circuits 202-205 has four side blocks, so that there are a total of 196,608 PMOS transistors. (large average 200K transistors) are connected in parallel and are controlled by the highest control bit PG_CNTRL<16>. Since the gate control circuit, side blocks, and gate blocks are dispersed around the core 101 and have the same architecture around each core, each core of the microprocessor 100 is surrounded by a relatively large number of PMOS devices. The PMOS devices are controlled by the highest control bit PG_CNTRL<16>. In one embodiment, each PMOS transistor is approximately 2 microns in micron size, and therefore, the transistor material is approximately 393216 microns (about 400 K microns) and is controlled by the highest control bit PG_CNTRL<16>.

The next most significant control bit PG_CNTRL<15> of the highest control bit PG_CNTRL<16> of the control character controls the buffer result I<15>, and the control bit PG_CNTRL<15> is buffered by the inverter group 503. Inverter group 503 The output is coupled to the PMOS transistor group 504. The transistors in the PMOS transistor group 504 are connected in parallel, and their gates are coupled to the output terminals of the corresponding inverter group, the source thereof receives the voltage VDD0, and the drain thereof generates the voltage VDD1. In the present embodiment, when the control bit PG_CNTRL<15> is low, each transistor in the PMOS transistor group 504 is turned on to provide a current path between VDD1 and VDD0. When the control bit PG_CNTRL<15> is at a high level, each transistor in the PMOS transistor group 504 is turned off.

In one possible embodiment, each PMOS transistor group 504 has 64 parallel PMOS transistors. Each gate block 401 has four PMOS transistor groups 504, each side block 301 has two gate blocks 401, and each of the gate control circuits 202-205 has four side blocks, so that there are a total of 8,192 PMOS transistors. Parallel to each other and controlled by the control bit PG_CNTRL<15>. In one embodiment, each PMOS transistor has a size of about 2 micron, and therefore, the transistor material requires approximately 16384 microns and is controlled by control bit PG_CNTRL<15>. Therefore, although the number of PMOS devices controlled by the control bit PG_CNTRL<15> is extremely smaller than the number of PMOS devices controlled by the control bit PG_CNTRL<16>, there are still many surrounding each core of the microprocessor 100. PMOS devices that are controlled by control bit PG_CNTRL<15>.

The next most significant control bit PG_CNTRL<14> of the control bit PG_CNTRL<15> of the control character controls the buffer result I<14>, and the control group PG_CNTRL<14> is buffered by the inverter group 505. The output of the inverter group 505 is coupled to the PMOS transistor group 506. The transistors in the PMOS transistor group 506 are connected in parallel, and their gates are coupled to the output terminals of the corresponding inverter group, the source thereof receives the voltage VDD0, and the drain thereof supplies the voltage VDD1. In this embodiment, when the control bit When the PG_CNTRL<14> is low, each transistor in the PMOS transistor group 506 is turned on to provide a current path between VDD1 and VDD0. When the control bit PG_CNTRL<14> is at a high level, each of the transistors in the PMOS transistor group 506 is not turned on.

In one possible embodiment, PMOS transistor group 506 has 64 parallel PMOS transistors. Each gate block 401 has two PMOS transistor groups 504, each side block 301 has two gate blocks 401, and each of the gate control circuits 202-205 has four side blocks, so that there are a total of 4,096 PMOS transistors. Parallel to each other and controlled by the control bit PG_CNTRL<14>. In one embodiment, each PMOS transistor has a size of about 2 micron, and therefore, the transistor material is about 8192 microns and is controlled by control bit PG_CNTRL<14>. Therefore, although the number of PMOS devices controlled by the control bit PG_CNTRL<14> is half the number of PMOS devices controlled by the control bit PG_CNTRL<15>, the periphery of each core of the microprocessor 100 remains There are a number of PMOS devices that are controlled by the control bit PG_CNTRL<14>.

The next most significant control bit PG_CNTRL<13> of the control bit PG_CNTRL<14> of the control character controls the buffer result I<13>, and the inverter group 507 buffers the control bit PG_CNTRL<13>. The output of the inverter group 507 is coupled to the PMOS transistor group 508. The difference is that the PMOS transistor group 508 has only 64 PMOS transistors. In the present embodiment, a total of 2,048 PMOS transistors are connected in parallel and controlled by the control bit PG_CNTRL<13>. In one embodiment, each PMOS transistor of transistor group 508 is approximately 2 microns in micron size, and thus the transistor material is approximately 4096 microns and is controlled by control bit PG_CNTRL<13>. Therefore, although controlled by control bits The number of PMOS devices of PG_CNTRL<13> is half of the number of PMOS devices controlled by the control bit PG_CNTRL<14>, but there are still many PMOS devices around each core of the microprocessor 100, and the PMOS devices Controlled by the control bit PG_CNTRL<13>.

The most significant bit of the control character, control bit PG_CNTRL<16>, controls approximately 200K PMOS transistors 502 dispersed in gate circuits 202-205 around core 101, requiring approximately 400K micron of transistor material. Control bits PG_CNTRL<15:13> are in binary format, with control bit PG_CNTRL<15> controlling approximately 16,384 micron transistor material, control bit PG_CNTRL<14> controlling approximately 8,192 micron transistor material, control bit PG_CNTRL<13> controls approximately 4,096 microns of transistor material. In this embodiment, when the corresponding control bit is triggered to the low level, the corresponding PMOS transistor can be turned on; when the control bit is triggered to the high level, the corresponding PMOS transistor is not turned on.

Figure 6 is a possible embodiment of a gate block 403 that receives the lower bit portion of the control character. Gate block 403 continues to process the remaining bits PG_CNTRL<12:0> (except for control bit PG_CNTRL<16>, control bits PG_CNTRL<15:00> are in binary format). For the control bit PG_CNTRL<12:0>, the number of PMOS transistors controlled by each bit and/or the transistor material is the number of PMOS transistors controlled by the previous bit and/or the transistor material. half. In addition, the gate of each PMOS transistor is controlled by a corresponding control bit, the source of which receives the voltage VDD0 and the drain of which provides the voltage VDD1.

The other bits of the control character PG_CNTRL<12:0> are in the gate block. The structure in 403 is similar to the control bit PG_CNTRL<13> and includes an inverter bank 601 and a PMOS transistor group 602, except that the number and/or size of the PMOS transistors are adjusted to continue the binary format. The size of the inverter bank 601 depends on the amount of transistor material in each design.

The control bit PG_CNTRL<12> of the control character controls the buffer result I<12>, which is connected to the inverter group 601 and the PMOS transistor group 602. The PMOS transistor group 602 has 64 PMOS transistors. The structure of the control bit PG_CNTRL<12> is similar to the structure of the control bit PG_CNTRL<13>. In each side block 301, there are two gate blocks 401 and one gate block 403. Therefore, the number of transistors controlled by the control bit PG_CNTRL<12> is the transistor controlled by the control bit PG_CNTRL<13>. Half the number to continue the binary format. Each bit of the next control bit PG_CNTRL<11:6> has the same architecture, except that the number of controlled transistors is half of the upper one. As shown, the buffer control bit I<11> controls 32 PMOS transistors in the PMOS transistor group 602; the buffer control bit I<10> controls 16 PMOS transistors in the PMOS transistor group 602; Control bit I<9> controls eight PMOS transistors in PMOS transistor group 602; buffer control bit I<8> controls four PMOS transistors in PMOS transistor group 602; buffer control bit I<7 > Controls two PMOS transistors in PMOS transistor group 602; buffer control bit I<6> controls one PMOS transistor in PMOS transistor group 602.

The next control bit I<5> controls only half of half of the PMOS transistors, such as PMOS transistor 604. In one possible embodiment, the width of the PMOS transistor 604 is only half the width of the PMOS transistor 602, so the PMOS transistor 604 requires only half of the transistor material compared to the PMOS transistor 602. Next control The bit element I<4> controls only 1/4 PMOS transistors, such as PMOS transistor 606. In one possible embodiment, PMOS transistor 606 has only half the width of PMOS transistor 604 and therefore has only half of the transistor material. The next control bit I<3> controls only 1/8 PMOS transistors, such as PMOS transistor 608. In one possible embodiment, PMOS transistor 608 has only half the width of PMOS transistor 606 and therefore has only half of the transistor material. The remaining control bits I<2:0> control only 1/16, 1/32, and 1/64 PMOS transistors, such as PMOS transistors 610, 612, and 614. Although each continuous transistor has a width of only half, it is twice as long. Therefore, the widths of the PMOS transistors 610, 612, and 614 are similar to the width of the PMOS transistor 608 except that the length of the PMOS transistor 610 is twice the length of the PMOS transistor 608, and the length of the PMOS transistor 612 is the PMOS transistor 608. Four times the length, the length of the PMOS transistor 614 is eight times the length of the PMOS transistor 608.

In this embodiment, the control bit PG_CNTRL<12> controls the 2048 micron transistor material, the control bit PG_CNTRL<11> controls the 1024 micron transistor material, and the control bit PG_CNTRL<10> controls the 512 micron transistor material. The control bit PG_CNTRL<9> controls the 256 micron transistor material, the control bit PG_CNTRL<8> controls the 128 micron transistor material, the control bit PG_CNTRL<7> controls the 64 micron transistor material, and the control bit PG_CNTRL <6> Control 32 micron transistor material, control bit PG_CNTRL<5> controls 16 micron transistor material, control bit PG_CNTRL<4> controls 8 micron transistor material, control bit PG_CNTRL<3> control 4 Micron transistor material, control bit PG_CNTRL<2> controls 2 micron transistor material, control bit PG_CNTRL<1> controls 1 micron transistor material, control bit PG_CNTRL<0> controls the 1/2 micron transistor material.

In this embodiment, the size of the PMOS transistor of each branch is gradually reduced, and when the control bit PG_CNTRL<6> is left, only a single transistor remains. Therefore, the width-to-length ratio (W/L) of the PMOS transistor can be adjusted to reduce the transistor material to minimize the binary pattern. For the next control bit PG_CNTRL<5>, its width has been reduced by half, and the widths of the control bits PG_CNTRL<4> and PG_CNTRL<3> are further reduced by half. Therefore, for the remaining 2 bits, the length parameter is variable to complete the binary pattern.

The specific structure and binary dispersion pattern of the above control bits and PMOS devices are one possible implementation, and may also be implemented by other variations. In general, many devices can be distributed around the core and coupled between the voltages VDD0 and VDD1, and when the power gating is performed, the conduction voltage is digitally switched between the supply voltages by conducting or non-conducting devices. The size of the current path. In a digital control method, the level of the voltage VDD1 with respect to VDD0 is changed. In a possible embodiment, the final level of voltage VDD1 must be sufficient to preserve core information during power gating operation to reduce leakage current.

Referring to FIG. 2, under normal operation, the power gating system 201 sets the control character PG_CNTRL to a preset value for clamping the voltage VDD1 to the voltage VDD0. In an embodiment, the bit PG_CNTRL<16, 11:0> of the control character is a low level for turning on the corresponding PMOS transistor, and the remaining bits of the control character PG_CNTRL<15:12> are high. The control bit PG_CNTRL<16:0> is an initial value of 01111000000000000b, where b is a binary representation. As mentioned above, The power controller 110 waits for the core 101 to enter the idle mode, or commands the core 101 to enter the idle mode, then turns off the function clock of the core 101, and enables the signal PGATE1 to perform power gating operation on the core 101. When the signal PGATE1 is triggered, the power gating operation is initialized, so the highest bit PG_CNTRL<16> of the control character is pulled up to the high level to turn off the main PMOS transistor (eg, about 200K). Since the core 101 is in an idle state and a leakage current is generated, when the control bit PG_CNTRL<16> turns off most of the transistor material between the voltages VDD0 and VDD1, the level of the voltage VDD1 does not significantly drop. At this time, only the bit PG_CNTRL<11:0> turns on the transistor material of about 4096 micrometers to maintain the voltage VDD1 sufficiently close to the voltage VDD0. It should be noted that the impedance, the impedance between the voltages VDD0 and VDD1 will be increased, and thus may cause a slight change in the voltage between the voltages VDD0 and VDD1.

The power gating system 201 then begins the bit PG_CNTRL<11:0> of the digital control control character to reduce the level of the gating supply voltage VDD1 to the final voltage level. In each successive step, the impedance between voltages VDD0 and VDD1 increases, so voltage VDD1 decreases until a final voltage level is reached. As described above, when the voltage VDD1 is equal to the final voltage level, the leakage current can be greatly reduced, and the state before the core 101 enters the power gating can be maintained.

Each of the power gate systems 105-108 shown in FIG. 1 selects a control PMOS device for each bit control using each bit of the character PG_CNTRL, wherein the PMOS device surrounds each of the microprocessors 100. Around the core. In a simple digital control architecture, at a fixed time interval, the control character PG_CNTRL is subtracted from a fixed digit adjustment value to achieve the final Voltage level. The gate supply voltage VDD1 generally varies with the value of the control word PG_CNTRL, so when the control word PG_CNTRL is decreased, the gate voltage VDD1 is also reduced. Under the power gating operation, by comparing the voltages VDD1_FB and PG_VREF_L, it is known whether the final voltage level is reached, and when the final voltage level is reached, the value of the control word PG_CNTRL is maintained. However, in the present embodiment, the control character PG_CNTRL may vary with the frequency of the operating clock and react with any further adjustment of the gate voltage.

However, when the PMOS device is turned off, the impedance between the voltages VDD0 and VDD1 will increase (but the capacitance will remain at the same value), so the RC time coefficient will be increased when the voltage VDD1 is adjusted. In the present embodiment, in each new adjustment, it takes a long time to change and stabilize the level of the voltage VDD1. When the adjusted value is too large, or the adjustment interval is too short, the voltage VDD1 may not reach the final voltage level. It must be understood that, in the case of power gating operation, if the core information needs to be maintained, the gate voltage cannot be less than a final voltage level, because if it is less than the final voltage level, the state information of the core 101 cannot be retained. Therefore, the adjustment value must be small enough, and/or the adjustment interval must be long enough to avoid the voltage VDD1 cannot be equal to the final voltage level.

In another embodiment, the adjustment value has a proportional relationship with the control value. In this example, when the control value decreases, the adjustment value will also decrease proportionally according to a fixed adjustment gain. In the present embodiment, the control value is quickly and greatly adjusted at the beginning, and then the control value is gradually reduced. The gate supply voltage VDD1 will vary according to the change in the control value. In the above number In the bitwise embodiment, the control character can be shifted to the right for a proportional adjustment, the control character can be proportionally decreased, and the adjustment value can be obtained. In one embodiment, the control character is shifted right 6 times to provide an adjustment value, which is 1/64 of the control character, and then subtracts the result of the right shift from the control character for proportionally Reduce control characters.

In another embodiment, the length of the adjustment period used to adjust the voltage VDD1 may be adjusted continuously or periodically. In an embodiment, when the period of the power gating clock that determines the adjustment time increases, the adjustment period also increases, and therefore, when the voltage VDD1 reaches the final voltage level, the adjusted frequency is minimized. In a possible embodiment, a clock is generated, which has a known period, and the clock is used to generate a complex clock signal, each clock signal having a different period. When making adjustments, the adjustment period is changed by selecting different clock signals. In another embodiment, the frequency of the clock signal can be adjusted using an oscillator, etc. In other embodiments, the adjustment period can be changed (e.g., increased) over time by changing the period of the clock.

In other embodiments, the adjustment value and the adjustment period may be changed simultaneously with time while starting or leaving the power gating operation.

The adjustment value and/or the adjustment period are preset to provide a fixed voltage adjustment curve at the beginning of the power gating operation or when leaving the power gating operation. In other embodiments, the adjustment values and/or adjustment periods are dynamically adjusted based on at least one of the monitoring inputs. In an embodiment, the gate supply voltage VDD1 is monitored, and the monitoring result is compared with at least one threshold voltage level (such as the reference voltage of the reference voltage group PG_VREF<1:N>), and the adjustment value is adjusted according to the comparison result. And / or adjustment cycle. In another embodiment, according to the control character In itself, an adjustment value and/or an adjustment period can be obtained, for example, the control character is equal to a specific preset control character. For example, when the control character is an initial value, the corresponding PMOS transistor is turned on by the bit PG_CNTRL<11:0>, and the high-order portion of the control character PG_CNTRL<15:12> turns off the corresponding PMOS. A transistor that adjusts the adjustment value and/or adjustment period.

In another possible embodiment, the threshold value and the critical value of the control character are monitored, and the adjustment value and/or the adjustment period are also obtained. The present invention provides a number of variations to the digital power gating operation.

7A and 7B are a possible embodiment of the power gating system 201 of the present invention. The power gating system 201 has a digital adjuster. The digital adjuster digitally adjusts the control character PG_CNTRL to control the voltage level of the gated supply bus 206. The gated supply busbar 206 provides a gated supply voltage VDD1. At some or all times of the power gating operation, or under power recovery operation (such as the incremental control character adjuster 801 of Figure 8), a digital adjustment value is gradually added or subtracted for digital digitization. The adjustment is made, or a large voltage shift (according to the change of the integrated supply voltage VDD0), plus a large digit adjustment value for digital adjustment. The size of the digital adjustment value may depend on the gate control state (gate operation or recovery operation), voltage VDD1, and control character itself. In the continuous adjustment period, the adjustment rate may be dependent on the period of the signal PG_CLK, and the period of the signal PG_CLK may also depend on the gate control state (gate operation or recovery operation), the voltage VDD1, and the control character itself. The power gating system 201 shown in Figures 7A and 7B is merely used to simply show related functional operations and is not intended to limit the invention. For example, in some specific architectures, many control signals may have many versions, including synchronization with available clock signals...etc. Wait. The versions of these particular control signals are not described herein as these control signals are not necessary to complete the present invention.

The power gating system 201 includes recovery logic 701. Recovery logic 701 receives signals PG_KILL_CORE1 and PGATE1 and provides a signal RESUME. In a partial power gating operation, the power controller 110 triggers a signal PGATE1 to cause the power gating circuit 105 to reduce the level of the voltage VDD1 to a final voltage level, such as a state retention level. The preset final voltage level can be any stable voltage level to achieve the above objectives. The method by which the power controller 110 controls the final voltage level selectively programs at least one reference voltage in the reference voltage group PG_VREF<1:N> for controlling the power gating process. The above voltage level is a state reserved level (ie, HIGH is triggered), which reduces leakage current for reducing power loss in a low power state. The state retention voltage level is sufficient to retain data to maintain the state of core 101 of microprocessor 100. When the signal PGATE1 is subsequently invalidated, the recovery logic 701 triggers the signal RESUME to leave the power gating operation and initiates a recovery operation to increase the level of the voltage VDD1 to the level of the voltage VDD0.

When the core 101 enters the full power gating operation, the power controller 110 triggers the signal PG_KILL_CORE1, and the power gate circuit 105 reduces the level of the voltage VDD1 to a level approximately equal to the voltage VSS0 (eg, ground). Under full power gating operation, power loss is minimal, but the state of core 101 and all recoverable core 101 information are lost. In a possible embodiment, signal PG_KILL_CORE1 invalidates (or does not trigger) all of the bits of control character PG_CNTRL<16:0> to turn off all PMOS devices to isolate core 101 from supply voltage VDD0. In a possible embodiment, though However, the priority of the signal PG_KILL_CORE1 is greater than the power gating operation, but the triggering of the signal PG_KILL_CORE1 can also trigger the signal PGATE1. When the signal PG_KILL_CORE1 is subsequently invalidated, the signal PGATE1 is also invalidated, and the signal RESUME is triggered to leave the full power gating operation and initiate the recovery operation.

Recovery logic 701 further receives a signal PG16 and provides a power ready signal PGOOD1. The signal PG16 is essentially the most significant bit PG_CNTRL<16> of the control character. When the signal PG16 is triggered to the low level, it indicates that the recovery process has been completed, and the recovery logic 701 triggers the signal PGOOD1 to a high level to notify the power controller 110 that the recovery process has been completed.

The power gating system 201 includes an OR logic 703. The OR logic 703 receives the signal group V_DOWN<4:0> and provides a signal V_DWN. When at least one of the signal groups V_DOWN<4:0> is triggered, it indicates that the level of the voltage VDD0 starts to drop, such as entering a low power mode. At this time, the signal V_DWN is triggered.

The power gating system 201 has a voltage comparison group 705 for comparing the level of the voltage VDD1_FB with each reference voltage of the reference voltage group PG_VREF<1:N> and providing corresponding comparison signals CMP1 CMPNHN. The comparison signal is usually invalidated to a high level. When the level of the voltage VDD1_FB meets the condition, the comparison signal is triggered to the low level. Each voltage comparator (not shown) can be implemented in any suitable manner, such as a sense amplifier...etc. As described above, the voltage VDD1_FB is a feedback result of the voltage VDD1. When the voltage VDD1 is less than the corresponding reference voltage, the comparison signals CMP1~CMPN are triggered to the low level. Therefore, when the voltage VDD1 is smaller than the reference voltage PG_VREF<1>, the ratio The comparison signal CMP1 will be triggered to the low level; when the voltage VDD1 is less than the reference voltage PG_VREF<2>, the comparison signal CMP2 will be triggered to the low level; the rest and so on; when the voltage VDD1 is less than the reference voltage PG_VREF<N>, the comparison The signal CMPN will be triggered to a low level. In a possible embodiment, the reference voltage PG_VREF<1> is the same as the signal PG_VREF_H, and is used to indicate a voltage level higher than the state retention voltage level. When the voltage VDD1 is less than the signal PG_VREF_H, the signal HIER will be triggered to a low level. Similarly, the reference voltage PG_VREF<2> is the same as the signal PG_VREF_L and is used to indicate the state retention voltage level. When the voltage VDD1 is less than the signal PG_VREF_L, the critical signal HIGH will be triggered to a low level. It can be appreciated that during voltage gating, any number of reference voltages or threshold voltage levels can be utilized to compare with voltage VDD1.

The power gating system 201 further includes a clock controller 706. During digital power gating, the clock controller 706 controls the period of the clock signal PG_CLK. In a possible embodiment, the clock controller 706 includes a clock generator 707, a frequency divider 709, a clock selection block 711, and a time decoder 712. In the present embodiment, the clock generator 707 receives the clock signal EESDCLK and the value FSB<3:0>, and outputs the clock signal CLK20. The clock signal EESDCLK may be received by an external source or generated internally by the microprocessor 100. The value FSB<3:0> represents the frequency of a bus clock of the microprocessor system. In this embodiment, the clock signal EESDCLK can be any known frequency, and the clock generator 707 generates the clock signal CLK20 using the clock signal EESDCLK and the value FSB<3:0>, and the clock signal CLK20 has approximately 20 ns cycle time. It can be understood that the known cycle time 20 nanoseconds (ns) can be any other value, and Other suitable known cycle times can be substituted.

The clock signal CLK20 is supplied to the frequency divider 709. The frequency divider 709 generates clock signals C20NS, C40NC, ..., C2.6MS. The clock signals C20NS, C40NC, ..., C2.6MS have corresponding clock cycles for the power gating function. The frequency divider 709 multiplies the period of the clock signal CLK20 by the parameters 2 ⁰ , 2 ¹ , 2 ² , 2 ³ , ..., 2 ¹⁷ to make the clock signals C20NS, C40NC, ..., C2.6MS have 20 ns, respectively. The cycle time of 40ns, 80ns, 160ns, ..., 2.6ms, the cycle time of the clock signal C2.6MS is 2.6ms. In the present embodiment, although 18 clock parameters are controlled by 20 possible control bits, it is not intended to limit the present invention. In other embodiments, multiple control bits can also be utilized to control the same clock frequency if desired. In one possible embodiment, the frequency divider 709 has a toggle flip-flop or a T-type register, etc. (not shown) connected in series. Each latch has twice the cycle time of the previous latch. The clock signals C20NS, C40NC, ..., C2.6MS are provided to the clock selection block 711. The clock selection block 711 uses one of the received clock signals as the signal PG_CLK according to the 20-bit time value PG_TIME<19:0>, and outputs the signal PG_CLK. At the same time, only one bit of the time value PG_TIME<19:0> is triggered to select a corresponding clock signal from the corresponding clock cycle. The clock selection block 711 may integrate at least one multiplexer or other selection logic (e.g., NAND/NOR).

According to the value PG_TIME<19:0>, the signal PG_CLK may have a cycle time which is one of cycle times 20 ns, 40 ns, 80 ns, 160 ns, ..., 2.6 ms. In a possible embodiment, at the same time, the value PG_TIME<19:0> will only be triggered by one bit, from 18 cycles. One is selected as the cycle time of the signal PG_CLK. In a possible embodiment, the low select bit (closest to the rightmost significant bit) of the value PG_TIME<19:0> corresponds to the signal PG_CLK (having the largest frequency) with the smallest cycle time. When the selected bit shifts to the left, the cycle time of the signal PG_CLK becomes larger. In other words, the least significant bit of the value PG_TIME<19:0> corresponds to the smallest cycle time (maximum frequency), and the most significant bit of the value PG_TIME<19:0> corresponds to the maximum cycle time (minimum frequency) . Further, in the power gating and recovery operation, the cycle time of the signal PG_CLK determines the adjustment time.

The clock generator 707 may further receive signals PGATE, V_DWN, PG16, and PG_KILL_CORE1 for controlling the operation of the signal PG_CLK. In another possible embodiment, at least one of these signals may be provided. Additionally, the frequency divider 709 and/or the clock selection block 711 perform the same function. Under normal operation, the signal PGATE1 will not be triggered, so the signal PG_CLK will not operate and will be maintained at a ready state value, such as a ready low logic or a logic zero. When signal PGATE1 is asserted to initiate a power gating operation, signal PG16 is deasserted (pushed to a high level as above) to turn off the associated PMOS device, and signal PG_CLK has a selected frequency. When signal PGATE1 is deasserted, recovery logic 701 triggers RESUME to restore voltage VDD1 to its normal operating voltage level. After the recovery process is completed, the signal PG16 is triggered to the low level to stop the operation of the clock signal PG_CLK.

When power gating is performed, when the signal V_DWN is triggered, the signal PG_CLK is briefly at its ready state value until the voltage is adjusted, and when the signal V_DWN is deactivated, the signal PG_CLK is re-started. Since the weight of the signal PG_KILL_CORE1 is higher than the power gating operation, The core 101 can be isolated from the voltage VDD0 by turning off the PMOS device coupled between the voltages VDD0 and VDD1. When the signal PG_KILL_CORE1 is triggered, the action of the signal PG_CLK is stopped (thus, the signal PG_CLK is triggered to its ready state value). When the signal PG_KILL_CORE1 is subsequently invalidated, the signal PG_CLK is again activated and a recovery operation is initiated to restore the voltage VDD1 to its normal operating voltage level.

The time decoder 712 receives a control character value PG<15:0>, an inverted signal HIER or HIERB, a signal RESUME, and a number of guaranteed wire (or scan) coefficients (eg, PU_FU_HIERB, PG_FU_ENT<10:5>, PG_FU_RES_PER<1). :0>, PG_FU_CONST_RES_CLK), and one of the trigger values PG_TIME<19:0> is used to select one of the cycle times between 20ns and 2.6ms as the signal PG_CLK. Inverter 710 receives signal HIER and outputs a signal HIERB. The cycle time of the signal PG_CLK determines the adjustment period of the control character PG_CNTRL<16:0> under power gating operation and upon exiting the power gating operation into recovery operation.

The period of the signal PG_CLK can also be adjusted according to the control character itself. As described above, under power gating, the highest bit PG_CNTRL<16> of the control character is invalidated (eg, triggered to a high level) and the bit PG_CNTRL<11:0> of the control character is initialized (eg, triggered to When the low level is), many PMOS transistors are turned off. An initial period of the signal PG_CLK and a difference value are selected to gradually reduce the control word when the signal PG_CLK is activated. When the control character is reduced to a predetermined value, the period of the signal PG_CLK may be adjusted to the slowest adjustment period, which is previously programmed into the time decoder 712. For example, when the bit PG_CNTRL<11> of the control character is When the level is high (invalid), the period of the signal PG_CLK may be doubled. When the bit PG_CNTRL<10> of the control character is high (invalid), the period of the signal PG_CLK may be doubled again. Therefore, the control character itself is used to adjust the period of the signal PG_CLK. Control characters may be programmed into any value to select the corresponding clock cycle.

The signal HIER indicates that the voltage VDD1 has fallen below the preset threshold voltage, and the signal HIER may be used to adjust the period of the signal PG_CLK. For example, when the signal HIER is triggered to the low level, it indicates that the voltage VDD1 has reached the highest threshold voltage level. Therefore, the clock period of the signal PG_CLK may increase as the level of the voltage VDD1 approaches the final voltage level, and finally The voltage level is indicated by the symbol HIGH to preserve the data and status of the core 101. For example, in some embodiments, voltage VDD1 drops from 1.05V to a final voltage level of 450mV, at which time signal HIER is set to approximately 550mV. The signal HIGH may be set to indicate a final voltage level of 450 mV. Therefore, when the voltage VDD1 reaches the threshold voltage level of 550 mV represented by the signal HIER, the period of the signal PG_CLK is decreased to lower the adjustment frequency to lower the possibility that the voltage VDD1 is lower than the final voltage level. In a possible embodiment, the period of the signal PG_CLK becomes four times the original when the voltage VDD1 reaches the threshold voltage level indicated by the signal HIER.

In other embodiments, other numbers of threshold voltage adjustment cycles PG_CLK may be utilized. For example, the cycle of the signal PG_CLK may be doubled every time the voltage VDD1 drops by 100 mV.

When the signal RESUME is triggered to leave the power gating, the signal PG_CLK may also be adjusted. For example, when the signal RESUME is touched When transmitting, the cycle time of the signal PG_CLK can be reduced to speed up the return of the voltage VDD1 to the normal voltage level. For example, when the signal RESUME is triggered, the selected total value is added to the bit PG<15:0> of the control character to update the control character PG_CNTRL<16:0>. However, it should be noted that since the inrush current may be caused or a current pulse is caused to enter the core 101, the adjustment action should not be too fast, and the charge sharing caused by the current will affect the operation of at least one of the surrounding cores 102-104. . Therefore, when the power-up speed of the core 101 is too fast, the voltage VDD0 is lowered, thereby affecting other cores or surrounding circuits.

The power gating system 201 further includes a power gate controller 713 for providing control characters PG_CNTRL<16:0> and PG<15:0>, and the character PG<15:0> is the control character PG_CNTRL<16. The lower 16 bits of :0> will be explained later in Fig. 11. The power gate controller 713 receives signals PG_FU_X, PGATE1, RESUME, PG_KILL_CORE1, V_DOWN<4:0>, V_DWN, CMP1~CMPN (including HIGH and HIER), and PG_CLK. As described above, the signal PG_FU_X includes the fuse or scan values PG_FU_ADD_GN, PG_FU_SUB_GN, PG_FU_HIERB, PG_FU_ENT<10:5>, PG_FU_RESUME_GN<1:0>, PG_FU_RES_PER<1:0>, PG_FU_CONST_RES_CLK, and PG_FU_RESUME_STOP for adjusting the power control process.

Figure 8 is a possible embodiment of a power gate controller 713. The power gate controller 713 includes an incremental control character adjuster 801, an integrated control word adjuster 803, a register set 805, and a control character logic 807. The register group 805 has a plurality of registers, and each register corresponds to one of the lower 16 bits of the control character. Incremental control character adjuster 801 receives and controls words The character PG<15:0> generated by the meta-logic 807 adds or subtracts an adjustment value to the character PG<15:0> for generating and outputting the control character value OPB<15:0>. The control character logic 807 determines the most significant bit of the control character PG_CNTRL<16>, which will be described later.

The adjustment value is a plus total value or a difference value depending on whether the control character PG_CNTRL<16:0> is to be increased or decreased. It should be noted that in the present embodiment, in order to control the transistor of the P channel (such as PMOS), the bit of the control character PG_CNTRL<16:0> is inverted, and the control character PG_CNTRL<16:0 The increment or decrement of > is taken from the size of the transistor of the P channel. In order to perform power gating, the control character is decremented, for example, depending on whether the signal PGATE1 is triggered or completely deactivated, for example, depending on whether the signal PG_KILL_CORE1 is triggered, and the voltage of the power gating voltage VDD1 is reduced. By incrementing the control word, it is used to increase the level of the voltage VDD1, such as returning to normal operation according to the signal RESUME. In a possible embodiment, the sum total value and the difference value are proportional to the current value of the control character. For example, according to the number y of the control character right shift, the 2y allocation control character is used to determine the adjustment value. The value PG_FU_SUB_GN may be used to change or adjust the number of right shifts y to adjust the adjusted gain under power gating operation. The total value may be defined by a similar method, and the total value may be adjusted using the signal PG_FU_ADD_GN.

The inverter 810 inverts the critical signal HIGH to provide an inverted critical signal HIGHB. The inverter 812 inverts the signal PG_KILL_CORE1 to provide an inverted suspension signal KILLB. The incremental control character adjuster 801 receives the signal PG_KILL_CORE1, the inverted suspension signal KILLB, and the signal RESUME. In this embodiment, the "B" in the symbol indicates that it is an inverted version and does not need to be More explanation. The signals HIGHB, KILLB, and RESUME are used to select an added total value or a difference value to increase or decrease the control character. For example, under power gating, the difference value is selected to reduce the control word and voltage VDD1. When the voltage VDD1 reaches the final voltage level, the signals HIGH and HIGHB will be converted to the opposite state. If the total value is selected, it is used to increase the control character and voltage VDD1. When the voltage VDD1 is greater than the final value, the signals HIGH and HIGHB will transition again and the difference value will be selected again. In this embodiment, the above operation may be repeated until the signal RESUME is triggered. When the state of the signal HIGH can retain data, the total value may be greater than the difference value to reduce the frequency of the oscillator. When the signal RESUME is then triggered, the selected total value will increase the level of the voltage VDD1 to return it to the normal level. The signal KILLB indicates that the full power gating operation is to be performed, and the signal HIGHB can be ignored at this time.

The integrated control character adjuster 803 receives the adjustment control characters OPB<15:0>. When a bit of the signal group V_DOWN<4:0> is triggered, as shown by the symbol V_DWN, the integrated control word adjuster 803 adjusts the control character once. For example, under power gating, when the voltage VDD0 is expected to be reduced, it is necessary to integrate and adjust the increment of the control word to avoid the voltage VDD1 being lower than the final voltage level and causing the state of the core 101 to be lost. When one of the signal groups V_DOWN<4:0> is triggered, the signal V_DWN is also triggered, and the integrated control character adjuster 803 adjusts according to the specific bit that is triggered by the signal group V_DOWN<4:0>. Control character.

In this embodiment, the integrated control character adjuster 803 outputs three different control character values, including an inverted clear value CB<15:0>, a set value S<15:0>, and a data value D. <15:0>. Inverted clear value CB<15:0>, set value S<15:0>, and data value D<15:0> are respectively input to the inverting clear input terminal CB of the register group 805, the set input terminal S, and the data input terminal D. . When the signal PG_CLK is not active, the inverted clear value CB<15:0> and the set value S<15:0> are not synchronously input to the register group 805 during initialization and integration of the control character adjustment. When the signal PG_CLK is activated, the data value D<15:0> is synchronously input to the register group 805. The integrated control character adjuster 803 further utilizes the signals PG_KILL_CORE1 and PGATE1 to generate the signal GATE and its inverted result, such as GATEB. Control character logic 807 receives signal GATE. Signals GATE and GATEB are used to generate an initial control character.

The register set 805 receives the signal PG_CLK and outputs the "temporary" result of the adjusted control character, as indicated by the symbol ROPB<15:0>, the control character may be completely adjusted or not. Control character logic 807 receives control characters ROPB<15:0>. The control character ROPB<15:0> is set asynchronously to an initial value. In the entire process of adjustment, when the signal PG_CLK is stopped, the control word ROPB<15:0> is updated asynchronously with the inverted value CB<15:0> and the set value S<15:0>. Under power gating and recovery operations, the data value D<15:0> is used to cause the control word ROPB<15:0> to be updated as the signal PG_CLK is synchronized.

Control character logic 807 includes a logic circuit for converting control characters ROPB<15:0> into lower bits of control characters, such as PG_CNTRL<15:0>. The control character logic 807 includes a logic circuit that generates the highest bit PG_CNTRL<16> (e.g., PG16) of the control character PG_CNTRL<16:0> based on the signals PG_KILL_CORE1, RESUME, PGATE1, and PG_FU_RESUME_STOP. Control character logic 807 utilizes control The characters ROPB<15:0> and PG_KILL_CORE1 generate the value PG<15:0> and provide the value PG<15:0> to the incremental control character adjuster 801 and the time decoder 712.

Figure 9 is a possible embodiment of an incremental control character adjuster 801 of the present invention. The incremental control character adjuster 801 may have a current limit 901. Current limiting 901 is used as a shield to prevent current from being too high or too low. As described below, the value PG<15:0> is shifted right by a selection number to generate an adjustment value. When the value PG<15:0> reaches a certain low value, the amount of change in the voltage VDD1 may be exceeded. For example, when the voltage VDD1 is at a low level, if the micro-reduction value PG<15:0>, the voltage VDD1 may be made lower than the minimum level at which data can be maintained. In the present embodiment, the current limit 901 limits the minimum value of the value PG<15:0> to 1111111111100000b (such as the inverted digit code of 31).

Current limit 901 receives the value PG<15:0> and provides a number of defined values PGTWO, PGTHREE, PGFOUR, PGFIVE, and PGSIX. Each defined value is used to replace the least significant bit (LSB) of a shifted value to prevent the post-displacement value from being below a predetermined minimum level. In a possible embodiment, the preset minimum level has 32 digit codes. The specific limit value is the number of right shifts based on the displacement value. For example, the defined value PGTWO is used to perform a second right shift; the limited value PGTHREE is used to perform a three-right shift; the limited value PGFOUR is used to perform a four-right shift; the defined value PGFIVE is used to perform five Second right shift; the limited value PGSIX is used to make six right shifts.

The multiplexer (MUX) 903 has an input terminal 0, an input terminal 1, a selection input terminal S, and an output terminal. Input 0 receives the value <*6>VSS0, PG<15:7>, PGSIX. Input 1 receives the value <*5>VSS0, PG<15:5>. The input terminal S is selected to receive the signal PG_FU_SUB_GN. The output of the multiplexer 903 provides a difference value SUB<15:0>. In the present embodiment, although only the single multiplexer 903 is displayed, the symbol "X16" inside the multiplexer 903 represents 16 parallel multiplexers, and each multiplexer processes 1 of 16 bits. Bit. The same marking method is also applied to other multiplexers, latches, scratchpads, and logic gates. The symbol "<*6>VSS0" represents 6 logical zeros to form the value of the leftmost bit, followed by the upper 9 bits of PG<15:0>, ie PG<15:7>, followed by The value PGSIX, the value PGSIX as the least significant bit of the final value. <*6> VSS0, PG<15:7> and PGSIX are the results of the value PG<15:0> shifted to the right six times, and six logical zeros are inserted on the leftmost side, and the value PGSIX is used as the lowest value of the final value. Valid bit. The final value represents 1/64 of the value of the control character PG<15:0> (ie, reduced to a preset limit value). The values <*5>VSS0, PG<15:5> are formed in the same way, the difference is only that the right bit is shifted by 5 bits, and the limit value is not used. Therefore, the value <*5>VSS0:PG<15:5> indicates 1/32 of the control character PG<15:0>.

The preset value PG_FU_SUB_GN is logic 0, so the values <*6>VSS0, PG<15:7> and PGSIX are preset values of the difference value SUB<15:0> (such as the inverted output of the multiplexer 903). , which represents a gain of 1/64 of the value of the control character value PG<15:0>, that is, the reduced adjustment value. When the preset value PG_FU_SUB_GN is triggered to logic 1, the value <*5>VSS0:PG<15:5> will be used as the difference value SUB<15:0> (after inversion), which indicates the control character value PG< The gain of 1/32 of the value of 15:0>, that is, the reduced adjustment value.

The input terminal A of the 16-bit subtractor 905 receives the control character PG<15:0>, whose input B receives the difference value SUB<15:0>. The subtracter 905 subtracts the value of the input terminal A from the value of the input terminal B, and provides the difference value FSUB<15:0> from the output terminal. In the present embodiment, based on the difference gain value PG_FU_SUB_GN, the difference value FSUB<15:0> indicates 1/64 or 1/32 of the control character PG<15:0>.

The sum gain can also be defined in the same way, but under power gating and recovery operations, a large amount of sum gain is generated for selection. The multiplexer 907 has input terminals 0 to 3, respectively receiving gain values <*2>VSS0: PG<15:3>: PGTWO, <*3> VSS0: PG<15:4>: PGTHREE, <*4> VSS0 : PG<15:5>: PGFOUR and <*5>VSS0: PG<15:6>: PGFIVE, the above gain values represent the added gain of 1/4, 1/8, 1/16 and 1/32, respectively. And each has a corresponding least significant bit limit value. The multiplexer 907 outputs the inverted bit and supplies it to the inverter 909. The inverter 909 inverts the output of the multiplexer 907 and takes the inverted result as an added total value ADD<15:0>. The multiplexers 907 and 903 have the same characteristics, and the multiplexer 907 has the symbol "X16" which is used to represent 16 parallel multiplexers. Similarly, inverter 909 has the sign "X16" and also represents 16 parallel inverters. The value-added decoder 911 selects a gain value based on the signals RESUME, PG_FU_ADD_GN, and PG_FU_RESUME_GN<1:0>. The value-added decoder 911 triggers one of the output signals S0 to S3. The multiplexer 907 outputs a gain value received by one of the input terminals 0 to 3 in accordance with the trigger condition of the output signals S0 to S3.

The value-added decoder 911 triggers an output signal according to the signals RESUME, PG_FU_ADD_GN, and PG_FU_RESUME_GN<1:0>. One of S0~S3 is used to select the value-added gain. The signal PG_FU_RESUME_GN<1:0> only applies to recovery operations when the signal RESUME is triggered to a logic 1. The signal PG_FU_ADD_GN is only used in power gating operations when the signal RESUME is triggered to logic 0.

When the signals RESUME and PG_FU_ADD_GN are both logic 0, the signal PG_FU_RESUME_GN<1:0> may be logic 0 or 1, that is, the unknown state (don't care), therefore, the bit value of the input signal of the value-added decoder 911 00XX, therefore, the value-added decoder 911 triggers the output signal S3 for selecting the value-added gain <*5>VSS0: PG<15:6>: PGFIVE, which is also the 1/32 gain for power gating operation. . When the signal RESUME is logic 0 and the signal PG_FU_ADD_GN is logic 1, the bit value of the input signal of the value-added decoder 911 is 01XX, therefore, the value-added decoder 911 triggers the output signal S2 for selecting the value-added gain <*4 >VSS0: PG<15:5>: PGFOUR, which is 1/16 gain for power gating operation.

When the signal RESUME is logic 1, the bit value of the signal PG_FU_RESUME_GN<1:0> is used to determine the gain of the added total value under the recovery operation. In this embodiment, when the bit values of the signals PG_FU_RESUME_GN<1:0> are 00, 01, 10, and 11, respectively, the value-added decoder 911 triggers the output signals S3 to S1 to select <*5, respectively. >VSS0:PG<15:6>: PGFIVE (or 1/32 gain), <*4>VSS0: PG<15:5>: PGFOUR (or 1/16 gain), <*3>VSS0: PG <15:4>: PGTHREE (or 1/8 gain) and <*2>VSS0: PG<15:3>: PGTWO (or 1/4 gain).

The input terminal A of the 16-bit adder 913 receives the control character value PG<15:0>, whose input B receives the added value ADD<15:0>. The adder 913 adds up the values received by the inputs A and B (A+B) to provide and output the added total value FADD<15:0>. It should be noted that in order to control the PMOS device, the bit value of the control word is an inverted value, so that the addition can be facilitated by the inverter 909.

The input 0 of the 2-input-multiplexer 915 receives the summed value FADD<15:0>, its input 1 receives the difference value FSUB<15:0>, and its inverted output provides the value OPB<15:0>. The symbol "X16" of the 2-input-multiplexer 915 indicates that the multiplexer 915 is composed of 16 parallel multiplexers. The 2-input-AND gate 917 receives the signals KILLB and HIGHB and provides an output signal to one of the inputs of the 2-input-NOR gate 919. The other input of the 2-input-NOR gate 919 receives the signal RESUME, the output of which is coupled to the selection input S of the 2-input-multiplexer 915. Therefore, when the signal RESUME is logic 1, the 2-input-multiplexer 915 inverts the added total value FADD<15:0> and outputs it to increase the control character PG_CNTRL<16:0> in the recovery operation. . When the signal RESUME is logic 0, as long as the signals KILLB and HIGHB are not all high levels, the 2-input-multiplexer 915 inverts the difference value FSUB<15:0> and outputs it. When the signal PG_KILL_CORE1 is triggered to a high level, the signal KILLB is at a low level for full power gating operation. When the voltage VDD1 falls enough to retain the final critical level of the data, the signal HIGH is at a low level, and therefore, the signal HIGHB is at a high level. Therefore, the 2-input-multiplexer 915 selects the summed value to prevent the voltage VDD1 from decreasing again.

10A and 10B are diagrams of one possible embodiment of the integrated control character adjuster 803 of the present invention. The adjustment control character value OPB<15:0> is provided to the input D of the latch group 1001, and the latch group 1001 has 16 latches. Latch group The output Q of 1001 outputs the latch result OOPB<15:0>. The inverting clock input CK of the latch group 1001 receives the signal V_DWN. When the signal V_DWN is triggered to the low level, the latch group 1001 is in the on mode, the control character value OPB<15:0> is not processed, and the control character value OPB<15:0> is directly used as the latch result OOPB<15. :0>Output. When the signal V_DWN is triggered to the high level, the latch group 1001 switches to the isolated mode, and the latched result OOPB<15:0> of the output is fixed regardless of how the control character value OPB<15:0> changes.

The bit of the latch result OOPB<15:0> is inverted by the 16 inverters 1003 to become another adjustment control character value VOP<15:0>. The value VOP<15:0> is shifted right once and VSS0 (logic 0) is added to form the value VSS0:VOP<15:1>, where VOP<15:1> is the value VSS0:VOP<15: 1> lower 15 bits. Therefore, the value VSS0:VOP<15:1> is 1/2 of the value VOP<15:0>. The input terminal A<15:0> of the 16-bit adder 1005 receives the value VOP<15:0>, Its input B<15:0> receives the value VSS0:VOP<15:1>, and its output provides the value DOP<15:0>, which is 1.5 times the original value VOP<15:0>.

With the values VOP<15:0> and DOP<15:0>, 1.5, 2, 3, 4, and 6 times the original value VOP<15:0> can be provided. As described above, the value DOP<15:0> is 1.5 times the value VOP<15:0>. The value VOP<14:0> is the result of shifting the value VOP<15:0> to the left by 1 bit, and adding the voltage VDD0 to the least significant bit. Therefore, the value VOP<14:0>: VDD0 is twice the value VOP<15:0>. Similarly, the value DOP<14:0>: VDD0 is the result of shifting the value DOP<15:0> to the left by 1 bit, so it is 3 times VOP<15:0>. In addition, the value VOP<13:0>:<*2>VDD0 indicates that the VOP<15:0> is shifted to the left by 2 bits. If you add 2 VDD0 to the far right, it can represent 4 times the value VOP<15:0>. Similarly, the value DOP<13:0>:<*2>VDD0 represents six times the value VOP<15:0>.

The input terminals 0 to 4 of the multiplexers 1007, 1009, and 1011 receive values of 1.5 times, 2 times, 3 times, 4 times, and 6 times of the value VOP<15:0>, respectively. The symbol "X16" of the multiplexers 1007, 1009, and 1011 indicates 16 parallel multiplexers. The input 5 of the multiplexer 1011 receives the original value VOP<15:0>. The 2-input-NOR gate 1013 receives the signals PG_KILL_CORE1 and PGATE1 and outputs an inverted gate signal GATEB. Inverter 1015 receives the inverted gate signal GATEB and produces a signal GATE. The input 5 of the multiplexer 1007 receives the value <*4>VSS0:<*12>GATEB. The input 5 of the multiplexer 1009 receives the value <*4>GATE:<*12>VDD0. The outputs of the multiplexers 1007, 1009, and 1011 respectively provide inverted clear values CB<15:0>, set values S<15:0>, and data values D<15:0> to the previous register group 805. .

The V_DOWN decoder 1017 receives the signal group V_DOWN<4:0> and outputs signals S0 to S5 to the input terminals S0 to S5 of the multiplexers 1007, 1009 and 1011. The signal group V_DOWN<4:0> is the priority decoding. Therefore, if the multi-bit of the signal group V_DOWN<4:0> is triggered at the same time, only the highest one of the signal group V_DOWN<4:0> is triggered. Bit. Therefore, the V_DOWN decoder 1017 decodes the highest bit of the signal group V_DOWN<4:0> and triggers the corresponding output signals S0~S5 for adjusting the control character once. When the signal V_DOWN<0> is triggered, the signal S0 is selected for 1.5 times adjustment. When the signal V_DOWN<1> is triggered, the signal S1 is selected for a 2x adjustment. When the signal V_DOWN<2> is triggered, the signal S2 is selected for use. To make a 3x adjustment. When the signal V_DOWN<3> is triggered, the signal S3 is selected for 4 times adjustment. When the signal V_DOWN<4> is triggered, the signal S4 is selected for 6 times adjustment. When no signal is triggered by the signal group V_DOWN<4:0>, the signal S5 is triggered. The multiplexers 1007, 1009, and 1011 invert the signals received by the corresponding input terminals according to the triggered signals S0 to S5, and output the inverted result.

The integrated control character adjuster 803 has been described in Figures 8 and 10. When powering up the microprocessor 100 and/or the core 101, or when resetting the microprocessor 100 and/or the core 101, the signal group V_DOWN<4:0> will not have a bit triggered, therefore, no The signal V_DWN is triggered. The latch 1001 is in the transmit state, the signal PG_CLK is maintained at a low level, therefore, the register set 805 is inactive, and the V_DOWN decoder 1017 triggers the signal S5 of the multiplexers 1007, 1009, and 1011. Since the register group 805 does not operate, the data output D<15:0> is invalidated. In addition, the input terminals 5 of the multiplexers 1007 and 1009 can also be coupled to the inverting clear input terminal and the set input terminal of the register group 805 for initializing the signal ROPB<15:0> to 1111000000000000b. Since the input terminals 5 of the multiplexers 1007 and 1009 are simultaneously triggered, the inverted clear bit from the multiplexer 1007 will cause the register group 805 to transmit a logic 0, a total of the set bits from the multiplexer 1009. Scratchpad group 805 will be caused to transfer a logic one.

In the present embodiment, the most significant bit of signal PG_CNTRL, signal PG16, controls a particular number of PMOS devices, while the other PMOS devices are controlled by signals PG_CNTRL<15:0>. In this example, the signal PG_CNTRL<15:0> is binary weighted. In this example, under normal operation, signal PG16 controls the important PMOS devices (eg, the maximum number) to effectively The gated supply busbar 206 is clamped to the integrated supply busbar 109, while the other PMOS devices have a lower impact on the level of the voltage VDD1. When the signal PGATE1 is triggered to initialize the power gating operation, the signal PG16 is deactivated to remove the voltage clamping effect, and an appropriate number of PMOS devices are continuously turned on to make the level of the voltage VDD1 approximately equal to the voltage VDD0. Level. While the lower bits PG_CNTRL<15:0> of the control character are used for power gating operations, in other embodiments, other numbers of bits may be used.

In this embodiment, under normal operation, the control character PG_CNTRL<16:0> is 01111000000000000b, so the lower bits of the control character PG_CNTRL<11:0> are low level, and the middle bit PG_CNTRL<15:12 > is high level, therefore, under normal operation, a certain number of PMOS devices are turned on. In this embodiment, under power up, reset, and normal operation, the levels on the gated supply busbar 206 are effectively clamped to the level on the integrated supply busbar 109, and the core 101 may function properly. When the signal PGATE1 is triggered to initialize the power gating, the signal PG16 will be invalidated. When the power gating is initialized, the PMOS device that was originally turned on due to the low bit PG_CNTRL<11:0> is no longer turned on. Therefore, the number of turned-on PMOS devices is reduced to reduce the level of the voltage VDD1 to the final voltage level under power gating operation, and the core state information can be retained. In another embodiment, under the power gating function, the initial values of the control characters PG_CNTRL<16:0> may be adjusted to control more or fewer PMOS devices.

When the signal PGATE1 is triggered for power gating operation, if the signal group V_DOWN<4:0> remains in the untriggered state, the latch 1001 remains in the on state, and the signal PG_CLK maintains the same frequency, To reduce the size of the control character PG_CNTRL<16:0> during power gating. Therefore, the level of the voltage VDD1 is similar to the voltage VDD0. The V_DOWN decoder 1017 triggers the signal S5. Since the signal PG_CLK is in an active state, the value VOP<15:0> of the input terminal 5 of the multiplexer 1011 is selected as the data value D<15:0>, and is supplied to the register group. 805 data input. In this embodiment, under normal power gating operation, the signals ROPB<15:0>, PG<15:0>, and PG_CNTRL<15:0> are adjusted and updated by the continuously triggered signal PG_CLK until the voltage VDD1 The level reaches the final voltage level.

Under power gating, regardless of which bit of the signal group V_DOWN<4:0> is triggered, the signal V_DWN is triggered, causing the latch 1001 to maintain its own output signal and temporarily abort the signal PG_CLK. The V_DOWN decoder 1017 triggers one of the output signals S0~S5, and the multiplexers 1007 and 1009 output signals of one of the input terminals 0~4 according to the triggered signal, so as to utilize different multiples (eg, 1.5, 2). The control characters of 3, 4, and 6 times update the register group 805 asynchronously, thus updating the control characters PG_CNTRL<16:0>. As described above, when a bit of the signal group V_DOWN<4:0> is updated, it indicates a voltage level VDD0 level down, therefore, the control word PG_CNTRL<16:0> is updated, and the level of the voltage VDD1 is increased. Once, to avoid the level of voltage VDD1 being too low.

Figure 11 is a possible implementation of control character logic 807. As described above, control character logic 807 receives the control character ROPB<15:0> temporarily stored by register group 805. The inverter 1101 receives the signal RESUME. The output of the inverter 1101 is coupled to a pair of 2-input-NOR gates 1103 and 1105. The other input of the 2-input-NOR gate 1103 receives the signal ROPB<14>. The other input of the 2-input-NOR gate 1105 receives the signal ROPB<13>. 2 input -NOR gates 1103 and 1105 The output terminals are respectively coupled to the input terminals 1 and 0 of the 2-input-multiplexer 1107. The input terminal S of the 2-input-multiplexer 1107 receives the signal PG_FU_RESUME_STOP, and the output terminal thereof provides a stop signal STP. The reset input terminal R of the set-reset (SR) latch 1109 receives the stop signal STP. The set input S of the SR latch 1109 receives the signal GATE. The signal GATE is used to trigger the control bit ROPB<16> output by the output terminal Q of the SR latch 1109. The signals ROPB<15:0> and ROPB<16> are provided by the value ROPB<16:> to generate the above control character PG_CNTRL<16:0>.

In operation, the signals GATE, RESUME, and ROPB<16> are initially lowered to a low level, and the signals ROPB<13> and ROPB<14> are initially initialized to a high level. Since the signal ROPB<16> is set to a low level under normal operation, the signal PG_CNTRL<16> (ie, the most significant bit PG16) is pulled down to the low level, thus turning on the most PMOS device for the voltage VDD1. The level of the level is equal to the level of the voltage VDD0. When the signal RESUME is low, the 2-input-multiplexer 1017 causes the stop signal STP to be low, regardless of the level of the signal PG_FU_RESUME_STOP. When the power gating operation is initialized, the signal GATE is set to a high level. Therefore, the SR latch 1109 triggers the signal ROPB<16> to a high level, so that a considerable number of PMOS devices are not turned on, and the PMOS devices are coupled. Connected between the voltage VDD0 and VDD1. However, since the core 101 has entered the idle mode, the voltage VDD1 does not vary considerably. When the signal PG_KILL_CORE1 or PGATE1 is triggered to the low level to stop the power gating operation and return to normal operation, the signal GATE changes to a low level, and the signal RESUME changes to a high level. The signals ROPB<13> and ROPB<14> are still at a high level, and therefore, the stop signal STP is maintained at a low level.

In a preset state, the signal PG_FU_RESUME_STOP is at a low level. Therefore, the 2-input-multiplexer 1107 selects the output signal of the 2-input-NOR gate 1105, that is, the inverted result of the output signal ROPB<13>. The signal ROPB<15:0> will be incremented until the signal ROPB<13> is triggered to a low level, therefore, the stop signal STP is triggered to a high level to reset the SR latch 1109, and the signal ROPB<16> Returning to the low level, the signal PG_CNTRL<16> is set to a low level to turn on a number of PMOS devices and clamp the level of the voltage VDD1 to the level of the voltage VDD0. If the number PG_FU_RESUME_STOP is programmed to a high level, the 2-input-multiplexer 1107 selects the output signal of the 2-input-NOR gate 1103. Therefore, the 2-input-multiplexer 1107 outputs the inverted result of the signal ROPB<14>. In other longer recovery processes, the operation is the same except that the stop signal STP is not set to a high level until the signal ROPB<14> is set to a low level. The stop signal is determined by the selected bit PG_CNTRL<16> in the control character, which represents a minimum stop value. In other words, once the control character becomes a specific value, the recovery process can be effectively suspended, and therefore, normal operation may continue.

Once the stop signal STP is high, the SR latch 1109 pulls the signal ROPB<16> from the high level to the low level to clamp the level of the voltage VDD1 back to the level of the voltage VDD0 and enter normal operation. The signal RESUME returns to the low level, and the integrated control character adjuster 803 initializes the control character to 01111000000000000b again, causing the signals ROPB<13> and ROPB<14> to return to the high level. In a possible embodiment, when the recovery operation is aborted based on the value of the control character, the control character can be reset using a stylized value such as a fuse or scan. Therefore, under normal operation, the level of voltage VDD1 Go back to the level it was originally set to.

In another possible embodiment, to control signal ROPB<16>, signal PGATE1 may be provided to clock controller 706, which may provide a synchronous temporary result (e.g., PGATE1R; not shown). When the signal PGATE1 changes to a high level, the synchronous temporary storage result, such as PGATE1R, also changes to a high level until the end of the recovery operation, when the signal PG16 is at a high level, the signal PGATE1 does not return to the low level. In the present embodiment, the signal PGATE1R (instead of the signal PGATE1) is supplied to the input of the 2-input-NOR gate 1013 for changing the signal GATE. The output signal of the 2-input-multiplexer 1107 is also inverted, and an AND gate (not shown) can be used in place of the SR latch 1109 for receiving signals GATE and STP. In this case, the signal STP will be pulled up to a high level (rather than a low level). Since the signal GATE is at a low level under normal operation, the signal ROPB<16> is also a low level. During power gating, the signal PGATE1 is pulled up to a high level, so the signal GATE changes to a high level. Since the signal STP is also at a high level, the signal ROPB<16> is pulled up to a high level. During the initialization recovery operation, when the signal PGATE1 is deactivated to a low level, the signal GATE1 is maintained at a high level (because it is controlled by PGATE1R, not PGATE1), and the signal STP is also at a high level. When the signal STP is pulled down to the low level to stop the recovery operation, the signal ROPB<16> is also triggered to the low level. When the signal ROPB<16> is low, the pull-down signal PG16 is at a low level, so that the signal GATE returns to a low level to maintain the signal ROPB<16> at a low level. The control character PG_CNTRL<16:0> is returned to the initial value such that the signals ROPB<13> and ROPB<14> are both high level, and therefore, the signal STP is pulled back to a high level (in another embodiment, The output of the 2-input-multiplexer 1107 is inverted, that is, the state of the signal STP in the inverted Figure 11).

The inverter 812 inverts the signal PG_KILL_CORE1 to generate the signal KILLB. The inverter 1111 inverts the signal KILLB for generating the signal KILL. The inverter 1113 inverts the signal KILL to generate another inverted result, such as KILLBB. The NAND gate group 1115 has seven NAND gates (denoted by the symbol "X7"), each NAND gate receives a corresponding bit of the signal ROPB<6:0>, and each NAND gate receives the signal KILLBB. The NAND gate group 1115 generates a low bit signal PG<6:0>. The NOR gate set 1117 has nine NOR gates (denoted by the symbol "X9"), each NOR gate receives a corresponding bit of the signal ROPB<15:7>, and all NOR gates receive the signal KILL. The NAND gate group 1117 provides a high bit signal PG<15:7>. When the signal PG_KILL_CORE1 is low, the control value PG<15:0> is the inverted result of the signal ROPB<15:0>, that is, the control character PG_CNTRL<15:0>. When the signal PG_KILL_CORE1 is high, the low bit signal PG<6:0> will be triggered to a high level, and the high level signal PG<15:7> will be pulled down to the low level. Therefore, the signal PG<15:0> will be It is set to an initial value of 0000000001111111b. Further, the initial value of the signal PG<15:0> is used to restore the operation after the full power gating operation, and when the signal PG_KILL_CORE1 is subsequently pulled back to the low level, the control character PG_CNTRL<16:0> is initialized. As shown in FIG. 8, the integrated control character PG<15:0> is supplied to the incremental control character adjuster 801 and the time decoder 712. Logic gates 1115 and 1117 operate according to the inverted results KILLBB and KILL of logic gates 812, 1111, 1113, and select the bits of the control character according to signal ROPB to form initialization logic, which can be operated at full power gate Next, when the signal RESUME representing the recovery operation is triggered, the value of the control character is initialized.

Signals ROPB<15:0> and ROPB<16> form a value ROPB<16:0>, which is used to generate the control character PG_CNTRL<16:0>. The AND gate group 1119 has 16 AND gates, and each AND gate receives one of the corresponding values of the value ROPB<16:0>. The inverter group 1121 processes the value ROPB<16:0> and supplies the processing result to the other input of the AND gate group 1119. The inverter group 1121 has 16 inverters connected in parallel. A total of six inverter groups 1121 are connected in series to delay the corresponding signals, which are transmitted through the inverter group. Although each bit of the value ROPB<16:0> is delayed by 6 inverters, it is not intended to limit the invention, and in other embodiments, each bit can be delayed to varying degrees. The OR gate group 1123 has 16 OR gates, and the output of the AND gate group 1119 is coupled to the corresponding OR gate. All OR gates of the OR gate group 1123 receive the signal KILL. The output of OR gate group 1123 provides control characters PG_CNTRL<16:0>.

When a bit of the control character PG_CNTRL<16:0> is a value of 1, it closes the corresponding PMOS device, and if it is a value of 0, it turns on the corresponding PMOS device. If a bit of the value ROPB<16:0> is changed from the value 0 to the value 1, the corresponding bit of the control character PG_CNTRL<16:0> also changes, so the corresponding PMOS device can be turned off. To lower the level of the voltage VDD1. Similarly, if a bit of the value ROPB<16:0> is changed from the value 1 to the value 0, the corresponding bit of the control character PG_CNTRL<16:0> also changes, thereby turning on the corresponding PMOS device. To increase the level of the voltage VDD1.

At the same time, when changing multiple bits to lower the control character PG_CNTRL<16:0>, a problem may be solved. Specifically, when many bits of the control character PG_CNTRL<16:0> are simultaneously changed from one value to another value, the value of the control character PG_CNTRL may be replaced by 0. The replaced bit will not turn on the PMOS device, thus making the level of the voltage VDD1 briefly decline. A brief drop in voltage VDD1 may be lower than the final voltage level. Under such considerations, if the level of the voltage VDD1 is too low, the state information of the core 101 may not be retained.

The inverter group 1121 and the AND gate group 1119 can prevent the above problem. When the AND gate group 1119 processes the signal, if some of the bits quickly change from the value 1 to the value 0, the bits can be changed from the value 0 to the value 1 by the inverter group 1121. In this embodiment, the PMOS transistor to be turned on is quickly turned on before being turned off. Therefore, when the control character is updated, the level of the voltage VDD1 can be briefly increased first. The effect of temporarily increasing the level of the voltage VDD1 is less than the effect of temporarily reducing the level of the voltage VDD1.

Figure 12 is a possible embodiment of a time decoder 712 of the present invention. The input of the single hot spot decoder 1201 receives the signal PG<15:0> and decodes the signal PG<15:0> into the value PGT<15:0>. As described above, the initial value of the control character ROPB<15:0> is 1111000000000000b, after the logic gates 1115 and 1117 are inverted, therefore, under the power gating, the initial value of the control character ROPB<15:0> It is 0000111111111111b. In the decoding process, at the same time, only one bit of the value PGT<15:0> will be triggered to a high level, while other bits are low level, wherein the high level indicates the most important signal PG<15:0> The position of the bit, that is, the position of the bit that is triggered to a high level to a logical one. In addition, the number of bits of the value PGT<15:0> is related to the number of bits of the signal PG<15:0>. In the present embodiment, when the initial value of the signal PG<15:0> is 0000111111111111b, the initial value of the value PGT<15:0> is 0000000000010000b, and the fourth bit PGT< of the value PGT<15:0> 4> is high, while other bits are low. By reading the value PG, you can know The value PGT, such as the bit PGT<4>, indicates that the bit of the value PG<15:0> is counted from the left, and the fifth bit is the most significant bit. Under full power gating operation, when the signal PG_KILL_CORE1 is high, the signal PG<15:0> becomes 0000000001111111b, so the value PGT<15:0> is 0000000001000000b. The value PGT<15:0> is used to generate the time value PG_TIME<19:0> for selecting the frequency of the signal PG_CLK according to the operation mode and the control character. The single hotspot decoder 1201 can be implemented with standard NOR/NAND gates, or other similar circuits.

The clock shifter 1203 receives the high bit signal PG<15:6> of the signal group PG<15:0> and the value PG_FU_ENT<10:5> to provide corresponding values FIVE, SIX, SEVEN, EIGHT, NINE and TEN is used to shift the time value, that is, to adjust the period of the clock signal PG_CLK. The value PG_FU_ENT<10:5> may be programmed by a fuse, etc., to shift the time base of the time signal PG_CLK according to a number of parameters of a particular architecture, such as voltage supply capacitance. For example, when the value of the control character is decreased, the PMOS device corresponding to the specific bit is turned off, so the signal PG_FU_ENT<10:5> is shifted by the coefficient 2 to compensate the corresponding frequency of the signal PG_CLK. The RC time coefficient (such as increasing the period of the signal PG_CLK to slow down the adjusted response). As described above, C is the total capacitance of the core 101, and R is the impedance value of the power gating devices (such as PMOS devices, 502, 504, 506, 508, and 601) coupled between the voltages VDD0 and VDD1. . The RC time factor will be changed when the power gating device is turned off or on.

The preset clock selection circuit 1205 receives the signals PGT<15:0 and RESUME, and outputs a preset time under partial power gating and recovery operations. The value DTIME<19:0>. In the local power gating and recovery operation, the preset time value is used to preset the period of the signal PG_CLK. Under power gating, the clock cycle is also adjusted, such as adjusting the specific level of voltage VDD1 and/or the specific value of control character PG_CNTRL. The value DTIME<19:0> is used to select the signal PG_CLK under recovery operation instead of using a fixed recovery clock. In addition, under power gating (signal RESUME is deactivated), when the signal HIERB is triggered to a high level, the value DTIME<19:0> is not considered.

The signal group PG_FU_RES_PER<1:0> is a programmable 2-bit value (programmed by fuse or scan mode), which can be operated away from the power gate and under recovery operation (when the signal RESUME is triggered) , adjust the period of the signal PG_CLK. A fixed recovery clock selection circuit 1207 receives the signal group PG_FU_RES_PER<1:0> for generating a value PGTIMEB<6:3>. When the signal PG_FU_CONST_RES_CLK is set to a high level by means of a fuse, etc., a programmable fixed recovery clock period is selected, and the normal recovery clock is ignored.

The clock cycle selector 1209 receives the values FIVE, SIX, SEVEN, EIGHT, NINE, and TEN and the values PG_FU_HIERB, RESUME, HIERB, PG_FU_CNST_RES_CLK, DTIME<19:0>, and PGTIMEB<6:0>, and generates the value PG_TIME<19: 0>, used to select the period of the signal PG_CLK. Inverter 1211 inverts signal RESUME for generating signal RESUMEB and provides signal RESUMEB to clock cycle selector 1209.

Figure 13 is a possible embodiment of the clock shifter 1203 of the present invention. Example. The clock shifter 1203 includes an inverter group 1301 having six inverters, an inverter group 1303 having two inverters, NOR gates 1305, 1307, 1309, 1311, 1319, 1321, 1323, 1325, 1327, 1329 and NAND gates 1313, 1315 and 1317. Each of the inverter group 1301 having six inverters inverts the signal group PG_FU_ENT<10:5> to generate a corresponding inverted value ENB<10:5>. The inverter group 1302 having two inverters has inverted values ENB<7:6> for generating corresponding inverted values ENBB<7:6>. The NOR gate 1305 receives the bit PG<15:13>. The NOR gate 1307 receives bits PG<12:10>. The NOR gate 1309 receives the bit PG<9:8>. The NOR gate 1311 receives the bits PG<7:6>.

The output of the NOR gate 1305 is coupled to the input terminals of the NAND gates 1313, 1315, and 1317. The output of the NOR gate 1307 is coupled to the input terminals of the NAND gates 1313, 1315, and 1317. The output of NOR gate 1309 is coupled to the inputs of NAND gates 1315 and 1317. The output of the NOR gate 1311 is coupled to the input of the NAND gate 1317. The NAND gates 1313, 1315, and 1317 output signals TENB, EIGHTB, and SIXB, respectively.

The NOR gate 1319 receives the signals ENBB<6> and SIXB and outputs a signal SIX. The NOR gate 1321 receives the signals ENB<8> and EIGHTB and outputs a signal EIGHT. The NOR gate 1323 receives the signals ENB<10> and TENB and outputs a signal TEN. The NOR gate 1325 receives signals ENB<9>, TENB, and PG<9>, and outputs a signal NINE. The NOR gate 1327 receives signals ENBB<7>, EIGHTB, and PG<7>, and outputs a signal SEVEN. The NOR gate 13295 receives the signals ENB<5>, SIXB, and PG<5>, and outputs a signal FIVE.

In the present embodiment, the signal PG_FU_ENT<10:5> can be used to adjust the circumference of the signal PG_CLK according to the specific value of the signal group PG<15:6>. Period, where the signal group PG<15:6> is related to the corresponding bit of the control character PG_CNTRL<15:6>. The clock cycle selector 1209 performs the required clock shift (to increase the clock period) based on the values FIVE~TEN. The byte PG_FU_ENT<7:6> is preset in advance, so even if the corresponding PG_FU_ENT<7:6> can be cleared by blowing the corresponding fuse or setting the scanning mode, under the preset condition, the value SIX And SEVEN will be triggered for displacement.

Figure 14 is a diagram of a possible embodiment of a preset clock selection circuit 1205 of the present invention. The preset clock selection circuit 1205 includes a decoder 1420 and a multiplexer 1413, wherein the symbol "X20" represents 20 parallel multiplexers. For the decoder 1420, the NOR gate 1401 receives the high-order portion PGT<15:13> of the value PGT. The NOR gate 1403 receives the next high-order portion PGT<12:10> of the value PGT. The NOR gate 1405 receives the lower bit portion PGT<5:3> of the value PGT. The NOR gate 1407 receives the next lower bit portion PGT<2:0> of the value PGT. The input of the NAND gate 1409 is coupled to the output terminals of the NOR gates 1401 and 1403. The input terminal of the NAND gate 1411 is coupled to the output terminals of the NOR gates 1405 and 1407. NAND gate 1409 provides signal PGTHI. The NAND gate 1411 provides the signal PGTLO.

The input terminal 0 of the multiplexer 1413 receives the first value <*4>VSS0:PGT<15:0>, and its input terminal 1 receives the second value <*14>VSS0: PGTLO: PGT<6>: PGT<7> :PGT<8>: PGT<9>: PGHI. The select input S of the multiplexer 1413 receives the signal RESUME, and its output provides the value DTIME<19:0>. The first value has a total of 20 bits, of which 16 bits are 16 bits of PGT<15:0>, and 4 logical 0s (VSS0) are added to the leftmost side. The second value also has 20 bits, and the 14 high bits are logic 0 (VSS0), followed by PGTLO, PGT<6>, PGT<7>, PGT<8>, PGT<9>, PGHI. When the signal RESUME is low (as in power gating operation), the first value is taken as the value DTIME<19:0>. When the signal RESUME is high, the second value is taken as the value DTIME<19:0>.

Figure 15 is a possible embodiment of one of the fixed recovery clock selection circuits 1207 of the present invention. The inverter pair 1501 receives the byte PG_FU_RES_PER<1:0> and provides a corresponding inverted value RPERB<1:0>. The inverter pair 1503 receives the inverted value RPERB<1:0> and outputs a corresponding non-inverted value RPER<1:0>. The NAND gate 1505 receives the bits RPERB<0> and RPERB<1>, and outputs the bit PGTIMEB<5>. The NAND gate 1507 receives the bits RPERB<0> and RPER<1>, and outputs the bit PGTIMEB<3>. The NAND gate 1509 receives the bits RPER<0> and RPERB<1>, and outputs the bit PGTIMEB<4>. The NAND gate 1511 receives the bits RPER<0> and RPER<1>, and outputs the bit PGTIMEB<6>. The clock cycle selector 1209 provides the value PGTIMEB<6:3>. When the signal PG_FU_CONST_RES_CLK is triggered, the clock cycle selector 1209 selects the fixed period PG_CLK according to PG_FU_RES_PER<1:0>.

As shown in Fig. 15, when the bit PG_FU_RES_PER<1:0> is 10b, the bit PGTIMEB<3> is triggered. When the bit PG_FU_RES_PER<1:0> is 01b, the bit PGTIMEB<4> is triggered. When the bit PG_FU_RES_PER<1:0> is 00b, the bit PGTIMEB<5> is triggered. When the bit PG_FU_RES_PER<1:0> is 11b, the bit PGTIMEB<6> is triggered. Therefore, in the recovery operation, the fixed period of the signal PG_CLK is based on a simple decoding function.

16A and 16B are diagrams showing a possible embodiment of the clock cycle selector 1209 of the present invention. As shown, the clock cycle selector 1209 includes a plurality of multiplexers having two inputs, such as 1601, 1603, 1605, 1607, 1609, 1611, 1613, 1615, and 1617. Each multiplexer has the symbol "X20" which indicates that each multiplexer has 20 inputs for receiving a time value PG_TIME<19:0> having 20 bits. When the multiplexer 1601 outputs a signal, the signal is not inverted, and the other multiplexers 1603~1617 will invert the signal before outputting the signal. The clock cycle selector 1209 further includes a plurality of AND gates having 2 inputs, such as 1602, 1604, 1606, 1608, 1610, 1612, 1614, and 1616. The selection input S of the multiplexer 1601 receives the signal PG_FU_HIERB. The input of the AND gate 1602 receives the signals HIERB and RESUMEB, and its output is coupled to the selection input S of the multiplexer 1603. The input of the AND gate 1604 receives the value TEN and the signal RESUMEB, and its output is coupled to the selection input S of the multiplexer 1605. The input of the AND gate 1606 receives the value NINE and the signal RESUMEB, and its output is coupled to the selection input S of the multiplexer 1607. The input of the AND gate 1608 receives the value EIGHT and the signal RESUMEB, and its output is coupled to the selection input S of the multiplexer 1609. The input terminal of the AND gate 1610 receives the value SEVEN and the signal RESUMEB, and its output terminal is coupled to the selection input terminal S of the multiplexer 1611. The input terminal of the AND gate 1612 receives the value SIX and the signal RESUMEB, and its output terminal is coupled to the selection input terminal S of the multiplexer 1613. The input of the AND gate 1614 receives the value FIVE and the signal RESUMEB, and its output is coupled to the selection input S of the multiplexer 1615. The input of the AND gate 1616 receives the signals RESUME and PG_FU_CONST_RES_CLK, and its output is coupled to the selection input S of the multiplexer 1617.

The input 0 of the multiplexer 1601 receives a value <*2>VSS0:PGT<15:0>:<*2>VSS0, and its input 1 receives a value <*3>VSS0:PGT<15:0>: VSS0, whose output is coupled to the input terminal 1 of the next multiplexer 1603. The input 0 of the multiplexer 1603 receives the value DTIME<19:0>, and its inverted output provides a value PG2T<19:0>. The input 0 of the multiplexer 1605 receives the value PG2T<19:0>, its input 1 receives the value PG2T<18:0>: VDD0, and its inverted output provides a value PG3T<19:0>. The input 0 of the multiplexer 1607 receives the value PG3T<19:0>, its input 1 receives the value PG3T<18:0>: VSS0, and its inverted output provides a value PG4T<19:0>. The input 0 of the multiplexer 1609 receives the value PG4T<19:0>, its input 1 receives the value PG4T<18:0>: VDD0, and its inverted output provides a value PG5T<19:0>. The input 0 of the multiplexer 1611 receives the value PG5T<19:0>, its input 1 receives the value PG5T<18:0>: VSS0, and its inverted output provides a value PG6T<19:0>. The input 0 of the multiplexer 1613 receives the value PG6T<19:0>, its input 1 receives the value PG6T<18:0>: VDD0, and its inverted output provides a value PG7T<19:0>. The input 0 of the multiplexer 1615 receives the value PG7T<19:0>, its input 1 receives the value PG7T<18:0>: VSS0, and its inverted output provides a value PG8T<19:0>. The input 0 of the multiplexer 1617 receives the value PG8T<19:0>, and its input terminal 1 receives the value <*13>VDD0: PGTIMEB<6:3>:<*3>VDD0, and its inverted output provides a value. PG_TIME<19:0>.

Since some of the multiplexers have inverting outputs, VSS0 and VDD0 are used to add logic 0 or 1 after the shift. For example, in the multiplexer stack, after the even values PG2T, PG4T, and PG6T are shifted, VDD0, that is, logic 1, is added, and the odd values PG3T, PG5T, and PG7T are performed. After the shift, add VSS0, which is logic 0. In other embodiments, if the multiplexer does not have an inverting output, then the value added after the displacement needs to be adjusted.

The principle of operation of the time decoder 712 of Fig. 7B will be explained below. Under normal operation, when the power gating is not performed, the signal RESUME is at a low level. To put it simply, first assume that the bit PG_FU_ENT<10:5> is programmed, so the signal FIVE~TEN is triggered to the low level (including the signals SIX and SEVEN), and the multiplexers 1605~1617 select the input 0 to receive. The signal to. The signal HIERB is triggered to a low level, so the multiplexer 1603 selects the preset value DTIME<19:0>, and after the multiplexer stacking process, the value PG_TIME<19:0> is generated. The multiplexer 1413 selects the value <*4>: VSS0: PGT<15:0> as the initial value or preset value of PG_TIME<19:0>. As described above, in the start clock cycle, the lower bit of the control character PG_CNTRL<15:0> (the bit other than the MSB) is initialized to 1111000000000000b and inverted to PG<15:0>, which The value is 0000111111111111b, so the value of PGT is 0000000000010000b. The initial value corresponding to the PGT PG_CLK the initial period is about 80ns (clock cycle multiplier architecture ²⁰ of the first set of three yuan set to any value). It can be understood that in different architectures, the clock value can be any value, and any different clock cycle can be selected as the initial value.

In the case of continuous power gating, when the control character PG_CNTRL<16:0> is reduced, the corresponding PG<15:0> is also reduced. When the 11th bit of PG<15:0> becomes 0, the 10th bit of the original PG<15:0> is set to 1, so PG<15:0> becomes 0000000000100000b. Since PGT<15:0> is integrated in <19:0>, it is used to adjust during power gating. PG_TIME<19:0>, so both DTIME<19:0> and PG_TIME<19:0> will be adjusted. Since the next larger period is selected, the value PGT<15:0> is increased to twice the period of PG_CLK. Thus, the period of PG_CLK is doubled, so each lower bit of PG<15:0> becomes a logic 0. As the period of PG_CLK increases, the adjustment speed of the control character becomes slower (because of the lower frequency).

As described above, in order to adjust the period of PG_CLK, any number (0 or more) of threshold voltages (such as PG_VREF<1:N>) can be defined. As shown, the threshold voltage represented by PG_REF<1> is not close enough to the final voltage level indicated by the threshold voltage PG_VREF<2>. When power gating is performed, if a large threshold voltage has been reached, HIER will become a low level and HIERB will become a high level. Therefore, the multiplexer 1603 selects the signal of the input terminal 1, that is, the output signal of the multiplexer 1601. If PG_FU_HIERB is low (preset value), the value <*2>VSS0:PGT<15:0>:<*2>VSS0 will be supplied to multiplexer 1603 instead of the value DTIME<19:0>. This new value indicates that the value of PGT<15:0> of PG_TIME<19:0> needs to be shifted to the left twice, that is, the period of PG_CLK is multiplied by a factor of 4. In addition to the normal single displacement, this additional two displacements are required during continuous power gating.

If PG_FU_HIERB is triggered to a high level, when HIERB becomes high, multiplexer 1601 selects the coefficient <*3>VSS0:PGT<15:0>:VSS0 to indicate an additional single left shift, which is PG_CLK. The period is multiplied by a factor of 2 instead of a factor of four. Therefore, the value PG_FU_HIERB allows a slight increase in the period of the power gating.

Until the final level is reached, otherwise in the local voltage gating, in order to adjust PG_CLK, only a single threshold voltage value can be used, but in other implementations In the example, other threshold voltages PG_VREF<1:N> may be used to perform any programmable number of clock adjustments according to the threshold voltage defined by the corresponding comparison signals CMP3~CMPN. The multiplexer structure of Figures 16A and 16B can be modified taking into account the additional threshold voltage and the corresponding clock cycle adjustment.

The clock shifter 1203 additionally adjusts the period of the PG_CLK according to the value of the bit PG<15:6> and the set value of the bit PG_FU_ENT<10:5>. The value of the bit PG_FU_ENT<10:5> is used to trigger at least one of the values FIVE~TEN, and each value causes the PG value to be correspondingly shifted to adjust the period of the signal PG_CLK. In each embodiment, when the value of the bit PG<15:0> reaches a corresponding value, the value of the bit PG<15:0> can be shifted according to the time value to multiply the period of the PG_CLK. The upper two coefficients. For example, under power gating, and the signal RESUMEB is also triggered to a high level, the value TEN is triggered to a high level, so the multiplexer 1605 selects the value PG2T<18:0>: VDD0 instead of the value PG2T<19 :0>. The value PG2T<19:0> is shifted to the left, and the logic 1 (VDD0) is added to the rightmost side of the value PG2T<19:0> to form the value PG2T<18:0>: VDD0. The other values NINE, EIGHT, SEVEN, SIX, and FIVE operate in the same principle, multiplying the clock cycle by two coefficients after the corresponding value is triggered. As mentioned above, the values SIX and SEVEN can be enabled in advance if necessary. In this embodiment, at the time of power gating, according to the corresponding value of the control character PG_CNTRL, at least one of the bit values PG_FU_ENT<15:0> enable values FIVE~TEN is used to adjust the period of the signal PG_CLK (and Thus increase the cycle).

As shown in Figures 9A and 9B, under the power gating operation, when the signal HIGHB is triggered to a high level, it indicates that the voltage level of the reserved data or state has been reached. Therefore, the action between the total value and the difference value is such that the voltage VDD1 is maintained at the reserved voltage level. The control word PG_CNTRL will only slightly change for a small change in the corresponding PG value. The period of the signal PG_CLK remains unchanged or is maintained between two values.

When the signal PGATE1 is deactivated, the signal RESUME is triggered to initiate the recovery operation. Under the recovery operation, it can be understood that the length of time to reply from the full power gate can be determined, and under the local power gating, the worse condition from the state retention level (ie, a longer reply) Time) can also be decided. When the restore operation is initialized, the actual recovery time depends on the stylized value and the specific value of the control character under the recovery operation. If PG_FU_CONST_RES_CLK is also triggered to the high level, when the signal RESUME is triggered, the multiplexer 1617 selects the value <*13>VDD0: PGTIMEB<6:3>:<*3>VDD0, according to the value of PG_FU_RES_PER<1:0> Stylized PGTIMEB<6:3>. Insert 13 logic 1 from the left side of the value PGTIMEB<16:3> and insert 3 logic 1 on the right side. As mentioned above, please refer to Figure 15, according to the value of PG_FU_RES_PER<1:0>, only one bit of the bit PGTIMEB<16:3> is triggered to logic 0, so that the period of PG_CLK is equal to a corresponding fixed cycle. It can be appreciated that the multiplexer 1617 inverts the value such that the corresponding logic 1 selects the corresponding clock cycle.

If the initial value of PG_FU_CONST_RES_CLK is logic 0, the output of the multiplexer stack will be selected. Since the signal RESUMEB is at a low level, the signal at the input 0 of each multiplexer 1603~1615 is selected such that the value DTIME<19:0> becomes PG_TIME<19:0>. As shown in Figure 14, by The signal RESUME is at a high level. Therefore, under recovery operation, select the value <*14>VSS0:PGTLO:PGT<6>:PGT<7>:PGT<8>:PGT<9>, PGTHI is the preset time value. DTIME. In the present embodiment, the decoder 1420 converts the lower bits PGT<5:0> into a single bit PGTLO, and converts the high bits PGT<15:10> into a single bit PGTHI. In another embodiment, the values PGTHI and PGTLO are inserted into the time value along with the remaining bits PGT<9:6>. As long as 1 bit of the bit PGT<5:0> is triggered, the value PGTLO is high, and the value PGTHI is high only when 1 bit of the bit PGT<15:10> is triggered. Therefore, when the values PGT<6>, PGT<7>, PGT<8>, PGT<9>, and PGTHI are triggered to a high level, a period of PG_CLK can be selected.

In the recovery operation, since the value of the PGT in the time value is inverted, the period of the initial signal PG_CLK is a relatively small value for fast frequency adjustment. Under the recovery operation, the 2-input-multiplexer 915 selects a total adjustment value, and therefore, the control character begins to gradually increase. At this time, the period of the signal PG_CLK is gradually increased to control the rise time of the voltage VDD1. However, the high bits of the PGT are combined into a single bit value PGTHI, so the signal PG_CLK will be maintained in a short period for a long time to rapidly increase the voltage VDD1. When the voltage VDD1 reaches the operating voltage level, the frequency of the signal PG_CLK decreases as the control word increases. In another embodiment, in the fast reset operation, when the rise time of the voltage VDD1 is within an appropriate range, the control word may be greatly increased to reduce the period of the signal PG_CLK. Once the control character PG_CNTRL<16:0> reaches a certain level, for example, the bit PG_CNTRL<13> or PG_CNTRL<14> depends on the setting of PG_FU_RESUME_STOP, the most significant bit PG16 will be touched. The control character PG_CNTRL<16:0> will return to the initial value and stop the action of the signal PG_CLK.

It can be appreciated that in another embodiment, the time during which the voltage VDD1 increases from the data retention level to the normal operation level may be faster than the time when the voltage VDD1 decreases from the normal operation level to the data retention level. However, an increase in control voltage VDD1 is required to ensure that voltage VDD0 is not significantly affected, thereby affecting the supply voltage of other cores (or circuits) of microprocessor 100. In addition, the voltage increased by the voltage VDD1 can be programmatically adjusted according to a specific structure.

When PG_CKILL_CORE1 is triggered to initiate a full power gating operation, the inverter 1111 of FIG. 11 triggers the signal KILL to a high level so that the OR gate group 1123 will control each bit of the character PG_CNTRL<16:0>. The element is pulled up to the high level (hence, each bit of the control character PG_CNTRL<16:0> is invalidated or not triggered). Therefore, the PMOS transistors 502, 504, 506, 508, and 601 are not turned on to isolate the voltages VDD1 and VDD0, and pull the voltage VDD1 to ground or VSS0. PG<15:0> is initialized to 0000000001111111b (through logic gates 1115 and 1117), so the period of PG_CLK is a start selection period. When PG_KILL_CORE1 is invalidated, RESUME can be triggered by initializing the PG and PGT values. When the PG is initialized, the control character PG_CNTRL<16:0> can be initialized under the recovery operation. If a fixed clock cycle is not selected during the recovery operation, when the value PGT is initialized, the frequency of PG_CLK can be set to a high clock frequency for fast recovery operation. In the present embodiment, at the time of the recovery operation, the cycle of the recovery clock is completely programmed according to the architecture. Although full power gating can be enabled quickly, it is necessary to control the increase in the gating supply voltage back to the normal operating level. Amount to avoid affecting the surrounding core and circuit.

The period of PG_CLK is programmed according to a number of coefficients to control the level change of voltage VDD1 under power gating or recovery operation. A coefficient is the control character itself. For example, the values PGT and PG_TIME<19:0> are changed according to the change of the bit PGT. Stylize additional time shifts by fuse or scan...etc. Another coefficient used to control the period is the level of the voltage VDD1, which is used to indicate a higher threshold voltage (such as the input signal of the switching multiplexer 1601) by triggering HIER as described above. Additional adjustments are made to the threshold voltage of voltage VDD1 using different implementations or architectures.

Clock controller 706 generates signal PG_CLK. In the present embodiment, the clock controller 706 generates a plurality of clock signals, and the time decoder 712 generates a time value PG_TIME<19:0> for selecting a clock signal. In another embodiment, the clock controller 706 may be implemented by a programmable clock generator, and the time value may be used to program the period of the clock signal. In other embodiments, the clock controller 706 can be implemented with a timer or counter, etc.

In the power gating or recovery operation, the adjustment of the control character is programmed by a number of coefficients to control the adjustment range of the voltage VDD1. A coefficient is the control character itself, and the adjustment gain can be controlled by a selectable amount, displacement control character.

The above embodiment has been shown to adjust PG_CLK based on the programmable threshold voltage. The gain can also be adjusted using a programmable threshold voltage. As shown in Fig. 17, additional gain adjustment is performed based on a threshold voltage (e.g., comparison signal CMP3). As shown in the 17th, the input end of the multiplexer 903 is coupled to the multiplexer The output of the 1701 and 1703. As described above, the multiplexers 903, 1701, and 1703 are 16-bit structures each having 16 multiplexers. The multiplexer 903 selects an output signal of the multiplexer 1701 or 1703 based on the stylized value PG_FU_SUB_GN. The multiplexer 1701 selects the displacement value SHIFTVAL1 or SHIFTVAL2 based on the comparison signal CMP3. The multiplexer 1703 selects the displacement value SHIFTVAL3 or SHIFTVAL4 based on the comparison signal CMP3. Each displacement value has 16 bits and, under power gating, represents a different displacement structure of the control character, which is relative to different gain values. In this embodiment, an additional multiplexer may be additionally added to perform gain adjustment by using the total value and/or the difference value according to any number of threshold voltages.

The system and method for digital power gating with data recovery function is fully programmable, and digitally controls a gate voltage according to the trigger condition of the current device, such as a local supply voltage, and the current device can be PMOS or NMOS. The transistor, etc., is coupled between two voltages, one of which is an integrated supply voltage. A microprocessor has varying degrees of power gating, so that a particular final voltage level can be adjusted statically or dynamically. In addition, specific structures such as circuits or cores, etc., such as integrated ECC memory, etc., can be changed. Therefore, the reference voltage that determines the final level may be adjusted or a different reference voltage may be selected. The actual final voltage level may depend on the particular structure and mode of operation. The digital power gating system and method with data recovery function is fully programmable to produce any suitable voltage level.

The binary value of the control character PG_CNTRL is dependent on a number of parameters such as processor, temperature, and final voltage level. The actual voltage will be measured and added or subtracted in a continuous or periodic manner in a control loop. Integer value to adjust the voltage. The system and method for digital power gating with data recovery function is similar to that of a voltage regulator, except that the above system and method coefficients are bit-controlled and applied in a binary decentralized device, according to the final voltage level. Control the binary device.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

101‧‧‧ core

105‧‧‧Power Gate System

201‧‧‧Power Gate Control System

PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204, PG_GATE_BOTTOM205‧‧‧ gate control circuit

206‧‧‧Gate control supply bus

VDD0, VDD1, VSS0‧‧‧ voltage

V_DOWN<4:0>‧‧‧Signal Group

PWR_GOOD‧‧‧ signal

PG_CNTRL<16:0>‧‧‧ control characters

VDD1_FB, I<16:0>‧‧‧ input

EESDCLK‧‧‧ clock signal

PG_VREF<1:N>‧‧‧reference voltage group

FSB<3:0>‧‧‧ front-end busbar values

PG_KILL_CORE1‧‧‧ signal

PGATE1‧‧‧Power gating signal

PGOOD1‧‧‧Power Ready Signal

PG_FU_ADD_GN, PG_FU_SUB_GN, PG_FU_CONST_RES_CLK, PG_FU_RESUME_STOP, PG_FU_HIERB‧‧‧ values

PG_FU_ENT<10:5>, PG_FU_RESUME_GN<1:0>, PG_FU_RES_PER<1:0>‧‧‧value group

PG_CNTRLA<16:0>, PG_CNTRLB<16:0>‧‧‧ buffer results

O<16:0>‧‧‧ output

Claims (42)

A digital power supply gate system for controlling a voltage of a gate control supply busbar, the gate control supply busbar being coupled to a supply voltage input end of a functional circuit, the functional circuit being related to a voltage of an integrated supply busbar, The digital power gate system comprises: a plurality of gate control devices, each gate control device has a current terminal pair and a control terminal, the current terminal pair is coupled to the integrated supply bus bar and the gate control supply bus bar; and a power gate control system Controlling a digital control value, wherein the digital control value comprises a plurality of bits, each bit of the digital control value being used to control at least one control terminal of the gate control device for enabling the gate control device a corresponding gate control device; and wherein the power gate control system continuously adjusts the digital control value, and performs power gating to reduce the voltage of the gate control supply bus to a state retention voltage level, while retaining When the function circuit is in a digital state, the leakage current is reduced. The digital power brake system of claim 1, wherein the bits of the digital control value are binary weighted. The digital power gate system of claim 1, wherein a power controller causes the function circuit to enter an idle mode, turning off a functional clock and triggering a gate control signal, the function circuit receiving the functionality The gate control signal causes the power gating system to lower the voltage of the gate control supply bus to the state retention voltage level according to a reference voltage. The digital power brake system of claim 1, wherein the power supply The gate control system includes a digital adjuster. After each of the plurality of consecutive adjustment periods, the digital adjuster reduces the voltage of the gate control supply bus by integrating a digital adjustment value and the digital control value. The digital power brake system of claim 4, wherein the digital adjuster periodically adjusts the digital adjustment value to maintain a fixed gain during the continuous adjustment period. The digital power brake system of claim 4, wherein the digital adjustment value is a displacement result of a current value of the digital control value. The digital power brake system of claim 4, wherein the digital adjuster periodically adjusts an adjustment rate and a magnitude of the digital adjustment value to avoid failing to reach the state retention voltage level. The digital power brake system of claim 4, wherein the digital adjuster increases the duration of the continuous adjustment period when the voltage of the gate supply busbar decreases toward the state retention voltage level, And reduce the digital adjustment value. The digital power gate system of claim 1, further comprising: a voltage comparator for comparing the voltage of the gate control supply bus and the complex threshold voltage, wherein the threshold voltage comprises a predetermined threshold voltage, The preset threshold voltage represents the state retention voltage level; and wherein the power gating system includes a clock controller that changes a period of a clock signal when the voltage of the gate supply bus bar reaches at least one When the voltage level is preset, the clock signal controls the adjustment time, and the preset voltage level is greater than the state retention voltage level. The digital power brake system of claim 1, wherein the power supply The gate control system includes a clock controller that changes a period of a clock signal. When the digit control value is equal to the preset voltage level, the clock signal controls the adjustment time. The digital power gate system of claim 1, wherein the power gate control system comprises an incremental adjuster, wherein the incremental adjuster selects one of a plurality of different displacement results of the digital control value for As the digit adjustment value, and when the digit control value reaches the preset value, the increment adjuster selects the other one of the different displacement results as the digit adjustment value. The digital power gate system of claim 1, further comprising: a voltage comparator for comparing a voltage of the gate control supply bus and a complex threshold voltage, the threshold voltage having a predetermined threshold voltage, The preset threshold voltage is indicative of the state retention voltage level; and wherein the power gating system includes an incremental regulator that selects one of a plurality of different displacement results of the digital control value for As the digit adjustment value, and when the voltage of the gate control supply bus bar reaches the preset voltage level, the incremental regulator selects the other one of the different displacement results as the digit adjustment value, the preset voltage bit It is more than this state to retain the voltage level. The digital power brake system of claim 1, wherein the power gating system periodically adjusts at least one of an adjustment rate and a magnitude of the digital adjustment value, so that the gate is supplied with a voltage of the bus bar. Follow a preset voltage curve. An integrated circuit comprising: An integrated supply bus; at least one gate is supplied to the bus; at least one functional block, each functional block has a voltage supply input coupled to the corresponding gate supply bus; and at least one digit The power gate system, each power gate control system is provided to a corresponding function block, and includes: a plurality of gate control devices, each gate control device has a current terminal pair and a control terminal, and the current terminal pair is coupled to the integration Supplying a bus bar and the state retaining voltage level; a power gating system controlling a digital control value, wherein the digital control value comprises a complex bit, each bit of the digital control value controlling at least one of the gating devices a control terminal for activating the corresponding gate device; and wherein the power gating system continuously adjusts the digital control value for power gating to reduce the voltage of the corresponding gating supply bus The state of the voltage is preserved to a state, and the leakage current is reduced while maintaining a digital state of the functional block. The integrated circuit of claim 14, wherein each of the gate devices comprises a PMOS transistor. The integrated circuit of claim 14, wherein the first bit of the digital control value controls one of the gate devices, and the other portions of the gate control device are other bits of the digital control value. Controlled by the yuan. The integrated circuit of claim 14, further comprising: a power controller, wherein the corresponding function block is in an idle mode, and So that the power gating system reduces the voltage of the gating control busbar to the state retention voltage level. The integrated circuit of claim 14, further comprising: a limiting circuit for limiting the digital control value to a predetermined minimum digital value. The integrated circuit of claim 14, further comprising: the function block includes a plurality of functional blocks; the gate control supply bus includes a plurality of gate control supply bus bars, and each of the gate control supply bus bars Providing a gated supply voltage to one of the functional blocks of the functional blocks; the digital power gate system includes a plurality of digital power gate systems, each of the digital power gate systems being one of the functional blocks Corresponding function block performs power gating; and a power controller triggers a corresponding gating signal in the plurality of gating signals for initializing the power gating operation of any of the functional blocks. The integrated circuit of claim 19, wherein the functional blocks comprise a plurality of processor cores, the processor cores being disposed in a multiprocessor system. The integrated circuit of claim 14, wherein the power control system comprises: a block controller that provides a clock signal for controlling a continuously adjusted adjustment rate of the digital control value, and when the corresponding The block adjuster adjusts when the voltage of the gated supply flow line reaches each of the complex threshold voltages a period of the clock signal; and a power gate controller receiving a power gating signal and the clock signal, and generating and adjusting the digital control value for performing the power gating. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller that provides a clock signal for controlling the continuous adjustment of the digital control value and is at the power gate Controlling the time, and adjusting the period of the clock signal when the digital control value reaches at least a preset value of the digital control value; and a power gate controller receiving a power gating signal and the clock signal, and generating And adjusting the digital control value to perform the power gating. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller that provides a clock signal for controlling the continuous adjustment of the digital control value and is at the power gate The timing of the clock signal is adjusted when the digital control value reaches each of the complex programmed values; and a power gate controller receives a power gate signal and the clock signal, and generates and adjusts The digital control value is used to perform the power gating. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller that provides a clock signal for controlling the adjustment rate of the continuous adjustment of the digital control value, and includes: a decoder that converts the digital control value into a time control value; And a selection logic, wherein the time control value is used to determine the period of the clock signal under the power gating; and a power gate controller receives a power gating signal and the clock signal, and generates and adjusts the The digital control value is used to perform the power gating. The integrated circuit of claim 24, wherein the decoder comprises a single hotspot decoder, and the time control value is adjusted to represent a highest bit of the digital control value, the highest bit being The triggering is in an off state, wherein during the power gating, the period of the clock signal is increased according to each change of the time control value. The integrated circuit of claim 25, wherein when the voltage of the corresponding gate supply bus is less than a high threshold voltage, the selection logic selects a digital displacement result of the time control value, the height The threshold voltage is greater than the state retention voltage level. The integrated circuit of claim 24, wherein the clock controller further comprises: a clock shifter that converts a portion of the digital control value into a complex period adjustment value; and a clock cycle selector, Under the power gating, the digital control value is adjusted, and the period of the clock signal is adjusted when any of the periodic adjustment values becomes a specific level. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller that provides a clock signal for controlling the digital control value a continuously adjusted adjustment rate; and a power gate controller that receives a power gating signal and the clock signal, and generates and adjusts the digital control value for performing the power gating control, wherein the power gate controller includes a digital subtractor that subtracts a digital adjustment value for adjusting the digital control value under the power gating, the digital control value being synchronized to the clock signal; and wherein the digital adjustment The numerical value is the result of controlling the numerical displacement of the digit. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller, providing a clock signal for controlling a continuously adjusted adjustment rate of the digital control value; and a power supply The gate controller receives a power gating signal and the clock signal, and generates and adjusts the digital control value for performing the power gating control, wherein the power gate controller comprises: a digital subtractor, the digital control The value is subtracted from the digital adjustment value for adjusting the digital control value at any time under power gating, the digital control value is synchronized with the clock signal; a selection logic is used to adjust the complex value of the value from the digital position Selecting; and a gain logic that, when the digit control value is equal to at least a predetermined value, causes the selection logic to select one of the different displacement results of the digit adjustment value. The integrated circuit of claim 14, wherein the power supply is controlled The system includes: a clock controller that provides a clock signal for controlling the adjustment rate of the continuous adjustment of the digital control value; and a power gate controller that receives a power gate control signal and the clock signal, and generates and adjusts The digital control value is used to perform the power gating control, wherein the power gate controller comprises: a digital subtractor, the digit control value is subtracted by a digit adjustment value, and the digit is adjusted at any time under power gating Controlling a value, the digital control value being synchronized to the clock signal; a selection logic selecting from a plurality of different displacement results of the digital adjustment value; and a gain logic, when the corresponding gate is supplied to the bus Each of the plurality of threshold voltages causes the selection logic to select one of the different displacement results of the digit adjustment value. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller, providing a clock signal for controlling a continuously adjusted adjustment rate of the digital control value; and a power gate The controller receives a power gating signal and the clock signal, and generates and adjusts the digital control value for performing the power gating control, wherein the power gate controller comprises: a digital subtractor, the digital control value Subtracting a digit difference value to provide a reduced digit value; a digit adder adding a digit plus a total value and the digit control value, Providing an increasing digit value; a selection logic for selecting between the decreasing digit value and the increasing digit value for providing a selected digit value; and a register logic for receiving the selected digit value for providing And updating the digital value, the updated digital value is synchronized with the clock signal; and wherein the digital difference value and the digital plus total value both include a displacement result of the digital control value. The integrated circuit of claim 14, wherein the power gating system comprises: a clock controller, providing a clock signal for controlling a continuously adjusted adjustment rate of the digital control value; and a power gate The controller receives a power gating signal and the clock signal, and generates and adjusts the digital control value for performing the power gating control, wherein the power gate controller comprises: a digital subtractor, the digital control value Subtracting a digit difference value to provide a reduced digit value; a digit adder adding a digit plus a total value and the digit control value for providing an increasing digit value; a selection logic at which the digit value is reduced Selecting between the increased digit value to provide a selected digit value; a register logic receiving the selected digit value for providing an updated digit value, the updated digit value being synchronized to the clock signal; a gain selector for selecting between a plurality of different digit difference values, each of the digit difference values including the digit A braking value Displacement results. A power gating method for providing a supply voltage to a functional block, and comprising: providing a digital control value, the digital control value controlling a plurality of current devices coupled to a non-gate controlled supply bus and a gate control is provided between the bus bars; triggering the digital control value to trigger a portion of the current devices such that in a full current mode, the voltage of the gate control supply bus is clamped to the non-gate controlled supply bus And receiving a gate control signal, and periodically adjusting the magnitude of the digital control value to perform power gating according to the gate control signal until the voltage of the gate control supply busbar reaches a state retention voltage Level, reducing leakage current while retaining a digital state of the function block. The power gating method according to claim 33, further comprising: binarizing the bit of the digital control value. The power gating method of claim 33, wherein the step of periodically adjusting the magnitude of the digital control value comprises periodically integrating the digital control value with a digital adjustment value. The power gating method according to claim 35, further comprising: using the digit adjustment value as a displacement result of the digit control value. The power gating method according to claim 35, further comprising: comparing a voltage of the gating control supply bus and at least one threshold voltage; selecting one of the complex displacement results of the digital control value as a first digit Adjust the value; When the gate control supply reaches the threshold voltage, the other of the displacement results of the digital control value is selected. The power gating method according to claim 35, further comprising: selecting one of the complex displacement results of the digital control value as a first digit adjustment value; and when the digit control value reaches at least a preset value At the time, the other of the displacement results of the digital control value is selected. The power gating method according to claim 35, further comprising: providing a clock signal, and wherein the step of periodically integrating comprises: selecting the digital control value and the digit according to a period of the clock signal Adjust the values to integrate in a proportional relationship. The power gating method according to claim 39, further comprising: comparing a voltage of the gating control bus and at least one threshold voltage; and the step of providing the clock signal includes: providing the clock signal, The clock signal has an initial value period; when the voltage of the gate supply bus bar reaches the threshold voltage, the period of the clock signal is changed. The power gating method of claim 39, wherein the step of providing the clock signal comprises: providing the clock signal, the clock signal having an initial value period; when the digital control value reaches at least one pre- When the value is set, the period of the clock signal is changed. The power gating method according to claim 39, further comprising: converting a partial bit of the digital control value into a complex period adjustment value; And changing the period of the clock signal when any of the periodic adjustment values is a specific level.