TW201448115A - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a metal electrode and a self-aligned contact structure and a method of fabricating the same.

As the integrated circuit (IC) accumulates continuously, the feature size of each semiconductor element in the integrated circuit continues to shrink. In order to meet various electrical or process limitations caused by the shrinkage of semiconductor components, the industry has also proposed various solutions. For example, in the case of a transistor device, in order to solve the problem of boron penetration and depletion effect caused by a conventional polysilicon gate, a gate last process is often used in the industry to have The metal gate of the metal electrode replaces the conventional polysilicon gate. In addition, as the distance between the gate structures is gradually reduced, the industry has also proposed a method of self-aligning the contact structure to cope with the shortage of space between the gate structures.

For a transistor device structure using both a metal gate and a self-aligned contact structure, in order to avoid unnecessary electrical contact between the metal electrode and the self-aligned contact structure in the metal gate, a mask is generally formed first. The layer covers the metal electrode within the metal gate such that the subsequently formed self-aligned contact structure can be blocked by the mask layer without unnecessarily contacting the metal gate.

However, the above-described process for preparing the crystal device still causes many problems. Due to the above shape The step of forming a mask layer includes sequentially etching away portions of the metal electrodes to leave a trench and filling the mask layer into the trench, thereby reducing the height of the metal gate. It is known that the height of the final metal gate is closely related to the electrical properties of the transistor device. In order to maintain the height of the final metal gate within a predetermined value, the manufacturer will correspondingly raise the initial dummy gate (dummy gate). The height, but too high a virtual gate will cause many process problems, for example, the dummy gate is easy to break in the grinding process, and the dummy gate is easy to produce a shadowing effect in the ion implantation process. The dielectric layer is not easy to fill in between the dummy gates and the metal layer is not easily filled into the gate trenches. In addition, since a planarization process is performed in the process of forming the mask layer, a portion of the larger-sized mask layer is dented.

Therefore, there is still a need in the industry for an improved metal gate and self-aligned contact structure and method of fabricating the same to effectively overcome the above disadvantages.

It is an object of the present invention to provide a semiconductor device having a metal gate and a self-aligned contact structure and a method of fabricating the same to address the deficiencies of the prior art.

In accordance with a preferred embodiment of the present invention, a method of fabricating a semiconductor device is provided that includes the following steps. First, a first interlayer dielectric layer is formed on the substrate. Thereafter, a gate electrode is formed on the substrate, wherein the periphery of the gate electrode is surrounded by the first interlayer dielectric layer. Thereafter, a patterned mask layer is formed on the gate electrode, wherein the bottom surface of the patterned mask layer is aligned with the top surface of the first interlayer dielectric layer. A second interlayer dielectric layer is then formed to cover the top surface and sides of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric layer and the second interlayer dielectric layer.

In accordance with another preferred embodiment of the present invention, a semiconductor device is provided that includes a metal gate electrode, a first interlayer dielectric layer, a patterned mask layer, a second interlayer dielectric layer, and a self-aligned contact structure. The metal gate electrode is disposed on the substrate, and the first interlayer dielectric layer surrounds the metal The perimeter of the gate electrode. The patterned mask layer is disposed on the metal gate electrode, and the bottom surface of the patterned mask layer is aligned with the top surface of the first interlayer dielectric layer. a second interlayer dielectric layer covering the top surface of the patterned mask layer and at least one sidewall. The self-aligned contact structure is disposed within the first interlayer dielectric layer and the second interlayer dielectric layer and electrically connected to the substrate.

100‧‧‧Substrate

110‧‧‧Virtual gate structure

112‧‧‧ sacrificial layer

114‧‧‧ cover

120‧‧‧ gate sidewall

130‧‧‧ epitaxial layer

140‧‧‧etch stop layer

150‧‧‧First interlayer dielectric layer

210‧‧‧ Ditch

212‧‧‧gate electrode

214‧‧‧ dielectric layer

220‧‧‧mask layer

220b‧‧‧ patterned mask layer

230‧‧‧ dielectric layer

232‧‧‧ Sidewall

232a‧‧‧lower side wall

232b‧‧‧Upper side wall

240‧‧‧Second interlayer dielectric layer

242‧‧‧Contact hole

243‧‧‧ Self-aligned contact structure

244‧‧‧Metal Telluride

245‧‧‧Barrier layer

246‧‧‧metal layer

310‧‧‧Metal gate structure

H1‧‧‧ first height

H2‧‧‧second height

H3‧‧‧ third height

L1‧‧‧ first length

W1‧‧‧ first width

W2‧‧‧ second width

W3‧‧‧ third width

1 to 9 are schematic views showing a semiconductor device according to a first preferred embodiment of the present invention, wherein: FIG. 1 is a schematic view of a semiconductor device in an initial stage of a process; and FIG. 2 is a semiconductor device in which a metal gate is replaced. Schematic diagram after the process; FIG. 3 is a schematic view after depositing the mask layer; FIG. 4 is a schematic view after forming the patterned mask layer; FIG. 5 is a schematic view after depositing the dielectric layer; FIG. 7 is a schematic view showing a contact hole; FIG. 8 and FIG. 9 are schematic views showing a contact structure; and FIG. 10 is a semiconductor device according to a variation of the first preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS Fig. 11 is a schematic view showing another variation of the semiconductor device of the first preferred embodiment of the present invention.

1 to 9 are schematic views showing a semiconductor device fabricated in accordance with a first preferred embodiment of the present invention. The process steps for fabricating a semiconductor device having a transistor structure and a contact structure will be described below. First, please refer to FIG. 1. FIG. 1 is a schematic view of the semiconductor device at the initial stage of the process. As shown in FIG. 1 , in the process stage, the substrate may include a stacked structure, a sidewall, an epitaxial layer, a doped region, a capping layer, and a dielectric layer. For example, the substrate 100 may be a semiconductor substrate whose surface may selectively have a plurality of fin-like structures, but is not limited thereto. The plurality of stacked structures may be, for example, dummy gate structures 110, which may include a dielectric layer (not shown), a sacrificial layer 112, and a cap layer 114 from bottom to top. The sidewalls may be, for example, gate sidewalls 120 that may be disposed on sidewalls of each dummy gate structure 110. The epitaxial layers 130 are disposed inside or outside the substrate 100 and are each located on each side of the dummy gate structure 110, but are not limited thereto. The doped region (not shown) may be, for example, a lightly doped drain region and/or a source/drain region, which may be disposed on both sides of each dummy gate structure 110 and may be selectively located on the substrate. Within 100 or within the epitaxial layer 130, but is not limited thereto. The opaque layer and the dielectric layer may be an etch stop layer 140 and a first interlayer dielectric layer 150, respectively, which are sequentially stacked on the substrate 100 from bottom to top, wherein the etch stop layer 140 can cover the gate compliantly The pole side wall 120, the epitaxial layer 130, and the cap layer 114.

The substrate 100 may be selected from a germanium substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. When the substrate 100 has a fin-like structure, the bottom of each dummy gate structure 110 may cover a portion of the corresponding fin-like structure. The dielectric layer (not shown), the sacrificial layer 112, and the cap layer 114 in the dummy gate structure 110 may correspond to an oxide layer, a tantalum layer, and a nitride layer, respectively, for example, corresponding to a hafnium oxide layer, a polysilicon layer, and a nitrogen layer, respectively. The layer of phlegm is not limited to this. The gate sidewalls 120 may be selected from the group consisting of tantalum nitride, tantalum carbide, tantalum carbide, niobium oxynitride or other suitable semiconductor compounds. The epitaxial layer 130 disposed on both sides of each dummy gate structure 110 may be selected from semiconductor materials with or without dopants, such as germanium, antimony, germanium, and the like, which may provide appropriate stress to the channel region. To improve the mobility of the carriers in the channel region. The etch stop layer 140 can be selected from the group consisting of niobium oxynitride, hafnium oxynitride, tantalum nitride, niobium carbide, or other suitable semiconductor compound that can apply appropriate stress to the channel region and/or as an etch stop layer for subsequent formation of the contact structure. The first interlayer dielectric layer 150 is selected from a dielectric material that is not electrically conductive, such as hafnium oxide.

In this process stage, the top surface of the cap layer 114 and the top surface of the substrate 100 have a first height H1, and the top surface of the sacrificial layer 112 and the top surface of the substrate 100 have a second height H2. Wherein, the first height H1 is between about 1000 angstroms and 2000 angstroms, preferably 1300 angstroms; and the second height H2 is between about 700 angstroms and 1200 angstroms, preferably 900 angstroms.

Next, a polishing process and/or an etching process, such as a chemical mechanical polishing process, is performed to completely remove the cap layer 114 and expose the top surface of the sacrificial layer 112. In this process, since the sacrificial layer 112 in each dummy gate structure 110 may be partially consumed, the distance between the top surface of the sacrificial layer 112 and the top surface of the substrate 100 is slightly reduced.

Referring to FIG. 1 and FIG. 2 simultaneously, FIG. 2 is a schematic view of a semiconductor device after the metal gate process is replaced by the first preferred embodiment of the present invention. After exposing the top surface of the sacrificial layer 112, a replacement metal gate (RMG) process can be performed to form the structure as shown in FIG. As shown in FIG. 1 and FIG. 2, the process may include: removing the sacrificial layer 112 in each dummy gate structure 110 to leave the trench 210, and continuing the dielectric layer 214 and the work function layer (Fig. Not shown) and the conductive layer is filled into the trench 210. Thereafter, a polishing process is performed to remove the dielectric layer 214, the work function layer (not shown), and the conductive layer outside the trench 210 until the interlayer dielectric layer 150 is exposed. At this time, the metal gate structure 310 is obtained, and the conductive layer located in each trench 210 serves as the gate electrode 212 of the metal gate structure 310.

At this stage, the top surface of the gate electrode 212 is preferably substantially aligned with the top surface of the first interlayer dielectric layer 150, and the top surface of the gate electrode 212 and the top surface of the substrate 100 have a third height. H3. Since the above polishing process removes a small number of gate sidewalls 120, an etch stop layer 140, and a first interlayer dielectric layer 150, in addition to removing the conductive layer, the third height H3 is approximately smaller than the second height. H2, the difference is between about 50 angstroms and 300 angstroms, preferably 150 angstroms. In addition, on The top surface of the gate electrode 212 may also be slightly lower than the gate sidewall 120, the etch stop layer 140, and the top surface of the first interlayer dielectric layer 150, but is not limited thereto.

The dielectric layer 214 is preferably a high dielectric constant dielectric layer having a dielectric constant of substantially greater than 20, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), oxidation Tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), zirconium silicate (ZrSiO ₄ ), hafnium zirconate (HfZrO), yttrium oxide (yttrium oxide, Yb ₂ O ₃ ), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAl), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide Titanium oxide, TiO ₂ ), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon oxynitride (HfSiON) , strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST), but not Limited to this. In addition, the work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (tungsten carbide). , WC) or aluminum titanium nitride (TiAlN), but is not limited thereto. The gate electrode 212 may include a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (aluminum), titanium aluminide (TiAl), titanium aluminum oxide (TiAlO). , tungsten (tungsten, W) or copper (copper, Cu), but is not limited to this.

In addition, since the process is a post-last process with a high-k last process, the dielectric layer 214 and the work function layer are preferably located in each trench. The side walls of the 210 and the bottom. However, the embodiment is not limited thereto, and the post-gate process can also be applied to a high-k first process. Therefore, the substrate 100 in the trench 210 is covered by the high-k dielectric layer before the sacrificial layer is removed. In this case, a barrier layer (not shown) may be selectively formed on the top surface of the high-k dielectric layer to prevent the high-k dielectric layer from being removed together with the sacrificial layer. Wherein, the barrier layer may be a metal layer such as a titanium nitride layer.

Please refer to FIG. 3, wherein FIG. 3 is a schematic view of a semiconductor device after depositing a mask layer according to a first preferred embodiment of the present invention. As shown in FIG. 3, a deposition process, such as a physical vapor deposition process, can be performed to form a mask layer 220 having a thickness of between about 200 angstroms and about 400 angstroms, preferably 350 angstroms. The mask layer 220 may completely cover the gate electrode 212, the gate sidewall spacer 120, the etch stop layer 140, and the first interlayer dielectric layer 150. Preferably, the mask layer 220 may include a material different from the first interlayer dielectric layer 150, such as lanthanum oxynitride, lanthanum oxynitride, tantalum nitride or tantalum carbide, so that there is a certain etching option between each other. Than, but not limited to.

Referring to Figure 4, a fourth embodiment of the present invention is a schematic view of a semiconductor device after forming a patterned mask layer in accordance with a first preferred embodiment of the present invention. Then, a photolithography and etching process is sequentially performed to form a patterned layer (not shown) on the mask layer 220, and the pattern of the patterned layer is transferred to the mask layer 220 to form a pattern as shown in FIG. The patterned mask layer 220b. Specifically, the patterned layer preferably has a multi-layer stack structure, for example, a stack structure including an organic dielectric layer (ODL)/antireflection layer/photoresist layer from bottom to top, but Not limited to this. In addition, the photolithography and/or etching process preferably includes a double patterning technology (DPT), but is not limited thereto.

As shown in FIG. 4, the patterned mask layer 220b is located on the gate electrode 212, the gate sidewall 120, the etch stop layer 140, and the first interlayer dielectric layer 150, so that the gate electrode 212 and the gate electrode The electrical layer 214 will be completely covered by the patterned mask layer 220b. For example, the patterned mask layer 220b and the gate electrode 212 and the dielectric layer 214 under it may have a first width W1, such that the patterned mask The cap layer 220b and the gate electrode 212 will have substantially the same critical dimension (CD). However, the invention is not limited thereto, in other words, the width of the patterned mask layer may be slightly larger or slightly smaller than the width of the gate electrode, and a slight misalignment is also allowed between the two.

Referring to FIG. 5 and FIG. 6, FIG. 5 is a schematic view showing a first embodiment of the present invention after depositing a dielectric layer, and FIG. 6 is a schematic view showing a first embodiment of the present invention after forming a sidewall. As shown in FIG. 5, a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic vapor deposition process, may be performed to form a dielectric layer 230 to completely cover the gate electrode 212 and the gate. The sidewall spacer 120, the etch stop layer 140, the first interlayer dielectric layer 150, and the patterned mask layer 220b. The dielectric layer 230 includes a material different from the first interlayer dielectric layer 150, such as lanthanum oxynitride, lanthanum oxynitride, tantalum nitride or tantalum carbide, so that there is a certain etching selectivity ratio between each other, but not Limited to this. Next, as shown in FIG. 6, a sidewall spacer 232 is formed on each sidewall of the patterned mask layer 220b by etching the dielectric layer 230 until the interlayer dielectric layer 150 is exposed. Preferably, each of the side walls 232 has a second width W2, and the second width W2 is preferably smaller than the first width W1 of the patterned mask layer 220b. One feature of this embodiment is that the patterned mask layer 220b along with the sidewalls 232 of its sidewalls completely covers the corresponding gate electrode 212, dielectric layer 214 and work function layer below. In other words, the width of the patterned mask layer 220b along with its sidewall sidewalls 232 may be greater than the width of the lower gate electrode 212.

Please refer to FIG. 7, wherein FIG. 7 is a schematic view of the first preferred embodiment of the present invention after forming a contact hole. After the patterning of the mask layer 220b and the sidewalls 232 are completed, as shown in FIG. 7, a second interlayer dielectric layer 240, such as a pre-metal dielectric (PMD), may be deposited. The patterned mask layer 220b, the sidewall spacers 232, and the first interlayer dielectric layer 150 are completely covered. The second interlayer dielectric layer 240 may be, for example, a material similar to the first interlayer dielectric layer 150 such as ruthenium oxide, so that the same or similar etch rate may be obtained from each other. Then, performing photolithography and etching processes, A contact hole 242 is formed in the second interlayer dielectric layer 240 and the first interlayer dielectric layer 150 to expose the epitaxial layer 130 or the substrate 100 between the gate electrodes 212.

It should be noted that the patterned mask layer 220b, the sidewall spacer 232, the gate sidewall spacer 120, the etch stop layer 140, the second interlayer dielectric layer 240, and the first interlayer dielectric layer 150 may have appropriate Etching selection ratio. More specifically, the patterned mask layer 220b, the sidewall spacers 232, the gate sidewall spacers 120, and the etch stop layer 140 are removed at a lower rate than the second interlayer dielectric layer 240 under selected etchants and etch procedures. And the rate at which the first interlayer dielectric layer 150 is removed such that the patterned mask layer 220b, the sidewall spacers 232, the gate sidewall spacers 120, and the etch stop layer 140 are only slightly etched away. Therefore, even if the photolithography process produces misalignment, the contact holes 242 will only expose the epitaxial layer 130 or the substrate 100 without exposing the gate electrodes 212. The etchant described above may be selected from suitable gas components, for example, one or a combination of etching gases including C ₄ F ₆ , C ₅ F ₈ , O ₂ , Ar, CO or CH ₂ F ₂ , but is not limited thereto.

Please refer to FIG. 8, which is a schematic view of the first preferred embodiment of the present invention after forming a contact structure. As shown in FIG. 8, a self-aligned germanium metallization process is performed to form a metal germanide 244 in the epitaxial layer 130. Thereafter, a self-aligned contact structure process is performed, and the barrier layer 245 and the metal layer 246 are sequentially filled into the contact holes 242 to form a self-aligned contact structure 243. It should be noted that the self-aligned contact structure 243 can directly contact the patterned mask layer 220b, the sidewall spacer 232, the gate sidewall spacer 120, the etch stop layer 140, the second interlayer dielectric layer 240, and the first interlayer layer. The dielectric layer 150 is electrically connected to the metal halide 244 below it, but is not limited thereto.

Wherein, the metal halide 244 may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), niobium (Nb), europium (Er), molybdenum (Mo), Cobalt (Co), nickel (Ni), A telluride of a group consisting of platinum (Pt) and its alloys. The self-aligned contact structure 243 may be selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), molybdenum (Mo), cobalt (Co), platinum (Pt), and alloys thereof. group. The barrier layer 245 includes titanium nitride (TiN), tantalum nitride (TaN), titanium/titanium nitride (Ti/TiN), or tantalum/tantalum nitride (Ta/TaN), but is not limited thereto.

Please refer to FIG. 9, wherein FIG. 9 is a schematic view of the first preferred embodiment of the present invention after forming a contact structure. The process time point and structure of FIG. 9 substantially correspond to the process time point and structure of FIG. 8, but FIG. 9 also shows the short axis and long axis cross-sectional structure of the metal gate structure 310. As shown in FIG. 9, the metal gate structure 310 on the left side has a first width W1 similar to that of the metal gate structure 310 of FIG. 8, and the metal gate structure 310 on the right side has a dimension larger than the first width W1. The first length L1 is preferably 5 times or more of the first width W1. Since the patterned mask layer 220b is formed by deposition and etching in this embodiment, it is not necessary to polish the patterned mask layer 220b. Therefore, the patterned mask layer 220b above the metal gate structure 310 on the right side of FIG. 9 is used. There is no case of dishing.

According to the first preferred embodiment described above, the patterned mask layer 220b is formed by deposition and patterning, since it is unnecessary to etch and remove the upper portion of the gate electrode 212 during and after the formation of the patterned mask layer 220b. It is also not necessary to grind the patterned mask layer 220b, so that the degree of height loss of the initial dummy gate structure 110 to the final metal gate structure 310 can be reduced. In this case, the height of the dummy gate structure 110 in the initial stage of the process can be effectively reduced, and the height of the subsequent trench 210 is reduced. Therefore, the dummy gate structure 110 can be easily broken, the shadowing effect of the dummy gate structure 110 during the ion implantation process can be avoided, and the interlayer dielectric layer 150 can be filled into the dummy layer. The ability between the gate structures 110 and the ability to enhance the filling of the conductive layers into the trenches 210. Moreover, since it is unnecessary to etch and remove the upper portion of the gate electrode 212, The etchant cannot etch the underlying structure of the gate electrode 212, such as a dielectric layer or substrate, via defects in the gate electrode 212, such as void defects, which also increases the yield of the process.

In addition, since the present embodiment can selectively form sidewall spacers 232 on the sidewalls of the patterned mask layer 220b, even if the initial dummy gate structures 110 are displaced, or the subsequent patterned mask layer 220b And/or the contact hole 242 has a misalignment situation, which can also complement the deviation through the sidewall 232, so that the patterned mask layer 220b and its corresponding sidewall 232 can still completely cover the corresponding lower side. The gate electrode 212, in turn, avoids unnecessary electrical connections between the self-aligned contact structure 243 and the gate electrode 212.

The variations of the first preferred embodiment of the present invention are described below. For the sake of brevity, the following description is only for the main differences, and the rest of the same or similar processes or structures are referred to the first preferred embodiment described above.

Please refer to FIG. 10, which is a schematic diagram of a semiconductor device according to a variation of the first preferred embodiment of the present invention. The process and structure of the present variation are substantially similar to the processes and structures of the first preferred embodiment described above, the main difference being that the sidewalls of the variant on each side of the patterned mask layer 220b have a multi-layer stack structure, such as The two-layer stacked structure composed of the lower sidewall 232a and the upper sidewall 232b, and the lower sidewall 232a and the upper sidewall 232b may correspond to the oxide layer and the nitride layer, but is not limited thereto. Since the sidewalls have a multi-layer stacked structure, it is not easy to over-etch the first interlayer dielectric layer 150 underneath the sidewalls during the formation of the sidewalls. Since other features and advantages of the present modification are similar to the first preferred embodiment, no further details are provided herein.

Please refer to FIG. 11, which is a schematic diagram of another variation of the semiconductor device according to the first preferred embodiment of the present invention. The process and structure of the present variation are substantially similar to the processes and structures of the first preferred embodiment described above, the main difference being that the side of the variant patterned mask layer 220b does not have sidewalls, so the gate electrode 212 is only The patterned mask layer 220b is covered. It should be noted here that in order to ensure that the gate electrode 212 can be completely protected even in the case of the above alignment error, the patterned mask layer 220b above the gate electrode 212 must have a large width to compensate for the alignment. Defects caused by errors. More specifically, the gate electrode 212 and the patterned mask layer 220b may have a first width W1 and a third width W3, respectively, wherein the first width W1 may be smaller than the third width W3. Since other features and advantages of the present modification are similar to the first preferred embodiment, no further details are provided herein.

Moreover, for the sake of brevity, the first preferred embodiment described above and variations thereof have only the optoelectronic device as the primary application. However, the present invention is not limited thereto, and the spirit thereof can be equally applied to the preparation of other kinds of semiconductor devices. For example, some or all of the above metal gate structures may be replaced by semiconductor devices such as a resistive structure, a capacitor structure, and an electric fuse structure. In other words, the self-aligned contact structure is not limited to be formed between two adjacent metal gate structures, and may be formed between two adjacent resistor structures or two adjacent resistor structures and metal gate structures. Between, but not limited to.

In summary, according to an embodiment of the present invention, a patterned mask layer is formed over the metal electrode by deposition and patterning, and a sidewall is selectively formed further on the sidewall of the patterned mask layer. Since it is not necessary to etch and remove the upper portion of the metal electrode during and after the formation of the patterned mask layer, it is not necessary to grind the patterned mask layer, thereby reducing the degree of height reduction of the initial stack structure to the final stack structure, The situation in which the patterned mask layer is recessed is avoided. In this case, there will be The effect is to reduce the height of the stack structure in the initial stage of the process, and reduce the height of the subsequent trench. Therefore, it is possible to avoid the situation that the stacked structure is easily broken, the shielding effect caused by the stacked structure during ion implantation, the ability to fill the interlayer dielectric layer between the stacked structures, and the ability of the conductive layer to be filled into the respective trenches. In addition, the etchant is also etched through the defects in the metal electrode to destroy the structure under the metal electrode.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Substrate

120‧‧‧ gate sidewall

130‧‧‧ epitaxial layer

140‧‧‧etch stop layer

150‧‧‧First interlayer dielectric layer

212‧‧‧gate electrode

214‧‧‧ dielectric layer

220b‧‧‧ patterned mask layer

232‧‧‧ Sidewall

240‧‧‧Second interlayer dielectric layer

242‧‧‧Contact hole

243‧‧‧ Self-aligned contact structure

244‧‧‧Metal Telluride

245‧‧‧Barrier layer

246‧‧‧metal layer

Claims (21)

A method of fabricating a semiconductor device includes: forming a first interlayer dielectric layer on a substrate; forming a gate electrode on the substrate, wherein a periphery of the gate electrode is formed by the first interlayer dielectric layer Surrounding; forming a patterned mask layer on the gate electrode, wherein a bottom surface of the patterned mask layer is aligned with a top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer And covering a top surface and each side of the patterned mask layer; and forming a self-aligned contact structure in the first interlayer dielectric layer and the second interlayer dielectric layer. The method of fabricating the semiconductor device of claim 1, further comprising: forming a dummy gate electrode on the substrate; removing the dummy gate electrode to leave a trench; forming a gate An electrode is disposed in the trench; a metal layer is deposited to fill the trench; and a portion of the metal layer is removed until the first interlayer dielectric layer is exposed. The method of fabricating the semiconductor device of claim 2, further comprising: forming a gate sidewall on each sidewall of the dummy gate electrode; and sequentially depositing an etch stop layer on each of the gate sidewalls And forming the self-aligned contact structure in the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the self-aligned contact structure directly contacts the etch stop layer. The method of fabricating the semiconductor device of claim 1, wherein the top surface of the first interlayer dielectric layer is substantially aligned with the top surface of the gate electrode before depositing the mask layer. The method of fabricating the semiconductor device of claim 1, further comprising: depositing a mask layer to directly cover a top surface of the gate electrode; and etching the mask layer to form the patterned mask Floor. The method of fabricating a semiconductor device according to claim 1, wherein the patterned mask layer has a width substantially greater than a width of the gate electrode. The method of fabricating the semiconductor device of claim 1, wherein before forming the self-aligned contact structure, further comprising forming a sidewall on each sidewall of the patterned mask layer. The method of fabricating a semiconductor device according to claim 7, wherein each of the sidewall sub-systems has a structure in which an oxide layer and a nitride layer are sequentially stacked. The method of fabricating the semiconductor device of claim 1, wherein the forming the sidewall includes: sequentially depositing a dielectric layer over the patterned mask layer; and etching the dielectric layer, To expose the first interlayer dielectric layer. The method of fabricating the semiconductor device of claim 1, wherein the step of forming the self-aligned contact structure comprises: sequentially etching the second interlayer dielectric layer, the patterned mask layer, and the first layer a dielectric layer to form a contact hole, wherein the contact hole exposes a portion of the substrate; a germanide is formed in the portion; and a metal layer is formed to fill the contact hole. The method of fabricating the semiconductor device of claim 1, wherein the self-aligned contact structure is straight Contact the patterned mask layer. A semiconductor device comprising: a metal gate electrode disposed on a substrate; a first interlayer dielectric layer surrounding the periphery of the metal gate electrode; and a patterned mask layer disposed on the metal gate electrode The bottom surface of one of the patterned mask layers is aligned with a top surface of the first interlayer dielectric layer; a second interlayer dielectric layer covering a top surface and at least one sidewall of the patterned mask layer And a self-aligned contact structure disposed in the first interlayer dielectric layer and the second interlayer dielectric layer and electrically connected to the substrate. The semiconductor device of claim 12, wherein a top surface of the metal gate electrode is substantially aligned with the top surface of the first interlayer dielectric layer. The semiconductor device of claim 12, wherein the first interlayer dielectric layer and the second interlayer dielectric layer comprise ruthenium oxide. The semiconductor device of claim 12, wherein the patterned mask layer comprises tantalum nitride, hafnium nitride, niobium oxynitride or tantalum carbide. The semiconductor device of claim 12, wherein the patterned mask layer has a width substantially greater than a width of the metal gate electrode. The semiconductor device of claim 12, further comprising a sidewall disposed on each sidewall of the patterned mask layer. The semiconductor device of claim 17, wherein each of the sidewalls comprises tantalum nitride, nitrogen carbon Chemical bismuth, bismuth oxynitride or strontium carbide. The semiconductor device of claim 17, wherein the patterned mask layer and each of the sidewalls completely cover the metal gate electrode. The semiconductor device of claim 12, further comprising: a gate sidewall disposed on each sidewall of the metal gate electrode; and an etch stop layer disposed on each of the gate sidewalls and the self Align between the contact structures. The semiconductor device of claim 20, wherein each of the gate sidewalls and each of the etch stop layers comprises tantalum nitride, hafnium nitrite, niobium oxynitride or tantalum carbide.