TW201448068A - Forming process and structure of bump on TSV bottom - Google Patents

Abstract

Disclosed is a forming process of bump on TSV bottom. Embedded in semiconductor material layer of a substrate is at least a TSV conductive pillar which surface is covered by a dielectric liner. Next, the thickness of the semiconductor material layer is reduced from a chip backside to make the bottom portion of the dielectric liner be exposed from the chip backside. A backside passivation is selectively deposited on the chip backside with formed on the bottom of the TSV conductive pillar. Next, the bottom portion of the dielectric liner is selectively etched off. An UBM layer is formed on the backside passivation. Next, a bump is formed on the UBM layer where the interface between the bump and the TSV conductive pillar is centrally lumped toward the bump. Accordingly, the interface between the bump and the TSV conductive pillar has an increased bonding area and an increased metal-to-metal complicated bonding shape.

Description

Process and structure for forming bumps at the bottom of the perforated hole

The present invention relates to a VIA connection of a semiconductor device, and more particularly to a process and structure for forming a bump at the bottom of a crucible.

Through Silicon Via can be applied to advanced semiconductor wafer bonding structures to achieve double-sided conduction of the wafer, enabling high stacking and small size stereo (3D) wafer-to-wafer stacking. The continuous development of Moore's Law can be achieved by using a three-dimensional (3D) wafer stacking technique of 矽 perforation, enabling integrated circuits with high speed and low power in a smaller size. At present, the timing of the formation of perforated perforation is mainly divided into three major schemes, namely, via-first, via-middle and via-last, in which the front section is drilled. The process is formed by the boring of the boring before the formation of the integrated circuit, and the drilling of the middle section is formed by the boring. After the formation of the integrated circuit and before the production of the back end of line (BEOL), the hole in the back is formed by the boring and perforation in the front channel ( FEOL) After the process and back channel (BEOL) process.

In addition, microbumps should also be fabricated on the surface of the wafer for bonding of the stacked wafers. For example, in the process of fabricating microbumps after the middle drilling process, if the microbumps are to be aligned with the tantalum perforated guide posts, the standard process is: crystal back grinding, deep reactive ion etching (DRIE) processing The back mode is to expose a dielectric liner, form a crystal back protective layer, and remove the 矽 perforated pillar by chemical mechanical planarization (CMP) The dielectric lining and the crystal back protective layer on the exit end are then formed into a bump under metal layer (UBM) and plated to form bumps. Wherein, the crystal back protective layer covers the protruding end of the crucible-perforated guide pillar at the same time, and the reason for selecting DRIE is to make the crucible-perforated guide pillar protrude more prominently on the crystal back. Generally, the protruding height needs to be controlled at 5-10 micrometers or more. This is because if the protrusion height is not enough, too many portions of the crystal back protective layer will be removed during chemical mechanical planarization (CMP), which will result in insufficient insulation protection of the crystal back while chemical mechanical planarization (CMP). There is also the problem of copper contamination resulting from the removal of the perforated guide post. In addition, in the structure in which the bump is formed at the bottom of the perforated hole, the metal-to-metal joint interface between the bump and the perforated guide post is relatively flat and smooth due to the above chemical mechanical planarization, and is easily caused by insufficient bonding force. Bump fracture problem.

In order to solve the above problems, the main object of the present invention is to provide a process and structure for forming a bump at the bottom of a perforated hole, which can be applied to a post-middle process, and can increase the bump and the perforated guide post. The interfacial bonding area and the metal-to-metal bonding shape complexity can simplify the thinning technique of the semiconductor material layer and reduce the thinning thickness, and can replace the conventional etching method in the step of thinning to expose the dielectric lining. The DRIE process, in the step of revealing the TSV pillar, can replace the conventional CMP surface planarization process by selectively etching the dielectric liner to reduce copper contamination and reduce the crystal back protective layer and under bump metal The thickness of the layer is used to achieve a low cost and high quality fabrication of the bumps at the bottom of the perforations.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a process for forming a bump on a bottom of a boring hole, comprising the steps of: firstly providing a substrate having a first surface and a second surface, the first surface of the substrate being attached to a wafer carrier a system in which one of the semiconductor material layers is embedded with at least one perforated guide post, and the column wall and the column bottom of the crucible perforation guide post are covered The cover has a dielectric lining. Thereafter, the thickness of the layer of semiconductor material is lowered by the second surface to reveal that the dielectric liner covers a bottom end portion of the column bottom of the crucible-perforated pillar. Thereafter, a crystal back protective layer is selectively deposited on the second surface, and the crystal back protective layer is not formed on the pillar bottom of the crucible perforation pillar. Thereafter, the bottom end portion of the dielectric liner is selectively etched without etching the back protective layer to reveal the bottom of the crucible via post. Thereafter, an under bump metal layer is formed on the crystal back protective layer, and the under bump metal layer is connected to the bottom of the crucible via pillar. Thereafter, a bump is formed on the underlying metal layer of the bump, and an interface between the bump and the meandering via pillar is convex toward the middle of the bump. The invention further discloses a structure in which a bump is formed at the bottom of the perforated hole.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing process, in the step of selectively etching the dielectric liner, the dielectric liner may be formed as a depressed notch ring between the pillar wall of the crucible-perforated pillar and the crystal back protective layer, and In the step of forming the underlying metal layer of the bump, the under bump metal layer is filled into the recessed notch ring, thereby increasing the metal bonding area and joint shape complexity of the under bump metal layer and the germanium via pillar.

In the foregoing process, the depth of the recessed notch ring may not be greater than the thickness of the crystal back protective layer, and the under bump metal layer may be prevented from contacting the semiconductor material layer.

In the foregoing process, the reducing the thickness of the semiconductor material layer may include a crystal back grinding step and a selective etching step, and the pillar bottom of the crucible perforation pillar may protrude slightly from the second surface.

In the foregoing process, the material of the crystal back protective layer is an organic polymer, and the material of the dielectric lining may be an inorganic nitride or an inorganic oxide.

In the foregoing process, the under bump metal layer may include a barrier layer and a plating seed layer.

In the foregoing process, the bump system may include a copper stud bump and a solder layer.

110‧‧‧Substrate

111‧‧‧ first surface

112‧‧‧ second surface

113‧‧‧Semiconductor material layer

114‧‧‧Back-end process circuit layer

120‧‧‧ Wafer Carrying System

121‧‧‧ Temporary adhesive layer

130‧‧‧矽Perforated guide post

131‧‧‧ bottom

140‧‧‧ dielectric lining

141‧‧‧ bottom part

142‧‧‧ Sag gap ring

150‧‧‧ Crystal back protective layer

160‧‧‧ under bump metal layer

161‧‧‧Barrier layer

162‧‧‧Electroplating seed layer

170‧‧‧Bumps

171‧‧‧ copper pillar bumps

172‧‧‧ solder layer

180‧‧‧Light resistance

181‧‧‧Bump opening

1A to 1J are views showing a cross-sectional view of an element in each step of forming a bump at the bottom of the crucible according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with an embodiment of the present invention, a process for forming a bump at the bottom of a crucible is illustrated in the cross-sectional views of the elements in the steps of FIGS. 1A to 1J. The process of forming the bumps at the bottom of the crucible includes the following steps.

First, as shown in FIG. 1A, a substrate 110 is provided having a first surface 111 and a second surface 112. The first surface 111 of the substrate 110 is attached to a wafer carrier system 120 (Wafer Support). The substrate, the semiconductor material layer 113 of the germanium, for example, is embedded with at least one via guide pillar 130. The pillar wall and the pillar bottom 131 of the crucible guide pillar 130 are covered with a dielectric liner 140. . The substrate 110 is The semiconductor wafer can be a via-middle process and a back end of line (BEOL) process, wherein the first surface 111 can be a wafer active surface. In this step, the second surface 112 can be a back surface of the wafer that has not been thinned. The thickness of the substrate 110 from the first surface 111 to the second surface 112 can be about 775 micrometers, which is much larger than the thickness. The length of the perforated guide post 130. The material of the crucible-perforated guide post 130 may be copper or a copper alloy. The material of the dielectric liner 140 may be an inorganic nitride or an inorganic oxide such as tantalum nitride or hafnium oxide. The column bottom 131 of the crucible-perforated guide post 130 faces the second surface 112. After the dowel-perforated pillars 130 are formed, a first back-end process wiring layer 114 is formed on the first surface 111 to electrically connect the crucible-perforated pillars 130. The wafer carrier system 120 adheres the first surface 111 of the substrate 110 with a temporary adhesive layer 121 to prevent deformation of the substrate 110 during the process. The wafer carrier system 120 can be a glass wafer or a wafer. The temporary adhesive layer 121 can be a photosensitive adhesive, for example, after being exposed to ultraviolet light, the viscosity can be lost to facilitate stripping the crystal after the process. The circular carrying system 120. After the following steps include the fabrication of the bumps 170, the substrate 110 is attached to the wafer carrier system 120.

Thereafter, as shown in FIG. 1B, the thickness of the semiconductor material layer 113 is lowered by the second surface 112. In this step, the reducing the thickness of the semiconductor material layer 113 may include a backside grinding step and a selective etching step. The back grinding step handles a substantial portion of the reduced thickness of the semiconductor material layer 113, but does not expose the germanium via pillars 130 and the dielectric liner 140. As shown in FIG. 1C, the selective etching step is a dry etching or wet etching method in which only the semiconductor material is etched but the dielectric liner 140 is not etched, and an inductive coupling plasma system (ICP) can be used as an example of the dry etching process. System,Inductively Coupled plasma system), the treatment room is fed with sulfur hexafluoride (SF6) as a plasma counter Gas, it may also contain oxygen, chlorine (Cl2), argon (Ar), helium (He), hydrogen bromide (HBr), etc., the power supply at the top of the processing chamber can be 500~3000W, the power supply at the bottom of the processing chamber can be In the wet etching process, for example, a semiconductor etchant of a potassium hydroxide (KOH) substrate or a TMAH (Tetramethylammonium hydroxide) substrate may be used. The thickness of the semiconductor material layer 113 is continuously reduced by the second surface 112 to expose the dielectric liner 140 covering a bottom end portion 141 of the column bottom 131 of the crucible perforation pillar 130. Preferably, the crucible is in the step. The column bottom 131 of the perforated guide post 130 protrudes slightly from the second surface 112. In this step, the thickness of the substrate 110 from the first surface 111 to the second surface 112 can be reduced to a level of 100 microns or less. The height of the pillar bottom 131 of the crucible-perforated pillar 130 slightly protruding from the second surface 112 may be between 1 and 5 micrometers, which is lower than the 5-10 micrometer required by the conventional DRIE process, and the There is a risk that the perforated guide post 130 will fail to engage the post 170 formed by the post process.

Thereafter, as shown in FIG. 1D, a back protective layer 150 is selectively deposited on the second surface 112, and the back protective layer 150 is not formed on the pillar bottom 131 of the crucible via pillar 130. In this embodiment, the material of the crystal back protective layer 150 is an organic polymer, and the dielectric lining 140 has different inorganic materials. The deposition thickness of the crystal back protective layer 150 may not be greater than the micro-protrusion height of the crucible-perforated pillars 130. The crystal back protective layer 150 is deposited only on the semiconductor material layer 113 and is not deposited on the dielectric liner 140. One of the above selective deposition methods is a wet process electrografting technology. A crystalline back protective layer 150 is not deposited on the dielectric liner 140.

Thereafter, as shown in FIG. 1E, the bottom end portion 141 of the dielectric liner 140 is selectively etched without etching the back protective layer 150 to expose the pillar bottom 131 of the crucible-perforated pillar 130. The selective etching step is to etch only the dielectric liner 140 but not to etch the crystal back protective layer 150. The dry etching or wet etching method of the crucible-perforated pillar 130 can be performed by using an inductively coupled plasma system (ICP system) as an example of a dry etching process, and sulfur tetrafluoride (CF4) is introduced into the processing chamber. The plasma reaction gas may further contain oxygen, octafluorocyclobutane (C4F8), argon (Ar), etc., the power supply at the top of the processing chamber may be 300~3000W, and the power supply at the bottom of the processing chamber may be 0~2000W; For example, the etching process may be performed by etching a mixture of hydrogen fluoride (HF) and a diluent in a ratio of 1:20 or other ratios to etch the dielectric liner 140, so that the back protective layer 150 is not etched during selective etching. Preferably, in the step of selectively etching the dielectric liner 140, the dielectric liner 140 may be formed as a concave notch ring 142 between the pillar wall of the crucible-perforated pillar 130 and the crystal back protective layer 150. . Therefore, in the step of exposing the crucible-perforated pillar 130, the conventional CMP surface planarization process can be replaced by selectively etching the dielectric liner 140 without consuming the crystal back protective layer 150 and the crucible perforation guide. Column 130, the copper contamination and process costs incurred in this step can be significantly reduced.

Then, as shown in FIG. 1F, a sub-bump metal layer 160 may be formed on the crystal back protective layer 150 by physical vapor deposition, and the under bump metal layer 160 is connected to the crucible via pillar 130. Column bottom 131. In this step, the under bump metal layer 160 may include a barrier layer 161 and a plating seed layer 162. The barrier layer 161 may be made of titanium (Ti), nickel (Ni), or titanium nitride. (TiN) or tantalum (Ta) or the like to prevent metal diffusion; the plating seed layer 162 has high conductivity, such as copper, aluminum, gold or an alloy thereof or a combination of layers. Moreover, in the step of forming the under bump metal layer 160, the under bump metal layer 160 is preferably filled into the recessed notch ring 142, thereby increasing the under bump metal layer 160 and the germanium via guide pillar. The metal joint area and joint shape complexity of 130. In addition, the depth of the recessed notch ring 142 may be no greater than the thickness of the crystal back protective layer 150, for example, less than 5 micrometers, to prevent the under bump metal layer 160 from contacting the semiconductor material layer. 113.

As shown in FIG. 1G, a photoresist 180 may be formed on the under bump metal layer 160 and exposed to develop at least one bump opening 181 aligned on the via via pillar 130. As shown in FIG. 1H, under the conduction of the under bump metal layer 160 and in accordance with the shape of the bump opening 181, a bump 170 may be electroplated to form the under bump metal layer 160, the bump 170 and The interface between the turns of the guide posts 130 is convex toward the middle of the bumps 170. The intermediate convex shape is hollow in accordance with the micro-protrusion height of the crucible-perforated guide post 130. In this embodiment, the bump 170 can include a copper stud bump 171 and a solder layer 172, which can be fabricated by the same photoresist in the same electroplating process.

As shown in FIG. 1I, the photoresist 180 is removed by photoresist removal to expose the under bump metal layer 160 at other portions of the bump 170. As shown in FIG. 1J, the exposed portion of the under bump metal layer 160 outside the bump 170 is removed by etching. Therefore, according to the above process, a structure in which a bump is formed at the bottom of the perforated hole as shown in FIG. 1J can be obtained.

Therefore, the process and structure for forming a bump on the bottom of the perforated hole can increase the interface joint area between the bump and the perforated guide post and the metal-to-metal joint shape complexity, and can simplify the thin layer of the semiconductor material. The technique and the reduction of the thickness of the thinning can be replaced by a conventional DRIE process in a general etching manner in the step of thinning to expose the dielectric liner, and the dielectric lining can be selectively etched in the step of revealing the TSV pillar. It replaces the conventional CMP surface flattening process to reduce copper contamination and reduce the thickness of the crystal back protective layer and the under bump metal layer, thereby achieving the low cost and high quality fabrication of the bump forming bottom.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the skilled artisan without departing from the technical scope of the present invention.

110‧‧‧Substrate

111‧‧‧ first surface

112‧‧‧ second surface

113‧‧‧Semiconductor material layer

114‧‧‧Back-end process circuit layer

120‧‧‧ Wafer Carrying System

121‧‧‧ Temporary adhesive layer

130‧‧‧矽Perforated guide post

131‧‧‧ bottom

140‧‧‧ dielectric lining

142‧‧‧ Sag gap ring

150‧‧‧ Crystal back protective layer

160‧‧‧ under bump metal layer

161‧‧‧Barrier layer

162‧‧‧Electroplating seed layer

170‧‧‧Bumps

171‧‧‧ copper pillar bumps

172‧‧‧ solder layer

Claims (10)

A process for forming a bump on a bottom of a perforated hole, comprising: providing a substrate having a first surface and a second surface, the first surface of the substrate being attached to a wafer carrying system, the semiconductor of the substrate At least one perforated guide post is embedded in the material layer, and the column wall and the column bottom of the crucible perforation guide post are covered with a dielectric lining; the thickness of the semiconductor material layer is lowered by the second surface to reveal the dielectric The lining covers a bottom end portion of the bottom of the column of the crucible perforated guide post; selectively depositing a back protective layer on the second surface, the back protective layer is not formed on the bottom of the crucible perforated guide post Selectively etching the bottom end portion of the dielectric liner without etching the crystal back protective layer to expose the bottom of the pillar of the crucible-perforated pillar; forming a sub-bump metal layer on the crystal back protective layer, An under bump metal layer is connected to the bottom of the crucible via post; and a bump is formed on the under bump metal layer, and an interface between the bump and the crucible via post is toward the bump The middle is convex. a process for forming a bump in a bottom of a perforated hole according to the first aspect of the patent application, wherein in the step of selectively etching the dielectric liner, the dielectric liner is on a column wall of the crucible-perforated guide post and the crystal back protective layer The interlayer is formed as a depressed notch ring, and in the step of forming the underlying metal layer of the bump, the under bump metal layer is filled into the depressed notch ring. According to the second aspect of the patent application, the process of forming a bump at the bottom of the perforation is performed, wherein the depth of the recessed notch is not greater than the thickness of the back protective layer. The method for forming a bump at the bottom of the perforated hole according to the first aspect of the patent application, wherein the reducing the thickness of the semiconductor material layer comprises a crystal back grinding step and a selective etching step, wherein the column bottom of the crucible perforating column is micro Projecting on the second surface. According to the first aspect of the patent application, the process of forming a bump at the bottom of the perforated layer is made of an organic polymer, and the material of the dielectric liner is an inorganic nitride or an inorganic oxide. According to the first aspect of the patent application, the process of forming a bump at the bottom of the perforation is provided, wherein the under bump metal layer comprises a barrier layer and a plating seed layer. According to the first aspect of the patent application, the process of forming a bump at the bottom of the perforated hole includes a copper stud bump and a solder layer. A structure for forming a bump on a bottom of a perforated hole, comprising: a substrate having a first surface and a second surface, the first surface of the substrate being attached to a wafer carrying system, the semiconductor material of the substrate The inner layer is embedded with at least one perforated guide post, the column wall of the crucible perforated guide post is covered with a dielectric lining; and a crystal back protective layer is selectively deposited on the second surface, the crystal back protective layer The bottom of the column of the crucible-perforated guide post is not slightly formed on the second surface; a sub-bump metal layer is formed on the crystal back protective layer. The under bump metal layer is connected to the pillar bottom of the crucible perforation pillar; and a bump is formed on the under bump metal layer, and the interface between the bump and the crucible perforation pillar is It is convex toward the middle of the bump. a structure in which a bump is formed at the bottom of the perforation according to the eighth aspect of the patent application, wherein the dielectric liner is formed as a concave notch ring between the pillar wall of the crucible perforation pillar and the crystal back protective layer, and the convex The under-metal layer is filled into the recessed notch ring. According to the eighth aspect of the patent application, the structure of the bottom of the perforated hole is formed by a bump, wherein the material of the back protective layer is an organic polymer, and the material of the dielectric liner is an inorganic nitride or an inorganic oxide.