TW201444284A - Semiconductor device - Google Patents

Abstract

To more precisely adjust impedance of an output terminal. Impedance of an output buffer (unit buffer) included in an I/O circuit is adjusted on the basis of impedance of a pull-up circuit (replica circuit) included in a calibration circuit. In the calibration circuit, a pull-up circuit (310), a damping resistor (R21), a correction resistor (311), an electrostatic protection unit (312), and an external resistor (Re) are connected in series. The potential at the connection of the correction resistor (311) with the electrostatic protection unit (312) is compared with a reference potential by a comparator (360). The resistance value of the correction resistor (311) is determined on the basis of line resistances of lines which are respectively connected to a data terminal and a calibration terminal (ZQ).

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an input/output circuit that can adjust the impedance of an output buffer.

In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a correction circuit for adjusting the impedance of the output buffer is provided in order to adjust the impedance of the output terminal (see Patent Document 1). The output buffer has a pull-up output unit and a pull-down output unit, and these impedances are controlled in accordance with the pull-up impedance code and the pull-down impedance code generated by the correction circuit.

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-183717

The correction circuit has a replica buffer substantially identical to the output buffer of the input/output circuit. First, the voltage of the correction terminal is compared with the reference voltage in a state where the external impedance is connected to the correction terminal, and the impedance of the replica buffer is adjusted. And, the adjustment content of the copy buffer is reflected in the output buffer.

In such a correction circuit, the impedance of the replica buffer and the output buffer is adjusted in response to the external impedance connected to the correction terminal.

However, since the correction circuit and the wiring structure of a part of the input/output circuit system are different, the inventors have thought about the difference, and the impedance of the adjusted output buffer has a slight deviation from the desired impedance. It is better to adjust the impedance of the output buffer after correcting the adjustment deviation according to such a wiring structure.

A semiconductor device according to one aspect of the present invention includes: a data terminal and a correction terminal; and an output buffer; and a first impedance portion connected to the output buffer at one end; and the data terminal and the first impedance portion are connected a first wiring at the other end thereof, a replica circuit having substantially the same impedance as the output buffer, a comparison circuit, and a second impedance portion connected to the replica circuit at one end, and connected to the aforementioned one end at one end a third impedance portion at the other end of the second impedance portion, a second wiring connecting the other end of the third impedance portion and the correction terminal, and a third terminal connected to the third impedance portion and a third portion of the comparison circuit In the line, the impedance value of the third impedance portion is characterized by being larger than the impedance value of the first wiring and the impedance value of the second wiring.

Semiconductor device harness through the other side of the invention Ready: Output buffer, and correction circuit. The correction circuit includes a replica circuit and a comparator, and the impedance of the replica circuit is adjusted according to the output of the comparator, and the adjustment result is reflected in the output buffer. Furthermore, the correction circuit includes a second damping resistor and a correction resistor connected in series between the replica circuit and an input terminal of the comparator.

According to the present invention, the impedance of the output buffer of the semiconductor device can be more preferably set.

2‧‧‧External substrate

10‧‧‧Semiconductor device

11‧‧‧Memory cell array

12‧‧‧ line decoder

13‧‧‧ column decoder

14‧‧‧ mode register

15‧‧‧Latch circuit

16‧‧‧Output and input circuit

18‧‧‧ Pulling circuit

19‧‧‧ Pulldown circuit

21‧‧‧Command Address Terminal

22‧‧‧ wafer selection terminal

23‧‧‧ Clock Terminal

24‧‧‧data terminal

25,26‧‧‧Power terminals

31‧‧‧CA input circuit

32‧‧‧ address latch circuit

34‧‧‧ instruction decoding circuit

36‧‧‧clock input circuit

39‧‧‧Internal power generation circuit

50‧‧‧Adjust buffer

54‧‧‧ clock generation circuit

100‧‧‧correction circuit

101‧‧‧Output circuit

110,120,130‧‧‧Output unit

111~114,121,122,131‧‧‧unit buffer

141~143‧‧‧front circuit

150‧‧‧Output control circuit

160‧‧‧Electrostatic Protection Department

170‧‧‧Input buffer

310,320‧‧‧ Pull-up circuit

311,321,331,3111~3113‧‧‧corrected impedance

312‧‧‧Electrostatic Protection Department

330‧‧‧ Pulldown circuit

340,350‧‧‧ counter

360, 370‧‧‧ comparator

380‧‧‧Voltage generation circuit

390‧‧‧correction control circuit

BWD, BWZ‧‧‧ bonding wire

DL‧‧‧ diffusion layer

DQP‧‧‧Material gasket

ESD1, ESD2‧‧‧ESD components

G‧‧‧gate electrode

GI‧‧‧gate insulating film

GL‧‧‧ gate wiring layer

IL1~IL4‧‧‧ interlayer insulation

L1~L4‧‧‧ wiring layer

PSDL, PSZL‧‧‧ power cord

R11~R14, R21~R23‧‧‧ damping resistor

Re‧‧‧External impedance

SS‧‧‧Substrate

TH0~TH3‧‧‧through hole electrode

TL‧‧‧Tungsten layer

ZQL1, ZQL2‧‧‧corrected wiring

ZQP‧‧‧ calibration gasket

Fig. 1 is a block diagram showing the overall configuration of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a block diagram showing the composition of an input/output circuit.

Figure 3 is a circuit diagram of a unit buffer.

Figure 4 is a circuit diagram of the correction circuit.

Figure 5 is a circuit diagram of the pull-up circuit.

Figure 6 is a circuit diagram of the pull-down circuit.

Figure 7 shows the wiring impedance when considering the wiring passing through the electrostatic protection portion. A circuit diagram of the connection relationship between the data terminal and the output circuit.

Fig. 8 is a schematic view showing the layout between the data terminal and the output circuit.

FIG. 9 is a view schematically showing a multilayer wiring structure included in the semiconductor device according to the embodiment.

Fig. 10 is a circuit diagram showing the configuration of an adjustment buffer of a conventional correction circuit.

Fig. 11 is a circuit diagram showing a connection relationship between a correction circuit, a correction impedance, an electrostatic protection unit, a comparator, and a correction terminal in the correction circuit of the present embodiment (first configuration example).

Fig. 12 is a schematic view showing the layout between the correction terminal and the pull-up circuit and the comparator in the first configuration example.

Fig. 13 is a circuit diagram showing a connection relationship between a correction circuit, a correction impedance, an electrostatic protection unit, a comparator, and a correction terminal in the correction circuit of the present embodiment (second configuration example).

Fig. 14 is a schematic view showing the layout between the data terminal and the output circuit in the second configuration example.

Fig. 15 is a schematic view showing the layout between the correction terminal and the pull-up circuit and the comparator in the second configuration example.

Fig. 16 is a circuit diagram showing the connection relationship between the data terminal and the output circuit in consideration of the power supply parasitic impedance and the combined impedance.

Fig. 17 is a circuit diagram showing a connection relationship between a correction circuit, a correction impedance, an electrostatic protection unit, a comparator, and a correction terminal in the correction circuit of the present embodiment (third configuration example).

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to additional drawings.

Fig. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

The semiconductor device 10 of the present embodiment is mounted on a DRAM of a single semiconductor wafer and mounted on the external substrate 2. The external substrate 2 is a wiring board such as a mother board, and is provided with an external impedance Re. One end of the external impedance Re is electrically connected to the correction terminal ZQ of the semiconductor device 10. The details of the correction circuit 100 will be described later. In the present embodiment, the external impedance Re has an impedance value of 240 Ω, and the other end of the external impedance Re is supplied with the ground potential VSS.

The semiconductor device 10 has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and the memory cells MC are arranged at such intersections. The word line WL is selected by the row decoder 12, and the bit line BL is selected by the column decoder 13. Further, the pulse terminal 23, the command address terminal 21, the wafer selection terminal 22, the data terminal 24, the power supply terminals 25, 26, and the correction terminal ZQ are provided as external terminals of the semiconductor device 10.

The clock terminal 23 is connected to a terminal having an external clock signal CK, /CK. In the present specification, a signal having a "/" at the head of the signal name means an inverted signal of a corresponding signal or a signal of low activity. Accordingly, the external clock signal / CK is an inverted signal of the external clock signal CK. The external clock signals CK and /CK are supplied to the clock input circuit 36. The external clock signal CK, /CK supplied to the clock input circuit 36 is supplied to the clock generating circuit 54. The clock generation circuit 54 generates an internal clock signal ICLK based on the external clock signals CK, /CK. The internal clock signal ICLK is supplied to the address latch circuit 32, the command decoding circuit 34, the circuit unit such as the correction circuit 100 and the latch circuit 15, and the operation time of these circuit units is specified.

For the instruction address terminal 21, the input has an instruction address. Signal CA. The command address signal constitutes a command signal CMD and an address signal ADD. A wafer selection signal /CS is input to the wafer selection terminal 22. These signals are supplied to an instruction address (CA) input circuit 31. Among the signals supplied to the command address input circuit, the address signal ADD is supplied to the address latch circuit 32, and the command signal CMD is supplied to the command decoding circuit 34.

The address latch circuit 32 is synchronized to the internal clock ICLK. The latch address signal ADD. The row address of the latched address signal ADD is supplied to the row decoder 12, and the column address is supplied to the column decoder 13. Further, in the case of input to the mode register device, the address signal ADD is supplied to the mode register 14 as a mode setting signal. The mode register 14 sets parameters for displaying the operation mode of the semiconductor device 10. The drive capability setting signal DS is displayed among the parameters of the operation mode displayed by the mode register of Fig. 1. Although the details are described later, the drive capability setting signal DS is a unit buffer that is specified to be activated by one or more of the unit buffers in the input/output circuit 16 and activated at the time of data output.

The instruction decode circuit 34 is synchronized to the internal clock ICLK, Various internal commands are generated when the command signal CMD is held, decoded, counted, or the like. The internal command system includes an enable signal IACT, a column signal ICOL, a mode register device signal MRS, a correction signal ZQCOM, and the like.

The start signal IACT is displayed on the command signal CMD. It is activated by access (start command). When the enable signal IACT is activated, the address signal ADD latched to the address latch circuit 32 is supplied to the row decoder 12 as a row address. Thereby, the word line WL specified by the address register is selected.

Column signal ICOL is displayed in the command signal CMD Activate it by taking the situation. Here, the column access means that the read access is prepared when each of the preparation command signals is a read command, and the write access is prepared when the command signal is a write command. When the internal column signal ICOL is activated, the address signal ADD latched to the address latch circuit 32 is supplied to the column decoder 13 as a column access. Thereby, the bit line BL specified by the column access is selected.

Then, while the start command and the read command are sequentially input, When the row address and the column address are input, the read data is read from the memory cells MC designated by the row address and the column address. The read data DQ is output from the data terminal 24 by the latch circuit 15 and the input/output circuit 16. On the other hand, while the start command and the write command are sequentially input, the input row address and the column address are synchronized, and then, when the write data DQ is input to the data terminal 24, the data DQ is written by lose The input circuit 16 and the latch circuit 15 are supplied to the memory cell array 11 and written to the memory cell MC designated by the row address and the column address. The latch circuit 15 performs data transfer between the memory cell array 11 and the input/output circuit 16 in synchronization with the internal clock signal ICLK.

The mode register device signal MRS is tied to the command signal CMD Then, the status of the register device command is displayed and activated. Accordingly, when the mode register device command is input, if the semiconductor device 10 is input to the mode register device, and the mode signal is input from the command address terminal 21 in synchronization with this, the mode register 14 can be rewritten. The set value.

The correction signal ZQCOM is displayed on the command signal CMD It is activated by correcting the command. The correction command is issued at the time of initializing the semiconductor device 10, and is also periodically issued during normal operation. The correction signal ZQCOM activates the correction circuit 100. The correction circuit 100 performs a correcting operation in synchronization with the internal clock signal ICLK in response to the correction signal ZQCOM, and thereby adjusts the impedance of the output circuit 101 included in the input/output circuit 16. The details of the correction circuit 100 and the output circuit 101 will be described later.

The power supply terminal 25 is supplied with a power supply potential VDD, VSS. The power supply potential VDD and VSS are supplied to the internal power supply circuit 39 via the power supply terminal 25. The internal power generating circuit 39 generates various internal potentials VPP, VOD, VARY, and VPERI in accordance with the power supply potentials VDD and VSS. The internal potential VPP is mainly used by the row decoder 12, and the internal potentials VOD, VARY are used in the sense amplifiers in the memory cell array 11, and the internal potential VPERI is in many other places. Used by circuit units.

The power supply terminal 26 is supplied with a power supply potential VDDQ, VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 16 and used as an operation power supply of the output circuit 101 included in the input/output circuit 16. The potential of the power supply potential VDDQ is the same as the power supply potential VDD, and the potential of the power supply potential VSSQ is the same as the power supply potential VSS. However, the power supply noise generated by the operation of the output circuit 101 is not transmitted to another circuit and the power supply path is separated. . However, it is not necessary to perform such a separation of the power paths in the present invention.

2 is a block diagram showing the configuration of the input/output circuit 16.

As shown in FIG. 2, the input/output circuit 16 includes an output circuit 101, an input buffer 170, front stage circuits 141, 142, and 143, and an output control circuit 150. The input/output circuit 16 further includes an electrostatic protection unit 160. The details of the electrostatic protection unit 160 will be described later.

The output circuit 101 includes three output units of the output units 110, 120, 130. However, the number of output units of the present invention is not limited to three.

Each of the output units 110 includes four unit buffers (output buffers) 111 to 114 and damping resistors R11 and R12 each connected in parallel with 60 Ω, and the output unit 120 includes two unit buffers (output buffers) 121. The output unit 130 includes one unit buffer (output buffer) 131 and 120 Ω (r1) damping resistor R14 (first impedance portion, first damping resistor). Here, as the damping resistors R11 to R14, for example, a diffusion layer, tungsten (W), titanium nitride can be used. High-impedance routers such as (TiN). However, the number of unit buffers, the number of damping resistors, and the impedance value in the output unit of the present invention are not limited to those shown in FIG. Each of the unit buffers 111 to 114, 121, 122, and 131 can adjust the impedance (first impedance). In the present embodiment, the impedance of each of the unit buffers 111 to 114, 121, 122, and 131 is adjusted to 120 Ω. As a component of this configuration, the correction circuit can be simplified by collectively adjusting the impedance of the complex unit buffer in one correction circuit.

In addition, when looking at each output unit, the output unit 110 is The data terminal 24 is adjusted by the 60 Ω driving data terminal, the output unit 120 is adjusted by driving the data terminal 24 with 120 Ω, and the output unit 130 is adjusted by driving the data terminal 24 with 240 Ω. In other words, each output unit is designed to have an impedance that is substantially equal to the value of the unit buffer included in itself and the impedance value of the external impedance Re after adjustment of the impedance of each unit buffer.

In addition, each unit buffer 111~114, 121, 122, When the reading operation is performed, the 131 system is activated by the activation of the output units 110, 120, and 130 included therein, and the data terminal 24 is driven to either the high level or the low level.

For the output units 110~130, the previous section is set with each front Segment circuits 141 to 143. The front-end circuits 141 to 143 specify whether or not to activate the corresponding output unit, and then adjust the impedance of the unit buffer included in the corresponding output unit. As shown in FIG. 2, the front-end circuits 141 to 143 are supplied with the activation signals 151P to 153P and the activation signals 151N to 153N from the output control circuit 150, and the impedance adjustment code is commonly supplied from the correction circuit 100. DRZQ. That is, the front-end circuits 141 to 143 pass through the activation signals 151P to 153P or the activation signals 151N to 153N, and only when the corresponding output unit is activated, whether or not to be included in the corresponding output unit is determined by the impedance adjustment code DRZQ. Any one of the plurality of output transistors (described later) of the unit buffers 111 to 114, 121, 122, and 131 is turned on. The on/off of these output transistors is specified by the activation signals 141P to 143P and the activation signals 141N to 143N.

The output control circuit 150 specifies a plurality of output units At the same time as the output units 110 to 130 which are activated in the range of 110 to 130, the output logic level of the unit buffer to be activated is designated. The designation of the output unit to be activated is based on the drive capability setting signal DS supplied from the mode register 14.

Thus, the output control circuit 150 is based on the driving capability. The signal DS is set to select the output unit of the activation target, and the number of unit buffers for driving the data terminal is changed. When the number of activated unit buffers changes, the impedance (output impedance) of the output terminals changes. As shown in FIG. 2, in the present embodiment, the unit buffers 111 to 114, 121, 122, and 131 are connected in parallel between the output control circuit 150 and the data terminal 24, and the activated unit buffer is As the number increases, the output impedance decreases, and conversely, as the number of activated unit buffers decreases, the output impedance increases.

FIG. 3 is a circuit diagram of the unit buffer 131.

As shown in FIG. 3, the unit buffer 131 is provided with a plurality of parallel connection between a power supply line (power supply potential VDDQ) and a node B. (5 in the present embodiment) P-channel MOS transistors (output transistors, first transistors) 211 to 215, and a plurality of parallel connection between the power supply line (power supply potential VSSQ) and the node B ( In the present embodiment, five) N-channel MOS transistors (output transistors, second transistors) 221 to 225 are used. Further, the node B is connected to the data terminal 24 by a damping resistor R14 and an electrostatic protection unit 160. Among the unit buffers 131, the portions of the P-channel MOS transistors 211 to 215 constitute the pull-up circuit 18, and the portions of the N-channel MOS transistors 221 to 225 constitute the pull-down circuit 19.

Five activation signals 143P1 to 143P5 constituting the activation signal 143P are supplied to the gates of the output transistors 211 to 215, and five activation signals 143N are supplied to the gates of the output transistors 221 to 225. The activation signal is 143N1~143N5. Thereby, the 10 MOS electro-crystal systems included in the unit buffer 131 are individually turned on/off controlled via the 10 activation signals 143P1 to 143P5 and the activation signals 143N1 to 143N5.

The pull-up circuit 18 and the pull-down circuit 19 are each designed to have a specific impedance (120 Ω in the embodiment) at the time of conduction. However, the desired impedance is not necessarily obtained from the case where the opening impedance of the output transistor is varied due to the uneven manufacturing conditions and the ambient temperature or the power supply voltage during the operation. Therefore, in order to use the actual impedance as the target value, it is necessary to adjust the number of output transistors to be turned on, and for the related purpose, a parallel circuit formed by a plurality of output transistors is used.

For the purpose of making the impedance of the unit buffer 131 fine and wide The range is adjusted so that the W/L ratio (gate width/gate length ratio) of the plurality of output transistors constituting the pull-up circuit 18 and the pull-down circuit 19 is preferably different from each other as a power of two. Weighting is especially desirable. That is, when the W/L ratio of the output transistor 211 is "1WLp", the W/L ratio of the output transistors 212 to 215 is set to "2WLp", "4WLp", "8WLp", and "16WLp". It is especially ideal. Similarly, when the W/L ratio of the output transistor 221 is "1WLn", the W/L ratios of the output transistors 222 to 225 are set to "2WLn", "4WLn", "8WLn", and "16WLn". It is especially ideal.

The other unit buffers 111-114, 121, 122 are substantially the same as the unit buffer 131 shown in FIG. 3 except that the corresponding activation signals 141P, 142P and the operation signals 141N, 142N are input. The circuit is constructed.

4 is a circuit diagram of the correction circuit 100.

As shown in FIG. 4, the correction circuit 100 includes: a pull-up circuit (replication circuit) 310, 320, and a pull-down circuit 330, and a counter 340 that controls the operation of the pull-up circuits 310, 320, and controls the action of the pull-down circuit 330. A counter 350, and a comparator 360 for controlling the counter 340, and a comparator 370 for controlling the counter 350, and a voltage generating circuit 380 for supplying a reference voltage ZQVREF (= 1/2 VDD) to the comparators 360, 370, and an action signal for generating a counter ACT1, ACT2 correction control circuit 390. Further, the correction circuit 100 includes a damping resistor R21 (second impedance portion, second damping impedance) connected in series between the pull-up circuit 310 and the correction terminal ZQ, and a correction impedance 311 (third impedance portion, The impedance is corrected, and the electrostatic protection portion 312. In addition, the correction circuit 100 includes: a damping resistor R22 and a correction impedance 321 connected between the pull-up circuit 320 and the node A, and a damping resistor R23 and a correction impedance connected between the pull-down circuit 330 and the node A. 331. Node A is connected to an input terminal of one of the comparators 370. The details of the correction impedance 311 and the electrostatic protection portion 312 will be described later.

FIG. 5 is a circuit diagram of the pull-up circuit 310.

As shown in FIG. 5, the pull-up circuit 310 has substantially the same circuit configuration as the pull-up circuit 18 included in the unit buffers 111-114, 121, 122, and 131. Specifically, the pull-up circuit 310 includes five P-channel MOS transistors 411 to 415 connected in parallel between the power supply line (power supply potential VDD) and the damping resistor R21.

Hereinafter, the pull-up circuit 310, the correction impedance 311, the electrostatic protection unit 312, the correction terminal ZQ, and the external impedance Re are referred to as "adjustment buffer 50 (second buffer)".

The transistors 411 to 415 included in the pull-up circuit 310 correspond to the output transistors 211 to 215 shown in FIG. 3, each having the same impedance. Accordingly, similarly to the W/L ratio of the transistors 211 to 215, the W/L ratios of the transistors 411 to 415 are also set to "1WLp", "2WLp", "4WLp", "8WLp", and "16WLp". However, if the impedances are substantially the same, the transistors 411 to 415 included in the pull-up circuit 310 and the output transistors 211 to 215 shown in FIG. 3 do not need to have the same crystal size, and a reduced transistor may be used.

For the gates of the transistors 411~415, the self-counter 340 The impedance codes DRZQP1 to DRZQP5 are supplied, and the pull-up circuit 310 is controlled thereby. The impedance codes DRZQP1 to DRZQP5 correspond to the activation signals 141P1 to 141P5, respectively.

For the pull-up circuit 320, it also has the pull-up as shown in FIG. Circuit 310 is constructed in the same circuit. The impedance codes DRZQP1 to DRZQP5 are also supplied to the gates of the five transistors included on the side of the pull-up circuit 320.

FIG. 6 is a circuit diagram of the pull-down circuit 330.

As shown in FIG. 6, the pull-down circuit 330 has and is included in the single The bit buffers 111 to 114, 121, 122, and 131 are substantially identical in circuit configuration. Specifically, the pull-down circuit 330 includes five N-channel MOS transistors 421 to 425 connected in parallel between the power supply line (power supply potential VSS) and the node A. The transistors 421 to 425 included in the pull-down circuit 330 correspond to the transistors 221 to 225 shown in FIG. 3, each having the same impedance. This point is the same as the pull-up circuit 310.

Damping resistor R21 corresponds to the output unit shown in Figure 2. The damping resistor R14 of 130 has an impedance value set at 120 Ω. The reason for this is that, in the present embodiment, the correction circuit 100 is configured to correspond to an output unit formed by one unit buffer, that is, the output unit 130 of FIG.

In addition, the damping resistor R22 and the correction impedance 321 are pairs Should be the impedance of the damping resistor R21 and the correction impedance 311. With such a configuration, the node C viewed from the pull-up circuit 310 and the node A viewed from the pull-up circuit 320 have substantially the same relationship. Here, the damping resistor R22 has substantially the same impedance value (120 Ω) as the damping resistor R21, and Further, the correction impedance 321 has substantially the same impedance value (described later) as the correction impedance 311.

In addition, the damping resistor R23 and the correction impedance 331 are pairs Should be the impedance of the damping resistor R22 and the correction impedance 321 . As a component of this configuration, the pull-up circuit 320 viewed from the node A has substantially the same relationship as the pull-down circuit 330 from the node A, and the adjuster of the pull-down circuit 330 can be performed more accurately. Here, the damping resistor R23 has substantially the same impedance value (120 Ω) as the damping resistor R22, and the correction impedance 331 has substantially the same impedance value as the correction impedance 321 .

For the gates of the transistors 421 ~ 425 from the counter 350 The impedance codes DRZQN1 to DRZQN5 are supplied, and the pull-down circuit 330 is controlled thereby. The impedance codes DRZQN1 to DRZQN5 correspond to the activation signals 161N1 to 161N5, respectively.

Thus, the pull-up circuits 310, 320 are all included with the single The pull-up circuits 18 of the bit buffers 111-114, 121, 122, 131 are substantially identical in circuit configuration, and the pull-down circuit 330 has the essence of the pull-down circuit 19 included in the unit buffers 111-114, 121, 122, 131. The same circuit is constructed.

As shown in FIG. 4, the pull-up circuit 320 and the pull-down circuit 330 A "copy buffer" having substantially the same circuit configuration as the unit buffer 111 is constructed. As used herein, "substantially the same" refers to the case where the transistor included in the replica buffer is reduced, and the same meaning is also considered. The contact A of the output of the replica buffer is connected to the non-inverting input terminal (+) of the comparator 370 as shown in FIG.

Correction control circuit 390 is responsible for correcting signal ZQCOM The action signal ACT1 of the counter 340 and the action signal ACT2 of the counter 350 are each generated with the internal clock ICLK.

Comparator 360 compares the potential of node C with the reference voltage ZQVREF outputs a comparison result signal COMP1 of the logic level of either the high level or the low level according to the comparison result.

Comparator 370 compares the potential of node A with the reference voltage ZQVREF outputs a comparison result signal COMP2 which obtains the logic level of either the high level or the low level according to the comparison result.

The counter 340 is synchronized with the action control signal ACT1, The count value of itself should be totaled or reciprocated at the logic level of the output signal COMP1 of the comparator 360. The count value of the counter 340 is used as the impedance code DRZQP.

On the other hand, the counter 350 is synchronized with the action control letter. The number ACT2 corresponds to the logical level of the output signal COMP2 of the comparator 370 to total or count the count value of itself. The count value of the counter 350 is used as the impedance code DRZQN.

The above is the structure of the input and output circuit 16 and the correction circuit 100. to make. In the correcting operation, the correction circuit 100 adjusts the impedance of the pull-up circuit 310 and the impedance of the pull-down circuit 330 to the combined impedance of the pull-up circuit 310 and the damping resistor R21 in accordance with the impedance of the external impedance Re. 120Ω. Then, the impedance of each of the pull-up circuit 18 and the pull-down circuit 19 of each unit buffer of the input/output circuit 16 is set to 120 Ω by the result of this adjustment. However, the previous correction circuit did not take into account the input and output. The wiring of the electrostatic protection unit 160 of the path 16 or the wiring impedance of the wiring of the electrostatic protection unit 312 of the correction circuit 100 affects the impedance of each unit buffer after the correction operation from the desired value. . In the present embodiment, in order to eliminate the deviation, the correction impedance 311 is disposed between the damping resistor R21 of the correction circuit 100 and the node C. Hereinafter, the influence of the wiring by the electrostatic protection unit 312 on the correction operation and the arrangement of the correction impedance 311 will be described in detail.

FIG. 7 shows wiring that is considered to pass through the electrostatic protection portion 160. A circuit diagram of the connection relationship between the data terminal 24 and the output circuit 101 at the time of wiring impedance. In particular, FIG. 7 focuses on the connection of the output unit 130 to the data terminal 24. The external terminal such as the data terminal 24 is provided with an ESD (Electro-Static Discharge) element ESD1 (first ESD element) in order to protect the semiconductor circuit from electrostatic discharge. This ESD element is constituted, for example, by a diode-connected MOS transistor or the like. In order to protect the internal circuit from electrostatic discharge, it is necessary to quickly discharge the static electricity applied to the external terminal to the power supply line (the VSS power supply line in Fig. 7). Therefore, a large-sized MOS transistor is used for the ESD element.

Figure 8 shows the data terminal 24 and the output circuit 101. Schematic diagram of the layout. In addition, FIG. 9 is a view schematically showing a multilayer wiring structure included in the semiconductor device 10 of the present embodiment.

As shown in FIG. 9, the semiconductor device 10 of the present embodiment is The surface on which the diffusion layer DL and the gate wiring layer GL are formed is formed on the substrate SS, and the first wiring layer L1, the second wiring layer L2, and the third wiring are sequentially stacked from the surface side close to the substrate SS. Layer L3, 4th wiring The construction of layer L4. The first wiring layer L1 is, for example, a wiring layer containing tungsten, and the second to fourth wiring layers each include a wiring layer of aluminum or copper. Each layer is insulated from each other via the interlayer insulating layers IL1 to IL4. Further, the upper surface of the fourth wiring layer L4 of the uppermost layer is covered by the interlayer insulating layer IL5 for protection. A thin gate insulating film GI is formed between the gate wiring layer GL and the surface of the substrate SS. The diffusion layer DL, the gate wiring layer GL, and the first wiring layer L1 are connected to each other only via a through-hole electrode TH0 that penetrates the interlayer insulating layer IL1. Similarly, the first interconnect layer L1 and the second interconnect layer L2 are connected to each other only via a through-hole electrode TH1 that penetrates the interlayer insulating layer IL2. In addition, the second interconnect layer L2 and the third interconnect layer L3 are connected to each other only via a through-hole electrode TH2 that penetrates the interlayer insulating layer IL3. Further, the third interconnect layer L3 and the fourth interconnect layer L4 are connected to each other only via a through-hole electrode TH3 that penetrates the interlayer insulating layer IL4.

As shown in FIG. 8, it is formed as the fourth wiring layer L4. The data pad DQP (corresponding to the data terminal 24) and the output circuit 101 include an ESD element ESD1 formed by a MOS transistor structure and damping resistors R11 to R14 formed as the first wiring layer L1. The data wiring DQL1 (first wiring) connected to each of the data pad DQP and the damping resistors R11 to R14 is connected to the upper side of the ESD element ESD1 formed as the second wiring layer L2, and the respective damping resistors R11 to R14 are connected. One or more of the corresponding ones of the corresponding ones and one or more of the unit buffers 111 to 114, 121, 122, and 131 DQL2. The ESD element ESD1 includes a diffusion layer DL formed as a source ‧ a drain and a gate electrode G formed on the substrate SS in a substrate SS such as 矽. One of the source and the drain of the ESD element 1 is connected to the data line DQL1 via the through hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 8). The other source of the ESD element ESD1 and the other side of the drain are connected to a power supply line (VSS potential) (not shown). The data pad DQP is connected to the data line DQL1 via the through hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 8). One end of each of the data wiring DQL1 and the damping resistors R11 to R14 is connected to each other by the through hole electrode TH1. Similarly, the other ends of the damping resistors R11 to R14 and the data wiring DQL2 are connected to each other via the corresponding through-hole electrodes TH1. As shown in FIG. 8, the data wiring DQL1 includes a slit-like portion for connection to the corresponding diffusion layer DL of the ESD element ESD1. Therefore, in the present embodiment, the data wiring DQL1 has a wiring impedance of about 1 Ω.

Returning to Figure 7 again, consider the above data wiring DQL1 The wiring impedance, when the output unit 130 calculates the impedance of the drive data terminal 24, becomes rm+r1+rdESD. The rm system shows the impedance of the pull-up circuit 18, and r1 shows the impedance value of the damping resistor R14. Further, the rdESD displays the impedance value of the data wiring DQL1, specifically, the impedance value from the data terminal 24 to one end of the damping resistor R14. That is, the rdESD is shown in FIG. 8 and shows the impedance value from the data pad DQP to the one end of the connection damping resistor R14 and the through hole electrode TH1 of the data line DQL1.

Figure 10 shows the adjustment buffer of the conventional correction circuit. Circuit diagram of the composition of 50' (no correction impedance). This adjustment buffer 50' corresponds to the adjustment buffer 50 shown in Fig. 4. As described above, similarly to the data terminal 24, the ESD element ESD2 (second ESD element) is also disposed for the correction terminal ZQ. Therefore, the correction wiring ZQL1 (impedance value rzESD) exists between the slave node C and the correction terminal ZQ.

When the impedance of the pull-up circuit 310 is taken as rm, the comparator The 360 system is not rm+r1=re. More strictly, it is to explore the rm of rm+r1=rzESD+re. Here, the re shows the impedance value of the external impedance Re. Further, r1 indicates the impedance value of the damping resistor R21, and this value is set to be equal to the damping resistor R14 of the output unit 130. Using this result, the impedance of the unit buffer 131 of the output unit 130 is adjusted, that is, the impedance rm of the unit buffer 131 of the output unit 130 is adjusted to be the impedance rm=rzESD+re-r1 of the pull-up circuit 310. In the case of the impedance of the unit buffer 131, the unit buffer of the output unit 130 drives the impedance of the data terminal 24 to be re+rdEDS+rzEDS. That is, the unit buffer of the output unit 130 drives the impedance of the data terminal 24 to have an impedance deviation from the external impedance Re. The same problem arises in other unit buffers. Accordingly, when the adjustment content of the pull-up circuit 310 is reflected in the copy buffer, and the adjustment content of the copy buffer is reflected in the pull-up circuit 18 of the output buffer, the data wiring shown in FIGS. 7 and 8 is also considered. It is preferable that the wiring resistance of the DQL1 and the correction wiring ZQL1 shown in FIG.

Figure 11 shows the addition of a correction impedance in this embodiment. Circuit diagram of the connection relationship between the pull-up circuit 310 of 311 and the correction terminal ZQ (First configuration example). In the present embodiment, the correction impedance 311 is added between the damping resistor R21 and the connection point C. Thereby, the impedance 311 is corrected to the influence of the wiring impedance of the data wiring DQL1 shown in Figs. 7 and 8 and the wiring impedance of the correction wiring ZQL1 shown in Figs.

Display the calibration terminal ZQ and pull of the circuit diagram shown in Figure 11. A schematic diagram of the layout between the riser circuit 310 and the comparator 360 is shown in FIG.

As shown in FIG. 12, it is formed as the fourth wiring layer L4. The correction pad ZQP (corresponding to the correction terminal ZQ) and the pull-up circuit 310 and the comparator 360 include: an ESD element ESD2 formed by a MOS transistor structure, and a correction wiring ZQL1 formed as a second wiring layer L2. (second wiring), ZQL2 (third wiring), and correction impedance 311, and damping resistor R21 formed as the first wiring layer L1. Similarly to the ESD element ESD1 shown in FIG. 8, the ESD element ESD2 includes a diffusion layer DL formed as a source ‧ a drain and a gate electrode G formed on the substrate SS in a substrate SS such as 矽. One of the source and the drain of the ESD element ESD2 is connected to the correction wiring ZQL1 by the through hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 12). The other source of the ESD element ESD1 and the other side of the drain are connected to a power supply line (VSS potential) (not shown). The correction pad ZQP is connected to the correction wiring ZQL1 via the through hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 12). As shown in FIG. 12, the correction wiring ZQL1 includes a slit-like portion for connection to the corresponding diffusion layer DL of the ESD element ESD2. Therefore, in the present embodiment, the correction wiring ZQL1 is provided. There is a wiring impedance of 1 Ω.

In addition, the correction wiring ZQL1 is divided into a comparator The divergence point of the correction wiring ZQL2 of 360 and the correction impedance 311 directed to the pull-up circuit 310 corresponds to the node C of FIG. The correction impedance 311 is connected to one end of the damping resistor R21 at one end by the through hole electrode TH1.

In Fig. 12, the correction wiring ZQL1 shown in Fig. 11 is matched. The impedance value rzESD of the line impedance corresponds to the impedance value from the correction pad ZQP to the node C.

Next, the decision value of the impedance value of the correction impedance 311 is determined. The law is explained. The impedance value rc of the correction impedance 311 is calculated by the following method. The impedance value rm of the pull-up circuit 310 is adjusted by establishing rm+r1+rc=rzESD+re. After the impedance value rm is reflected in the output buffer, rm+r1+rdESD=re must be established in the output buffer (refer to Figure 7). When re is removed from the above equation 2, rm+r1+rc=rzESD+(rm+r1+rdESD) becomes rc=rzESD+rdESD. In other words, when the correction impedance 311 of rc=(rzESD+rdESD) is added, the influence of the wiring impedance of the data wiring DQL1 shown in FIGS. 7 and 8 and the wiring impedance of the correction wiring ZQL1 shown in FIGS. As a result, the impedance rm=re-r1 of each unit buffer of the output circuit 101 is improved, and the accuracy of the impedance of the data terminal 24 driven by the output units 110, 120, and 130 of each output circuit 101 is improved. Here, the case of rc=rzESD+rdESD is better, and the rc system can obtain a certain correction effect even if it is a near-edge value, and the rc system is 1.5 times less than rzESD+rdESD. good.

Fig. 13 shows the addition of the correction impedance in the present embodiment. Circuit diagram of circuit 310 (adjustment buffer 50) (second configuration example). As shown in FIG. 8 and FIG. 12, in the first embodiment, the display data line DQL1 and the correction line ZQL1 are simultaneously formed as the second wiring layer L2. On the other hand, in the second configuration example, as shown in Figs. 14 and 15, the data wiring DQL1' and the correction wiring ZQL1 are formed in mutually different wiring layers. Here, FIG. 14 is a schematic diagram showing the layout between the data terminal 24 and the output circuit 101 of the second configuration example, and FIG. 15 is a diagram showing the correction terminal ZQ and the pull-up circuit 310 and the comparator of the second configuration example. A pattern diagram of the layout between 360s. It is noted that the same reference numerals are attached to the same components as those in FIG. 8 and FIG. 12, and the overlapping description will be omitted.

As shown in FIG. 14, in the second configuration example, the data wiring DQL1' is formed as the third wiring layer L3. On the other hand, as shown in FIG. 15, the correction wiring ZQL1 is formed as the second wiring layer L2 in the same manner as the first configuration example.

Therefore, as shown in FIG. 13 and FIG. 15, in the second configuration example In the middle, the correction impedance 311' is formed as a series impedance of two correction impedances 3111 and 3112. Specifically, the correction impedance 3112 (first impedance component) has a wiring layer which is the same as the data wiring DQL1', that is, is formed as the third wiring layer L3, and is substantially equal in impedance to the data wiring DQL1'. Value (rc'1). On the other hand, the correction impedance 3111 (second impedance component) has the same wiring layer as the correction wiring ZQL1, that is, The second wiring layer L2 is formed and has the same impedance value (rc'2) as the correction wiring ZQL1. When the correction impedance is configured based on the impedance of the two types as described above, the temperature characteristics of the two wirings DQL1' and ZQL1 and the temperature characteristics of the correction impedance can be approximated.

Figure 16 shows the power supply parasitic impedance and combined impedance. A circuit diagram of the connection relationship between the data terminal 24 and the output circuit 101. In addition to the impedance of the data wiring DQL1 or the correction wiring ZQL1, the power supply parasitic impedance (resistance value rsd) of the power supply line PSDL exists for the source of the MOS transistor, and the packaged bonding wire or BWD exists for the outer side of the external terminal. Bonding impedance (impedance value rud).

Fig. 17 shows the addition of the correction impedance in the present embodiment. A circuit diagram of a connection relationship between the pull-up circuit 310 and the correction terminal ZQ (third configuration example). The correction impedance 3113 of the third configuration example also considers the power supply parasitic impedance of the power supply line PSDL or the bonding impedance of the bonding wire or BWZ. The power supply line PSZL of the pull-up circuit 310 also has a junction impedance (impedance value rur) due to the connection of the power supply parasitic impedance (impedance value rsr) or the external impedance Re.

Not only the wiring DQL1', ZQL1 impedance, but also the power supply The impedance value rc2 of the parasitic impedance or the corrected impedance 3113 of the joint impedance is calculated by the following method. In the adjustment buffer 50, rsr+rm+r1+rc2=rzESD+rur+re is established, and the impedance value rm of the pull-up circuit 310 is adjusted. After the impedance value rm at this time is reflected in the output buffer, rsd+rm+r1+rdESD=rerud must be established in the output buffer (refer to FIG. 16). When re is removed from the above formula 2, it becomes rsr+rm +r1+rc2=rzESD+rur+(rsd+rm+r1+rdESD+rud). Become rc2=rzESD+rdESD+(rsd-rsr)+(rud+rur). In other words, when the additional impedance value rc2 is the correction impedance 3113 of rzESD+rdESD+(rsd-rsr)+(rud+rur), the wiring DQL1 and ZQL1 can be corrected to the difference between the power supply parasitic impedance or the junction impedance. . Rc2=rzESD+rdESD+(rsd-rsr)+(rud+rur) is better, but the rc2 system can get a certain correction effect even if it is a near-edge value.

The above, according to the embodiment, for the semiconductor device 10 Explain. By introducing the correction impedance to the adjustment buffer 50, the wiring impedance of the data wiring or the correction wiring, the power supply parasitic impedance, and the influence of the junction impedance are offset, and this can be corrected more accurately. Regarding whether or not to consider the wiring impedance of the data wiring or the correction wiring, any of the power supply parasitic impedance and the bonding impedance is arbitrary. For example, the bonding impedance is sufficiently smaller than the wiring impedance or the power supply parasitic impedance of the data wiring or the correction wiring, and only the influence of the wiring impedance of the data wiring or the correction wiring and the parasitic impedance of the power supply may be considered.

When the impedance value of the correction impedance becomes large, the adjustment buffer 50 is adjusted. The linearity of the IV characteristic is stronger. In other words, the influence of the adjustment buffer 50 of the IV characteristic (non-linear) of the transistor group included in the pull-up circuit 310 becomes small. However, according to the investigation by the present inventors, for rm+r1=240 Ω, the correction impedance is about 1 Ω, and the maximum is about 5 Ω. Further, the correction impedance is 5 Ω or less, and the influence of the correction impedance on the IV characteristic of the adjustment damper 50 is confirmed to be almost ungenerated.

Above, it has been done for the ideal embodiment of the present invention. The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention, and these are of course included in the scope of the invention. For example, the present invention is also applicable to a semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 2008-228332, and No. 2011-61580. It is incorporated herein by reference to the disclosure of such publication.

ZQVREF‧‧‧ reference voltage

VDD, VSS‧‧‧ power supply potential

DRZQP‧‧‧ Impedance code

ZQ‧‧‧correction terminal

ZQL1‧‧‧corrected wiring

Re‧‧‧External impedance

rzESD‧‧‧ impedance value

Rm‧‧‧impedance

Rc‧‧‧ impedance value

R21‧‧‧damping resistor

310‧‧‧ Pulling circuit

311‧‧‧corrected impedance

312‧‧‧Electrostatic Protection Department

360‧‧‧ comparator

Claims (18)

A semiconductor device comprising: a data terminal and a correction terminal; and an output buffer; and a first impedance portion connected to the output buffer at one end; and another end connecting the data terminal and the first impedance portion a first wiring, a replica circuit having substantially the same impedance as the output buffer, and a comparison circuit, and a second impedance portion connected to the replica circuit at one end, and connected to the second impedance at one end a third impedance portion at the other end of the portion, a second wiring connecting the other end of the third impedance portion and the correction terminal, and a third wiring connecting the other end of the third impedance portion and the comparison circuit, the The impedance value of the impedance portion is larger than the impedance value of the first wiring and the impedance value of the second wiring. The semiconductor device according to claim 1, wherein the impedance value of the third impedance portion is substantially equal to a sum of an impedance value of the first wiring and an impedance value of the second wiring. The semiconductor device according to the first or second aspect of the invention, wherein the third impedance portion includes: having the first wiring The first part of the same temperature characteristic and the second part having the same temperature characteristics as the second wiring. The semiconductor device according to any one of claims 1 to 3, further comprising: a first protective element connected to the first wiring; and a second protective element connected to the second wiring. The semiconductor device according to claim 4, wherein the first and second protection elements are ESD protection elements. The semiconductor device according to the first to fifth aspect of the invention, further comprising a multilayer wiring structure including a first wiring layer and a second wiring layer formed above the first wiring layer, each of the first and The second wiring and the third impedance portion are formed as the second wiring layer. The semiconductor device according to claim 6, wherein each of the first and second impedance portions is formed as the first wiring layer. A semiconductor device comprising: an output buffer; and a correction circuit including a replica circuit and a comparator, wherein an impedance of the replica circuit is adjusted according to an output of the comparator, and an adjustment result is reflected in the output buffer; The correction circuit further includes a second damping resistor and a correction resistor connected in series between the replica circuit and an input terminal of one of the comparators. The semiconductor device according to claim 8, wherein the semiconductor device further includes a correction terminal. The correction impedance is connected to the second damping resistor at one end and to the correction terminal at the other end. The semiconductor device according to claim 9, further comprising a data terminal, wherein the output buffer further includes: a pull-up circuit connected to the pull-up circuit at one end and connected to the aforementioned end at the other end The first damping resistor of the data terminal. The semiconductor device according to claim 10, further comprising: a first wiring connecting the other end of the first damping resistor and the data terminal; and a second terminal connecting the correction impedance and the second correction terminal Wiring person. The semiconductor device according to claim 11, wherein the impedance value of the correction impedance is set based on an impedance value of the first wiring and an impedance value of the second wiring. The semiconductor device according to claim 12, wherein the impedance value of the correction impedance is substantially equal to a total value of the impedance value of the first wiring and the impedance value of the second wiring. The semiconductor device according to any one of the preceding claims, further comprising: a first protective element connected to the first wiring; and a second protective element connected to the second wiring. The semiconductor device according to any one of the first aspect, wherein the semiconductor device further includes a multilayer wiring structure including the first wiring layer and a second wiring layer formed above the first wiring layer, and each of the foregoing The first and second damping resistors are used as the first wiring layer The first and second wirings and the correction impedance are formed as the second wiring layer. The semiconductor device according to any one of the aspects of the present invention, further comprising: a first wiring layer, a second wiring layer formed over the first wiring layer, and a second wiring layer In the multilayer wiring structure of the third wiring layer, each of the first and second damping resistors is formed as the first wiring layer, and the first wiring is formed as the second wiring layer, and the second wiring is formed. The third wiring layer is formed as the third wiring layer, and the correction impedance includes a first portion formed as the second wiring layer and a third portion formed as the third wiring layer. The semiconductor device according to any one of claims 10 to 16, wherein the impedance value of the correction impedance is based on an impedance value of a junction impedance of the data terminal and an impedance value of a junction impedance of the correction terminal. Setter. The semiconductor device according to any one of claims 8 to 17, wherein the impedance value of the correction impedance is based on an impedance value of a power supply parasitic impedance of the output buffer and a power supply parasitic impedance of the replica circuit. The impedance value is set.