JP2001352238A - Constant impedance driver and method for designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant impedance driver for maintaining output impedance characteristics constant in the case of an impedance mismatch to a load connected to an output terminal from the result that the output impedance characteristics (current-voltage characteristics of the output terminal) does not become constant when a constant impedance range of an output terminal voltage arrives at a saturated region in a constant impedance output circuit. SOLUTION: An output circuit 2 having a switching timing delay mechanism made of a delay circuit 3 by connecting a plurality of output circuits 1 and 2 for supplying currents to an output terminal A of a former stage circuit is switched at timing when a current supplied from the output circuit 1 not having the switching timing delay mechanism having the circuit 3 arrives at the saturation region. Thus, it is possible to set the output impedance characteristic of an output terminal B to constant, and impedance matching to the load can be easily realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant impedance driver circuit for driving a load, and more particularly to a constant impedance driver circuit that requires impedance matching with a load in high-speed and high-frequency signal transmission, and a design method thereof. Things.

[0002]

2. Description of the Related Art A conventional output circuit using a MOS transistor will be described with reference to the drawings. In the respective drawings, the same reference numerals are used for the same parts, and the description is omitted.

When driving high-speed and high-frequency signals, it is necessary to match the output impedance of the output circuit with the load in order to prevent signal reflection noise at the output end during signal transmission. FIG. 1 is a diagram in which an output circuit generally used in the related art is connected to a transmission line as a load. FIG. 2 shows an output current-voltage characteristic at point B in FIG. As shown in FIG. 2, the MOS transistor has a current saturation region (2). In the saturation region (2), the output impedance of the MOS transistor is not constant. In particular, the output circuit of the lower current type has a shorter time to reach the saturation region, and as a result, the variation of the output impedance value increases.

As a method of impedance matching between the output circuit and the load, Rd shown in FIG.
Is used to insert a resistor Rd called a damping resistor at the position of. The optimum value of the damping resistor Rd is obtained by the following equation. When the output impedance value dynamically changes as can be seen from the following equation, the damping resistor Rd must be dynamically changed, and the output It becomes very difficult to match the impedance between the circuit and the load. <Equation for Determining Damping Resistance> Rd = Zo−Rp Rd: Damping Resistance Rd = Zo−Rn Zo: Characteristic Impedance Rp: Internal Resistance Rn: Internal Resistance Conventionally, the impedance between the output circuit and the load as described above. In order to solve the mismatch problem, there has been a method of using a MOS driver circuit as a constant impedance output circuit.

Hereinafter, a conventional constant impedance output circuit will be described based on a second conventional example (Japanese Patent Laid-Open No. 5-267952). FIG. 3 is a diagram of the constant impedance output circuit that can be realized in the conventional example. According to the present invention, the output current at the output terminal B is also supplied from the input terminal A via the gate-source resistance Rgs. In such a case, the output impedance until the MOS transistor constituting the constant impedance output circuit reaches the saturation region, that is, the value in the region where the output impedance characteristic is constant, the input resistance Rgt and the gate-source resistance By adding Rgs, the combined output impedance at the output terminal B may differ.

[0006]

The first problem is that in the second conventional example, the current from the gate of the output circuit, that is, the current of the preceding circuit (not shown) is set in order to keep the output impedance characteristic constant. It was necessary to supply a current to the output terminal B. The current supply capability of the output circuit of the pre-stage circuit usually used inside the LSI is much smaller than the current supply capability of the output circuit that supplies current to an external load. Therefore,
The structure in which the output terminal current depends on the current supply from inside the LSI has a disadvantage that a sufficient current is not supplied.

The second problem is that the current supply amount at the output terminal depends on the current supply amount of the output circuit and the current supply amount from the gate. Therefore, when realizing the low current type output circuit, the transistor size is small. Needs to be smaller. In general, as the size of the transistor becomes smaller, the current-voltage characteristics at the output end reach the saturation region (2) earlier, and the current supply amount from the gate needs to be increased accordingly. However, as described above, the current supply from the gate depends on the output circuit capability inside the LSI.
Therefore, the structure of the second conventional example has a disadvantage that it is difficult to realize constant impedance in the low-current type output circuit.

According to the present invention, in order to solve the above-mentioned conventional problems, a plurality of output circuits are connected to an output terminal of a preceding circuit, and a switching timing between the output circuits is delayed to supply a current to the output circuit. It is an object of the present invention to provide a constant impedance driver circuit in which output impedance characteristics are made constant by complementing a necessary current without changing the capability.

[0009]

In order to achieve the above object, a constant impedance driver circuit according to the present invention is a constant impedance driver circuit comprising a plurality of output circuits for supplying current from an output terminal of a preceding circuit. At least one or more output circuits of the plurality of output circuits are provided with a switching timing delay mechanism comprising a delay circuit for delaying and outputting a current more than the other output circuits, and the output including the delay mechanism is provided. The circuit is characterized in that the switching timing delay mechanism is configured to switch at a timing when a current supplied from another output circuit not including the delay mechanism reaches a saturation region to make output impedance characteristics constant. I do.

Further, the constant impedance driver circuit of the present invention shifts to a high potential in order to output a current to at least one or more of the plurality of output circuits with a current slower than the other output circuits. An output circuit including a reference potential shift mechanism, the output circuit including the reference potential shift mechanism is configured so that the reference potential shift mechanism allows a current supplied from another output circuit not including the reference potential shift mechanism to reach a saturation region. It is characterized in that the output impedance characteristic is switched to be constant.

Further, the constant impedance driver circuit according to the present invention may further comprise a second output circuit for outputting a current to at least one of the plurality of output circuits with a current delayed more than the other output circuits. A threshold potential shift mechanism that shifts the threshold value of negative logic to a lower potential and shifts the threshold potential of positive logic to a higher potential,
The output circuit including the threshold potential shift mechanism is switched by the threshold potential shift mechanism at a timing when a current supplied from another output circuit not including the threshold potential shift mechanism reaches a saturation region. The output impedance characteristic is made constant.

According to the method of designing a constant impedance driver circuit of the present invention, a step of obtaining a piecewise linear curve of an output-end current-voltage curve of an output circuit, obtaining a straight line approximating the piecewise linear curve, -Point analysis step of calculating a section point of an output-end current-voltage curve from a straight line approximating a linear line, a delay time analysis step of calculating a delay time up to the section point calculated in the section point analysis step, and the delay time analysis A delay time determined in step, the delay switching time of the output circuit comprising the switching timing delay mechanism, and a time equal to the difference between the switching time of the output circuit without the switching timing delay mechanism, , Consisting of

Further, in the method for designing a constant impedance driver circuit according to the present invention, the delay time determined in the delay time analyzing step may include a delay switching time of the output circuit including the reference potential shift mechanism, Setting the time equal to the difference from the switching time of the output circuit without the shift mechanism.

Further, in the method of designing a constant impedance driver circuit according to the present invention, the delay time determined in the delay time analyzing step may include a delay switching time of the output circuit including the threshold potential shift mechanism, Setting the time equal to the difference from the switching time of the output circuit without the threshold potential shift mechanism.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. In the respective drawings, the same reference numerals are used for the same parts, and the description is omitted.

FIG. 4 is a circuit diagram of a first embodiment of the constant impedance driver circuit of the present invention, FIG. 5 is a circuit diagram of a second embodiment of the constant impedance driver circuit of the present invention, and FIG. 6 is a constant impedance of the present invention. FIG. 7 is a circuit diagram of a driver circuit according to a third embodiment, and FIG. 7 is a current-voltage characteristic diagram at an output terminal B in the first, second, and third embodiments of the present invention. FIG. 8 shows the third
It is a conceptual diagram of the logical threshold value shift in the Example of FIG. (First Embodiment) First, the first embodiment of FIG. 4 differs from the conventional one in a mechanism in which one output circuit is constituted by a plurality of output circuits that perform multi-stage switching. In the first embodiment, the output circuit 1 includes a PMOS transistor and an NM
The OS transistor is connected in series, one end of the PMOS transistor is connected to the power supply Vdd, the other end of the NMOS transistor is connected to GND, the gate is connected to the input terminal A, and the connection point is connected to the output terminal B. The other output circuit 2 is a PMO
An S transistor and an NMOS transistor are connected in series, and one end of the PMOS transistor is connected to a power supply Vdd, and NM
The other end of the OS transistor is connected to GND, the gate is connected to the input terminal A via the delay circuit 3, and the connection point is connected to the output terminal B.

In the first embodiment shown in FIG. 4, the delay circuit 3 is provided between the common gate of the output circuit 2 and the input terminal A as described above. This delay circuit is a circuit for delaying the signal at the input terminal A using the capacitance. The constant impedance driver circuit can delay the switching timing between the output circuits 1 and 2 by including the switching timing delay mechanism.
The switching timing of the output circuit 2 provided with the switching timing delay mechanism is determined when the current supplied from the output circuit 1 not provided with the switching timing delay mechanism to the output terminal B side reaches the saturation region, or Switching before and after. As described above, the switching of the output circuit 2 is delayed.
In the current-voltage characteristics at the point, as shown in FIG. 7, the saturation region (2) shifts to a high Vds (drain-source potential). When this is regarded as constant impedance, a constant output impedance characteristic is secured. This will be further described.

Now, it is assumed that a current is supplied to the terminal A from a preceding circuit (not shown). At this time, the potential of the output terminal B is determined by the state of the load, the load impedance, the load power supply, and the like. As can be seen from FIG. 2, in the constant impedance region (1), the potential of the output terminal B shows a constant output impedance characteristic, but when the potential Vds of the output terminal B increases, the operation shifts to the saturation region (2). It can be seen that it changes dynamically when viewed as the constant impedance.

However, in the first embodiment, the output circuits 1 and 2 are connected to each other by the action of the delay circuit 3 which is a switching timing delay mechanism connected to the gate of the output circuit 2. Switching timing can be delayed. By delaying the switching timing in this way, when the current supplied from the output circuit 1 reaches the saturation region (2) in FIG.
When the current is supplied from the output circuit 2, the saturation region (2) appears to be shifted to a high Vds apparently as shown in FIG. For this reason, there is an advantage that the region where the output impedance characteristic is constant increases and impedance matching with a load can be easily performed.

Next, a method of designing the constant impedance driver circuit of the first embodiment will be described below. First, the output terminal current-voltage curve piecewise linear (piecewis
e-linear) to obtain a straight line approximating this piecewise linear. The output terminal current −
A section point of the voltage curve is determined, and a delay time is determined from the determined section point.

The determined delay time is the delay switching time of the output circuit 2 provided with the switching timing delay mechanism (delay circuit 3), and the switching time of the output circuit 1 not provided with the switching timing delay mechanism. Time equal to the difference of (Second Embodiment) A second embodiment of FIG.
2 is a constant impedance driver circuit including a reference potential shift mechanism capable of setting the source potential of the output circuit 2 high. In the second embodiment, the output circuit 2 is not provided with the delay circuit 3, and instead, one end of the PMOS transistor is connected to the power supply Vdd via a resistor, and the other end of the NMOS transistor is connected to GND via a resistor. Connected.

The differences between the second embodiment and the first embodiment will be described below. When a current is supplied to the terminal A, the output circuit 2 provided with the reference potential shift mechanism (the resistance of one end of the PMOS transistor and the resistance of the other end of the NMOS transistor of the output circuit 2), and the reference potential shift mechanism is not provided. If the logical threshold potential level of the output circuit 1 is the same, the switching timing of the output circuit 1 and the output circuit 2 is shifted, and the current of the output circuit 2 is delayed from the current of the output circuit 1 so that the output terminal B Supplied to this is,
This is because the MOS transistor switches with the gate-source potential Vgs and the actual current has finite rise and fall times. Therefore, similarly to the first embodiment, it is possible to make the output impedance characteristic constant as a result.

Next, a method of designing the constant impedance driver circuit according to the second embodiment will be described below. First, a delay time is determined in the same manner as in the first embodiment. Then, the determined delay time is set to a time equal to the difference between the delay switching time of the output circuit including the reference potential shift mechanism and the switching time of the output circuit without the reference potential shift mechanism. (Third Embodiment) A third embodiment of FIG.
2 has a PMOS transistor and an NMOS transistor connected in series, and one end of the PMOS transistor is connected to a power supply V.
dd, the other end of the NMOS transistor is connected to GND, the common gate is connected to the input terminal A, and the connection point is connected to the output terminal B.

However, the positive logic threshold value of the output circuit 2 is shifted to a higher potential than the positive logic threshold value of the output circuit 1, and the negative logic threshold value of the output circuit 2 is This is a constant impedance driver circuit including a threshold potential shift mechanism for shifting to a potential lower than a threshold.
The output circuit 1 having a logical threshold 1 indicated by a broken line in FIG.
In the output circuit 2 having the logic threshold 2 indicated by the dashed line in which the positive logic shifts to a higher potential than the logic threshold 1 and the negative logic shifts to a lower potential, the switching timing of the output circuit 2 It is delayed from the switching timing of the output circuit 1. As a result, similarly to the first and second embodiments, the constant impedance driver circuit has a characteristic that the output impedance characteristic is constant.

Next, a method of designing the constant impedance driver circuit according to the third embodiment will be described below. First, a delay time is determined in the same manner as in the first embodiment. And
The determined delay time is a delay switching time of the output circuit including the threshold potential shift mechanism,
The time is set to be equal to the difference from the switching time of the output circuit without the threshold potential shift mechanism.

In each of the first, second and third embodiments,
By using transistors having the same current supply capability as current sources, the output impedance does not exceed the output impedance when a single transistor is used, and only the saturation region shifts to high Vds. . This is a conventional example (Japanese Patent Laid-Open No. 5-267952).
As compared with the above, the current supply capability can be determined only by the capability of the transistor, and there is an advantage that a low-current type constant impedance driver circuit can be easily configured.

Further, compared with the conventional example (Japanese Patent Laid-Open No. Hei 5-267952), there is no need to supply current from the preceding circuit to the output terminal B, so that there is an advantage that the load on the output circuit of the preceding circuit in the LSI is small. . From the above, it is possible to supplement the necessary current by using the switching timing delay mechanism, the reference potential shift mechanism, and the threshold potential shift mechanism by the plurality of output circuits and the delay circuit of the present embodiment, and to keep the output impedance characteristic constant. It is possible to

The present invention is not limited to the above-described embodiments, but can be implemented in various modifications without departing from the scope of the invention. In the above-described embodiment, the delay circuit is realized by a capacitance, but a latch circuit, a flip-flop, a buffer, or a resistor can be used.

Also, the reference potential shift mechanism can be realized by a constant voltage source in addition to the resistance voltage division.
Although the number of output circuits in one constant impedance driver circuit is two each in FIGS. 4, 5, and 6, it may be plural. The switching timing delay mechanism, the reference potential shift mechanism, and the threshold potential shift mechanism may be provided in a plurality of output circuits. Further, the current supply capabilities of the plurality of transistors and other characteristics may vary.

[0030]

As described above, according to the present invention, a switching timing delay mechanism, a reference potential shift mechanism, and a switching timing delay mechanism are provided to at least one or more of the plurality of output circuits for supplying current from the output terminal of the preceding circuit. By providing the threshold potential shift mechanism, the necessary current can be supplemented without increasing the current supply amount as compared with the case where the current is supplied by a single transistor, and the output impedance characteristic at the output terminal is made constant. It is possible. With such a configuration, impedance matching with a load can be more easily realized than in the related art, so that the output impedance characteristics can be made constant even in the low-current type output circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram in which a MOS driver circuit generally used in the related art is connected to a transmission line.

FIG. 2 is an output terminal current-voltage characteristic diagram at point B in FIG. 1;

FIG. 3 is a diagram illustrating a conventional example of a constant impedance output circuit.

FIG. 4 shows a first example of the constant impedance driver circuit of the present invention.
FIG. 3 is a circuit diagram of the embodiment of FIG.

FIG. 5 shows a second example of the constant impedance driver circuit of the present invention.
FIG. 3 is a circuit diagram of the embodiment of FIG.

FIG. 6 shows a third example of the constant impedance driver circuit of the present invention.
FIG. 3 is a circuit diagram of the embodiment of FIG.

FIG. 7 is a current-voltage characteristic diagram at an output terminal point B in the first, second, and third embodiments of the present invention.

FIG. 8 is a conceptual diagram of a logical threshold shift according to a third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 output circuit 2 output circuit 3 delay circuit Rd damping resistance A input terminal B output terminal Ids drain-source current value Vds drain-source potential value (1) constant impedance region (2) saturation region Rt load resistance Vt load power supply Vdd Power supply potential Vss Ground potential Rgt Input resistance Rgs Gate-source resistance

Claims (6)

[Claims] 1. A constant impedance driver circuit comprising a plurality of output circuits for supplying a current from an output terminal of a preceding stage circuit, wherein at least one of the plurality of output circuits has a higher output level than other output circuits. A switching timing delay mechanism comprising a delay circuit for delaying and outputting a current is provided. The output circuit including the delay mechanism is supplied from another output circuit not including the delay mechanism by the switching timing delay mechanism. A constant impedance driver circuit configured to switch at a timing when a current to be supplied reaches a saturation region to make output impedance characteristics constant. 2. A constant impedance driver circuit comprising a plurality of output circuits for supplying a current from an output terminal of a preceding circuit, wherein at least one of the plurality of output circuits has a higher output level than other output circuits. In order to output the current with a delay, a reference potential shift mechanism that shifts to a high potential is provided, and an output circuit including the reference potential shift mechanism is configured so that the reference potential shift mechanism does not include a reference potential shift mechanism. A constant impedance driver circuit configured to switch at a timing when a current supplied from an output circuit reaches a saturation region to make output impedance characteristics constant. 3. A constant impedance driver circuit comprising a plurality of output circuits for supplying a current from an output terminal of a preceding circuit, wherein at least one of the plurality of output circuits is connected to another output circuit. A threshold potential shift mechanism that shifts the negative logic threshold to a lower potential and shifts the positive logic threshold to a higher potential than other output circuits in order to output the current with a delay. The output circuit provided with the threshold potential shift mechanism is configured such that the current supplied from another output circuit not provided with the threshold potential shift mechanism reaches a saturation region by the threshold potential shift mechanism. A constant impedance driver circuit configured to perform switching to make output impedance characteristics constant. 4. A method for designing a constant impedance driver circuit comprising a plurality of output circuits for supplying a current from an output terminal of a preceding circuit, wherein a current-voltage curve of an output terminal of the output circuit is expressed in a piecewise linear manner.
A step of obtaining a straight line approximating the piecewise linear, a step of analyzing the section of the current-voltage curve at the output end from the straight line approximating the piecewise linear obtained in the step, Delay time analyzing step to determine the delay time up to the segment point, the delay time determined in the delay time analyzing step,
A method for designing a constant impedance driver circuit comprising: a time equal to a difference between a delay switching time of the output circuit including the switching timing delay mechanism and a switching time of the output circuit without the switching timing delay mechanism. . 5. The delay time determined in the delay time analysis step is defined by a delay switching time of the output circuit including the reference potential shift mechanism and a switching time of the output circuit without the reference potential shift mechanism. 5. The method for designing a constant impedance driver circuit according to claim 4, wherein the step of setting the time is equal to the difference. 6. The delay switching time of the output circuit comprising the threshold potential shift mechanism and the delay switching time of the output circuit without the threshold potential shift mechanism. 5. The method for designing a constant impedance driver circuit according to claim 4, wherein the time is equal to a difference from the switching time.