TW201444093A - A process method and structure for high voltage MOSFETs - Google Patents
A process method and structure for high voltage MOSFETs Download PDFInfo
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- 239000007943 implant Substances 0.000 claims description 15
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Abstract
Description
本發明主要涉及半導體功率器件的結構和製備工藝。更確切的說，本發明涉及改良型高壓（HV）金屬氧化物半導體場效應電晶體（MOSFET）簡化結構性配置和製備工藝。The present invention generally relates to the structure and fabrication process of semiconductor power devices. More specifically, the present invention relates to a simplified high voltage (HV) metal oxide semiconductor field effect transistor (MOSFET) simplified structural configuration and fabrication process.
製備高壓（HV）MOSFET器件的傳統技術，由於存在各種取捨，進一步提高器件性能的話，仍然面臨許多困難和局限。在垂直半導體功率器件中，性能屬性之一的汲源電阻（即導通狀態電阻，常用RdsA表示，即Rds×主動區面積）與功率器件可承受的擊穿電壓之間存在取捨關係。為解決這些性能取捨所帶來的困難與局限，我們已研究了多種器件結構。為此還專門研發了特殊P-合成（PCOM）結構。確切地說，帶有PCOM結構的高壓（HV）MOSFET器件包括包圍著遮罩溝槽側壁的P-型摻雜區，以便在半導體襯底頂面上的P-型本體區和遮罩溝槽下方的P-型摻雜區之間形成連接。為了在溝槽側壁周圍形成側壁摻雜區，傳統方法採用帶有注入開口的附加的注入掩膜，在遮罩溝槽所選位置處的溝槽側壁上進行注入工藝。另外，為確保摻雜離子注入到溝槽側壁的底部，必須注入高能量的摻雜離子。需要使用附加掩膜以及高能摻雜離子工藝，這些都增加了製備成本。此外，溝槽側壁底部的高能注入以及擴散工藝，通常不易於控制摻雜區的形成。這些製備工藝的不確定性導致器件性能劇烈變化，不便於精確控制製備品質。Conventional techniques for fabricating high voltage (HV) MOSFET devices still face many difficulties and limitations due to various trade-offs that further improve device performance. In vertical semiconductor power devices, there is a trade-off between the source resistance of one of the performance properties (ie, the on-state resistance, commonly referred to by RdsA, ie, Rds x active area) and the breakdown voltage that the power device can withstand. To address the difficulties and limitations of these performance trade-offs, we have studied a variety of device structures. A special P-synthesis (PCOM) structure has also been specially developed for this purpose. Specifically, a high voltage (HV) MOSFET device with a PCOM structure includes a P-type doped region surrounding the sidewalls of the mask trench for P-type body regions and mask trenches on the top surface of the semiconductor substrate. A connection is formed between the lower P-type doped regions. In order to form sidewall doped regions around the trench sidewalls, conventional methods employ an additional implantation mask with an implant opening to perform an implant process on the sidewalls of the trench at selected locations of the mask trench. In addition, to ensure that dopant ions are implanted into the bottom of the trench sidewalls, high energy dopant ions must be implanted. Additional masking and high energy doping ion processes are required, all of which increase manufacturing costs. In addition, high energy implantation and diffusion processes at the bottom of the trench sidewalls are generally not easy to control the formation of doped regions. The uncertainty of these preparation processes leads to drastic changes in device performance, making it inconvenient to accurately control the quality of the preparation.
第1A圖表示傳統工藝中所用的注入掩膜100的俯視圖，第1B圖和第1C圖表示沿第1A圖的線1-1’和2-2’，利用傳統的工藝製備高壓（HV）MOSFET器件結構的兩個剖面圖。如第1A圖所示，注入開口11位於溝槽12所選區域上。為了製備能夠承受高功率操作的MOSFET器件，要形成PCOM（P-合成）結構。在該PCOM MOSFET結構中，透過注入開口11，在P-型本體區13下方的那部分區域16中，形成專用的摻雜區，從而如第1C圖所示，將P-型本體區和溝槽12下方的P-型摻雜區15連接起來。同時，在其他區域中，透過注入掩膜100，防止在本體區下方注入形成摻雜區。第1A圖所示的注入掩膜防止通過1-1’周圍區域中的溝槽側壁，注入摻雜物。第1B圖表示一種沒有摻雜區包圍著溝槽側壁的結構，連接溝槽底部下方的本體區和摻雜區。如第1B-1C圖所示，高壓（HV）MOSFET器件還包括一個平面閘極17，形成在半導體襯底上方，以及一個源極18和一個P++接頭19，形成在P-型本體區13頂部。1A is a plan view showing an implantation mask 100 used in a conventional process, and FIGS. 1B and 1C are diagrams showing a high voltage (HV) MOSFET fabricated by a conventional process along lines 1-1' and 2-2' of FIG. 1A. Two cross-sectional views of the device structure. As shown in FIG. 1A, the injection opening 11 is located on a selected area of the trench 12. In order to prepare a MOSFET device capable of withstanding high power operation, a PCOM (P-synthesis) structure is formed. In the PCOM MOSFET structure, a dedicated doped region is formed in the portion 16 below the P-type body region 13 through the implantation opening 11, thereby, as shown in FIG. 1C, the P-type body region and the trench are formed. The P-type doped regions 15 under the trenches 12 are connected. At the same time, in other regions, by implanting the mask 100, formation of a doped region under the body region is prevented. The implantation mask shown in Fig. 1A prevents the dopant from being implanted through the sidewalls of the trench in the region around 1-1'. Fig. 1B shows a structure in which a doped region surrounds the sidewall of the trench, connecting the body region and the doped region below the bottom of the trench. As shown in FIG. 1B-1C, the high voltage (HV) MOSFET device further includes a planar gate 17 formed over the semiconductor substrate, and a source 18 and a P++ junction 19 formed on top of the P-type body region 13. .
如第1A至1C圖所示的傳統製備工藝需要額外的注入掩膜。另外，需要高能注入P-型摻雜物，例如在Mev區中的P-型摻雜注入物，如第1C圖所示，在溝槽側壁周圍的本體區下方形成摻雜區。額外掩膜和高能注入的要求，增加了製備成本。The conventional fabrication process as shown in Figures 1A through 1C requires an additional implantation mask. In addition, high energy implantation of a P-type dopant, such as a P-type dopant implant in the Mev region, is required, as shown in FIG. 1C, forming a doped region below the body region surrounding the trench sidewall. Additional masking and high energy injection requirements increase manufacturing costs.
因此，對於本領域的技術人員來說，必須改善功率器件的製備方法，尤其是帶有PCOM結構的器件，才能解決上述技術局限。本發明的目的在於提出新式、改良的製備方法和器件結構，使之不再需要額外的注入掩膜和高能注入，從而克服上述困難與局限。Therefore, it is necessary for those skilled in the art to improve the manufacturing method of the power device, especially the device with the PCOM structure, to solve the above technical limitations. SUMMARY OF THE INVENTION It is an object of the present invention to provide a new and improved method of fabrication and device structure that eliminates the need for additional implantation masks and high energy implants to overcome the aforementioned difficulties and limitations.
因此，本發明的一個方面在於，提出了一種新式、改良的製備方法，無需額外的注入掩膜和高能摻雜注入，就能實現溝槽側壁P-型摻雜區的注入，從而降低製備成本，並解決上述局限與困難。Therefore, an aspect of the present invention is to provide a new and improved preparation method capable of implanting a P-type doped region of a trench sidewall without an additional implantation mask and high energy doping implantation, thereby reducing the fabrication cost. And solve the above limitations and difficulties.
確切地說，本發明的一方面在於，注入工藝利用了溝槽終點處側壁的特殊結構，垂直於溝槽縱向的側壁裸露出來，打開空間作為溝槽的一部分。由於無需穿透半導體襯底，僅透過溝槽的開口空間，就能發射摻雜離子，因此，透過該終點溝槽，可以進行P-型摻雜區注入，無需使用高能摻雜離子，就能觸及形成在溝槽底部的底部P-型摻雜區。連接形成在半導體襯底頂面上的P-型本體區和溝槽底部P-型摻雜區的PCOM摻雜區，僅僅形成在溝槽終點的側壁處。與傳統方法相比，無需高能摻雜注入，節省了成本。Specifically, an aspect of the present invention is that the implantation process utilizes a special structure of the sidewalls at the end of the trench, the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Since there is no need to penetrate the semiconductor substrate, only the opening space of the trench can be used to emit the doping ions. Therefore, the P-type doping region can be implanted through the end trench, without using high-energy doping ions. The bottom P-type doped region formed at the bottom of the trench is touched. A PCOM-doped region connecting the P-type body region formed on the top surface of the semiconductor substrate and the P-type doping region at the bottom of the trench is formed only at the sidewall of the trench end point. Compared with the traditional method, high energy doping injection is not required, which saves cost.
另外，本發明的一個方面在於，注入工藝利用了溝槽彎曲處溝槽側壁的特殊結構，在溝槽彎曲處，垂直於溝槽縱向的側壁裸露出來，打開空間作為溝槽的一部分。另外，本發明的一個方面在於，注入工藝利用了溝槽凹口處溝槽側壁的特殊結構，在溝槽凹口處，垂直於溝槽縱向的側壁裸露出來，打開空間作為溝槽的一部分。由於無需穿透半導體襯底，僅透過溝槽的開口空間，就能發射摻雜離子，因此，透過該側壁，就可以進行P-型摻雜區注入，無需使用高能摻雜離子，就能觸及形成在溝槽底部的底部P-型摻雜區。In addition, one aspect of the present invention is that the implantation process utilizes a special structure of the sidewalls of the trench at which the trench is bent, where the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Additionally, one aspect of the present invention is that the implantation process utilizes a special configuration of the sidewalls of the trench at the trench recess where the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Since there is no need to penetrate the semiconductor substrate, only the opening space of the trench can be used to emit the doping ions. Therefore, the P-type doping region can be implanted through the sidewall, and the high-energy doping ions can be used without touching. A bottom P-type doped region is formed at the bottom of the trench.
本發明的另一方面在於，在溝槽終點、溝槽彎曲和溝槽凹口處的溝槽側壁上方，沿溝槽的縱向通過打開空間，進行側壁摻雜注入，可以較好地控制注入工藝。更精確地控制器件性能參數，並且減少高能摻雜注入所帶來的不確定性導致的製備工藝變化。Another aspect of the present invention is that the sidewall doping implantation is performed in the longitudinal direction of the trench above the trench sidewall at the end of the trench, the trench curvature and the trench recess, and the implantation process can be better controlled. . More precise control of device performance parameters and reduced manufacturing process variations due to uncertainty caused by high energy doping implantation.
在一個較佳實施例中，本發明提出了一種設置在半導體襯底中的半導體功率器件。該半導體功率器件包括多個遮罩溝槽，形成在半導體襯底的頂部，每個遮罩溝槽都有一個溝槽終點，終點側壁垂直於溝槽的縱向方向，並且從頂面開始垂直向下延伸到溝槽底面。該半導體功率器件還包括一個溝槽底部P-型摻雜區，設置在溝槽底面下方，以及一個側壁P-型摻雜區，沿終點側壁設置，其中側壁P-型摻雜區沿溝槽的終點側壁垂直向下延伸，以觸及溝槽底部P-型摻雜區，並將溝槽底部P-型摻雜區連接到形成在半導體襯底頂面的P-型本體區。In a preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a trench end point, the end sidewalls being perpendicular to the longitudinal direction of the trench and starting vertically from the top surface The lower portion extends to the bottom surface of the groove. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the end sidewall, wherein the sidewall P-type doped region is along the trench The end sidewall extends vertically downward to access the P-type doped region at the bottom of the trench and connects the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate.
在另一個較佳實施例中，本發明提出了一種設置在半導體襯底中的半導體功率器件。該半導體功率器件包括多個遮罩溝槽，形成在半導體襯底的頂部，每個遮罩溝槽在預定區域中都有多個微小彎曲，溝槽側壁垂直於溝槽的縱向方向，並從頂面開始垂直延伸到溝槽底面。該半導體功率器件還包括一個溝槽底部P-型摻雜區，設置在溝槽底面下方，以及一個側壁P-型摻雜區，沿彎曲側壁設置，其中側壁P-型摻雜區沿溝槽的彎曲側壁垂直向下延伸，以觸及溝槽底部P-型摻雜區，並將溝槽底部P-型摻雜區連接到形成在半導體襯底頂面的P-型本體區。In another preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a plurality of minute bends in a predetermined region, the trench sidewalls being perpendicular to the longitudinal direction of the trench and from The top surface begins to extend vertically to the underside of the trench. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the curved sidewall, wherein the sidewall P-type doped region is along the trench The curved sidewall extends vertically downward to access the P-type doped region at the bottom of the trench and connects the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate.
在另一個較佳實施例中，本發明提出了一種設置在半導體襯底中的半導體功率器件。該半導體功率器件包括多個遮罩溝槽，形成在半導體襯底的頂部，每個遮罩溝槽在預定區域中都有多個微小凹口，溝槽側壁垂直於溝槽的縱向方向，並從頂面開始垂直延伸到溝槽底面。該半導體功率器件還包括一個溝槽底部P-型摻雜區，設置在溝槽底面下方，以及一個側壁P-型摻雜區，沿凹口側壁設置，其中側壁P-型摻雜區沿溝槽的凹口側壁垂直向下延伸，以觸及溝槽底部P-型摻雜區，並將溝槽底部P-型摻雜區連接到形成在半導體襯底頂面的P-型本體區。In another preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a plurality of minute recesses in a predetermined region, the trench sidewalls being perpendicular to the longitudinal direction of the trenches, and Vertically extending from the top surface to the bottom surface of the groove. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the sidewall of the recess, wherein the sidewall P-type doped region is along the trench The recessed sidewalls of the trench extend vertically downward to contact the P-type doped region at the bottom of the trench and connect the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate.
在一個較佳實施例中，本發明還提出了一種用於在半導體襯底上製備半導體功率器件的方法。該方法包括以下步驟：a）在半導體襯底上方使用一個硬氧化物掩膜，然後根據預定義的溝槽結構形成硬氧化物掩膜的圖案；b）透過帶圖案的硬掩膜刻蝕，在半導體襯底的頂部形成多個溝槽，每個溝槽都有一個溝槽終點、一個微小彎曲或一個微小凹口，側壁垂直於溝槽的縱向方向，並從頂面開始垂直向下延伸到溝槽底面；c）利用垂直（零度）高能注入在溝槽底面下方形成溝槽底部P-型摻雜區，然後去除硬掩膜；d）在溝槽的側壁和底部的矽表面上方，生長一個氧化物襯裡；以及e）利用低能傾斜注入，其中沿預定的傾斜角度，注入摻雜離子，沿垂直側壁形成側壁P-型摻雜區，側壁P-型摻雜區沿溝槽側壁垂直向下延伸，以觸及溝槽底部P-型摻雜區，並將溝槽底部P-型摻雜區連接到形成在半導體襯底頂面上的P-型本體區。在一個實施例中，注入的摻雜離子傾斜角與側壁表面大約呈45度角。In a preferred embodiment, the present invention also provides a method for fabricating a semiconductor power device on a semiconductor substrate. The method comprises the steps of: a) using a hard oxide mask over the semiconductor substrate, then forming a pattern of the hard oxide mask according to the predefined trench structure; b) etching through the patterned hard mask, Forming a plurality of trenches on the top of the semiconductor substrate, each trench having a trench end point, a slight bend or a minute recess, the sidewall being perpendicular to the longitudinal direction of the trench and extending vertically downward from the top surface To the bottom surface of the trench; c) using a vertical (zero) high energy implant to form a trench bottom P-type doped region under the trench bottom surface, and then remove the hard mask; d) above the trench sidewall and the bottom surface of the trench, Growing an oxide liner; and e) utilizing a low energy tilt implant in which dopant ions are implanted along a predetermined tilt angle, sidewall P-type doped regions are formed along vertical sidewalls, and sidewall P-type doped regions are vertically along trench sidewalls Extending downwardly to touch the P-type doped region at the bottom of the trench and connecting the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate. In one embodiment, the implanted dopant ion tilt angle is approximately 45 degrees from the sidewall surface.
閱讀以下詳細說明並參照附圖之後，本發明的這些和其他的特點和優勢，對於本領域的技術人員而言，無疑將顯而易見。These and other features and advantages of the present invention will become apparent to those skilled in the <RTIgt;
11．．．注入開口11. . . Injection opening
12．．．溝槽12. . . Trench
13．．．P-型本體區13. . . P-type body area
15．．．P-型摻雜區15. . . P-type doped region
16．．．區域16. . . region
17．．．平面閘極17. . . Plane gate
18．．．源極18. . . Source
19．．．P++接頭19. . . P++ connector
100．．．注入掩膜100. . . Injection mask
101．．．襯底101. . . Substrate
110．．．溝槽終點側壁110. . . Groove end wall
110’．．．溝槽終點側壁110’. . . Groove end wall
111．．．硬掩膜111. . . Hard mask
115．．．薄氧化層115. . . Thin oxide layer
120．．．溝槽120. . . Trench
120’．．．溝槽120’. . . Trench
125’．．．氧化層125’. . . Oxide layer
130．．．P-型摻雜區130. . . P-type doped region
140．．．P-型摻雜區140. . . P-type doped region
142．．．犧牲材料142. . . Sacrificial material
200．．．溝槽200. . . Trench
210．．．彎曲210. . . bending
220．．．側壁220. . . Side wall
250．．．溝槽250. . . Trench
260．．．凹口260. . . Notch
270．．．側壁270. . . Side wall
t．．．厚度t. . . thickness
t2．．．厚度T2. . . thickness
t1．．．厚度T1. . . thickness
第1A圖表示傳統工藝中所用的注入掩膜的俯視圖，第1B和1C圖表示穿過第1A圖所示的注入掩膜上生長的溝槽，沿兩個不同的方向，PCOMP結構的兩個側視圖。Figure 1A shows a top view of the implantation mask used in the conventional process, and Figs. 1B and 1C show the grooves grown through the implantation mask shown in Fig. 1A, in two different directions, two of the PCOMP structures. Side view.
第2A圖表示半導體襯底上傳統的溝槽結構的俯視圖。Figure 2A shows a top view of a conventional trench structure on a semiconductor substrate.
第2B、2C-1、2C-2、2D-1、2D-2、2E-1、2E-2圖所示的側視圖分別表示在本發明所述溝槽的兩個不同方位上製備PCOMP結構的工藝步驟。The side views shown in Figures 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, and 2E-2 respectively show the preparation of a PCOMP structure in two different orientations of the trench of the present invention. Process steps.
第2F-1和2F-2圖所示的側視圖表示第2E-1和2E-2圖所示的可選實施例。The side views shown in Figs. 2F-1 and 2F-2 show alternative embodiments shown in Figs. 2E-1 and 2E-2.
第2G-1、2G-2、2H-1和2H-2圖所示的側視圖分別表示第2E-1和2E-2圖所示的另一個可選實施例。The side views shown in Figs. 2G-1, 2G-2, 2H-1, and 2H-2 respectively show another alternative embodiment shown in Figs. 2E-1 and 2E-2.
第3A圖表示在本發明的半導體襯底上，不同長度溝槽的可選結構的俯視圖。Figure 3A shows a top view of an alternative structure of trenches of different lengths on a semiconductor substrate of the present invention.
第3B圖表示垂直和傾斜注入形成PCOMP結構之後，圖3A所示半導體襯底的俯視圖。Fig. 3B shows a plan view of the semiconductor substrate shown in Fig. 3A after vertical and oblique implantation to form a PCOMP structure.
第4A圖表示依據本發明的一個實施例，在半導體襯底上溝槽的一個可選結構的俯視圖，其中溝槽具有一個含有微小彎曲的非線性部分。Figure 4A shows a top view of an alternative structure of a trench on a semiconductor substrate in accordance with one embodiment of the present invention, wherein the trench has a non-linear portion containing a slight curvature.
第4B圖表示垂直和傾斜注入形成PCOMP結構之後，圖4B所示半導體襯底的俯視圖。Fig. 4B is a plan view showing the semiconductor substrate shown in Fig. 4B after vertical and oblique implantation to form a PCOMP structure.
第5A圖表示依據本發明的一個實施例，在半導體襯底上溝槽的另一個可選結構的俯視圖，其中溝槽具有一個含有微小凹口的非線性部分。Figure 5A shows a top view of another alternative structure of a trench on a semiconductor substrate in accordance with one embodiment of the present invention, wherein the trench has a non-linear portion containing minute recesses.
第5B圖表示垂直和傾斜注入形成PCOMP結構之後，第5A圖所示半導體襯底的俯視圖。Fig. 5B is a plan view showing the semiconductor substrate shown in Fig. 5A after vertical and oblique implantation to form a PCOMP structure.
以下結合附圖對本發明的技術方案作進一步地說明。The technical solution of the present invention will be further described below with reference to the accompanying drawings.
第2A圖表示在半導體襯底上傳統的溝槽結構的俯視圖。第2B、2C-1、2C-2、2D-1、2D-2、2E-1、2E-2、2F-1、2F-2、2G-1、2G-2、2H-1和2H-2圖所示的側視圖，分別表示在本發明的不同實施例中，沿第2A圖中的線1-1’和線2-2’，製備PCOM結構配置的工藝步驟。Figure 2A shows a top view of a conventional trench structure on a semiconductor substrate. 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, 2E-2, 2F-1, 2F-2, 2G-1, 2G-2, 2H-1 and 2H-2 The side views shown in the figures represent process steps for preparing a PCOM structural arrangement along line 1-1' and line 2-2' in Figure 2A, respectively, in various embodiments of the present invention.
如第2A圖所示，多個溝槽120形成在半導體襯底101上，每個溝槽120都具有一個溝槽終點側壁110。製備多個溝槽120如下所述：如第2B圖所示，在半導體襯底上方沉積一個氧化物硬掩膜111；然後，根據與如第2A圖所示類似的預定義結構，形成硬掩膜111的圖案；然後透過帶圖案的硬掩膜111，各向異性地刻蝕掉半導體襯底101，形成多個溝槽120，如第2C-1和2C-2圖所示，每個溝槽120都有溝槽終點110。As shown in FIG. 2A, a plurality of trenches 120 are formed on the semiconductor substrate 101, each of which has a trench end sidewall 110. A plurality of trenches 120 are prepared as follows: as shown in FIG. 2B, an oxide hard mask 111 is deposited over the semiconductor substrate; then, a hard mask is formed according to a predefined structure similar to that shown in FIG. 2A a pattern of the film 111; then the semiconductor substrate 101 is anisotropically etched through the patterned hard mask 111 to form a plurality of trenches 120, as shown in Figures 2C-1 and 2C-2, each trench The slot 120 has a groove end point 110.
首先進行垂直高能P-型摻雜注入（零度），透過帶圖案的硬掩膜111，在溝槽120的底面下方形成P-型摻雜區130，如第2D-1和2D-2圖所示。P-型摻雜區130在溝槽底部作為RESURF，提供最大的擊穿電壓（BV）閉鎖性能。First, a vertical high-energy P-type doping implant (zero degree) is performed, and a patterned hard mask 111 is formed to form a P-type doped region 130 under the bottom surface of the trench 120, as shown in FIGS. 2D-1 and 2D-2. Show. The P-type doped region 130 acts as a RESURF at the bottom of the trench, providing maximum breakdown voltage (BV) latching performance.
如第2E- 1和2E-2圖所示，移除硬掩膜111，然後在襯底101的頂面上、在溝槽120的側壁和底面上以及在終點側壁110處，沉積一個薄氧化層115，相同的厚度用t表示。然後進行低能傾斜P-型摻雜注入，例如45度角。在第2E-1圖中，在襯底的頂面上、溝槽120的底面下方，以及溝槽側壁周圍的頂部，製備P-型摻雜區140。在第2E-2圖中，在溝槽120的終點處的終點側壁110處，也進行傾斜注入，因此沿溝槽終點側壁110的整個長度、在溝槽120的底面下方以及襯底101的頂面上，製備P-型摻雜區140。獲得PCOMP結構配置，所形成的P-型摻雜區140沿溝槽終點側壁110的整個長度，溝槽終點側壁110將P-本體區（圖中沒有表示出）連接到底部P-型摻雜區130，無需額外的注入掩膜，並且無需高能注入。製備工藝繼續進行標準的工藝步驟，完成整個器件。As shown in Figures 2E-1 and 2E-2, the hard mask 111 is removed, and then a thin oxide is deposited on the top surface of the substrate 101, on the sidewalls and bottom surface of the trench 120, and at the end sidewall 110. Layer 115, the same thickness is indicated by t. A low energy tilted P-type dopant implant is then performed, such as a 45 degree angle. In the 2E-1 diagram, a P-type doped region 140 is prepared on the top surface of the substrate, under the bottom surface of the trench 120, and at the top of the trench sidewall. In the 2E-2 diagram, oblique implantation is also performed at the end point sidewall 110 at the end of the trench 120, so that the entire length along the trench end sidewall 110, below the bottom surface of the trench 120, and at the top of the substrate 101 On the surface, a P-type doping region 140 is prepared. A PCOMP structure configuration is obtained, the formed P-type doped region 140 is along the entire length of the trench end sidewall 110, and the trench end sidewall 110 connects the P-body region (not shown) to the bottom P-type doping. Zone 130 requires no additional implant mask and does not require high energy implants. The fabrication process continues with standard process steps to complete the entire device.
在第2E-1和2E-2圖中，如上所述，在襯底101的頂面上以及溝槽120和終點側壁110的側壁和底面上，沉積一個厚度t均勻薄氧化層115。第2F-1和2F-2圖所示的側視圖與第2E-1和2E-2圖類似。在本實施例中，氧化層125’沉積在襯底101的頂面上以及溝槽120的底面上，氧化層125’的厚度t2大於氧化層125的厚度t1，氧化層125覆蓋著溝槽120的側壁和溝槽終點側壁110。因此，進行低能傾斜角注入後，如第2F-1圖所示，P-型摻雜區140僅形成在溝槽120側壁周圍的頂部。在第2F-2圖中，P摻雜區140僅沿溝槽終點側壁110的整個長度形成。因此，獲得PCOMP結構配置，所形成的摻雜區140沿溝槽終點側壁110的整個長度，將形成在半導體襯底底面的P-型本體區（圖中沒有表示出）連接到底部P-型摻雜區130，無需額外的注入掩膜，無需高能注入。按照標準的製備過程，完成整個器件的製備。In the 2E-1 and 2E-2 diagrams, as described above, a thin oxide layer 115 of uniform thickness t is deposited on the top surface of the substrate 101 and on the sidewalls and the bottom surface of the trench 120 and the end sidewall 110. The side views shown in Figures 2F-1 and 2F-2 are similar to those in Figures 2E-1 and 2E-2. In the present embodiment, the oxide layer 125' is deposited on the top surface of the substrate 101 and the bottom surface of the trench 120. The thickness t2 of the oxide layer 125' is greater than the thickness t1 of the oxide layer 125, and the oxide layer 125 covers the trench 120. The sidewalls and the trench end sidewalls 110. Therefore, after the low energy tilt angle implantation is performed, as shown in FIG. 2F-1, the P-type doping region 140 is formed only at the top portion around the sidewall of the trench 120. In the 2F-2 diagram, the P-doped region 140 is formed only along the entire length of the trench end sidewall 110. Therefore, the PCOMP structure configuration is obtained, and the doped region 140 is formed along the entire length of the trench end sidewall 110 to connect the P-type body region (not shown) formed on the bottom surface of the semiconductor substrate to the bottom P-type. The doped region 130 eliminates the need for an additional implantation mask and does not require high energy implantation. The preparation of the entire device was completed in accordance with standard preparation procedures.
在一個可選實施例中，如果厚度t均勻的薄氧化層115沉積在襯底101的頂面上，以及溝槽120和終點側壁110的側壁和底面上，與第2E-1和2E-2圖所示類似，防止傾斜注入穿通溝槽120底部的氧化層，在進行傾斜注入之前，如第2G-1和2G-2圖所示，先在溝槽120的底部沉積一層犧牲材料142，沉積厚度可控。層142可以是高密度等離子（HDP）氧化物光致抗蝕劑、TEOS等等。因此，進行低能傾斜角注入後，如第2G-1圖所示，P-型摻雜區140僅僅形成在溝槽120側壁周圍的頂部以及半導體襯底101的頂面，在第2G-2圖中，所形成的P摻雜區140僅僅沿溝槽終點側壁110的整個長度以及半導體襯底101的頂面上。然後，在用多晶矽填充溝槽120的下一個工藝步驟之前，如第2H-1和2H-2圖所示，先除去犧牲材料層142。按照標準的製備過程，完成整個器件的製備。In an alternative embodiment, if a thin oxide layer 115 having a uniform thickness t is deposited on the top surface of the substrate 101, as well as the sidewalls and bottom surfaces of the trenches 120 and the end sidewalls 110, and 2E-1 and 2E-2 Similar to the figure, the oblique injection of the oxide layer at the bottom of the trench 120 is prevented. Before the oblique implant is performed, as shown in the 2G-1 and 2G-2 diagrams, a sacrificial material 142 is deposited on the bottom of the trench 120 for deposition. The thickness is controllable. Layer 142 can be a high density plasma (HDP) oxide photoresist, TEOS, and the like. Therefore, after the low energy tilt angle implantation, as shown in FIG. 2G-1, the P-type doping region 140 is formed only on the top of the sidewall around the trench 120 and the top surface of the semiconductor substrate 101, in the second G-2 diagram. The P-doped region 140 is formed only along the entire length of the trench end sidewall 110 and the top surface of the semiconductor substrate 101. Then, prior to the next process step of filling the trenches 120 with polysilicon, as shown in Figures 2H-1 and 2H-2, the sacrificial material layer 142 is removed first. The preparation of the entire device was completed in accordance with standard preparation procedures.
第3A-3B圖表示本發明的一個可選實施例。如第3A圖所示，本發明所述的半導體襯底101上的一個可選溝槽結構的俯視圖，在預定區域製備溝槽終點，可以調節溝槽120’的長度（例如使溝槽120’的長度小於第2A圖所示的溝槽120的長度），從而調節溝槽終點側壁110’的密度以及PCOMP結構配置的密度，因此帶有P-型摻雜區的PCOMP結構配置沿溝槽終點側壁的整個長度，將形成在半導體襯底頂面上的P-型本體區連接到溝槽底部P-型摻雜區，PCOMP結構配置分佈在半導體襯底的整個區域上。第3B圖表示利用上述製備PCOMP結構配置的注入工藝，進行注入之後的半導體襯底101的俯視圖。如第3B圖所示，透過溝槽硬掩膜垂直注入P-型摻雜物，可以在溝槽120’的底面下方構成P-型摻雜區130，在溝槽終點側壁110’處傾斜注入P-型摻雜物，可以沿溝槽終點側壁110’的整個長度形成P-型摻雜區140。根據兩個相鄰溝槽120’的兩個終點之間的空間，P-型摻雜區140可以合併在一起，如第3B圖所示，或者相互間隔開（圖中沒有表示出）。Figures 3A-3B illustrate an alternate embodiment of the present invention. As shown in FIG. 3A, a top view of an optional trench structure on the semiconductor substrate 101 of the present invention, the trench end point is prepared in a predetermined area, and the length of the trench 120' can be adjusted (eg, the trench 120' The length is smaller than the length of the trench 120 shown in FIG. 2A, thereby adjusting the density of the trench end sidewall 110' and the density of the PCOMP structure configuration, so the PCOMP structure with the P-type doping region is along the trench end point. The entire length of the sidewall is connected to the P-type body region formed on the top surface of the semiconductor substrate to the P-type doped region at the bottom of the trench, and the PCOMP structure is disposed over the entire region of the semiconductor substrate. Fig. 3B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in FIG. 3B, a P-type dopant is vertically implanted through the trench hard mask, and a P-type doping region 130 may be formed under the bottom surface of the trench 120', and obliquely implanted at the trench end sidewall 110'. The P-type dopant can form a P-type doped region 140 along the entire length of the trench end sidewall 110'. Depending on the space between the two end points of two adjacent trenches 120', the P-type doped regions 140 may be merged together, as shown in Figure 3B, or spaced apart from one another (not shown).
第4A-4B圖表示本發明所述的一個可選實施例。第4A圖表示在本發明所述的半導體襯底101上的一種可選溝槽結構的俯視圖，如第4A圖所示，每個溝槽200都有一個非線性部分，由在預定區域的微小彎曲組成，從而構成溝槽側壁220，沿與溝槽軸向不在同一直線上的方向。在第4A圖所示的彎曲210中，溝槽側壁220垂直於溝槽200的軸向。因此，側壁220的整個垂直長度裸露出來，帶有傾斜角的沿溝槽軸向入射的摻雜離子進行傾斜離子注入。鑒於溝槽側壁的整個垂直長度都裸露出來，因此可以用低能摻雜離子進行傾斜離子注入，以觸及溝槽側壁220的底部。第4B圖表示利用上述製備PCOMP結構配置的注入工藝，進行注入之後的半導體襯底101的俯視圖。如第4B圖所示，透過溝槽硬掩膜垂直注入P-型摻雜物，在溝槽200的底面下方形成P-型摻雜區130，在溝槽側壁220和溝槽終點側壁110處的傾斜角P-型摻雜注入，沿溝槽側壁220和終點側壁110的整個長度形成P-型摻雜區140。Figures 4A-4B show an alternative embodiment of the invention. 4A is a plan view showing an alternative trench structure on the semiconductor substrate 101 of the present invention. As shown in FIG. 4A, each trench 200 has a nonlinear portion, which is minutely formed in a predetermined region. The composition is curved to form the trench sidewalls 220 in a direction that is not in line with the axial direction of the trenches. In the bend 210 shown in FIG. 4A, the trench sidewall 220 is perpendicular to the axial direction of the trench 200. Therefore, the entire vertical length of the side wall 220 is exposed, and the doping ions incident along the axial direction of the groove with the oblique angle perform oblique ion implantation. Since the entire vertical length of the trench sidewalls is exposed, oblique ion implantation can be performed with low energy dopant ions to reach the bottom of the trench sidewalls 220. Fig. 4B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in FIG. 4B, a P-type dopant is vertically implanted through the trench hard mask, and a P-type doped region 130 is formed under the bottom surface of the trench 200, at the trench sidewall 220 and the trench end sidewall 110. The tilt angle P-type doping implant forms a P-type doped region 140 along the entire length of the trench sidewall 220 and the end sidewall 110.
第5A-5B圖表示本發明的一個可選實施例。第5A圖表示在本發明所述的半導體襯底101上的一個可選溝槽結構的俯視圖，如第5A圖所示，每個溝槽250都有一個非線性部分，由在預定區域的微小凹口260組成，從而構成溝槽側壁270，沿與溝槽軸向不在同一直線上的方向。在第5A圖所示的凹口260中，溝槽側壁270垂直於溝槽250的軸向。因此，側壁270的整個垂直長度裸露出來，帶有傾斜角的沿溝槽軸向入射的摻雜離子進行傾斜離子注入。鑒於溝槽側壁的整個垂直長度都裸露出來，因此可以用低能摻雜離子進行傾斜離子注入，以觸及溝槽側壁270的底部。第5B圖表示利用上述製備PCOMP結構配置的注入工藝，進行注入之後的半導體襯底101的俯視圖。如第5B圖所示，透過溝槽硬掩膜垂直注入P-型摻雜物，在溝槽250的底面下方形成P-型摻雜區130，在凹口260飛溝槽側壁270和溝槽終點側壁110處的傾斜角P-型摻雜注入，沿溝槽側壁220和終點側壁110的整個長度形成P-型摻雜區140。Figures 5A-5B illustrate an alternate embodiment of the present invention. Figure 5A shows a top view of an optional trench structure on the semiconductor substrate 101 of the present invention. As shown in Figure 5A, each trench 250 has a non-linear portion, which is tiny in a predetermined area. The recesses 260 are formed to form the trench sidewalls 270 in a direction that is not in line with the axial direction of the trenches. In the recess 260 shown in FIG. 5A, the trench sidewall 270 is perpendicular to the axial direction of the trench 250. Therefore, the entire vertical length of the side wall 270 is exposed, and the doping ions incident along the axial direction of the groove with the oblique angle perform oblique ion implantation. Since the entire vertical length of the trench sidewalls is exposed, oblique ion implantation can be performed with low energy dopant ions to reach the bottom of the trench sidewalls 270. Fig. 5B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in FIG. 5B, the P-type dopant is vertically implanted through the trench hard mask, a P-type doped region 130 is formed under the bottom surface of the trench 250, and the trench sidewall 270 and the trench are floated at the recess 260. An oblique angle P-type doping implant at the end sidewall 110 forms a P-type doped region 140 along the entire length of the trench sidewall 220 and the endpoint sidewall 110.
一般來說，可以透過製備溝槽進一步配置如第4A、4B和5A、5B圖所示的可選溝槽結構，以便在特定區域構成寬度可以縮小或放大的部分。在這些區域的溝槽部分形成溝槽側壁，沿垂直于溝槽軸向的方向，從而使側壁的整個垂直長度裸露出來，使注入離子穿透側壁的整個垂直深度，無需製備PCOMP結構配置時的高能離子注入。另外，還可以透過製備帶有橫向完全結構的溝槽，配置可選溝槽結構，從而使溝槽保持裸露出來，用於製備PCOMP結構配置時進行全垂直深度注入，而無需高能離子注入。In general, the optional trench structure as shown in Figs. 4A, 4B and 5A, 5B can be further configured by preparing the trenches to form portions of the width reduction or enlargement in a specific region. Forming trench sidewalls in the trench portions of these regions, in a direction perpendicular to the axial direction of the trenches, thereby exposing the entire vertical length of the sidewalls so that the implanted ions penetrate the entire vertical depth of the sidewalls without the need to fabricate a PCOMP structure High energy ion implantation. In addition, an optional trench structure can be configured by preparing trenches with laterally complete structures to keep the trenches exposed for full vertical depth implants in the PCOMP structure configuration without the need for high energy ion implantation.
儘管本發明已經詳細說明了現有的較佳實施例，但應理解這些說明不應作為本發明的局限。領域的技術人員閱讀上述詳細說明後，各種變化和修正無疑將顯而易見。因此，應認為所附的申請專利範圍涵蓋本發明的真實意圖和範圍內的全部變化和修正。While the invention has been described in detail, the preferred embodiments of the invention Various changes and modifications will no doubt become apparent to those skilled in the art after reading the Detailed Description. Accordingly, the appended claims are intended to cover all such modifications and modifications
130．．．P-型摻雜區130. . . P-type doped region
140．．．P-型摻雜區140. . . P-type doped region
200．．．溝槽200. . . Trench
Claims (10)
一個形成在半導體襯底的頂部的溝槽，穿過該半導體襯底，沿軸向水準延伸，其中該溝槽還包括一個非線性部分，該非線性部分包含沿與軸向不在同一方向延伸的非線性溝槽側壁，使該非線性溝槽側壁的整個垂直長度裸露出來，以直接接收沿軸向傾斜注入的摻雜離子，沿該非線性溝槽側壁的整個垂直長度，構成側壁摻雜區；以及一個設置在該溝槽底面下方的溝槽底部摻雜區，該側壁摻雜區沿該非線性溝槽側壁向下延伸，以觸及該溝槽底部摻雜區，拾取該溝槽底部摻雜區到該半導體襯底的頂面。A semiconductor power device disposed in a semiconductor substrate, characterized in that it comprises:
a trench formed on top of the semiconductor substrate, extending through the semiconductor substrate, along an axial level, wherein the trench further includes a non-linear portion including a non-non-linear extension a linear trench sidewall that exposes the entire vertical length of the non-linear trench sidewall to directly receive the doped ions implanted obliquely in the axial direction, forming a sidewall doped region along the entire vertical length of the nonlinear trench sidewall; a trench doped region disposed under the bottom surface of the trench, the sidewall doped region extending downward along the sidewall of the non-linear trench to touch the doped region at the bottom of the trench, and picking the doped region at the bottom of the trench The top surface of the semiconductor substrate.
透過帶圖案的該硬掩膜，刻蝕該半導體襯底，在該半導體襯底頂部形成多個溝槽，每個溝槽都有一個水準非線性部分，由沿與軸向不在同一方向上的非線性溝槽側壁組成；
利用垂直高能注入，在溝槽底面下方形成該溝槽底部摻雜區，然後除去該硬掩膜；
沉積一個絕緣層，覆蓋該溝槽側壁，以及該溝槽底面；並且沿溝槽軸向進行低能傾斜注入，以便沿該非線性溝槽側壁的整個垂直長度形成一個側壁摻雜區，其中，該側壁摻雜區沿該非線性溝槽的整個垂直長度向下延伸，以觸及該溝槽底部摻雜區，拾取該溝槽底部摻雜區到該半導體襯底的頂面。A method for fabricating a semiconductor power device on a semiconductor substrate, the method comprising: providing a hard mask over the semiconductor substrate, and forming a pattern of the hard mask according to a predefined trench structure;
Etching the semiconductor substrate through the patterned hard mask, forming a plurality of trenches on top of the semiconductor substrate, each trench having a level nonlinear portion, which is not in the same direction as the axial direction Nonlinear groove sidewall composition;
Forming the bottom doped region of the trench under the bottom surface of the trench by vertical high energy implantation, and then removing the hard mask;
Depositing an insulating layer covering the sidewalls of the trench and the bottom surface of the trench; and performing a low energy oblique implant along the axial direction of the trench to form a sidewall doping region along the entire vertical length of the sidewall of the nonlinear trench, wherein the sidewall A doped region extends down the entire vertical length of the non-linear trench to contact the trench doped region of the trench, and the trench bottom doped region is picked up to the top surface of the semiconductor substrate.
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