CN104143572B - The structure and processing method of high-voltage MOSFET - Google Patents
The structure and processing method of high-voltage MOSFET Download PDFInfo
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- CN104143572B CN104143572B CN201410173266.6A CN201410173266A CN104143572B CN 104143572 B CN104143572 B CN 104143572B CN 201410173266 A CN201410173266 A CN 201410173266A CN 104143572 B CN104143572 B CN 104143572B
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- 239000007924 injection Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 9
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- 238000005468 ion implantation Methods 0.000 claims description 7
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- 238000002360 preparation method Methods 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 14
- 238000010276 construction Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
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- 230000015556 catabolic process Effects 0.000 description 2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
The invention discloses a kind of structure of high-voltage MOSFET and processing method, it is a kind of semiconductor power device set in the semiconductor substrate.The semiconductor power device includes the multiple grooves formed at the top of Semiconductor substrate, it is horizontal-extending vertically through Semiconductor substrate, each groove contains a non-linear partial, including the side wall one perpendicular to groove axial direction, the semiconductor power device extends vertically downward into trench bottom surfaces since top surface.The semiconductor power device also includes a channel bottom doped region being arranged on below trench bottom surfaces, and a wall doping area set along vertical sidewall, wherein vertical sidewall of the wall doping area along groove extends downward vertically, to touch channel bottom doped region, the top surface of pickup channel bottom doped region to Semiconductor substrate.
Description
Technical field
The invention mainly relates to the structure of semiconductor power device and preparation technology.More precisely, the present invention relates to change
Good figure high pressure（HV）Mos field effect transistor（MOSFET）Simplify structural configuration and preparation technology.
Background technology
Prepare high pressure（HV）The conventional art of MOSFET element, due to there are various choices, further improves device performance
If, still suffer from many difficult and limitation.In vertical semiconductor power device, the drain-source resistance of one of attribute of performance（I.e.
On-state resistance, conventional RdsA represents, i.e. Rds × active region area）Deposited between the breakdown voltage that can be born with power device
In the relation of choice.Brought difficulty and limitation are accepted or rejected to solve these performances, we have studied a variety of device architectures.For this
It also specially have developed special P- synthesis（PCOM）Structure.Exactly, the high pressure with PCOM structures（HV）MOSFET element bag
The P-type doped region for surrounding shield trenches side wall is included, so as to the P-type body zone and shield trenches on Semiconductor substrate top surface
Connection is formed between the P-type doped region of lower section.In order to form wall doping area around trenched side-wall, conventional method uses band
The additional injection mask for having injection to be open, injection technology is carried out on the trenched side-wall at shield trenches selected location.In addition,
To ensure that Doped ions are injected into the bottom of trenched side-wall, it is necessary to inject the Doped ions of high-energy.Need to use additional mask
And high energy Doped ions technique, each of which increases prepare cost.In addition, high energy ion implantation and the diffusion of trenched side-wall bottom
Technique, is generally not easy to control the formation of doped region.The uncertainty of these preparation technologies causes device performance acute variation, no
It is easy to accurate control to prepare quality.
Figure 1A represents the top view of injection mask 100 used in traditional handicraft, and Figure 1B and 1C represent the line 1- along Figure 1A
1 ' and 2-2 ', high pressure is prepared using traditional technique（HV）Two profiles of MOSFET element structure.As shown in Figure 1A, inject
Opening 11 is located on the selected areas of groove 12.In order to prepare the MOSFET element that can bear high power operation, PCOM is formed
（P- is synthesized）Structure.In the PCOM MOSFET structures, by injecting opening 11, the part below P-type body zone 13
In region 16, special doped region is formed, so that as shown in Figure 1 C, by P-type body zone and the P-type doped region of the lower section of groove 12
15 connect.Meanwhile, in other regions, by injecting mask 100, prevent that injection forms doped region below body zone.
Injection mask shown in Figure 1A prevents from, by the trenched side-wall in 1-1 ' peripheral regions, injecting dopant.Figure 1B represents that one kind does not have
There is doped region to surround body zone and doped region below the structure of trenched side-wall, connection channel bottom.As shown in Figure 1B -1C,
High pressure（HV）MOSFET element also includes a planar gate 17, forms side, an and He of source electrode 18 on a semiconductor substrate
One P++ joint 19, is formed at the top of P-type body zone 13.
Conventional preparation techniques as shown in Figure 1A to 1C need extra injection mask.In addition, it is necessary to high energy ion implantation P-type
Dopant, such as P-type doping infusion in Mev areas is as shown in Figure 1 C, square under the body zone around trenched side-wall
Into doped region.The requirement of extra mask and high energy ion implantation, adds preparation cost.
Therefore, for those skilled in the art, it is necessary to improve the preparation method of power device, especially with
The device of PCOM structures, could solve above-mentioned technology limitation.It is an object of the invention to propose it is new, improvement preparation method and
Device architecture, is allowed to no longer need extra injection mask and high energy ion implantation, so as to overcome above-mentioned difficulties and limitation.
The content of the invention
Therefore, one aspect of the present invention is, it is proposed that a kind of new, improvement preparation method, without extra note
Enter mask and high energy doping injection, can be achieved with the injection of trenched side-wall P-type doped region, so as to reduce preparation cost, and solve
Above-mentioned limitation and difficulty.
Exactly, it is an aspect of the invention to injection technology make use of the special construction of groove destination county side wall, hang down
The straight side wall in groove longitudinal direction, which is exposed, to be come, and opens space as a part for groove.Due to Semiconductor substrate need not be penetrated, only
By the open space of groove, with regard to Doped ions can be launched, therefore, by the terminal groove, P-type doped region note can be carried out
Enter, without using high energy Doped ions, with regard to the bottom P-type doped region to be formed in channel bottom can be touched.Connection is formed and partly led
The PCOM doped regions of P-type body zone and channel bottom P-type doped region on body substrate surface, are formed only into groove terminal
Side-walls.Compared with conventional method, adulterate and inject without high energy, save cost.
In addition, one aspect of the present invention is, injection technology make use of the special construction of groove knee trenched side-wall,
In groove knee, the side wall perpendicular to groove longitudinal direction, which is exposed, to be come, and opens space as a part for groove.In addition, this hair
Bright one side is that injection technology make use of the special construction of groove indent trenched side-wall, in groove indent, vertically
Side wall in groove longitudinal direction, which is exposed, to be come, and opens space as a part for groove.Due to Semiconductor substrate need not be penetrated, only lead to
The open space of groove is crossed, with regard to Doped ions can be launched, therefore, passes through the side wall, it is possible to carry out P-type doped region injection,
Without using high energy Doped ions, with regard to the bottom P-type doped region to be formed in channel bottom can be touched.
Another aspect of the present invention is, above the trenched side-wall of groove terminal, groove bending and groove indent, edge
Groove longitudinally through open space, carry out wall doping injection, can preferably control injection technology.Precisely control device
Part performance parameter, and reduce preparation technology change caused by the brought uncertainty of high energy doping injection.
In a preferred embodiment, the present invention proposes a kind of semiconductor power device set in the semiconductor substrate
Part.The semiconductor power device includes multiple shield trenches, is formed at the top of Semiconductor substrate, each shield trenches have one
Individual groove terminal, terminus wall and extends vertically downward into since top surface trench bottom surfaces perpendicular to the longitudinal direction of groove.
The semiconductor power device also includes a channel bottom P-type doped region, is arranged on below trench bottom surfaces, and a side wall
P-type doped region, is set along terminus wall, and wherein terminus wall of the side wall P-type doped region along groove extends vertically downward, to touch
And channel bottom P-type doped region, and channel bottom P-type doped region is connected to the P-type sheet to be formed in Semiconductor substrate top surface
Body area.
In another preferred embodiment, the present invention proposes a kind of semiconductor power device set in the semiconductor substrate
Part.The semiconductor power device includes multiple shield trenches, is formed at the top of Semiconductor substrate, each shield trenches are predetermined
There are multiple slight curves in region, trenched side-wall and extends vertically up to since top surface ditch perpendicular to the longitudinal direction of groove
Groove bottom.The semiconductor power device also includes a channel bottom P-type doped region, is arranged on below trench bottom surfaces, Yi Jiyi
Individual side wall P-type doped region, is set along crooked sidewall, and wherein crooked sidewall of the side wall P-type doped region along groove prolongs vertically downward
Stretch, to touch channel bottom P-type doped region, and channel bottom P-type doped region is connected to be formed in Semiconductor substrate top surface
P-type body zone.
In another preferred embodiment, the present invention proposes a kind of semiconductor power device set in the semiconductor substrate
Part.The semiconductor power device includes multiple shield trenches, is formed at the top of Semiconductor substrate, each shield trenches are predetermined
There are multiple small recesses in region, trenched side-wall and extends vertically up to since top surface ditch perpendicular to the longitudinal direction of groove
Groove bottom.The semiconductor power device also includes a channel bottom P-type doped region, is arranged on below trench bottom surfaces, Yi Jiyi
Individual side wall P-type doped region, is set along recess sidewall, and wherein recess sidewall of the side wall P-type doped region along groove is prolonged vertically downward
Stretch, to touch channel bottom P-type doped region, and channel bottom P-type doped region is connected to be formed in Semiconductor substrate top surface
P-type body zone.
In a preferred embodiment, the invention also provides one kind is used to prepare semiconductor power on a semiconductor substrate
The method of device.This method comprises the following steps：a）Side uses a hard oxide mask on a semiconductor substrate, then basis
Predefined groove structure forms the pattern of hard oxide mask；b）By patterned hard mask etching, in Semiconductor substrate
Top form multiple grooves, each groove has a groove terminal, a slight curves or a small recess, and side wall hangs down
Directly in the longitudinal direction of groove, and extend vertically downward into since top surface trench bottom surfaces；c）Using vertical（Zero degree）High energy is noted
Enter in trench bottom surfaces channel bottom P-type doped region formed below, then remove hard mask；d）Side wall and bottom in groove
Above silicon face, in one oxide liner of growth；And e）Tilted and injected using low energy, wherein along predetermined angle of inclination, noting
Enter Doped ions, along vertical sidewall formation side wall P-type doped region, side wall P-type doped region extends vertically downward along trenched side-wall,
To touch channel bottom P-type doped region, and channel bottom P-type doped region is connected to be formed on Semiconductor substrate top surface
P-type body zone.In one embodiment, the Doped ions inclination angle of injection is about in 45 degree of angles with sidewall surfaces.
Read it is described further below and referring to the drawings after, it is of the invention these and other the characteristics of and advantage, for this
For the technical staff in field, undoubtedly it will be evident.
Brief description of the drawings
Figure 1A represents the top view of injection mask used in traditional handicraft, and Figure 1B and 1C are represented through the note shown in Figure 1A
Enter the groove grown on mask, along two different directions, two side views of PCOMP structures.
Fig. 2A represents the top view of groove structure traditional in Semiconductor substrate.
Side view shown in Fig. 2 B, 2C-1,2C-2,2D-1,2D-2,2E-1,2E-2 is illustrated respectively in ditch of the present invention
The processing step of PCOMP structures is prepared in two different azimuths of groove.
Side view shown in Fig. 2 F-1 and 2F-2 represents the alternative embodiment shown in Fig. 2 E-1 and 2E-2.
Side view shown in Fig. 2 G-1,2G-2,2H-1 and 2H-2 represent respectively shown in Fig. 2 E-1 and 2E-2 another can
Select embodiment.
Fig. 3 A represent the present invention Semiconductor substrate on, the top view of the alternative construction of different length groove.
Fig. 3 B represent that vertical and inclination injection is formed after PCOMP structures, the top view of Semiconductor substrate shown in Fig. 3 A.
Fig. 4 A represent the vertical view according to one embodiment of the present of invention, on a semiconductor substrate groove a alternative construction
Figure, wherein groove have a non-linear partial containing slight curves.
Fig. 4 B represent that vertical and inclination injection is formed after PCOMP structures, the top view of Semiconductor substrate shown in Fig. 4 B.
Fig. 5 A are represented according to one embodiment of the present of invention, and another alternative construction of groove is bowed on a semiconductor substrate
View, wherein groove have a non-linear partial for containing small recess.
Fig. 5 B represent that vertical and inclination injection is formed after PCOMP structures, the top view of Semiconductor substrate shown in Fig. 5 A.
Embodiment
Technical scheme is further described below in conjunction with accompanying drawing.
Fig. 2A represents the top view of groove structure traditional on a semiconductor substrate.Fig. 2 B, 2C-1,2C-2,2D-1,2D-
2nd, the side view shown in 2E-1,2E-2,2F-1,2F-2,2G-1,2G-2,2H-1 and 2H-2, is illustrated respectively in the difference of the present invention
In embodiment, along the line 1-1 ' and line 2-2 ' in Fig. 2A, the processing step of PCOM structures configuration is prepared.
As shown in Figure 2 A, multiple grooves 120 are formed in Semiconductor substrate 101, and each groove 120 has a groove
Terminus wall 110.Prepare multiple grooves 120 as described below：As shown in Figure 2 B, side deposits an oxide on a semiconductor substrate
Hard mask 111；Then, according to similar predefined structure as shown in Figure 2 A, form the pattern of hard mask 111；Then pass through
Patterned hard mask 111, anisotropically etches away Semiconductor substrate 101, forms multiple grooves 120, such as Fig. 2 C-1 and 2C-
Shown in 2, each groove 120 has groove terminal 110.
Vertical high energy P-type doping injection is carried out first（Zero degree）, by patterned hard mask 111, in groove 120
Subjacent formation P-type doped region 130, as shown in Fig. 2 D-1 and 2D-2.P-type doped region 130 is in channel bottom conduct
There is provided maximum breakdown voltage by RESURF（BV）Latch performance.
As shown in Fig. 2 E-1 and 2E-2, hard mask 111 is removed, then on the top surface of substrate 101, in the side of groove 120
On wall and bottom surface and at terminus wall 110, a thin oxide layer 115 is deposited, identical thickness is represented with t.Then carry out
Low energy tilts P-type doping injection, such as 45 degree angles.In Fig. 2 E-1, on the top surface of substrate, the subjacent of groove 120,
And the top around trenched side-wall, prepare P-type doped region 140.In Fig. 2 E-2, in the terminal side of the destination county of groove 120
At wall 110, also enter line tilt injection, therefore along the whole length of groove terminus wall 110, groove 120 subjacent with
And on the top surface of substrate 101, prepare P-type doped region 140.Obtain the configuration of PCOMP structures, the edge of P-type doped region 140 formed
The whole length of groove terminus wall 110, groove terminus wall 110 is by P- body zones（Do not represented in figure）It is connected to bottom
P-type doped region 130, without extra injection mask, and without high energy ion implantation.The technique that preparation technology proceeds standard
Step, completes whole device.
In Fig. 2 E-1 and 2E-2, as described above, on the top surface of substrate 101 and groove 120 and terminus wall 110
On side wall and bottom surface, the uniform thin oxide layers 115 of a thickness t are deposited.Side view shown in Fig. 2 F-1 and 2F-2 and Fig. 2 E-1 and
2E-2 is similar.In the present embodiment, oxide layer 125 ' is deposited on the top surface of substrate 101 and on the bottom surface of groove 120, oxidation
The thickness t2 of layer 125 ' is more than the thickness t1 of oxide layer 125, and oxide layer 125 is covered with side wall and the groove terminal side of groove 120
Wall 110.Therefore, carry out after low energy inclination angle injection, as shown in Fig. 2 F-1, P-type doped region 140 is made only in the side wall of groove 120
The top of surrounding.In Fig. 2 F-2, P doped regions 140 are only formed along the whole length of groove terminus wall 110.Therefore, obtain
PCOMP structures are configured, and whole length of the doped region 140 formed along groove terminus wall 110 will be formed in Semiconductor substrate
The P-type body zone of bottom surface（Do not represented in figure）Bottom P-type doped region 130 is connected to, without extra injection mask, nothing
Need high energy ion implantation.According to the preparation process of standard, the preparation of whole device is completed.
In one alternate embodiment, if the uniform thin oxide layers 115 of thickness t are deposited on the top surface of substrate 101, with
And on groove 120 and the side wall of terminus wall 110 and bottom surface, it is similar with shown in Fig. 2 E-1 and 2E-2, prevent from tilting injection break-through
The oxide layer of the bottom of groove 120, before line tilt injection is entered, as shown in Fig. 2 G-1 and 2G-2, first sinks in the bottom of groove 120
One layer of expendable material 142 of product, deposit thickness is controllable.Layer 142 can be high-density plasma（HDP）Oxide photoresist,
TEOS etc..Therefore, carry out after low energy inclination angle injection, as shown in Fig. 2 G-1, P-type doped region 140 is formed only into groove
The top of 120 lateral wall circumferences and the top surface of Semiconductor substrate 101, in Fig. 2 G-2, the P doped regions 140 formed only edge
In the whole length of groove terminus wall 110 and the top surface of Semiconductor substrate 101.Then, groove 120 is being filled with polysilicon
Next processing step before, as shown in Fig. 2 H-1 and 2H-2, first remove sacrificial material layer 142.According to the preparation of standard
Journey, completes the preparation of whole device.
Fig. 3 A-3B represent the alternative embodiment of the present invention.As shown in Figure 3A, Semiconductor substrate of the present invention
The top view of an optional groove structure on 101, groove terminal is prepared in presumptive area, can adjust the length of groove 120 '
（The length of groove 120 ' is for example set to be less than the length of the groove 120 shown in Fig. 2A）, so as to adjust groove terminus wall 110 '
Density and the density of PCOMP structures configuration, therefore the configuration of the PCOMP structures with P-type doped region is along groove terminus wall
Whole length, the P-type body zone that will be formed on Semiconductor substrate top surface is connected to channel bottom P-type doped region, PCOMP knots
Structure configuration is distributed in the whole region of Semiconductor substrate.Fig. 3 B represent to utilize the above-mentioned injection work for preparing the configuration of PCOMP structures
Skill, the top view of the Semiconductor substrate 101 after being injected.As shown in Figure 3 B, the hard mask vertical injection P-type of groove is passed through
Dopant, can constitute P-type doped region 130 in the subjacent of groove 120 ', tilt and inject at the place of groove terminus wall 110 '
P-type dopant, can form P-type doped region 140 along the whole length of groove terminus wall 110 '.According to two adjacent trenches
Space between 120 ' two terminals, P-type doped region 140 may be incorporated in together, as shown in Figure 3 B, or spaced
Open（Do not represented in figure）.
Fig. 4 A-4B represent an alternative embodiment of the present invention.Fig. 4 A represent to serve as a contrast in semiconductor of the present invention
A kind of top view of optional groove structure on bottom 101, as shown in Figure 4 A, each groove 200 has a non-linear partial, by
Constituted in the slight curves of presumptive area, so that trenched side-wall 220 is constituted, along the side with groove axially not on the same line
To.In the bending 210 shown in Fig. 4 A, trenched side-wall 220 is perpendicular to the axial direction of groove 200.Therefore, the whole of side wall 220 is hung down
Straight length, which is exposed, to be come, and the Doped ions incident along groove axial direction with inclination angle carry out angle-tilt ion injection.In view of groove
The whole vertical length of side wall, which is all exposed, to be come, therefore can carry out angle-tilt ion injection with low energy Doped ions, to touch ditch
The bottom of groove sidewall 220.Fig. 4 B represent to utilize the above-mentioned injection technology for preparing the configuration of PCOMP structures, half after being injected
The top view of conductor substrate 101.As shown in Figure 4 B, by the hard mask vertical injection P-type dopant of groove, at the bottom of groove 200
Face P-type doped region 130 formed below, the inclination angle P-type doping injection at trenched side-wall 220 and groove terminus wall 110,
Along the whole length formation P-type doped region 140 of trenched side-wall 220 and terminus wall 110.
Fig. 5 A-5B represent the alternative embodiment of the present invention.Fig. 5 A are represented in Semiconductor substrate 101 of the present invention
On an optional groove structure top view, as shown in Figure 5A, each groove 250 has a non-linear partial, by pre-
The small recess 260 for determining region is constituted, so that trenched side-wall 270 is constituted, along the direction with groove axially not on the same line.
In the recess 260 shown in Fig. 5 A, trenched side-wall 270 is perpendicular to the axial direction of groove 250.Therefore, side wall 270 is whole vertically long
Degree, which is exposed, to be come, and the Doped ions incident along groove axial direction with inclination angle carry out angle-tilt ion injection.In view of trenched side-wall
Whole vertical length all expose, therefore angle-tilt ion injection can be carried out with low energy Doped ions, to touch channel side
The bottom of wall 270.Fig. 5 B represent to prepare the injection technology that PCOMP structures are configured, the semiconductor after being injected using above-mentioned
The top view of substrate 101.As shown in Figure 5 B, by the hard mask vertical injection P-type dopant of groove, under the bottom surface of groove 250
It is square into P-type doped region 130, fly the inclination angle P-type doping at trenched side-wall 270 and groove terminus wall 110 in recess 260
Injection, along the whole length formation P-type doped region 140 of trenched side-wall 220 and terminus wall 110.
In general, can be by preparing groove further optional groove knot of the configuration as shown in Fig. 4 A, 4B and 5A, 5B
Structure, to constitute the part that width can be zoomed in or out in specific region.Trench portions formation channel side in these regions
Wall, along perpendicular to groove axially direction, comes so that the whole vertical length of side wall is exposed, makes injection ion penetration side wall
Whole vertical depth, without prepare PCOMP structures configuration when energetic ion injection.Furthermore it is also possible to be carried by preparing
The groove of horizontal complete lattice, configures optional groove structure, comes so that groove keeps exposing, for preparing PCOMP structures
Full vertical depth injection is carried out during configuration, without energetic ion injection.
Although existing preferred embodiment has been described in detail in the present invention, it should be understood that these explanations should not be used as this hair
Bright limitation.The technical staff in field is read after above-mentioned detailed description, and various changes and modifications undoubtedly will be evident.Therefore,
Be considered as appended claims cover the present invention true intention and scope in whole variations and modifications.
Claims (10)
1. a kind of semiconductor power device set in the semiconductor substrate, it is characterised in that it includes：
One formation is in the groove at the top of Semiconductor substrate, and axially extending along groove, wherein groove is also non-linear including one
Part, non-linear partial is included in semiconductor substrate surface along the non-linear channels side not extended with groove in same direction axially
Wall, makes the whole vertical length of non-linear channels side wall expose, directly to receive the doping along the axially inclined injection of groove
Ion, along the whole vertical length of non-linear channels side wall, constitutes wall doping area；And
One channel bottom doped region for being arranged on below trench bottom surfaces, wall doping area is along non-linear channels side wall to downward
Stretch, to touch channel bottom doped region, the top surface of pickup channel bottom doped region to Semiconductor substrate.
2. semiconductor power device as claimed in claim 1, it is characterised in that：The non-linear partial of groove contains including one
Slight curves groove, the slight curves groove includes the trenched side-wall perpendicular to groove axial direction.
3. semiconductor power device as claimed in claim 1, it is characterised in that：The non-linear partial of groove includes ditch geosynclinal concave
Mouthful, each groove recess has the notch part that a groove width reduces, and includes the groove notched side perpendicular to groove axial direction
Wall.
4. semiconductor power device as claimed in claim 1, it is characterised in that：Groove is lined with an insulating barrier, and insulating barrier covers
It is covered with side wall and trench bottom surfaces.
5. semiconductor power device as claimed in claim 1, it is characterised in that：Groove is lined with an insulating barrier, and insulating barrier covers
Side wall and trench bottom surfaces are covered with, wherein, insulating barrier covering side wall is identical with the thickness of trench bottom surfaces.
6. semiconductor power device as claimed in claim 1, it is characterised in that：Groove is lined with an insulating barrier, and insulating barrier covers
Side wall and trench bottom surfaces are covered with, wherein, the thickness of insulating barrier covering side wall is less than the thickness of insulating barrier covering groove bottom surface.
7. semiconductor power device as claimed in claim 1, it is characterised in that：The non-linear partial of configuration trench, is distributed in
Specified location in the whole region of Semiconductor substrate.
8. semiconductor power device as claimed in claim 1, it is characterised in that the device also includes：One high-voltage MOSFET
Device.
9. semiconductor power device as claimed in claim 1, it is characterised in that the device also includes：One high pressure IGBT device
Part.
10. a kind of method for preparing semiconductor power device on a semiconductor substrate, it is characterised in that this method includes：
Side sets a hard mask on a semiconductor substrate, and forms according to predefined groove structure the pattern of hard mask；
By patterned hard mask, etch semiconductor substrates form multiple grooves, edge and semiconductor at the top of Semiconductor substrate
The parallel groove of substrate surface is axially extending, wherein, each groove has a horizontal nonlinearity part, by Semiconductor substrate
Surface along and the non-linear channels side wall that does not extend in the same direction axially of groove constitute, the non-linear channels side wall it is whole
Vertical length, which is exposed, to be come；
Using vertical high energy ion implantation, in trench bottom surfaces channel bottom doped region formed below, hard mask is then removed；
Deposit an insulating barrier, covering groove side wall, and trench bottom surfaces；And
Low energy is axially carried out along groove and tilts injection, to form a side wall along the whole vertical length of non-linear channels side wall
Doped region, wherein, wall doping area is extended downwardly along the whole vertical length of non-linear channels, to touch channel bottom doping
Area, the top surface of pickup channel bottom doped region to Semiconductor substrate.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/892,191 US9887283B2 (en) | 2013-05-10 | 2013-05-10 | Process method and structure for high voltage MOSFETs |
| US13/892,191 | 2013-05-10 | ||
| US14/011,078 | 2013-08-27 | ||
| US14/011,078 US9755052B2 (en) | 2013-05-10 | 2013-08-27 | Process method and structure for high voltage MOSFETS |
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| CN104143572B true CN104143572B (en) | 2017-08-25 |
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| US6800904B2 (en) * | 2002-10-17 | 2004-10-05 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| US7405452B2 (en) * | 2004-02-02 | 2008-07-29 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
| US7078756B2 (en) * | 2004-12-06 | 2006-07-18 | International Business Machines Corporation | Collarless trench DRAM device |
| US7790549B2 (en) * | 2008-08-20 | 2010-09-07 | Alpha & Omega Semiconductor, Ltd | Configurations and methods for manufacturing charge balanced devices |
| KR100871983B1 (en) * | 2007-07-24 | 2008-12-03 | 주식회사 동부하이텍 | Semiconductor memory device and method for fabricating the same |
| US20090166722A1 (en) * | 2007-12-28 | 2009-07-02 | Alpha & Omega Semiconductor, Ltd: | High voltage structures and methods for vertical power devices with improved manufacturability |
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| CN104143572A (en) | 2014-11-12 |
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Effective date of registration: 20200428 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Park Road, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |