TW201442196A - A stacked chip system - Google Patents

Abstract

A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Description

Stacked wafer system

This invention relates to a stacked wafer system, and more particularly to a stacked wafer system using through-via vias.

In order to save valuable layout space or increase the efficiency of interconnects, a plurality of integrated circuit (IC) chips can be stacked together to form an IC package structure. To achieve this, a three-dimensional (3D) stacked package technology can be used to package multiple integrated circuit chips together. Such three-dimensional (3D) stacked package technology is widely used to penetrate through vias (TSVs). A Through Through Hole (TSV) is a vertical conductive via that can extend completely through a wafer, a raft, or a substrate or wafer of any material. Today, 3D integrated circuits (3D ICs) are widely used in many fields such as memory stacking, image sensing wafers, and the like.

Manufacturing a single wafer of integrated circuits typically involves hundreds of steps, and failure of a single step or tiny particles on the wafer can ruin the entire wafer and disable it. Applying 3-D integrated circuit (3D IC) technology to the wafer, as many additional steps are added, the steps that may fail are more numerous, and the situation is only worse than better. Therefore, a solution is needed to increase the fault tolerance of the wafer, thereby increasing the yield of the wafer.

A stacked wafer system includes: a first wafer; a second wafer; a first set of through-via vias (TSV) connecting the first wafer and the second wafer and including at least one first VSS through via, at least a first VDD through the through hole, a plurality of first signals extending through the through hole and at least one first redundant through hole; and a second through through hole (TSV) connecting the first wafer and the second The chip includes at least one second VSS through-hole, at least one second VDD through-hole, a plurality of second signal through-holes and at least one second redundant through-hole, wherein the first group runs through All of the through-holes of the through-hole are defined by at least one through-hole through-hole for selecting the at least one first redundant through-hole and bypassing the remaining through-holes of the first set of through-holes a selection circuit is coupled, and wherein the at least one first redundant through hole and the at least one second redundant through hole are connected by a second selection circuit for allowing the two through holes to be replaced with each other coupling.

1. . . Wafer

2. . . Wafer

500. . . system

600. . . system

The above objects and advantages of the present invention will become more apparent from the written description of the appended claims.

1 shows an overview of a stacked wafer system operating in a normal mode in accordance with an embodiment of the present invention;

2 shows an overview of a stacked wafer system operating in a defect mode in accordance with an embodiment of the present invention;

3 shows a top view of a set of through-via vias (TSVs) in accordance with an embodiment of the present invention;

4 shows an upper schematic view of a wafer including a plurality of through-via vias (TSVs) in accordance with an embodiment of the present invention;

Figure 5 shows an overview of a stacked wafer system in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the preferred embodiments of the present invention will be described in detail, and the components, components, structures, materials, configurations, and the like described herein may be arbitrarily combined into new embodiments without the order of the description or the embodiments. These embodiments are within the scope of the invention. After reading the present invention, it will be apparent to those skilled in the art that the above-described elements, components, structures, materials, configurations, etc. may be modified and retouched without departing from the spirit and scope of the invention. The scope of patent protection is subject to the definition of the scope of the patent application attached to the specification, and such modifications and refinements fall within the scope of the present invention.

The embodiments of the invention and the figures are numerous, and similar elements are denoted by the same or like numerals in order to avoid obscuring. The figures illustrate the concepts and spirit of the present invention, so that the distances, sizes, ratios, shapes, connection relationships, etc. shown in the figures are all illustrative and not actual, all of which can achieve the same function or result in the same manner. Distance, size, proportion, shape, connection relationship, etc. can be regarded as equivalents.

1 shows an overview of a stacked wafer system operating in a normal mode in accordance with an embodiment of the present invention. System 500 includes wafer 1 and wafer 2 stacked together (or may be referred to as a die, if not yet separated from its wafer) and a plurality of through-via vias (TSVs) that electrically couple the two wafers. Through the through hole 11 , through the through hole 12 , through the through hole 13 . . . through the through hole 1 n and through the through hole 1R to form a first set of through through holes, and they are physically embedded in the wafer 1 or wafer 2 in. It should be noted that the first set of through-via vias may include at least one VSS through-via via (one of TSV11-TSV1n), at least one VDD through via via (the other of TSV11-TSV1n), and some signals throughout The through hole (the remaining TSV11-TSV1n) and the at least one redundant through hole (TSV 1R). The VSS through-hole is used to couple the operating voltage VSS (in most cases, VSS is grounded, but in some cases VSS is a potential lower than VDD) to the integrated circuit formed in the wafer 2. (not shown); the VDD through-via is used to couple the positive operating voltage VDD to an integrated circuit (not shown) formed on the wafer 2; and the signal through the via is used to couple the operational signal, such as a clock signal. To an integrated circuit (not shown) formed on the wafer 2. In Figure 1, wafer 1 is the signal input and wafer 2 is the signal output. However, the present invention is not limited thereto, as long as one of the wafer 1 and the wafer 2 is a signal input terminal and the other is a signal output terminal.

The system 500 also includes a plurality of multiplexers in the wafer 1 (the multiplexer 112, the multiplexer 113, the multiplexer 114.., the multiplexer 11n and the multiplexer 11R), and the complex multiplexer in the wafer 2 ( Multiplexer 211, multiplexer 212, multiplexer 213, multiplexer 214... multiplexer 21n and multiplexer 21R), complex buffer in the wafer 1 (buffer 111, buffer 112, buffer The buffers 11 (n-1) and the buffer 11R) and the complex buffers in the wafer 2 (the buffer 212, the buffer 213, the buffer 214, the buffer 21n and the buffer 21R). The through-hole via, the multiplexer and the buffer form a signal path, and the input signals (input 111, input 112, input 113..... input 11n) pass through the wafer interface to become output signals (output 211, output 212, Output 213..... Output 21n). It should be noted that the multiplexer in the wafer 1 and the wafer 2 is controlled by internal or external logic, which is omitted in the present invention in order not to blur the focus. Also, for a two-digit number after a symbol (for example, the TSV in TSV11 is a symbol and 11 is a two-digit number after the symbol), the first digit represents its group and the subsequent digit represents its position/sequence within the group. The last digit starts at 1. The through through hole 1n (TSV 1n) represents the through hole through hole being the nth through hole through hole in the first group through hole; the through hole 1R represents the through hole in the first group through the hole The redundancy in the through holes runs through the through holes. For the three digits after the name (for example, the multiplexer in multiplexer 113 is the name and 113 is the three digits after the name), the first digit represents its wafer, the second digit represents its group, and the last one The number of digits represents its position/sequence within the group; the last digit starts at 1.

Still referring to Figure 1, there is shown the path of the signal (the path is indicated by a thick dashed line) when all of the through-holes are active. The input signal 111 passes through the through hole 11 and the multiplexer 211 to become the output 211; the input 112 passes through the multiplexer 112, passes through the through hole 12 and the multiplexer 212 to become the output 212.....the input 11n passes The multiplexer 11n passes through the through hole 1n and the multiplexer 21n to become the output 21n. In this case, not all of the buffers are used and the multiplexer 11R, the through-hole 1R, and the multiplexer 21R are not used.

Referring now to Figure 2, there is shown an overview of a stacked wafer system operating in a defect mode in accordance with an embodiment of the present invention. In FIG. 2, the through-holes 12 indicated by the large "X" are ineffective (defective and cannot operate normally), so that it is not possible to transmit signals between the wafer 1 and the wafer 2 through the through-holes 12. A multiplexer controlled by internal or external logic will generate a new signal path (represented by a thin dashed line) to bypass the invalid through-hole 12, select the redundant through-hole 1R and re-enter the input The signal is directed to the output location it should arrive at. In this case, the input 111 will still pass through the through hole 11 and the multiplexer 211 as in the normal operation mode, but all other inputs (input 112, input 113.....input 11n) will be "offset" to the wafer 1. The next multiplexer in the middle passes through the next through hole. For example, the input 112 passes through the buffer 112, the multiplexer 113, the through-hole 13, the buffer 213, and the multiplexer 212 to output the component 212; the input 113 passes through the buffer 113, the multiplexer 114, and the through-pass The hole 14, the buffer 214, and the multiplexer 213 and the component output 213..... The input 11n passes through the buffer 11n, the multiplexer 11R, the through hole 1R, the buffer 21R, and the multiplexer 21n, and the component output 212n.

Referring now to Figure 3, there is shown a top plan view of a set of through through vias (TSVs) in accordance with an embodiment of the present invention. The first group of through-holes is a group of a plurality of through-holes. Each set of through vias can form an array (3x3 array in Figure 3) and redundant through vias can be placed in the center of the array. In this case, the through-holes 1i may be through the through-holes 11 and through the through-holes 12 . . . through one of the through holes 18 and may be VSS through through holes, VDD through through holes Or the signal runs through the through hole. Referring to Figures 1-3, this means that n is equal to eight. However, the present invention is not limited thereto, and the array may be larger (having more through-holes such as 4x4, 3x4, . . . ) or smaller (having fewer through-holes, such as 2x2, 2x3, .... As long as each array includes at least one VSS through-via, at least one VDD through-via, at least one signal through-via and at least one redundant through-via.

Referring now to Figure 4, there is shown a top plan view of a wafer comprising a plurality of sets of through-via vias (TSVs) in accordance with an embodiment of the present invention. As shown in FIG. 4, the wafer 1 or wafer 2 may comprise a plurality of sets of through-holes. Although the sets of through-holes have the same size (all groups are 3x3 arrays, having the same number of through-holes), the invention is not limited thereto. Such sets of through-holes may have different sizes (ie, have different numbers of through-holes) as long as they can be laid out in the same wafer without violating design rules or causing manufacturing difficulties.

Reference is now made to Fig. 5, which shows an overview of a stacked wafer system in accordance with another embodiment of the present invention. The system 600 shown in Figure 5 is very similar to the system 500 shown in Figures 1 and 2. Rather than the system 500 utilizing the multiplexer and buffer to connect all of the through-holes in the same group, the system 600 similarly passes all of the redundancy from the different groups through the through-holes (through the first group) The through-holes 1R, the through-holes 2R from the second group, the through-holes 3R from the third group, the through-holes mR from the m-th group are joined together so that they can be replaced with each other.

In accordance with the present invention, the yield of a stacked wafer system can be improved by adding additional redundancy through the vias and adding control logic to one or both of the stacked wafers. In this way, when one of the plurality of through-holes is ineffective, the redundant through-holes can perform their functions so that the entire wafer can still operate normally.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1. . . Wafer

2. . . Wafer

500. . . system

Claims (10)

A stacked wafer system comprising:
First wafer;
Second wafer;
a first set of through-via vias (TSVs) connected between the first die and the second die and including at least one first VSS through via, at least one first VDD through via, and a plurality of first signals a hole and at least one first redundant through hole; and a second set of through holes (TSV) connecting the first die and the second die and including at least one second VSS through hole, at least one The second VDD penetrates the through hole, the plurality of second signals penetrate the through hole and the at least one second redundant through hole,
Wherein the first through-hole through-holes of the first set of through-holes are selected by at least one of the first redundant through-holes and bypassing the remaining through-holes of the first set of through-holes a first selection circuit extending through the through hole, wherein the at least one first redundant through hole and the at least one second through through hole are configured to allow the two through holes to pass each other An alternate second selection circuit is coupled. The stacked wafer system of claim 1, wherein the first set of through-vias forms a first array and the second set of through-vias forms a second array. The stacked wafer system of claim 2, wherein the first array and the second array have the same number or different numbers of through-holes. The stacked wafer system of claim 1, wherein the at least one through-hole of the first through-hole through-hole of the first through-hole is ineffective. The stacked wafer system of claim 1, wherein the first selection circuit includes a first number of 2:1 multiplexers in the first wafer and a second number of 2:1 in the second wafer A multiplexer, wherein the first quantity is different from the second quantity. The stacked wafer system of claim 1, wherein the first selection circuit further comprises a first number of buffers in the first wafer and a second number of buffers in the second wafer, wherein the first A quantity is the same as the second quantity. The stacked wafer system of claim 1, wherein one of the first wafer and the second wafer is a signal input end and the other of the first wafer and the second wafer is a signal output end. For example, the stacked wafer system of claim 1 of the patent scope further includes:
a third group of through-holes (TSVs) connected to the first wafer and the second wafer and including at least one third VSS through-via, at least one third VDD through-via, and a plurality of third signals a hole and at least a third redundant through hole,
The at least one third redundant through via (TSV) is also coupled by a second selection circuit for allowing the plurality of through vias to be coupled to each other. A stacked wafer system according to claim 8 wherein the second selection circuit comprises a plurality of polymorphs in the first wafer and a plurality of multiplexers in the second wafer. A stacked wafer system according to claim 8 wherein the second selection circuit comprises a plurality of buffers in the first wafer and a plurality of buffers in the second wafer.