TW201442082A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

Decrease in the width of a bit line caused resistance to sharply increase. In the present invention, a semiconductor device is equipped with: a common source line; a common bit line; multiple memory cells which are arranged in multiple rows and multiple columns, each of said multiple memory cells being constructed by serially connecting a selection component having first and second control electrodes and a memory component between the common source line and the common bit line; multiple first selection lines, each of said multiple first selection lines being commonly connected to the first control electrode of a respective memory cell which belongs to a corresponding row of the multiple rows; and multiple second selection lines, each of said multiple second selection lines being commonly connected to the second control electrode of a respective memory cell which belongs to a corresponding column of the multiple columns.

Description

Semiconductor device and method of manufacturing same

(about the record of the related application)

The present invention claims priority based on Japanese Patent Application No. 2013-014454 (filed on Jan. 29, 2013) and Japanese Patent Application No. 2013-014455 (filed on Jan. 29, 2013). The entire contents of the description are incorporated herein by reference.

The present invention relates to a semiconductor device, and more particularly to a semiconductor as a semiconductor memory such as a variable resistance semiconductor memory (ReRAM), a layer change semiconductor memory (PRAM), or a magnetically variable semiconductor memory (MRAM). Device.

In a semiconductor device of the prior art, particularly in a ReRAM, a plurality of bit lines having a line shape formed in parallel with each other are formed, and are formed in parallel with each other so as to intersect the bit lines. a linear complex word line, and a memory cell disposed at each intersection of the bit line and the word line, each of the memory cells being a selective transistor having one connected in series And remember based on changes in resistance One of the information elements of the information (for example, refer to Patent Document 1).

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-85003

The disclosure of the above-mentioned patent documents is incorporated herein by reference. The following analysis is performed by the inventor of the present invention.

In the case of using a semiconductor device of the prior art, with further miniaturization, the voltage drop at the bit line is caused by a sharp increase in the thickness of the bit line due to the thinning of the bit line. Increasing, the applied voltage of the bit line is increased, and the place dependence of the memory element electrically connected to the bit line becomes significant (due to the difference in distance from the peripheral circuit to the memory element) The resulting difference in voltage drop becomes significant).

The semiconductor device obtained by the first aspect of the present invention includes: a common source line; and a common bit line; and a plurality of memory cells are plural numbers arranged in a plurality of rows and a plurality of columns memory a cell, and a selection element and a memory element having the first and second control electrodes are connected in series between the common source line and the common bit line; and the first selection line of the plurality is respectively And being connected in common to the first control electrode of each of the memory cells belonging to the row corresponding to the plurality of lines; and the second selection line of the plurality of lines are respectively associated with the plurality of columns belonging to the foregoing plurality The second control electrodes of the respective memory cells corresponding to each other are connected in common.

The semiconductor device obtained by the second aspect of the present invention includes a plurality of memory blocks each having a common bit line and a plurality of memory cells configured to be configured a plurality of memory cells on a plurality of rows and a plurality of columns, and a selection element and a memory element having the first and second control electrodes are connected in series between the common bit line and the reference potential line, respectively And the first selection line of the plural number are respectively connected in common with the first control electrode of each memory cell belonging to the corresponding row in the row of the plural number; and the second selection line of the plural number is respectively The second control electrode is connected in common to each of the memory cells belonging to the corresponding one of the plurality of columns, and the plurality of memory blocks are arranged in a matrix having a plurality of rows and a plurality of columns. The first selection line of the plurality of memory blocks belonging to the memory block arranged on the same row is respectively connected in common, and belongs to the second selection of the plurality of memory blocks arranged in the same column. Lines, as lines are connected in common.

According to a third aspect of the present invention, a semiconductor device includes: a plurality of semiconductor columns arranged in a plurality of rows and a plurality of columns a first region, a channel region, and a second region are stacked in a matrix, and a plurality of first wirings are formed by passing the channel region belonging to the same row among the plurality of semiconductor columns via the first gate Covering the insulating film; and the plurality of second wirings are disposed on the different layers with respect to the plurality of first wirings, and the plurality of semiconductor pillars belong to the same row of the channel regions Covered by the second gate insulating film; and a plurality of memory elements are disposed on the second region and electrically connected to the second region; and the conductor layer is disposed in the plural The memory element is electrically connected in common with the plurality of memory elements of the plurality of memory elements in a plurality of rows and a predetermined range of the plurality of columns.

The semiconductor device according to the fourth aspect of the present invention includes a plurality of semiconductor pillars each including a first region and a second region, and a first region between the first region and the second region 1 and the second channel region; and the plurality of first wires are formed to extend in the first direction, and the semiconductors which are adjacent to the first direction in the plurality of semiconductor columns are arranged side by side The first channel layer of the pillar is covered by the first gate insulating film; and the plurality of second wirings are formed to extend in the second direction, respectively, and are to be included in the plurality of semiconductor pillars The second channel layer of the semiconductor pillars arranged side by side in the second direction is covered by the second gate insulating film; and the conductor layer is commonly connected to the plurality of semiconductors via the information memory. At the aforementioned first region of the column.

A semiconductor device obtained by the fifth aspect of the present invention, The utility model is characterized in that: a conductor plate is provided; and a plurality of memory cells are memory cells arranged in a plurality of rows and a plurality of columns, and respectively include: first and second regions and a semiconductor pillar constituting the first and second channel regions between the first and second regions in series, and an information memory layer interposed between the first region and the conductor plate; and the first plurality The wiring is formed to extend in the row direction, and the first channel layer of the semiconductor pillars which are adjacent to each other in the row direction among the plurality of semiconductor pillars is covered by the first gate insulating film. And the second plurality of wirings are formed to extend in the column direction, and the second channel layer of the semiconductor pillars which are arranged side by side in the column direction among the plurality of semiconductor pillars is passed through 2 gate insulating film for covering.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device, the semiconductor substrate includes an extension in a first direction and a second direction intersecting the first direction. a process of forming a first groove which is arranged side by side at a predetermined interval; and a process of forming a first region which is formed in a layered manner at the semiconductor substrate near the bottom of the first groove; and the semiconductor a second groove which is formed to extend in the second direction and which is spaced apart in the first direction and has a predetermined interval in the first direction, thereby forming a plurality of rows and a plurality of columns a process of forming a semiconductor column in a matrix shape; and forming a first wiring that covers the wall surface of the semiconductor pillar via the first gate insulating film and extending along the second trench; and the first wiring Further above, forming a wall surface of the aforementioned semiconductor pillar a second gate insulating film covering the second wiring extending along the first trench; and a second region forming the upper portion of the semiconductor pillar above the second wiring; and Forming a memory element on the second region; and forming, on the memory element, a conductor layer electrically interconnecting each of the memory elements in a predetermined range of a plurality of rows and a plurality of columns engineering.

According to the present invention, it is possible to prevent the miniaturization of the bit line width due to the miniaturization of the wiring, and it is possible to achieve a low resistance of the bit line.

1‧‧‧Semiconductor device

2‧‧‧ memory cells

3, 3a, 3b‧‧‧1st choice of crystal

4, 4a, 4b‧‧‧2nd choice of crystal

5‧‧‧ memory components

5a‧‧‧resistive change element (memory element)

6‧‧‧Common source line

7‧‧‧Common bit line

7a‧‧‧Common bit line flat section

7b‧‧‧Common bit line wiring department

8, 8a‧‧‧ line word line (1st word line)

8b‧‧‧ line character line (other 1st character line)

9, 9a‧‧‧ column word line (2nd word line)

9b‧‧‧ column line (other 2nd character line)

11‧‧‧ Memory Cell Array

11a‧‧‧ memory cell unit

12‧‧‧ line decoder

13, 13a, 13b‧‧‧ row selector

14‧‧‧ column decoder

[figure 1]

It is a circuit diagram schematically showing the configuration of a memory cell in the semiconductor device according to the first embodiment of the present invention.

[figure 2]

It is a block diagram schematically showing the circuit configuration of the semiconductor device according to the first embodiment of the present invention.

[image 3]

It is a circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to the first embodiment of the present invention.

[Figure 4]

It is a partial plan view schematically showing the configuration of the memory cell array and the peripheral circuits in the semiconductor device according to the first embodiment of the present invention.

[Figure 5]

It is a perspective view schematically showing the configuration of a part of the memory cell unit in the semiconductor device according to the first embodiment of the present invention.

[Figure 6]

A circuit diagram for schematically showing the configuration of a memory cell in the semiconductor device according to the second embodiment of the present invention.

[Figure 7]

It is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to the second embodiment of the present invention.

[Figure 8]

It is a partial cross-sectional view between X-X' and Y-Y' which schematically shows the configuration of the memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Figure 9]

It is a partial cross-sectional view between X-X' and Y-Y' which is schematically shown in the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 10]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 9 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Figure 11]

It is a partial cross-sectional view taken between X-X' and Y-Y' of Fig. 10 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 12]

It is a partial cross-sectional view taken between X-X' and Y-Y' of Fig. 11 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 13]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 12, which schematically shows a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 14]

It is a partial cross-sectional view taken between X-X' and Y-Y' of Fig. 13 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 15]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 14 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 16]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 15 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 17]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 16 which is schematically shown in the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 18]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 17 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 19]

It is a partial cross-sectional view taken between X-X' and Y-Y' of Fig. 18 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 20]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 19, which schematically shows a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.

[Fig. 21]

A circuit diagram for schematically showing the configuration of a memory cell in the semiconductor device according to the fourth embodiment of the present invention.

[Fig. 22]

It is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to the fourth embodiment of the present invention.

[Fig. 23]

Is a note in the semiconductor device of the fifth embodiment of the present invention. Recall the composition of the body cell as a circuit diagram of the mode display.

[Fig. 24]

It is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to the fifth embodiment of the present invention.

[Fig. 25]

It is a partial cross-sectional view between X-X' and Y-Y' which schematically shows the configuration of the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 26]

It is a partial cross-sectional view between X-X' and Y-Y' which is schematically shown in the method of manufacturing a memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 27]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 26, which is a schematic representation of a method of manufacturing a memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 28]

It is a partial cross-sectional view taken between X-X' and Y-Y' of Fig. 27 schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 29]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 28, which is a schematic representation of a method of manufacturing a memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 30]

It is a partial cross-sectional view taken along line X-X' and Y-Y' of Fig. 29, which schematically shows a method of manufacturing a memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

[Fig. 31]

It is a partial cross-sectional view taken along line Z-Z' of Fig. 32 which schematically shows the configuration of the memory cell array in the semiconductor device of the seventh embodiment of the present invention.

[Fig. 32]

It is a partial plan view schematically showing the configuration of the memory cell array in the semiconductor device of the seventh embodiment of the present invention.

[Fig. 33]

It is a partial cross-sectional view between Z-Z' of Fig. 34 which is a schematic representation of the constitution of the memory cell array in the semiconductor device of the comparative example.

[Fig. 34]

It is a partial plan view schematically showing the constitution of the memory cell array in the semiconductor device of the comparative example.

[Fig. 35]

The formation voltage at the variable resistance film in the semiconductor device according to the seventh embodiment of the present invention is compared with a comparative example.

(Embodiment 1)

The semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram schematically showing the configuration of a memory cell in the semiconductor device according to the first embodiment of the present invention.

The semiconductor device of the first embodiment is a semiconductor memory device (semiconductor memory) capable of storing information in a circuit composed of a semiconductor element. The semiconductor device is provided with a memory cell 2 as shown in FIG. The memory cell 2 is provided with a memory element 5 connected in series and a selection element having two control electrodes. In the present embodiment, the selection element is constituted by two transistors. In other words, between the common source line 6 and the common bit line 7 (BL_k), the first selection transistor 3 and the second selection transistor 4 are sequentially arranged from the common source line 6 side. The memory elements 5 are constructed in series. The memory cell 2 is arranged in a matrix of a plurality of rows and a plurality of columns in a memory cell array (11 of FIG. 3).

The first selection transistor 3 is a transistor for selecting the corresponding memory element 5. At the first selection transistor 3, for example, a field effect of a single gate type in which an electric field is generated at a channel to control a current between a source terminal and a gate terminal by applying a voltage to a gate electrode can be used. Transistor. The first selection transistor 3 is electrically connected to the row word line 8 (RWL_m) as the first selection line at the gate electrode as the control electrode, and is common to the source terminal. The source line 6 is electrically connected and electrically connected to the source terminal of the second selection transistor 4 at the gate terminal. The first selection of the transistor 3 can also constitute In order to be disposed in parallel between the common source line 6 and the second selection transistor 4, the parallel gate electrodes are connected to the same row word line 8.

The second selection transistor 4 is a transistor for selecting the corresponding memory element 5. At the second selection transistor 4, for example, a single gate type field effect transistor can be used. The second selection transistor 4 is electrically connected to the column word line 9 (CWL_n) as the second selection line at the gate electrode as the control electrode, and is electrically connected to the source terminal. 1 Selecting the 汲 terminal of the transistor 3 for electrical connection, and being electrically connected to the input terminal of the memory element 5 at the 汲 terminal. The second selection transistor 4 may be configured to be disposed in parallel between the first selection transistor 3 and the memory element 5, and the parallel gate electrodes are connected to the same column word line 8.

The memory element 5 is an information memory that memorizes information of 0 or 1 (High or Low). In the memory element 5, for example, a resistance change element capable of changing a resistance value of the resistance change film by applying a voltage to a resistance change film disposed between the electrodes can be used, by being A capacitor or the like which is capable of changing a charge accumulation amount at the capacity insulating film by applying a voltage between the electrodes and allowing a current to flow. The memory element 5 is electrically connected to the first terminal of the second selective transistor 4 at the input terminal, and is electrically connected to the common bit line 7 (BL-k) at the output terminal. In addition, the memory element 5 is separately provided at each memory cell 2, but if it is used as a resistance change element, it does not electrically connect with the adjacent memory cell 2. The toucher may be configured to be connected in a line shape in the row direction or the column direction, or may be configured to be connected in a flat shape in the row direction and the column direction.

The common source line 6 is a wiring for supplying a common reference potential to each of the memory cells 2. The common source line 6 is electrically connected to a power supply circuit (not shown) that outputs a reference potential.

The common bit line 7 (BL_k) is a bit that is electrically connected to at least the memory cell 2 (which may also be connected to all of the memory cells 2) in a matrix of a plurality of rows and a plurality of columns. line. The common bit line 7 is provided in a flat plate shape in such a manner that at least a plurality of memory cells 2 arranged in a matrix of a plurality of rows and a plurality of columns are covered in a batch. The common bit line 7 is electrically connected to the sense amplifier (18 of FIG. 2) and the write amplifier (17 of FIG. 2) via the multiplexer (19 of FIG. 2) or directly. .

The line word line 8 (RWL_m, m+1) is a word line (selection line) for selecting each memory cell 2 belonging to the same row. The line word line 8 is electrically connected in common to the gate electrodes of the first selection transistor 3 of the respective memory cells 2 belonging to the same row. The row word line 8 is electrically connected to the row selector (13 of Fig. 2), and one of RWL_m, m+1 is selected by the row selector.

The column word line 9 (CWL_n, n+1) is a word line (selection line) for selecting each memory cell 2 belonging to the same column. Column character line 9, is the memory of the same column The gate electrode of the second selective transistor 4 of the cell 2 is electrically connected in common. The column word line 9 is electrically connected to the column selector (20 of Fig. 2), and one of CWL_n, n+1 is selected by the column selector.

Next, the circuit configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a block diagram showing a schematic configuration of a circuit configuration of a semiconductor device according to Embodiment 1 of the present invention. Fig. 3 is a partial circuit diagram showing a schematic configuration of a memory cell array in the semiconductor device according to the first embodiment of the present invention.

The general memory cell 2 of Fig. 1 can be used in the circuit configuration of the semiconductor device 1 of Fig. 2 in general. The semiconductor device 1 includes a memory circuit and a peripheral circuit provided at the periphery of the memory circuit. The semiconductor device 1 is a memory circuit, and includes a memory cell array 11 that is divided into a plurality of banks 0 to 1, and a row decoder 12, a row selector 13, and a column decoder that are attached to each bank 0 to 1. 14. Data register 15, decision circuit 16, write amplifier 17, sense amplifier 18, multiplexer 19, and column selector 20. Further, the semiconductor device 1 is provided as a peripheral circuit, and includes a row address buffer 21, an array control circuit 22, and a phase counter 23, and a control logic circuit 24, an instruction register 25, and a state register. 26. A control signal input circuit 27, an input/output control circuit 28, an address register 29, a column address buffer 30, and a transistor 31. Further, in the example of Fig. 2, although two banks 0 to 1 are provided, the number of banks is not particularly limited. Further, although not shown, the external power supply voltages VDD and VSS are supplied from the outside in the semiconductor device.

The memory cell array 11 is a circuit in which a plurality of memory cells 2 (MC) are arranged in a matrix of a plurality of rows and a plurality of columns (refer to FIG. 2). The memory cell array 11 is provided with a column word line 9 (CWL_n), and a line word line 8 (RWL_m), and a memory cell 2 (MC), and a common bit line 7 (BL_k), and a common source. Polar line 6. Column word lines 9 (CWL_n) are arranged to extend side by side and are arranged side by side in the other direction (the direction of the right angle of one direction). Each column of word lines 9 (CWL_n) is electrically connected to column selector 20. The line word line 8 (RWL_m) is extended in the other direction and arranged side by side in one of the directions. Each row of word lines 8 (RWL_m) is electrically connected to the row selector 13. The memory cell 2 (MC) is disposed in the vicinity (may also be an intersection) of each intersection of the column word line 9 (CWL_n) and the line word line 8 (RWL_m). The memory cell 2 (MC) is electrically connected to the corresponding column word line 9 (CWL_n), row word line 8 (RWL_m), common bit line 7 (BL_k), and common source line 6. . The common bit line 7 (BL_k) is electrically connected in common with the memory cell 2 (MC) located within a predetermined range of the complex row and the complex column. Each common bit line 7 (BL_k) is electrically connected to the multiplexer 19. The common source line 6 supplies a common reference potential to each memory cell 2 (MC). The details of the memory cell array 11 will be described later.

The row decoder 12 is a circuit for decoding signals (arranged line word line selection signals, row addresses) from the array control circuit 22 and the row address buffer 21. Row decoder 12 The decoded signal (row address) is output toward the line selector 13.

The row selector 13 is based on the row address from the row decoder 12 (corresponding to XA(m), XA(m+1) of FIG. 4), and the row character line corresponding to the address. 8 (RWL_m) is activated and the circuit of the row address in the memory cell array 11 is selected via the row word line 8 (RWL_m).

Column decoder 14 is a circuit that decodes signals from array control circuit 22 and column address buffer 30 (encoded column word line select signals, column addresses). The column decoder 14 outputs the decoded signal (column address) toward the column selector 20. Further, the column decoder 14 outputs a signal (area address) for selecting the common bit line 7 corresponding to the column address toward the multiplexer 19.

The data register 15 is a register for holding data. The data register 15 exchanges data between it and the input/output control circuit 28. The data register 15 holds data from the input/output control circuit 28 or the sense amplifier 18. The data register 15 outputs the held data toward the write amplifier 17 based on the signal from the array control circuit 22 when writing. The data register 15 outputs the held data toward the input/output control circuit 28 based on the signal from the array control circuit 22 when reading.

The decision circuit 16 determines whether the transmission is based on the signal from the array control circuit 22 by comparing the written data at the write amplifier 17 with the read data at the sense amplifier 18. Failed (VERIFY action) circuit. The determination circuit 16 performs a rewriting of the memory cell array 11 and repeats the rewriting and reading of the memory cell array 11 until all the memory cells 2 (MC) pass through. until.

The write amplifier 17 is a circuit that amplifies the potential of the data from the data register 15 based on the signal from the array control circuit 22. The write amplifier 17 outputs the potential amplified data to the memory cell array 11 via the multiplexer 19 and the selected common bit line 7 (BL_k).

The sense amplifier 18 is read from the memory cell array 11 via the selected common bit line 7 (BL_k) and the multiplexer 19 based on the signal from the array control circuit 22. The potential of the data is amplified. The sense amplifier 18 outputs the data for potential amplification toward the data register 15 and the decision circuit 16.

The multiplexer 19 selects a memory via the common bit line 7 (BL_k) based on the region address from the column decoder 14 (corresponding to YA2(k), YA2(k+1) of FIG. 4). A circuit of a block address in the cell array 11. Each multiplexer 19 is electrically connected to the write amplifier 17 and the sense amplifier 18.

The column selector 20 is based on the column address from the column decoder 14 (corresponding to YA1(n), YA1(n+1) of FIG. 4), and the corresponding column word line 9 (CWL_n). The circuit is activated and the column address in the memory cell array 11 is selected via the column word line 9 (CWL_n).

The row address buffer 21 is a buffer for holding the row address in the address from the address register 29. The row address buffer 21 outputs the held row address toward the row decoder 12.

The array control circuit 22 is based on the signals from the control logic circuit 24 and the phase counter 23 for the row decoder 12, the column decoder 14, the data register 15, the decision circuit 16, the write amplifier 17, and the sense. A circuit that controls the individual actions of amplifier 18 to control. The array control circuit 22 supplies the row word line selection signal to the row decoder 12, and supplies the column word line selection signal to the column decoder 14, and supplies the data corresponding to the data register 15, the sense amplifier 18, and the write. Various control signals of the amplifier 17 and the decision circuit 16.

The phase counter 23 is a counter for controlling the phase of the access object.

The control logic circuit 24 is a logic circuit that outputs various control signals toward the peripheral circuits. The control logic circuit 24 outputs various control signals toward the array control circuit 22, the state register 26, and the transistor 31 based on signals from the control signal input circuit 27 and the instruction register 25. Control logic circuit 24 performs the exchange of signals between it and array control circuit 22.

The instruction register 25 is a register for holding instructions from the input/output control circuit 28. The instruction register 25 outputs the held command toward the control logic circuit 24.

The state register 26 is a register that holds the state (signal) from the control logic circuit 24. Status register 26, is The held state signal is output toward the input/output control circuit 28. Here, the status is information indicating a state of writing, failure, or the like.

The control signal input circuit 27 is input with an instruction (wafer enable/CE, instruction latch enable CLE, address latch enable ALE, write enable/WE, read enable/RE, /WP). ) The circuit.

Here, /CE is a device selection signal. For example, if it is set to High in the read state, it is in the standby mode.

Further, CLE is a signal for controlling the import of an instruction into the instruction register 25 inside the device. By setting CLE to the High level when the /WE is raised and down, the data on the I/O terminals (I/O_0~7) is introduced into the instruction register 25 as an instruction.

Further, the ALE is a signal for controlling the event in the address register 29 and the data register 15 for importing data into the device. By setting ALE to the High level when the /WE is raised and down, the data on the I/O terminals (I/O_0~7) is imported into the address register 29 as the address data. . Further, by setting ALE to the Low level, the data on the I/O terminals (I/O_0~7) is introduced into the data register 15 as input data.

Further, /WE is a write signal for importing data from the I/O terminals (I/O_0~7) into the device.

Also, /RE is a signal for outputting data (sequence output).

Moreover, /WP is a control signal for protecting data by prohibiting writing and erasing operations. Normally, it is set to /WP=High, and is set to /WP=Low when the power supply is turned off.

The input/output control circuit 28 is a circuit for controlling the input and output of instructions, addresses, and data. The input/output control circuit 28 exchanges commands, addresses, and data via I/O terminals (I/O_0~7) for the outside. The input/output control circuit 28 outputs the input command to the command register 25. The input/output control circuit 28 outputs the input address address to the address register 29. The input/output control circuit 28 exchanges data between it and the data register 15. The input/output control circuit 28 controls the input and output of the command, the address, and the data based on the signals from the control signal input circuit 27 and the state register 26.

Here, I/O_0~7 is a terminal (埠) for inputting and outputting address, command, and data.

The address register 29 is a register that holds the address from the input/output control circuit 28. The address register 29 outputs the row address in the held address toward the row address buffer 21. The address register 29 outputs the column address in the held address toward the column address buffer 30.

The column address buffer 30 is a buffer for holding the column address in the address from the address register 29. At the column address buffer 30, the held column address is output toward the column decoder 14.

The transistor 31 is formed by an open drain nMOS transistor. The gate electrode of the transistor 31 is electrically connected to the control logic circuit 24. The source terminal of the transistor 31 is electrically connected to the ground. The 汲 terminal of the transistor 31 is electrically connected to the output terminal of the internal state notification signal RY/BY. The gate electrode of the transistor 31 is set to a High potential during the operation of programming, erasing, and reading operations. The gate of the transistor 31 is turned on and becomes RY/BY=Low(Busy). If the operation is completed, it is set to the Low potential, and the RY/BY is pulled up. To the power supply potential, and become RY / BY = High (Ready).

Here, RY/BY is a signal for notifying the internal state of the device to the outside.

Next, a detailed configuration of the memory cell array in the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Fig. 3 is a circuit diagram schematically showing the configuration of a memory cell unit in the semiconductor device according to the first embodiment of the present invention. Fig. 4 is a partial plan view schematically showing the configuration of a memory cell array and peripheral circuits in the semiconductor device according to the first embodiment of the present invention. Fig. 5 is a perspective view schematically showing a configuration of a part of a memory cell unit in the semiconductor device according to the first embodiment of the present invention.

The memory cell unit 11a shown in FIG. 3 is a part of a memory cell array (11 of FIG. 2), and is a memory cell to be connected to one common bit line BL_0. 2 (2 of Fig. 1) is an example of 16 (4 bits × 4 bits, 4 rows and 4 columns). The memory cell unit 11a is provided with an extension present in one of the directions The parallel line character lines 8 (RWL_0~3) which are arranged side by side and in the other direction (the direction of the right angle of one direction), and the plurality of lines extending in the other direction and side by side in one side The word line 9 (CWL_0~3) and the complex number set at each intersection of the line word line 8 (RWL_0~3) and the column word line 9 (CWL_0~3) (which may also be near the intersection) The memory cell 2, and a common bit line 7 (BL_0) electrically connected to the memory cell 2 (MC) in the range of 4 rows and 4 columns, and for each memory cell 2 (MC) supplies a common source line 6 of a common reference potential.

If the general memory cell unit 11a shown in FIG. 3 is arranged in a matrix of 4 rows and 4 columns, it can be configured as a general plane (16 bits x 16 bits) as shown in FIG. Memory cell array 11. The plurality of line character lines 8 belonging to the memory unit 11a arranged on the same column are connected in common. The plurality of column word lines 9 belonging to the memory cells 11a arranged on the same row are connected in common. Around the memory cell array 11, in FIG. 4, the even-numbered row selectors 13a (RWL_m) for the row address are arranged on the right side, and the row address is configured on the left side. An odd number of row selectors 13b (RWL_m+1) are selected, and the column selectors 20a (CWL_n) and the multiplexer 19a (BL_k) are arranged at the upper side with the column address and the region address. And at the lower side, the column address and the odd-numbered column selector 20b (CWL_n+1) and the multiplexer 19b (BL_k+1) of the region address are arranged.

Row selector 13a (RWL_m) and row selector 13b (RWL_m+1) corresponds to the row selector 13 of FIG. The row selector 13a (RWL_m) is electrically connected to the even-numbered RWL_0, 2, 4, 6, 8, 10, 12, 14 of the plurality of row line lines 8 which are arranged side by side in the other direction. . The row selector 13a (RWL_m) selects the corresponding row word line by inputting an even number of signals (XA(m)) of the row address from the row decoder 12 of FIG. 8. The row selector 13b (RWL_m+1) is electrically powered by the odd-numbered RWL_1, 3, 5, 7, 9, 11, 13, 15 in the line word line 8 of the plurality of side-by-side parallel lines. Sexual connection. The row selector 13b (RWL_m+1) selects the corresponding signal by the odd-numbered signal (XA(m+1)) to which the row address from the row decoder 12 of FIG. 2 is input. Line word line 8.

Column selector 20a (CWL_n) and column selector 20b (CWL_n+1) correspond to column selector 20 of FIG. The column selector 20a (CWL_n) is electrically connected to the even-numbered CWL_0, 2, 4, 6, 8, 10, 12, 14 of the plurality of column word lines 9 side by side. . The column selector 20a (CWL_m) selects the corresponding column word line by inputting an even number of signals (YA1(n)) of the column address from the decoder 14 of FIG. 9. The column selector 20b (CWL_n+1) is electrically powered by the odd-numbered CWL_1, 3, 5, 7, 9, 11, 13, 15 in the plurality of column word lines 9 side by side. Sexual connection. The column selector 20b (CWL_n+1) is selected by the odd-numbered signals (YA1(n+1)) to which the column address from the decoder 14 of FIG. 2 is input. Corresponding column word line 9.

The multiplexer 19a (BL_k) and the multiplexer 19b (BL_k+1) correspond to the multiplexer 19 of FIG. The multiplexer 19a (BL_k) is the same as the even number of BL_0, 2 in the common bit line flat portion 7a of the predetermined area address via the corresponding common bit line wiring portion 7b as shown in FIG. , 4, 6, 8, 10, 12, 14 for electrical connection. The multiplexer 19a (BL_k) selects the corresponding common bit line by inputting an even number of signals (YA2(k)) of the area address from the decoder 14 of FIG. Flat plate portion 7a. The multiplexer 19b (BL_k+1) is the odd-numbered BL_1 of the common bit line flat portion 7a that is defined with the area address via the corresponding common bit line wiring portion 7b as shown in FIG. , 3, 5, 7, 9, 11, 13, 15 for electrical connection. The multiplexer 19b (BL_k+1) is selected by the odd-numbered signals (YA2(k+1)) to which the address of the region from the decoder 14 of FIG. 2 is input. The bit line flat portion 7a is common.

The common bit line flat portion 7a and the common bit line wiring portion 7b correspond to the common bit line 7 of FIG. The common bit line flat portion 7a is a flat portion that covers a plurality of memory cells 2 in the memory cell unit 11 in a batch. The common bit line wiring portion 7b electrically connects the corresponding common bit line flat portion 7a and the multiplexer 19a or 19b. The common bit line flat portion 7a and the common bit line wiring portion 7b are connected to the write amplifier 17 and the sense amplifier 18 of FIG. 2 via the global bit line GBL. In addition, the common bit line flat portion 7a belonging to the plurality of memory cells 11a is independent of each other in FIG. However, it is also possible to make a common configuration without using the multiplexers 19a and 19b.

If a part of the memory cell unit 11a of FIG. 4 is displayed in a three-dimensional manner, it can be configured as shown in FIG. In the memory cell unit 11a of FIG. 5, a common bit line flat portion 7a is disposed on the common source line 6 with a space therebetween, and the common source line 6 and the common bit line flat portion 7a are disposed. The first selection transistor 3, the second selection transistor 4, and the variable resistance element 5a are connected in series from the common source line 6 side in this order. The first selection transistor 3 and the second selection transistor 4 are arranged in a matrix in the row direction and the column direction. The variable resistance element 5a is corresponding to the memory element 5 of FIG. 4, and is connected to each of the second selection transistors 4 located in the region of the common bit line flat portion 7a, and is connected to the common bit line plate. The portions 7a are connected in such a manner as to overlap each other. The plurality of first selection transistors 3 arranged on the same row are connected to the common line word line 8. The plurality of second selection transistors 4 arranged on the same column are connected to the common column word line 9. The common bit line flat portion 7a is connected to the common bit line wiring portion 7b.

At the memory cell array 11 of the above-described general semiconductor device 1, the memory cell 2 which is selected as the intersection of the row address and the column address is selected, and the selected memory cell 2 is selected here. At the same time, information can be memorized by whether or not a current flows between the common source line 6 and the common bit line 7.

According to the first embodiment, by making the common bit line 7 The common connection of the memory cells 2 at the plurality of memory cell units 11a prevents the miniaturization of the bit line width caused by the miniaturization of the wiring, and becomes capable of achieving the bit line. Low resistance. Further, by using the memory element 5 as a structure in which the variable resistance element is not electrically connected to the adjacent memory cell 2 and is connected in a line shape or a flat shape, it can be reduced. The etching damage of the memory element 5 can be helpful for the improvement of the yield.

(Embodiment 2)

A semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. Fig. 6 is a circuit diagram schematically showing the configuration of a memory cell in the semiconductor device according to the second embodiment of the present invention. Fig. 7 is a partial circuit diagram showing a schematic configuration of a memory cell unit in the semiconductor device according to the second embodiment of the present invention.

The second embodiment is a modification of the first embodiment, and is a selection element that is connected in series with the memory element 5 and has two control electrodes, instead of using the first selection of two single gate types as shown in FIG. The transistor 3 and the second selection transistor 4 are connected in series, and are configured to use one double gate type selection transistor 33.

The double gate type selection transistor 33 is a field effect transistor having two gate electrodes 33a and 33b as control electrodes on a channel between the source terminal and the gate terminal (refer to FIG. 6). The double gate type selection transistor 33 is electrically connected to the row word line 8 (RWL_m) at the gate electrode 33a, and is connected to the column word at the gate electrode 33b. The wire 9 (CWL_n) is electrically connected, and is electrically connected to the common source line 6 at the source terminal, and electrically connected to the input terminal of the memory element 5 at the terminal. The double gate type selection transistor 33 may be configured to be disposed in parallel between the common source line 6 and the memory element 5, and the parallel gate electrodes 33a are connected to the same row word line 8 in parallel. The gate electrode 33b is connected to the same column word line 9.

Further, the line word line 8 is electrically connected in common to the gate electrode 33a of the double gate type selection transistor 33 of each of the memory cells 2 arranged in the row direction (refer to FIG. 7). Further, the column word line 9 is electrically connected in common to the gate electrode 33b of the double gate type selection transistor 33 of each of the memory cells 2 arranged in the column direction (refer to FIG. 7).

The other configuration is the same as that of the first embodiment.

According to the second embodiment, the same effects as those of the first embodiment can be obtained, and the structure of the memory cell can be simplified as compared with the first embodiment.

(Embodiment 3)

A semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. Fig. 6 is a partial cross-sectional view showing the relationship between X-X' and Y-Y' schematically showing the configuration of the memory cell array in the semiconductor device according to the third embodiment of the present invention.

The semiconductor device of the third embodiment is an example of a structure equivalent to the circuit of the second embodiment. The semiconductor device is provided in a trench formed at the semiconductor substrate 41 (for example, a P-type germanium substrate) An element isolation region 42 (for example, a tantalum oxide film) having an insulator or the like is buried. At a predetermined position on the semiconductor substrate 41, a diffusion region 43 (for example, an N-type impurity diffusion region) having a predetermined depth is formed. The diffusion region 43 is a part of a common source line (corresponding to symbol 6 in FIGS. 6 and 7). At a predetermined position on the semiconductor substrate 41 including the semiconductor pillar 82 and the diffusion region 43, a mask insulating film 44 (for example, a tantalum nitride film) is formed. On the semiconductor substrate 41 including the diffusion region 43 and the mask insulating film 44, a groove 45 extending in the column direction and juxtaposed in the row direction at a predetermined depth is formed. Further, on the semiconductor substrate 41 including the diffusion region 43, a groove 48 extending in the row direction and juxtaposed in the column direction is formed. The groove 45 and the groove 48 intersect each other, and the grooves 45 and 48 are combined in a planar shape to have a mesh shape. The grooves 45 and the grooves 48 are of the same degree (including the same).

A columnar semiconductor pillar 82 (P-type germanium) derived from the semiconductor substrate 41 is provided in a portion (mesh portion) surrounded by the trenches 45 and 48. The semiconductor pillar 82 is provided with a channel region 82a between the diffusion region 46 and the diffusion region 60 at the double gate type selection transistor (corresponding to reference numeral 33 in FIGS. 6 and 7). The semiconductor pillars 82 are arranged in a matrix of a plurality of rows and a plurality of columns. The semiconductor substrate 41 is formed with a diffusion region 46 (for example, an N + -type impurity diffusion region) which is formed in a layered manner in the vicinity of the bottom of the trenches 45 and 48 or in the vicinity of the base of the semiconductor pillar 82. The diffusion region 46 is disposed below the gate electrodes 51a, 51b, and 51c. Diffusion region 46, tie and diffusion region 43 Make a connection. The diffusion region 46 is a source terminal of a double gate type selection transistor (corresponding to symbol 33 of FIGS. 6 and 7), and is a part of a common source line (corresponding to symbol 6 of FIGS. 6 and 7). . At the upper portion of the semiconductor pillar 82, a diffusion region 60 (for example, an N+ type impurity diffusion region) is formed. The diffusion region 60 is disposed above the gate electrodes 56a, 56b, and 56c. The diffusion region 60 is connected to the contact plug 61. The diffusion region 60 is a 汲 terminal of a double gate type selection transistor (corresponding to symbol 33 of FIGS. 6 and 7).

In the trench 45, an insulating film 47 (for example, a laminated film of a tantalum oxide film/germanium nitride film/germanium oxide film) and an insulating film 54 (for example, tantalum nitride) are buried in this order from the bottom. A laminated film of a film/tantalum oxide film), gate electrodes 56a, 56b, and 56c (for example, titanium nitride) and an insulating film 58 (for example, a laminated film of a tantalum nitride film/tantalum oxide film). In the layer of the trench 45 where the gate electrodes 56a, 56b, 56c are formed, the semiconductor pillars 82 on both sides of the wall surface of the trench 45 are interposed, and a gate insulating film 55 (for example, a tantalum oxide film) is interposed. The gate electrodes 56a, 56b, and 56c are formed on the ground, and the gate electrodes 56a, 56b, and 56c are separated into two, and between the gate electrodes of either of the gate electrodes 56a, 56b, and 56c. An insulating film 57 (for example, a laminated film of a tantalum nitride film/tantalum oxide film) is buried. The layer in which the gate electrodes 56a, 56b, and 56c are formed is disposed at a layer higher than the layer on which the gate electrodes 51a, 51b, and 51c are formed. The gate electrodes 56a and 56b are gate electrodes arranged in a normal cell region 84 used as a normal memory cell 2. The gate electrodes 56a and 56b are double-gate type selection transistors (corresponding to the symbols of Figs. 6 and 7). The second gate electrode of No. 33) (symbol 33b of Figs. 6 and 7) is also used as a column word line (corresponding to symbol 9 in Figs. 6 and 7). A pair of gate electrodes 56a on both sides of the semiconductor post 82 are connected to each other as a common word line. A pair of gate electrodes 56b on both sides of the adjacent semiconductor pillars adjacent to the semiconductor pillars 82 are also common column word lines (different from the column word lines common to the gate electrodes 56a), And at the same time action. The gate electrode 56c is a gate electrode disposed at the dummy cell region 83 which is not used as the normal memory cell 2.

In the trench 48, an insulating film 49 (for example, a laminated film of a tantalum nitride film/tantalum oxide film) and gate electrodes 51a, 51b, 51c (for example, nitrided) are sequentially buried from the bottom. Titanium), an insulating film 53 (for example, a laminated film of a tantalum nitride film/tantalum oxide film). In the layer of the trench 48 where the gate electrodes 51a, 51b, 51c are formed, the semiconductor pillars 82 on both sides of the wall surface of the trench 45 are interposed via the gate insulating film 50 (for example, a tantalum oxide film). The gate electrodes 51a, 51b, and 51c are formed on the ground, and the gate electrodes 51a, 51b, and 51c are separated into two, and between the gate electrodes of any one of the gate electrodes 51a, 51b, and 51c. An insulating film 52 (for example, a laminated film of a tantalum nitride film/tantalum oxide film) is buried. The layer in which the gate electrodes 51a, 51b, and 51c are formed is disposed at a layer lower than the layer on which the gate electrodes 56a, 56b, and 56c are formed. The gate electrodes 51a, 51b, 51c and the gate electrodes 56a, 56b, 56c are three-dimensionally intersected each other. The gate electrodes 51a and 51b are gate electrodes arranged in a normal cell region 84 used as a normal memory cell 2. The gate electrodes 51a and 51b are double gate type selection transistors (corresponding to FIG. 6 and FIG. 7). The first gate electrode (symbol 33a in Fig. 6 and Fig. 7) of symbol 33) is also used as a line word line (corresponding to symbol 8 in Figs. 6 and 7). A pair of gate electrodes 51a on both sides of the semiconductor post 82 are connected to each other as a common line of word lines. A pair of gate electrodes 51b on both sides of the adjacent semiconductor pillars adjacent to the semiconductor pillar 82 are also common row word lines (different from the common word line used for the gate electrode 51a), And at the same time action. The gate electrode 51c is a gate electrode disposed at the dummy cell region 83 which is not used as the normal memory cell 2.

A contact plug 61 (for example, DOPOD, doped polysilicon) is buried in the hole 59 of the diffusion region 60 in the region surrounded by the insulating films 53, 58. A mask insulating film 62 (for example, a tantalum nitride film) is formed at a predetermined region on the mask insulating film 44 including the insulating films 53, 58. On the semiconductor substrate 41 including the mask insulating film 62, the mask insulating film 44, the diffusion region 43, and the element isolation region 42, a cover insulating film 63 (for example, a tantalum oxide film/germanium nitride film layer) is formed. Accumulation). On the cover insulating film 63, interlayer insulating films 64 and 65 are formed (for example, a tantalum oxide film, and the interlayer insulating films 64 and 65 may be integrated).

Holes 66a passing through the diffusion region 43 are formed on the interlayer insulating films 65, 64 and the cover insulating film 63. In the hole 66a, a contact plug 67a (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 67a is a part of a common source line (corresponding to the symbol 6 of FIGS. 6 and 7). On the interlayer insulating films 65, 64, the cover insulating film 63, and the insulating film 58, gate electrodes 56a, 56b are formed. Each of them individually passes through the hole 66b. In the hole 66b, a contact plug 67b (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 67b is a part of a column word line (corresponding to the symbol 9 of FIGS. 6 and 7). In the interlayer insulating films 65 and 64, the cover insulating film 63, the mask insulating film 62, the mask insulating film 44, and the insulating film 53, holes 66c through which the gate electrodes 51a and 51b are individually passed are formed. . In the hole 66c, a contact plug 67c (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 67c is a part of a line word line (corresponding to the symbol 8 of FIGS. 6 and 7).

A mask insulating film 68 (for example, a tantalum nitride film) is formed on the interlayer insulating film 65. On the mask insulating film 68, the interlayer insulating films 65, 64, the cover insulating film 63, and the mask insulating film 62, a hole 69 through which the contact plug 61 passes is formed. In the hole 69, a contact plug 70 (for example, a laminated film of titanium/titanium nitride) is buried. The contact plug 70 is a lower electrode of the variable resistance element 5a (memory element).

At a predetermined region on the mask insulating film 68 including the contact plugs 70, a resistance change film 71 (for example, hafnium oxide) and an upper electrode 72 (for example, germanium) are sequentially laminated from the bottom. The common bit line flat portion 73 (for example, tungsten) and the mask insulating film 74 (for example, a tantalum nitride film). The common bit line flat portion 73 is formed with a planar (flat plate) conductor layer so as to cover the contact plug 70 in a predetermined range of the plurality of rows and the plurality of columns. In addition, the common bit line flat portion 73 can also cover all of the contact plugs 70 in the memory cell array (corresponding to the symbol 11 in FIG. 2). And was formed. A cover insulating film 75 (for example, a tantalum nitride film) is formed on the mask insulating film 68 including the variable resistance film 71, the upper electrode 72, the common bit line flat portion 73, and the mask insulating film 74. On the cover insulating film 75, an interlayer insulating film 76 (for example, a tantalum oxide film) is formed. The variable resistance film 71 and the upper electrode 72 are constituent parts of the variable resistance element 5a (memory element).

On the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 68, a hole 77a through which the contact plug 67a passes is formed. In the hole 77a, a contact plug 78a (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 78a is a part of a common source line (corresponding to the symbol 6 of FIGS. 6 and 7). Further, at the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 68, a hole 77b through which the contact plug 67b passes is formed. In the hole 77b, a contact plug 78b (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 78b is a part of a column word line (corresponding to the symbol 9 of FIGS. 6 and 7). Further, at the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 68, a hole 77c through which the contact plug 67c passes is formed. In the hole 77c, a contact plug 78c (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 77c is a part of a line word line (corresponding to the symbol 8 of Figs. 6 and 7). On the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 74, a hole 77d through which the common bit line flat portion 73 passes is formed. In the hole 77d, a contact plug 78d (for example, a laminated film of titanium nitride/tungsten) is buried. The contact plug 78d is a common bit line (corresponding to the symbol 7 of FIG. 6 and FIG. 7). portion.

At a predetermined position on the interlayer insulating film 76 including the contact plugs 78a, wirings 79a (for example, a laminated film of tungsten nitride/tungsten) are formed in this order from the bottom, and the mask is insulated. A film 80 (for example, a tantalum nitride film). The wiring 79a is a part of a common source line (corresponding to the symbol 6 of FIGS. 6 and 7). At a predetermined position on the interlayer insulating film 76 including the contact plug 78b, a wiring 79b (for example, a laminated film of tungsten nitride/tungsten) is formed in this order from the bottom, and the mask is insulated. A film 80 (for example, a tantalum nitride film). The wiring 79b is a part of a column word line (corresponding to the symbol 9 of FIGS. 6 and 7). At a predetermined position on the interlayer insulating film 76 including the contact plug 78c, a wiring 79c (for example, a laminated film of tungsten nitride/tungsten) is formed in this order from the bottom, and the mask is insulated. A film 80 (for example, a tantalum nitride film). The wiring 79c is a part of a line word line (corresponding to the symbol 8 of FIGS. 6 and 7). At a predetermined position on the interlayer insulating film 76 including the contact plug 78d, a wiring 79d (for example, a laminated film of tungsten nitride/tungsten) is formed in this order from the bottom, and the mask is insulated. A film 80 (for example, a tantalum nitride film). The wiring 79d is a part of a common bit line (corresponding to the symbol 7 of FIGS. 6 and 7). An interlayer insulating film 81 (for example, a tantalum oxide film) is formed on the interlayer insulating film 76 between the wirings 79a, 79b, 79c, and 79d.

According to the above general configuration, it is possible to associate the gate electrode 51a (or 51b) belonging to one of the selected row word lines and one of the selected column word lines. Right brake The memory cell 2 of the semiconductor pillar 82 of one of the intersections between the pole electrodes 56a (or 56b) is selected. Further, in the case of the semiconductor pillar 82, the semiconductor substrate 41 (P-type germanium) is used as it is, because even if the portion is a P-type, the gate electrode 51a (or 51b) which becomes a row line line is used. The gap (interval) between the gate electrode 56a (or 56b) which becomes the column word line is reduced, and the inversion occurs at the channel when the gate electrodes of both sides become the high level (HIGH level) The layer system will be substantially connected, and the double gate type electrification system will become ON.

Further, in the third embodiment, the double gate type selection transistor 33 is taken as an example, but by the gate electrode 51a, 51b at the semiconductor pillar 82 and the gate electrode 56a, 56b. A diffusion region (separated into two channels by the diffusion region) is formed in the portion, and two single-gate type selection transistors can be connected in series (corresponding to the first embodiment).

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. 9 to 20 are partial cross-sectional views between X-X' and Y-Y' which are schematically shown in the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.

First, an element isolation region 42 (for example, a tantalum oxide film) is formed at a predetermined region on a semiconductor substrate 41 (for example, a P-type germanium substrate), and then a predetermined depth is formed at other predetermined regions on the semiconductor substrate 41. A region 43 (for example, a phosphorus ion diffusion region) (step A1, see Fig. 9).

Here, the element isolation region 42 can be formed, for example, as follows. First, a tantalum oxide film (SiO ₂ , not shown) and a tantalum nitride film (Si ₃ N ₄ , not shown) for the mask are sequentially deposited on the semiconductor substrate 41. Thereafter, using the photolithography technique and the dry etching technique, patterning of the germanium nitride film, the germanium oxide film, and the semiconductor substrate 41 is sequentially performed, and trenches (ditches) are formed, and then, by thermal oxidation. An oxide film is formed on the wall surface (including the bottom surface) of the trench, and then the insulating film is formed by embedding the trench (for example, an oxide film by HDP-CVD or SOD (Spin On) a coating material such as Dirlectric), and then, by CMP (Chemical Mechanical Polishing), an excess insulating film that is not buried in the groove, a tantalum nitride film for a mask, and The tantalum oxide film is removed until the semiconductor substrate 41 is exposed, and the surface is flattened. In this manner, the element isolation region 42 of the STI (Shallow Trench Isolation) type can be formed.

Further, the diffusion region 43 can be formed, for example, as follows. First, a photoresist (not shown) that is opened at a region where the diffusion region 43 is formed is formed on the semiconductor substrate 41 by photolithography, and then the photoresist is ion-implanted as a mask. After the implantation (for example, phosphorus ion implantation), the photoresist is removed, whereby the diffusion region 43 can be formed.

Next, a mask insulating film 44 (for example, a tantalum nitride film) is deposited on the semiconductor substrate 41 including the element isolation region 42 and the diffusion region 43 (step A2, see FIG. 10).

Next, the mask insulating film 44 is patterned using a photolithography technique and a dry etching technique, and then the semiconductor substrate 41 (including the diffusion region 43) is patterned by using the mask insulating film 44 as a mask. The groove 45 is formed to extend in the X direction and is disposed in the Y direction with a predetermined interval (step A3, see FIG. 11).

Next, a diffusion region 46 (for example, a phosphorus ion diffusion region) is formed at the semiconductor substrate 41 around the bottom of the trench 45, and thereafter, an insulating film 47 buried in the trench 45 is formed (for example, tantalum oxide film/germanium nitride) A laminated film of a film/tantalum oxide film) (step A4, see FIG. 12).

Here, the diffusion region 46 can be formed by masking the insulating film 44 and ion implantation (for example, phosphorus ion implantation) on the semiconductor substrate 41 around the bottom of the trench 45 at a predetermined temperature. Annealing is carried out to form it. The diffusion regions 46 are connected in a layered manner and are formed to be connected to the diffusion regions 43.

Further, the insulating film 47 can be formed by laminating an insulating film on the entire substrate by CVD (Chemical Vapor Deposition) (for example, a laminated film of a tantalum oxide film / a tantalum nitride film / a tantalum oxide film). Then, the insulating film is polished (planarized) by CMP (Chemical Mechanical Polishing) until the mask insulating film 44 is exposed.

Next, the mask insulating film 44 (including the insulating film 47) is patterned by photolithography and dry etching, and then the semiconductor substrate 41 is masked by using the mask insulating film 44 as a mask. (including the diffusion region 43, the insulating film 47, and the diffusion region 46) is patterned to form a groove 48 extending in the Y direction and vacating at a predetermined interval in the X direction (step A5, reference drawing) 13). Thereby, the semiconductor pillars 82 arranged in a matrix of a plurality of rows and a plurality of columns are formed. Further, the depth of the groove 48 is set to be equal to the depth of the groove 45.

Next, an insulating film 49 is formed at a lower portion of the trench 48, and thereafter, a row line layer (formed with a gate insulating film 50, a gate electrode 51a, 51b, 51c, an insulating film) is formed on the insulating film 49 in the trench 48. After the layer 52, the insulating film 53 is formed on the row line layer in the trench 48 (step A6, see FIG. 14).

Here, the insulating film 49 can be formed by depositing an insulating film (for example, a laminated film of a tantalum nitride film/tantalum oxide film) on the entire surface of the substrate (to be deposited so as not to fill the groove 48), and then The insulating film is dry etched until it becomes a predetermined thickness, and is formed at the lower portion of the trench 48.

Further, the line word line layer can be formed as follows. First, a gate insulating film 50 (for example, a tantalum oxide film) is formed on the wall surface of each of the semiconductor pillars 82 exposed from the trenches 48 by thermal oxidation, and then stacked on the entire substrate (to not fill the trenches 48). a conductive film (for example, titanium nitride) for the gate electrodes 51a, 51b, and 51c, and then sidewall-shaped gate electrodes 51a, 51b, and 51c are formed by dry etching the conductive film. Thereafter, the insulating film 52 is deposited on the entire surface of the substrate (to be deposited so as not to fill the groove 48) (for example, 矽 a laminated film of a nitride film/tantalum oxide film), and thereafter, the gate insulating film 50, the gate electrodes 51a, 51b, 51c, and the insulating film 52 are dry-etched until a predetermined thickness is obtained, whereby A line word line layer can be formed.

Further, the insulating film 53 can be deposited on the entire surface of the substrate (to be deposited so as to fill the trenches 48) (for example, a laminated film of a tantalum nitride film/germanium oxide film), and then by CMP. The insulating film is polished (planarized) until the mask insulating film 44 is exposed.

Next, using the photolithography technique and the dry etching technique, the insulating film 47 (including the insulating film 53) in the trench 45 is removed until it reaches a predetermined thickness, whereby the extension is formed in the X direction and is in Y. A groove 45 having a predetermined interval and having the insulating film 47 as a bottom surface is disposed in the direction (step A7, see FIG. 15). Further, the depth of the groove 45 at the step A7 is set to be lower than the upper surface of the gate electrodes 51a, 51b, 51c.

Next, an insulating film 54 is formed on the insulating film 47 (including the insulating film 53) of the trench 45, and thereafter, a column line layer is formed on the insulating film 54 in the trench 45 (having a gate insulating film 55, a gate) The electrodes 56a, 56b, 56c and the layers of the insulating film 57 are formed, and then an insulating film 58 is formed on the column line layer in the trench 45 (step A8, see FIG. 16).

Further, the insulating film 54 can be formed by the same method and material as the formation of the insulating film 49 of the step A6 (refer to FIG. 14). Further, the word line layer (having a gate insulating film 55, a gate electrode 56a, 56b, 56c, a layer of the insulating film 57), which is also provided by the row line layer with the step A6 (refer to FIG. 14) (having the gate insulating film 50, the gate electrodes 51a, 51b, 51c, the insulating film) The layer 52 is formed by the same method and material. Further, the insulating film 58 can also be formed by the same method and material as the insulating film 53 of the step A6 (refer to FIG. 14).

Next, the mask insulating film 44 on the semiconductor pillars 82 of the normal cell region 84 is removed using photolithography and dry etching techniques, thereby forming holes 59 through the semiconductor pillars 82, and then in the semiconductor pillars. A diffusion region 60 is formed at the upper portion of 82, and thereafter, a contact plug 61 buried in the hole 59 is formed (step A9, see Fig. 17).

Here, the diffusion region 60 can be formed by masking the mask insulating film 44, the insulating film 53, and the insulating film 58 and implanting N-type impurities (for example, As ions) on the semiconductor pillar 82 exposed from the hole 59. ), and formed.

Further, the contact plug 61 can be electrically conductive (for example, a DOPOS film (doped polysilicon film)) by being deposited on the entire substrate (to fill the holes 59), and then electrically conductive by CMP. The film is polished (planarized) until the mask insulating film 44 is exposed.

Next, a mask insulating film 62 (for example, a tantalum nitride film) is deposited on the mask insulating film 44 including the mask insulating film 44, the insulating film 53, and the contact plug 61, and then, using photolithography and The dry etching technique removes a portion of the mask insulating film 62 until the mask insulating film 44 is exposed, and thereafter, using photolithography and dry etching techniques, The mask insulating film 44 (including the insulating films 53 and 58) is partially removed until the semiconductor substrate 41, the element isolation region 42 and the diffusion region 43 are exposed, and thereafter, the semiconductor substrate 41, the element isolation region 42, the diffusion region 43, A cover insulating film 63 (for example, a laminated film of a tantalum oxide film/yttrium nitride film) is deposited on the mask insulating film 44 and the mask insulating film 62, and then an interlayer insulating film 64 is deposited on the cover insulating film 63 (for example, After the ruthenium oxide film), the interlayer insulating film 64 is polished (planarized) by CMP, and then an interlayer insulating film 65 (for example, a tantalum oxide film) is deposited on the interlayer insulating film 64, and then, light lithography is used. The technique and the dry etching technique form a hole 66a passing through the diffusion region 43, a hole 66b passing through the gate electrode 56a, 56b, a hole 66c passing through the gate electrode 51a, 51b, and then forming a contact in the hole 66a, 66b, 66c. Plugs 67a, 67b, 67c (for example, a laminated film of titanium nitride/tungsten), and thereafter, a mask insulating film 68 is deposited on the interlayer insulating film 65 including the contact plugs 67a, 67b, 67c (for example, niobium nitrogen) Filming), and then using photolithography The etching technique is used to pattern the mask insulating film 68. Thereafter, the mask insulating film 68 is formed as a mask to form a hole 69 through the contact plug 61, and thereafter, a contact plug 70 is formed in the hole 69 (for example, A laminated film of titanium/titanium nitride) (step A10, see Fig. 18). Further, the construction of the interlayer insulating film 65 may be omitted.

Here, the hole 66a can be formed by etching the interlayer insulating films 65, 64 and the cover insulating film 63 by using a photolithography technique and a dry etching technique. Moreover, the holes 66b can be covered by the interlayer insulating film 65, 64 by using the photolithography technique and the dry etching technique. The edge film 63 and the insulating film 58 are etched to form them. Further, the hole 66c can be formed by etching the interlayer insulating films 65, 64, the cover insulating film 63, and the insulating film 53 by using a photolithography technique and a dry etching technique.

Further, the contact plugs 67a, 67b, and 67c can be stacked on the entire surface of the substrate (to be filled so as to fill the holes 66a, 66b, and 66c) (for example, a laminated film of titanium nitride/tungsten) Then, the conductive film is polished (planarized) by CMP until the interlayer insulating film 65 is exposed.

Further, the hole 69 can be formed by etching the mask insulating film 68, the interlayer insulating films 65, 64, and the cover insulating film 63 by using a photolithography technique and a dry etching technique.

Further, the contact plug 70 can be electrically conductive (for example, a laminated film of titanium/titanium nitride) by being deposited on the entire surface of the substrate (to fill the hole 70), and then electrically conductive by CMP. The film is polished (planarized) until the mask insulating film 68 is exposed.

Next, the variable resistance film 71 is deposited on the mask insulating film 68 including the contact plug 70, and then the upper electrode 72 is deposited on the variable resistance film 71 (step A11, see FIG. 19).

Here, in the variable resistance film 71, for example, an insulating film of HfO ₂ , ZrO ₂ , NiO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , MoO ₃ or the like can be used. At the upper electrode 72, for example, a metal film of Ta, Pt, Hf, Ni, W or the like can be used.

Next, a common bit line plate is stacked on the upper electrode 72. a portion 73 (for example, tungsten), after which a mask insulating film 74 (for example, a tantalum nitride film) is deposited on the common bit line flat portion 73, and then, using a photolithography technique and a dry etching technique, for the mask The insulating film 74 is patterned, and then the mask insulating film 74 is used as a mask, and the common bit line flat portion 73, the upper electrode 72, and the variable resistance film 71 are etched until the mask insulating film 68 is exposed, and thereafter, A cover insulating film 75 (for example, a tantalum nitride film) is deposited on the mask insulating film 68 including the mask insulating film 74, the common bit line flat portion 73, the upper electrode 72, and the variable resistance film 71, and then, An interlayer insulating film 76 (for example, a tantalum oxide film) is deposited on the insulating film 75, and then the interlayer insulating film 76 is polished (planarized) by CMP (step A12, see FIG. 20).

Finally, by using the photolithography technique and the dry etching technique, the hole 77a passing through the contact plug 67a, the hole 77b passing through the contact plug 67b, the hole 77c passing through the contact plug 67c, and the common bit line flat portion 73 are formed. After the holes 77d, the contact plugs 78a, 78b, 78c, and 78d are formed in the holes 77a, 77b, 77c, and 77d, and then deposited on the interlayer insulating film 76 including the contact plugs 78a, 78b, 78c, and 78d. a conductive film of wirings 79a, 79b, 79c, and 79d (for example, a laminated film of tungsten nitride/tungsten), after which a mask insulating film 80 (for example, a tantalum nitride film) is deposited on the conductive film, and then used. The lithography technique and the dry etching technique are used to pattern the mask insulating film 80. Thereafter, the mask insulating film 80 is used as a mask, and the conductive film is etched until the interlayer insulating film 76 is exposed. Wiring lines 79a, 79b, 79c, and 79d are formed, and thereafter, mask insulating film 80, wirings 79a, 79b, 79c, and 79d are included. An interlayer insulating film 81 (for example, a tantalum oxide film) is deposited on the interlayer insulating film 76, and then the interlayer insulating film 81 is polished (planarized) by CMP (step A13, see FIG. 8). As in the above, it is possible to manufacture a semiconductor device as shown in Fig. 8.

Here, the holes 77a, 77b, and 77c can be formed by etching the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 68 by using a photolithography technique and a dry etching technique. Further, the hole 77d can be formed by etching the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 74 by using a photolithography technique and a dry etching technique. Further, the wirings 79a, 79b, 79c, and 79d are formed to be connected to the corresponding contact plugs 78a, 78b, 78c, and 78d.

According to the third embodiment, it is possible to associate the gate electrode 51a (or 51b) belonging to one of the selected row word lines and one of the selected column word lines. The memory cells 2 of the semiconductor pillars 82 of one of the intersections of the gate electrodes 56a (or 56b) are selected, and therefore, adjacent to each other in the row direction and the column direction The memory cell 2 shares the upper common bit line flat portion 73. Therefore, it is possible to increase the bit line width which is etched at the minimum pitch, and to set the bit line impedance to a lower impedance.

Further, according to the third embodiment, it is possible to minimize the pitch of the upper electrode 72 and the variable resistance film 71 which are the constituent portions of the memory element which are simultaneously etched with the bit line as in the prior art. Since the etching is performed as an avoidance, it is possible to further reduce the etching damage to the sidewalls of the upper electrode 72 and the variable resistance film 71, which is advantageous for the improvement of the yield.

(Embodiment 4)

A semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings. Fig. 21 is a circuit diagram schematically showing the configuration of a memory cell in the semiconductor device according to the fourth embodiment of the present invention. Fig. 22 is a partial circuit diagram showing a schematic configuration of a memory cell unit in the semiconductor device according to the fourth embodiment of the present invention.

Fig. 21 of the fourth embodiment is a modification of the first embodiment, and the first selection transistor 3 is constituted by two transistors 3a and 3b connected in parallel, and the same is made by The second selective transistors 4 are formed by two transistors 4a and 4b connected in parallel. However, the configuration of the four transistors is based on the viewpoint of an equivalent circuit. In the actual device configuration, as will be described later, the channel regions of the transistors 3a and 3b are respectively Formed at the common semiconductor layer, the channel regions of the transistors 4a, 4b are also formed at the common semiconductor layer, respectively. Further, along with this, there are four gate electrode systems at the selection element. The gate electrodes of the transistors 3a and 3b in the memory cell 2 are respectively connected to the different line lines 8a and 8b, and the gate electrodes of the transistors 4a and 4b are respectively different from each other. The column word lines 9a, 9b are connected. The line word line 8a is electrically connected to the gate electrode of the first selection transistor 3a of each of the memory cells 2 belonging to the same row. Connection (refer to Figure 22). The line word line 8b is electrically connected in common with the gate electrode of the first selection transistor 3b of each of the memory cells 2 belonging to the same row (refer to Fig. 22). The column word line 9a is electrically connected in common to the gate electrodes of the second selection transistor 4a of the respective memory cells 2 belonging to the same column (refer to FIG. 22). The column word line 9b is electrically connected in common with the gate electrode of the second selection transistor 4b of each of the memory cells 2 belonging to the same column (refer to FIG. 22). The other configuration is the same as that of the first embodiment.

Further, in the operation of the semiconductor device of the fourth embodiment, one row word line 8 and one column word line 9 are not selected as in the first embodiment (see FIG. 1) to select one memory. The cell 2 is selected to select one of the row cell lines 8a and 8b adjacent to each other and the column word lines 9a and 9b adjacent to each other to select one. Further, when a high level is applied to the line word lines 8a, 8b and the memory cell on the left side is selected, the transistor 3a of the memory cell on the right side is also in an ON state, but since the line word line 8 is As a non-starting level, the current flowing in the memory cell on the left side is such an extent that it does not affect the potential of the common bit line 7.

According to the embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 5)

Using the drawing, the semiconductor device of the fifth embodiment of the present invention is used. Description. Fig. 23 is a circuit diagram schematically showing the configuration of a memory cell in the semiconductor device of the fifth embodiment of the present invention. Fig. 24 is a partial circuit diagram showing a schematic configuration of a memory cell unit in the semiconductor device according to the fifth embodiment of the present invention.

The fifth embodiment is a modification of the second embodiment, and the two double-gate type selection transistors 34 and 35 are connected in parallel. Also in such a configuration, from the viewpoint of the device structure, the channel regions of the two double gate type selection transistors 34, 35 are formed at the common semiconductor layers, respectively.

The double gate type selection transistor 34 is a field effect transistor in which two gate electrodes 34a, 34b are arranged in series on a channel between the source terminal and the gate terminal (refer to FIG. 23). The double gate type selection transistor 34 is electrically connected to the row word line 8a (RWL_m) at the gate electrode 34a and electrically connected to the column word line 9a (CWL_n) at the gate electrode 34b. Connected and electrically connected to the common source line 6 at the source terminal and electrically connected to the input terminal of the memory element 5 at the terminal.

The double gate type selection transistor 35 is a field effect transistor in which two gate electrodes 35a and 35b are arranged in series on a channel between the source terminal and the gate terminal (refer to FIG. 23). The double gate type selection transistor 35 is electrically connected to the row word line 8b (RWL_m+1) at the gate electrode 35a and to the column word line 9b (CWL_n+1) at the gate electrode 35b. Electrically connected, and electrically connected to the common source line 6 at the source terminal, and with the memory element at the terminal The input terminal of the piece 5 is electrically connected.

Further, the line word line 8a is electrically connected in common to the gate electrode 34a of the double gate type selection transistor 34 of each of the memory cells 2 arranged in the row direction (refer to Fig. 24). Further, the line word line 8b is electrically connected in common to the gate electrode 35 of the double gate type selection transistor 35 of each of the memory cells 2 arranged in the row direction (refer to FIG. 24). Further, the column word line 9a is electrically connected in common to the gate electrode 34b of the double gate type selection transistor 34 of each of the memory cells 2 arranged in the column direction (refer to FIG. 24). Further, the column word line 9b is electrically connected in common to the gate electrode 35b of the double gate type selection transistor 35 of each of the memory cells 2 arranged in the column direction (refer to FIG. 24).

The other configuration is the same as that of the fourth embodiment.

According to the fifth embodiment, the same effects as those of the fourth embodiment can be obtained, and the structure of the memory cell can be simplified as compared with the fourth embodiment.

(Embodiment 6)

A semiconductor device according to a sixth embodiment of the present invention will be described with reference to the drawings. Fig. 25 is a partial cross-sectional view showing the relationship between X-X' and Y-Y' schematically showing the configuration of the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.

The sixth embodiment is an example of a structure equivalent to the circuit of the second embodiment. The semiconductor device of the sixth embodiment is in the row word line layer and the column word line layer, and is not in the same manner as in the third embodiment (reference drawing). 8) Generally, between the adjacent semiconductor pillars 82, the gate electrodes 51a, 51b, 51c which become the line word lines are separated into two and the gate electrodes 56a, 56b, 56c which are the column word lines are separated. In the case of two configurations, between the adjacent semiconductor pillars 82, the gate electrodes 51a, 51b, and 51c which are the line word lines are set to have only one, and the gates of the column word lines are formed. Only one of the electrodes 56a, 56b, and 56c is provided.

The gate electrodes 51a and 51b adjacent to each other in the X direction of the semiconductor pillar 82 are not common. If only the gate electrode of one side is selected, the semiconductor pillar 82 to be selected is not selected. Alternatively, the semiconductor pillars 82 to be selected are selected by selecting the gate electrodes on both sides. The gate electrodes 56a and 56b adjacent to each other in the Y direction of the semiconductor pillar 82 are not common. If only the gate electrode of one side is selected, the semiconductor pillar 82 to be selected is not selected. Alternatively, the semiconductor pillars 82 to be selected are selected by selecting the gate electrodes on both sides. That is, only the memory cells 2 of the semiconductor pillar 82 belonging to the region (intersection) surrounded by the selected four gate electrodes 51a, 51b, 56a, 56b are selected.

The other configurations are the same as those of the third embodiment.

Further, the semiconductor pillar 82 is the same as the third embodiment (see FIG. 8), and the semiconductor substrate 41 (P-type germanium) is used as it is, because even if the portion is a P-type, it will become a line. The gap (interval) between the gate electrodes 51a, 51b of the word line and the gate electrodes 56a, 56b which are the column word lines is reduced, and the gate electrodes of both sides are When it becomes the starting level (HIGH level), the inversion layer generated at the channel will be substantially connected, and the double gate type selection cell system will become ON.

Further, in the sixth embodiment, the double gate type selection transistor 33 is taken as an example, but by the gate electrode 51a, 51b at the semiconductor pillar 82 and the gate electrode 56a, 56b. A diffusion region (separated into two channels by the diffusion region) is formed in the portion, and two single gate type selection transistors can be connected in series (corresponding to the fourth embodiment).

Next, a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to the drawings. Figs. 26 to 30 are partial cross-sectional views between X-X' and Y-Y' which are schematically shown in the method of manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention. Here, the portion common to the manufacturing method of the third embodiment will be described with reference to the manufacturing method of the third embodiment.

First, a substrate having the same configuration as that of Fig. 13 is manufactured by the same procedure as step A1 (refer to Fig. 9) to step A5 (refer to Fig. 13) of the third embodiment (step B1).

Next, an insulating film 49 is formed at a lower portion of the trench 48, and thereafter, a row line layer (formed with a gate insulating film 50, a gate electrode 51a, 51b, 51c, an insulating film) is formed on the insulating film 49 in the trench 48. After the layer 52, an insulating film 53 is formed on the row line layer in the trench 48 (step B2, see Fig. 26). Further, in each of the grooves 48, the gate electrodes 51a, 51b, and 51c are not separated into two as shown in Fig. 14, but one gate electrode 51a, 51b, and 51c are provided.

Here, the insulating film 49 and the insulating film 53 can be formed by the same method as the step A6 (refer to FIG. 14) of the third embodiment. For the line word line layer, it can be formed as follows. First, a gate insulating film 50 (for example, a tantalum oxide film) is formed on the wall surface of each of the semiconductor pillars 82 exposed from the trenches 48 by thermal oxidation, and then stacked on the entire substrate (to not fill the trenches 48). To the extent that the conductive films (for example, titanium nitride) for the gate electrodes 51a, 51b, and 51c are stacked, and then the insulating film 52 is deposited on the entire surface of the substrate (to be stacked so as not to fill the trenches 48) (for example, Then, the gate insulating film 50, the conductive film, and the insulating film 52 are dry-etched until they have a predetermined thickness, whereby A row line layer of a gate electrode formed with one of the gate electrodes 51a, 51b, 51c is formed in the trench 48.

Next, using the photolithography technique and the dry etching technique, the insulating film 47 (including the insulating film 53) in the trench 45 is removed until it reaches a predetermined thickness, whereby the extension is formed in the X direction and is in Y. A groove 45 having the insulating film 47 as a bottom surface disposed at a predetermined interval is disposed in the direction (step B3, see FIG. 27). Further, the depth of the groove 45 at the step B3 is set to be lower than the upper surface of the gate electrodes 51a, 51b, 51c.

Next, an insulating film 54 is formed on the insulating film 47 (including the insulating film 53) of the trench 45, and thereafter, a column line layer is formed on the insulating film 54 in the trench 45 (having a gate insulating film 55, a gate) The electrodes 56a, 56b, 56c, the layer of the insulating film 57), and then the character elements in the groove 45 An insulating film 58 is formed on the wiring layer (step B4, see FIG. 28).

Further, the insulating film 54 and the insulating film 58 may be formed by the same method as the step A6 (refer to Fig. 14) of the third embodiment. Further, the column word line layer (having a layer including the gate insulating film 55, the gate electrodes 56a, 56b, 56c, and the insulating film 57) can be formed as follows. First, a gate insulating film 55 (for example, a tantalum oxide film) is formed on the wall surface of each of the semiconductor pillars 82 exposed from the trench 45 by thermal oxidation, and then stacked on the entire substrate (to not fill the trench 45). To the extent that the conductive film (for example, titanium nitride) for the gate electrodes 51a, 56b, and 56c is deposited, and then the insulating film 57 is deposited on the entire surface of the substrate (to be stacked so as not to fill the groove 45) (for example, Then, the gate insulating film 55, the conductive film, and the insulating film 57 are dry-etched until they have a predetermined thickness, whereby A column line layer of a gate electrode formed with one of the gate electrodes 56a, 56b, 56c is formed in the trench 45.

Next, the mask insulating film 44 on the semiconductor pillars 82 of the normal cell region 84 is removed using photolithography and dry etching techniques, thereby forming holes 59 through the semiconductor pillars 82, and then in the semiconductor pillars. A diffusion region 60 is formed at the upper portion of 82, and thereafter, a contact plug 61 buried in the hole 59 is formed (step B5, see Fig. 29).

Here, the diffusion region 60 and the contact plug 61 may be formed by the same method as the step A9 (refer to FIG. 17) of the third embodiment.

Next, the mask insulating film 44 and the insulating film 53 are included. And a mask insulating film 62 (for example, a tantalum nitride film) is deposited on the mask insulating film 44 of the contact plug 61, and then a portion of the mask insulating film 62 is removed using photolithography and dry etching. Until the mask insulating film 44 is exposed, one portion of the mask insulating film 44 (including the insulating films 53 and 58) is removed by the photolithography technique and the dry etching technique until the semiconductor substrate 41, the element isolation region 42 and the diffusion. After the region 43 is exposed, the insulating film 63 is deposited on the semiconductor substrate 41, the element isolation region 42, the diffusion region 43, the mask insulating film 44, and the mask insulating film 62 (for example, a tantalum oxide film/yttrium nitride film). After laminating the film, an interlayer insulating film 64 (for example, a tantalum oxide film) is deposited on the cover insulating film 63, and then the interlayer insulating film 64 is polished (planarized) by CMP, and then, in the interlayer insulating film. An interlayer insulating film 65 (for example, a tantalum oxide film) is deposited on 64, and thereafter, a hole 66a passing through the diffusion region 43, a hole 66b passing through the gate electrode 56a, 56b, and a gate are formed by using a photolithography technique and a dry etching technique. Polar electrode 51 a hole 66c of a, 51b, after which contact plugs 67a, 67b, 67c (for example, a laminated film of titanium nitride/tungsten) are formed in the holes 66a, 66b, 66c, and thereafter, the contact plugs 67a, 67b are included. A mask insulating film 68 (for example, a tantalum nitride film) is deposited on the interlayer insulating film 65 of 67c, and then the mask insulating film 68 is patterned by photolithography and dry etching, and then masked. The cover insulating film 68 is formed as a mask to form a hole 69 through the contact plug 61, and thereafter, a contact plug 70 (for example, a laminated film of titanium/titanium nitride) is formed in the hole 69 (step B6, see FIG. 30). . Further, the construction of the interlayer insulating film 65 may be omitted.

Here, the holes 66a, 66b, and 66c can be formed by the same method as the step A10 (refer to Fig. 18) of the third embodiment, but the holes 66b and 66c are respectively for one groove 45, 48. On the other hand, the holes 66b and 66c are formed in a different manner from the third embodiment in which the holes 66b and 66c are formed for one groove 45 and 48.

Further, the contact plugs 67a, 67b, 67c, the holes 69, and the contact plugs 70 can be formed by the same method as the step A10 (refer to Fig. 18) of the third embodiment.

Finally, a semiconductor device having the same configuration as that of Fig. 25 is manufactured by the same procedure as step A11 (refer to Fig. 19) to step A13 (refer to Fig. 8) of the third embodiment (step B7, see Fig. 25).

According to the sixth embodiment, the same effects as those of the fifth embodiment can be obtained, and the manufacturing method of the third embodiment can be simplified.

(Embodiment 7)

A semiconductor device according to a seventh embodiment of the present invention will be described using a drawing and a comparative example. Figure 31 is a partial cross-sectional view taken along the line Z-Z' of Figure 32 schematically showing the configuration of the memory cell array in the semiconductor device of the seventh embodiment of the present invention. Fig. 32 is a partial plan view schematically showing the configuration of a memory cell array in the semiconductor device of the seventh embodiment of the present invention. Figure 33 is a partial cross-sectional view taken along line Z-Z' of Figure 34 for schematically showing the configuration of the memory cell array in the semiconductor device of the comparative example. Figure 34 is for the semiconductor in the comparative example The memory cell array in the device is constructed as a partial plan view of the mode display. Fig. 35 is a view showing a comparison of a forming voltage at a variable resistance film in the semiconductor device of the seventh embodiment of the present invention with a comparative example.

The seventh embodiment is a modification of the third embodiment, and is a contact plug 78d to be connected to the common bit line flat portion 73 so as not to be in contact with the contact plug 70 connected to the variable resistance film 71. The position (the same position as the semiconductor post 82) overlaps the set (refer to Figs. 31 and 32). The contact plug 78d may be connected in plural to one common bit line flat portion 73. The other configuration is the same as that of the third embodiment (refer to Fig. 8). Further, the seventh embodiment can be applied to the sixth embodiment (see Fig. 25).

Here, the contact plug 78d is electrically connected to a peripheral circuit (corresponding to the multiplexer 19 of FIG. 2) via the wiring 79d which becomes a common bit line. In the evaluation and analysis performed by the inventors of the semiconductor devices of the third and sixth embodiments, it has been found that the position of the contact plug 78d that connects the common bit line flat portion 73 and the peripheral circuit is determined. There is a difference in the generated voltage. Here, the generated voltage refers to a voltage necessary to make a resistance change current path in the film.

As a comparative example, in the structure of the third embodiment, the common bit line is formed directly above the contact plug 70 (the same position as the semiconductor post 82) connected to the variable resistance film 71. The flat portion 73 is configured to connect the contact plugs 78d (refer to FIG. 33 and FIG. 34).

The position of the contact plug 78d connected to the common bit line flat portion 73 is located directly above the contact plug 70 (the same position as the semiconductor post 82), and is in the common bit line The position of the contact plug 78d to which the flat plate portion 73 is connected is not in the embodiment 7 which is directly above the contact plug 70 (the same position as the semiconductor post 82), the memory element (resistance change element; the contact plug 70, The withstand voltage (generation voltage) of the variable resistance film 51 and the upper electrode 72) is lowered (refer to FIG. 35). According to this, it is found that the position of the contact plug 78d connected to the common bit line flat portion 73 is in the comparative example directly above the contact plug 70 (the same position as the semiconductor post 82). The withstand voltage (generation voltage) of the memory element (resistance variable element; contact plug 70, resistance change film 51, upper electrode 72) rises.

The increase in withstand voltage (generation voltage) of the memory element (resistance change element; contact plug 70, resistance change film 51, upper electrode 72) causes a circuit that requires a high voltage and a large supply current, and also consumes The current increases, the circuit area increases, and the influence on the wafer becomes large.

Further, in the seventh embodiment, when there is an unused cell (pseudo cell) region, the contact plug 78d which is connected to the common bit line flat portion 73 in the pseudo cell region may be used. It is formed directly above the contact plug 70 (the same position as the semiconductor post 82).

According to the seventh embodiment, compared with the comparative example, since the withstand voltage (generation voltage) can be lowered, high power is not required. The circuit for generating and supplying a large current can reduce the current consumption and the circuit area, and can reduce the influence on the wafer. In other words, the withstand voltage (generation voltage) of the memory element can be reduced, and the current can be rewritten with less current and voltage. Therefore, it is possible to reduce the area of the circuit for supplying current and voltage, and it is also useful for reducing the current consumption.

In addition, in the case of the present invention, the present invention is not limited to the illustrated embodiment, and is not intended to limit the invention to the illustrated embodiment.

Further, in the scope of the entire disclosure of the present invention (including the scope of the claims and the drawings), the embodiments and the modifications and adjustments of the embodiments can be carried out based on the basic technical idea of the present invention. Further, within the scope of the patent application scope of the present invention, it is possible to carry out various kinds of disclosure elements (including each element of each request item, each embodiment, each element of the embodiment, each element of each drawing, etc.). The combination of sex is even chosen. In other words, the present invention includes various modifications and corrections that can be made by the practitioner in accordance with the entire disclosure and technical idea contained in the scope of the patent application and the drawings. Further, the numerical values and numerical ranges described in the present invention are considered to be arbitrary intermediate values, lower numerical values, and small ranges, even if they are not clearly stated.

(attachment)

A semiconductor device obtained by the first aspect of the present invention is provided There are: a common source line; and a common bit line; and a plurality of memory cells, which are memory cells that are arranged in a plurality of rows and a plurality of columns, and have the first and second, respectively. a selection element and a memory element of the control electrode are connected in series between the common source line and the common bit line; and a plurality of first selection lines are respectively associated with the plurality of lines belonging to the plurality of lines The first control electrode of each of the memory cells is connected in common; and the plurality of second selection lines are respectively associated with the second control of each of the memory cells belonging to the corresponding column of the plurality of memory cells The electrodes are connected in common.

In the semiconductor device of the present invention, preferably, the selection element includes first and second transistors that are connected in series, and the first and second control electrodes are respectively associated with the first and the first The gate of the second transistor is connected.

In the semiconductor device of the present invention, preferably, the selection element includes a double gate transistor, and the first and second control electrodes are respectively connected to two gates of the double gate transistor. .

In the semiconductor device of the present invention, preferably, the selection element further includes: third and fourth control electrodes, a first parallel connection of the first and second transistors, and third and third In the second parallel connection body of the transistor, the first and second parallel connection systems are connected in series, and the first and third control electrode systems are connected to the gates of the first and second transistors, respectively. The second and fourth control electrode systems are connected to the third and fourth transistors, respectively. The third control electrode is connected to the first electrode of the adjacent memory cell, and the fourth control electrode is connected to the second electrode of the adjacent memory cell.

In the semiconductor device of the present invention, preferably, the memory device further includes: third and fourth control electrodes, and first and second double gate transistors connected in parallel, the first 1 and the second control electrode are respectively connected to the gates of the first double gate transistor, and the third and fourth control electrodes are respectively connected to the gates of the second double gate transistor. The third control electrode is connected to the first electrode of the adjacent memory cell, and the fourth control electrode is connected to the second electrode of the adjacent memory cell.

A semiconductor device obtained by the second aspect of the present invention is characterized in that the memory device includes a plurality of memory blocks each having a common bit line and a plurality of memory cells. a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and respectively selecting a selection element and a memory element having the first and second control electrodes between the common bit line and the reference potential line a series connection; and a plurality of first selection lines are commonly connected to the first control electrode of each of the memory cells belonging to the corresponding row in the plurality of rows; and the second selection of the plurality The lines are connected in common to the second control electrode of each of the memory cells belonging to the corresponding one of the plurality of columns, and the plurality of memory blocks are configured to have a plurality of rows and a plurality of columns a matrix, belonging to the record that is placed on the same line The first selection line of the plural number of the memory block is connected in common, and the second selection line belonging to the plural of the memory blocks arranged in the same column is connected in common.

In the above semiconductor device of the present invention, preferably, the plurality of common bit lines in the plurality of memory blocks are independent of each other.

Preferably, in the semiconductor device of the present invention, the multiplexer further includes a multiplexer connected to the plurality of common bit lines, and the multiplexer selects the plurality of common bit lines. One of them.

Preferably, in the semiconductor device of the present invention, a global bit line is further provided, and the multiplexer electrically elects the selected common bit line and the global bit line. Sexual connection.

Preferably, in the semiconductor device of the present invention, the first and second selection circuits, the third and fourth selection circuits are further provided, and the first and second selection circuits are sandwiched between the two. The plurality of memory blocks are arranged in a matrix, and the third and fourth selection circuits are arranged in a matrix arrangement in which the plurality of memory blocks are interposed therebetween, and the plurality of A first selection line of a part of the first selection line is connected to the first selection circuit, and the remaining first selection line of the plurality of first selection lines is connected to the second selection circuit. a second selection line of a part of the plurality of second selection lines is connected to the third selection circuit, and the foregoing The remaining second selection line among the second selection lines is connected to the fourth selection circuit.

According to a third aspect of the present invention, a semiconductor device includes a plurality of semiconductor pillars arranged in a matrix of a plurality of rows and a plurality of columns, and sequentially stacking the first region, the channel region, and the second region. And a plurality of first wirings, wherein the channel regions belonging to the same row of the plurality of semiconductor columns are covered by the first gate insulating film; and the plurality of second wirings are relative to the plurality of wires The first wiring is disposed in the different layer, and the channel region belonging to the same row among the plurality of semiconductor columns is covered by the second gate insulating film; and the plurality of memory elements are Arranged on the second region and electrically connected to the second region; and the conductor layer is disposed on the plurality of memory elements, and is in a plurality of bits in the plurality of memory elements The aforementioned plurality of memory elements within a predetermined range of the plurality of columns and the plurality of columns are electrically connected in common.

In the semiconductor device of the present invention, preferably, the conductor layer is formed by covering the plurality of memory elements of the plurality of memory elements within a predetermined range of a plurality of rows and a plurality of columns. It is flat.

In the above-described semiconductor device of the present invention, it is preferable that the memory element is a resistance change element in which a lower electrode, a variable resistance film, and an upper electrode are sequentially laminated from the second region side, and is located in the predetermined range. The variable resistance film and the upper electrode of the variable resistance element described above are commonly connected to each other and formed into a flat plate shape.

In the semiconductor device of the present invention, preferably, the lower electrodes of the variable resistance elements located within the predetermined range are independent of each other.

In the semiconductor device of the present invention, preferably, the first wiring is divided into two between the adjacent semiconductor pillars, and is controlled independently of each other, and the second wiring is in phase The adjacent semiconductor pillars are divided into two, and are controlled independently of each other.

In the semiconductor device of the present invention, preferably, the pair of first wirings disposed on both sides of the vicinity of the semiconductor pillar are simultaneously controlled and disposed on both sides of the semiconductor pillar. The second wiring of the pair is controlled at the same time.

The semiconductor device according to the fourth aspect of the present invention includes a plurality of semiconductor pillars each including a first region and a second region, and a first region between the first region and the second region 1 and the second channel region; and the plurality of first wires are formed to extend in the first direction, and the semiconductors which are adjacent to the first direction in the plurality of semiconductor columns are arranged side by side The first channel layer of the pillar is covered by the first gate insulating film; and the plurality of second wirings are formed to extend in the second direction, respectively, and are to be included in the plurality of semiconductor pillars The second channel layer of the semiconductor pillars arranged side by side in the second direction is covered by the second gate insulating film; and the conductor layer is commonly connected to the plurality of semiconductors via the information memory. At the aforementioned first region of the column.

According to a fifth aspect of the present invention, a semiconductor device includes: a conductor plate; and a plurality of memory cells, which are memory cells arranged in a plurality of rows and a plurality of columns, and respectively The semiconductor column including the first and second regions and the first and second channel regions between the first and second regions formed in series, and the first region and the conductor are interposed An information memory layer between the flat plates; and a plurality of first wirings which are formed to extend in the row direction, respectively, and which are to be adjacent to the first channel of the semiconductor pillars of the plurality of semiconductor pillars arranged side by side in the row direction The layer is covered by the first gate insulating film; and the plurality of second wirings are formed to extend in the column direction, and are formed in the column direction of the plurality of semiconductor pillars The second channel layer of the semiconductor column of the row is covered by the second gate insulating film.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device, the semiconductor substrate includes an extension in a first direction and a second direction intersecting the first direction. a process of forming a first groove which is arranged side by side at a predetermined interval; and a process of forming a first region which is formed in a layered manner at the semiconductor substrate near the bottom of the first groove; and the semiconductor a second groove which is formed to extend in the second direction and which is spaced apart in the first direction and has a predetermined interval in the first direction, thereby forming a plurality of rows and a plurality of columns a project of a semiconductor column in a matrix shape; and a process of forming a first wiring in which a wall surface of the semiconductor post is covered by a first gate insulating film and extending along the second trench; and Further, a portion of the first wiring is formed so that a wall surface of the semiconductor post is covered by the second gate insulating film and a second wiring extending along the first trench is formed; and the second wiring is formed more than the second wiring a process of forming a second region at an upper portion of the upper semiconductor pillar; and a process of forming a memory element on the second region; and forming a predetermined range of the plurality of rows and the plurality of columns over the memory element Each of the aforementioned memory elements collectively serves as an electrically conductive layer of electrical conductors.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that before the process of forming the first trench, a process of forming a fourth region having a predetermined depth in a predetermined region of the semiconductor substrate is included. In the process of forming the first region, the first region is formed so as to be connected to the second region.

In the method of fabricating the semiconductor device of the present invention, preferably, after the process of forming the first region, and before the process of forming the semiconductor pillar, the first insulating film is buried in the first trench. In the above-described process of forming a semiconductor pillar, the second trench is formed on the semiconductor substrate including the first insulating film.

In the method of manufacturing the semiconductor device of the present invention, preferably, in the process of forming the first wiring, the second insulating film is formed under the second trench, and then the second trench is formed in the second trench. The first gate insulating film, the first wiring, and the third insulating film are formed on the second insulating film, and then the first gate insulating film in the second trench, the first wiring, and the third On the insulating film, form the 4th Insulating film.

In the method of manufacturing the semiconductor device of the present invention, preferably, in the process of forming the first wiring, when the first gate insulating film, the first wiring, and the third insulating film are formed, The first gate insulating film is formed on a wall surface of the semiconductor pillar in the second trench, and the first wiring is deposited on the second insulating film including the first gate insulating film in the second trench. Thereafter, the first wiring is etched back until the second insulating film is present, and the first wiring is separated into two in the second trench, and then the first trench is included in the first trench. The third insulating film is deposited on the second insulating film of the wiring, and then the first gate insulating film in the second trench and the upper portion of the first wiring and the third insulating film are removed.

In the method of manufacturing the semiconductor device of the present invention, preferably, in the step of forming the second wiring, a part of the first insulating film in the first trench is removed, and then in the first trench. a fifth insulating film is formed on the first insulating film, and then the second gate insulating film, the second wiring, and the sixth insulating film are formed on the fifth insulating film of the first trench, and then A seventh insulating film is formed on the second gate insulating film in the first trench, the second wiring, and the sixth insulating film.

In the method of manufacturing the semiconductor device of the present invention, preferably, in the process of forming the second wiring, when the second gate insulating film, the second wiring, and the sixth insulating film are formed, Forming the second gate on the wall surface of the semiconductor pillar in the first trench In the insulating film, the second wiring is deposited on the fifth insulating film including the first gate insulating film in the first trench, and then the second wiring is etched back to the fifth insulating layer. After the film is formed, the second wiring is separated into two in the first trench, and then the sixth insulating film is deposited on the fifth insulating film including the second wiring in the first trench. The second gate insulating film in the first trench, the second wiring, and the upper portion of the sixth insulating film are removed.

In the method of fabricating the semiconductor device of the present invention, preferably, in the process of forming the memory device, the eighth insulating film is formed on the second region, and then on the eighth insulating film. A lower electrode is electrically connected to the second region, and then a variable resistance film is deposited on the eighth insulating film including the lower electrode, and then the upper electrode is deposited on the variable resistance film.

In the method for fabricating the semiconductor device of the present invention, preferably, in the step of forming the conductor layer, the conductor layer is deposited on the upper electrode, and then the conductor layer and the upper electrode are One of the aforementioned resistance change films is partially removed.

In the method for fabricating the semiconductor device of the present invention, preferably, in the step of forming the conductor layer, the conductor layer is formed so as not to overlap the region of the semiconductor pillar. The process of forming a contact plug.

2‧‧‧ memory cells

3‧‧‧1st choice of crystal

4‧‧‧2nd choice of crystal

5‧‧‧ memory components

6‧‧‧Common source line

7‧‧‧Common bit line

8‧‧‧ line character line (first character line)

9‧‧‧ column word line (2nd character line)

Claims (28)

A semiconductor device comprising: a common source line; and a common bit line; and a plurality of memory cells, which are complex memory cells arranged on a plurality of rows and a plurality of columns, and Selecting a selection element and a memory element having the first and second control electrodes in series between the common source line and the common bit line, respectively; and the plurality of first selection lines are respectively associated with The first control electrode of each of the memory cells of the corresponding row in the plurality of rows is connected in common; and the second selection line of the plurality of rows is associated with the corresponding column in the plurality of columns The second control electrode of each memory cell is connected in common. The semiconductor device according to claim 1, wherein the selection element includes first and second transistors that are connected in series, and the first and second control electrodes are respectively The gates of the first and second transistors are connected. The semiconductor device according to claim 1, wherein the selection element includes a double gate transistor, and the first and second control electrodes are respectively connected to two gates of the double gate transistor. Extreme connection. The semiconductor device according to claim 1, wherein Further, the selection element further includes: third and fourth control electrodes, a first parallel connection of the first and second transistors, and a second parallel connection of the third and fourth transistors, wherein the 1 and the second parallel connection system are connected in series, and the first and third control electrode systems are connected to the gates of the first and second transistors, respectively, and the second and fourth control electrode systems are respectively connected The third and fourth transistors are connected, and the third control electrode is connected to the first electrode of the adjacent memory cell, and the fourth control electrode is connected to the adjacent memory cell. 2 electrodes are connected. The semiconductor device according to the first aspect of the invention, wherein the memory device further includes: third and fourth control electrodes, and first and second double gate transistors connected in parallel The first and second control electrode systems are respectively connected to two gates of the first double gate transistor, and the third and fourth control electrode systems are respectively connected to the second double gate transistor. The gates are connected, the third control electrode is connected to the first electrode of the adjacent memory cell, and the fourth control electrode is connected to the second electrode of the adjacent memory cell. . A semiconductor device characterized by comprising a plurality of memory blocks, wherein the plurality of memory blocks are respectively provided with: a common bit line; and a plurality of memory cells are arranged in a plurality of lines And plural a plurality of memory cells on the column, and connecting the selection element and the memory element having the first and second control electrodes in series between the common bit line and the reference potential line; and the first selection of the plurality The lines are respectively connected in common to the first control electrode of each of the memory cells belonging to the corresponding row in the plurality of rows; and the second selection line of the plurality is respectively associated with the plurality of The second control electrodes of the memory cells of the corresponding columns in the column are connected in common, and the plurality of memory blocks are arranged in a matrix having a plurality of rows and a plurality of columns, and are arranged in the same The first selection line of the plural number of the memory blocks on the line is respectively connected in common, and the second selection line belonging to the plural number of the memory blocks arranged on the same column is respectively connected in common. . The semiconductor device according to claim 6, wherein the plurality of common bit lines in the plurality of memory blocks are independent of each other. The semiconductor device according to claim 7, further comprising a multiplexer connected to the plurality of common bit lines, wherein the multiplexer selects the plurality of common bits One of the lines. The semiconductor device according to claim 8, wherein the semiconductor device further includes a global bit line, and the foregoing The multiplexer electrically connects the selected common bit line to the global bit line. The semiconductor device according to claim 7, further comprising first and second selection circuits, third and fourth selection circuits, wherein the first and second selection circuits are between the two The third and fourth selection circuits are arranged in a matrix arrangement in which the plurality of memory blocks are arranged, and the third and fourth selection circuits are arranged in a matrix arrangement in which the plurality of memory blocks are sandwiched. A first selection line of a part of the plurality of first selection lines is connected to the first selection circuit, and a remaining first selection line among the plurality of first selection lines is selected from the second selection a circuit is connected, and a second selection line of a part of the plurality of second selection lines is connected to the third selection circuit, and a remaining second selection line of the plurality of second selection lines is connected The aforementioned fourth selection circuit is connected. A semiconductor device comprising: a plurality of semiconductor pillars arranged in a matrix of a plurality of rows and a plurality of columns, and sequentially stacking a first region, a channel region, and a second region; and a plurality of In the wiring, the channel region belonging to the same row among the plurality of semiconductor columns is covered by the first gate insulating film; and the plurality of second wires are connected to the plurality of first wires. Is disposed at a different layer and belongs to the aforementioned plurality of semiconductor columns The same channel region is covered by the second gate insulating film; and a plurality of memory elements are disposed on the second region and electrically connected to the second region; and conductive The bulk layer is disposed on the plurality of memory elements and is electrically connected in common with the plurality of memory elements of the plurality of memory elements in a predetermined range of the plurality of lines and the plurality of columns. The semiconductor device according to claim 11, wherein the conductor layer covers the plurality of memory elements of the plurality of memory elements within a predetermined range of a plurality of rows and a plurality of columns. It is formed into a flat shape. The semiconductor device according to claim 12, wherein the memory element is a resistance change element in which a lower electrode, a variable resistance film, and an upper electrode are sequentially stacked from the second region side, and is located in the foregoing The variable resistance film and the upper electrode of the variable resistance element in a predetermined range are connected in common and formed into a flat plate shape. The semiconductor device according to claim 13, wherein the lower electrodes of the variable resistance elements located within the predetermined range are independent of each other. The semiconductor device according to claim 11, wherein the first wiring is divided into two between the adjacent semiconductor pillars, and is controlled independently of each other, and the second wiring is controlled by the second wiring. It is divided into two between the adjacent semiconductor pillars and is respectively mutually Independently controlled. The semiconductor device according to claim 15, wherein the pair of first wirings disposed on both sides of the vicinity of the semiconductor pillar are simultaneously controlled and disposed near the semiconductor pillar. The pair of second wirings on both sides of the pair are simultaneously controlled. A semiconductor device comprising: a plurality of semiconductor pillars each having a first and a second region; and first and second channels between the first and second regions formed in series a first region and a plurality of first wirings are formed to extend in the first direction, and the first column of the semiconductor pillars that are adjacent to each other in the first direction among the plurality of semiconductor pillars The channel layer is covered by the first gate insulating film; and the plurality of second wires are formed to extend in the second direction, respectively, and are included in the plurality of semiconductor pillars The second channel layer of the semiconductor pillars arranged side by side in the two directions is covered by the second gate insulating film; and the conductor layer is commonly connected to the plurality of semiconductor pillars via the information memory. At the first area. A semiconductor device comprising: a conductor plate; and a plurality of memory cells, which are memory cells arranged in a plurality of rows and a plurality of columns, and each of which includes: first and second The first region and the first region between the first and second regions are formed in series And a semiconductor column in the second channel region and an information memory layer interposed between the first region and the conductive plate; and a plurality of first wires are formed to extend in the row direction, and are to be attached The first channel layer of the semiconductor column which is arranged side by side in the row direction among the plurality of semiconductor columns is covered by the first gate insulating film; and the plurality of second wirings are respectively extended in the column direction The second channel layer of the semiconductor pillars which are adjacent to each other in the column direction among the plurality of semiconductor pillars is covered with the second gate insulating film. A method of manufacturing a semiconductor device, comprising: forming a semiconductor substrate having a predetermined interval extending in a first direction and intersecting a first direction intersecting the first direction a process of forming a first trench arranged side by side; and a process of forming a first region in a layered manner at the semiconductor substrate near the bottom of the first trench; and forming an extension on the semiconductor substrate In the second direction and in the first direction, the second groove is formed by arranging a predetermined interval, thereby forming a semiconductor column arranged in a matrix of a plurality of rows and a plurality of columns. And a process of forming a first wiring extending over the wall surface of the semiconductor post via the first gate insulating film and extending along the second trench; and a portion of the second wiring extending over the wall surface of the semiconductor post via the second gate insulating film and extending along the first trench is formed above the first wiring; 2 a process of forming a second region at an upper portion of the semiconductor pillar above the wiring; and a process of forming a memory device on the second region; and forming a predetermined row to be in a plurality of rows and a plurality of columns on the memory element Each of the aforementioned memory elements within the range is commonly used for the electrical connection of electrically conductive layers. The method of manufacturing a semiconductor device according to claim 19, wherein before the process of forming the first trench, the fourth region including a predetermined depth in a predetermined region of the semiconductor substrate is included In the above-described process of forming the first region, the first region is formed so as to be connected to the second region. The method of manufacturing a semiconductor device according to claim 19, wherein, after the process of forming the first region, and before the step of forming the semiconductor pillar, the method of embedding the first trench is included In the case of forming an insulating film, in the above-described process of forming a semiconductor pillar, the second trench is formed on the semiconductor substrate including the first insulating film. The method of manufacturing a semiconductor device according to claim 19, wherein in the step of forming the first wiring, a second insulating film is formed under the second trench, and then the second trench is formed. Forming the first gate insulating film on the second insulating film and the foregoing After the first wiring and the third insulating film, a fourth insulating film is formed on the first gate insulating film in the second trench, the first wiring, and the third insulating film. The method of manufacturing a semiconductor device according to claim 22, wherein in the forming the first wiring, the first gate insulating film, the first wiring, and the third insulating film are formed Forming the first gate insulating film on a wall surface of the semiconductor pillar in the second trench, and depositing the first insulating film on the second insulating film including the first gate insulating film in the second trench After the first wiring is etched back to the second insulating film, the first wiring is separated into two in the second trench, and then included in the second trench. The third insulating film is deposited on the second insulating film of the first wiring, and then the first gate insulating film in the second trench and the upper portion of the first wiring and the third insulating film are removed. The method of manufacturing a semiconductor device according to claim 19, wherein in the step of forming the second wiring, a part of the first insulating film in the first trench is removed, and then the a fifth insulating film is formed on the first insulating film in the trench, and then the second gate insulating film, the second wiring, and the sixth insulating film are formed on the fifth insulating film in the first trench. Thereafter, a seventh insulating film is formed on the second gate insulating film in the first trench, the second wiring, and the sixth insulating film. For example, the semiconductor device described in claim 24 In the above-described method of forming the second wiring, in the case where the second gate insulating film, the second wiring, and the sixth insulating film are formed, the wall surface of the semiconductor pillar in the first trench is formed The second gate insulating film is formed thereon, and the second wiring is deposited on the fifth insulating film including the first gate insulating film in the first trench, and then the second wiring is formed on the second wiring. The etchback is performed until the fifth insulating film is formed, and the second wiring is separated into two in the first trench, and then the second insulating film including the second wiring in the first trench is deposited on the fifth insulating film. After the sixth insulating film, the second gate insulating film in the first trench, the second wiring, and the upper portion of the sixth insulating film are removed. The method of manufacturing a semiconductor device according to claim 19, wherein in the forming the memory device, the eighth insulating film is formed on the second region, and then formed on the eighth insulating film. The lower electrode is electrically connected to the second region, and then the variable resistance film is deposited on the eighth insulating film including the lower electrode, and then the upper electrode is deposited on the variable resistance film. The method of manufacturing a semiconductor device according to claim 26, wherein in the forming the conductor layer, the conductor layer is deposited on the upper electrode, and then the conductor layer and the upper electrode and the One part of the resistance change film is removed. The method of manufacturing a semiconductor device according to claim 19, wherein in the step of forming the conductor layer, the conductor layer is not overlapped with the region of the semiconductor pillar. The way to form the contact plug works.