TW201440182A - Semiconductor package and method of manufacture - Google Patents

Abstract

Disclosed is a semiconductor package, including forming an encapsulant having a semiconductor element embedded therein, a plurality of supporting members formed in the encapsulant at the peripheral of the semiconductor element, and a strengthening portion connecting each of the supporting members, wherein the supporting members comprise a first pillar and a second pillar penetrating through the first pillar, thereby strengthening structures of the encapsulant and the package as a result. The invention further provides a method for manufacturing the semiconductor package as described above.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package without a package substrate and a method of fabricating the same.

With the evolution of semiconductor technology, semiconductor products have developed different package product types, and in pursuit of thinness and thinness of semiconductor packages, a chip scale package (CSP) has been developed, which is characterized by such a wafer. The grade package has only dimensions that are equal or slightly larger than the wafer size.

1A to 1E are schematic cross-sectional views showing a method of fabricating a wafer-level semiconductor package 1 of a conventional packageless substrate.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10.

As shown in FIG. 1B, a plurality of semiconductor wafers 11 are disposed on the thermal release adhesive layer 100. The semiconductor wafers 11 have opposite active surfaces 11a and inactive surfaces 11b, each of which has a plurality of active surfaces 11a. The electrode pads 110 are adhered to the thermal release adhesive layer 100.

As shown in FIG. 1C, the insulating material is formed by molding. 12 is on the thermal release layer 100 to coat the semiconductor wafer 11.

As shown in FIG. 1D, a baking process is performed to harden the insulating material 12 to form the package body 13, and at the same time, the heated release layer 100 loses viscosity due to heat, so the heating can be removed together. The release layer 100 and the carrier 10 expose the active surface 11a of the semiconductor wafer 11.

As shown in FIG. 1E, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 18 on the package body 13 and the active surface 11a of the semiconductor wafer 11, so that the line is re-wired. 18 is electrically connected to the electrode pad 110 of the semiconductor wafer 11. Thereafter, the entire package 13 is diced to complete a package structure without a package substrate. By eliminating the package substrate, the package is made light, thin, and short to meet the trend of modern electronic products.

However, in the manufacturing method of the conventional semiconductor package 1, the Molding compound is used as the insulating material 12, and the Young's modulus is large, so that it is hard and brittle, so the semiconductor package 1 is tilted. The degree of warpage is large, so that the alignment between the subsequently formed line redistribution structure 18 and the electrode pad 110 of the semiconductor wafer 11 will be offset, and when the offset tolerance is too large, the line redistribution structure 18 will The electrode pad 110 of the semiconductor wafer 11 cannot be connected, which causes the electrical connection between the circuit redistribution structure 18 and the semiconductor wafer 11 to be greatly affected, thereby causing problems such as low yield and poor product reliability.

Furthermore, the formation of the line redistribution structure 18 only on one side of the package body 13 has failed to meet the multiplex requirements of the terminal product.

Therefore, 遂 developed a structure as shown in Figures 1 and 1 to make the seal Both sides of the package 13 can be connected to a circuit board, a semiconductor wafer, a passive component 1b or other package 1a.

As shown in FIGS. 1' and 1', the conventional semiconductor package 1' is embedded in a semiconductor wafer 11 inside a first surface 13a of a package body 13, and has a first connection between the semiconductor package 11 and the package body 13. The conductive vias 14 of the second surface 13a, 13b, and the first and second circuit redistribution structures 15, 16 respectively formed on the first and second surfaces 13a, 13b of the package body 13 to make the first line The redistribution structure 15 is electrically connected to the semiconductor wafer 11 , and the conductive via 14 is electrically connected to the first and second circuit redistribution structures 15 , 16 , so that the semiconductor wafer 11 is electrically connected to the conductive via 14 and the first a two-line redistribution structure 16. Further, a conductive element 17 such as a solder ball is formed on the first circuit redistribution structure 15 to connect an electronic device such as a circuit board (not shown), and re-distribute to the second line. The structure 16 is connected to an electronic structure such as a semiconductor wafer, a passive component 1b or another package 1a.

In the process of the semiconductor package 1 ′, a dielectric material such as ABF (Ajinomoto Build-up Film) or other dielectric material having a small Young's modulus is used as the insulating material 12 to press the semiconductor wafer 11 , thereby avoiding The warpage is too large to perform subsequent RDL and other processes.

However, in the process of the semiconductor package 1 ′, the dielectric structure of the semiconductor package 1 ′ is not good due to the use of a dielectric material having a small Young's modulus, so that the semiconductor wafer, the passive component 1 b or the subsequent connection is performed. In the case of the other package 1a, the structure of the lower package 13 may be warped or the second line redistribution structure 16 may collapse (e.g., the dotted line range A of the first figure).

Moreover, because the Young's coefficient of the semiconductor wafer 11 and the dielectric material are too large, the stress is concentrated on a portion of the first line redistribution structure 15, and the first line redistribution structure 15 is broken ( Crack) (as in the dotted line range B) of the 1st and 1st figures.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: a package having opposite first and second surfaces, and at least one semiconductor embedded in the first surface of the package An element having a plurality of active and non-active surfaces, and having a plurality of electrode pads on the active surface; a plurality of support members formed in the package and located on a periphery of the semiconductor element, and the support members Is electrically insulated from the semiconductor component, and the support member includes a first columnar portion and a second columnar portion that is disposed in the first columnar portion; and a reinforcing portion that is coupled to the second adjacent portion Between the supports.

The invention provides a method for fabricating a semiconductor package, comprising: providing a package having a first surface and a second surface opposite to each other, wherein the first surface of the package is embedded with at least one semiconductor component and a plurality of first pillars The semiconductor component has opposite active and inactive surfaces, and has a plurality of electrode pads on the active surface, and the first pillars are located on the periphery of the semiconductor component; forming a communication relationship between the first surface and the first surface a second surface extending through the plurality of perforations of the first columnar portion and forming a groove communicating between the perforations; and forming a second columnar portion in each of the perforations to make the second columnar shape a portion is formed in the first column portion to form a support member with the first column portion, the support members are electrically insulated from the semiconductor element, and a reinforcing portion is formed in the groove to make each The support members are connected by the reinforcing portion.

In the above manufacturing method, the process of the package includes: disposing the semiconductor element and the first columnar portions on a carrier; and covering the semiconductor component and the first columnar portions with an insulating material to form The package, and the first surface of the package is bonded to the carrier; and the carrier is removed.

In the foregoing semiconductor package and method of manufacturing the same, the package system is a rectangular body, and the through holes are located at four corners of the rectangular body.

In the foregoing semiconductor package and method of fabricating the same, the active surface of the semiconductor component is flush with the first surface of the package.

In the above semiconductor package and the method of manufacturing the same, the material of the first columnar portion and the second columnar portion is different.

In the above semiconductor package and method of manufacturing the same, the reinforcing portions are electrically insulated from the semiconductor device. Further, the material of the reinforcing portion is made of metal.

In the foregoing semiconductor package and method of manufacturing the same, the first circuit redistribution structure is disposed on the first surface of the package, and the first circuit redistribution structure is electrically connected to the semiconductor component.

In addition, in the foregoing semiconductor package and the manufacturing method thereof, the second circuit redistribution structure is further disposed on the second surface of the package, and the second circuit redistribution structure is electrically connected to the semiconductor component.

It can be seen from the above that the semiconductor package of the present invention and the manufacturing method thereof are designed by the support member and the reinforcing portion having no electrical function to increase the strength of the package and thereby increase the structural strength of the semiconductor package, so Insulating materials with a large Young's coefficient or smaller can avoid various problems of the prior art.

1,1',2‧‧‧ semiconductor package

1a‧‧‧Package

1b‧‧‧ Passive components

10,20‧‧‧Carrier

100‧‧‧heating release layer

11‧‧‧Semiconductor wafer

11a, 21a‧‧‧ active face

11b, 21b‧‧‧ inactive surface

110,210‧‧‧electrode pads

12,22‧‧‧Insulation

13,23‧‧‧Package

13a, 23a‧‧‧ first surface

13b, 23b‧‧‧ second surface

14‧‧‧Electrical through holes

15,25‧‧‧First line redistribution structure

16,26‧‧‧Second line redistribution structure

17,27‧‧‧Conducting components

18‧‧‧Line redistribution structure

200‧‧‧ bonding layer

21‧‧‧Semiconductor components

24,24’‧‧‧Support

240‧‧‧Perforation

241‧‧‧first columnar

242‧‧‧Second column

34‧‧‧ Strengthening Department

340‧‧‧ trench

A, B‧‧‧ dotted line range

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; FIGS. 1' and 1' are schematic cross-sectional views showing other aspects of a conventional semiconductor package; FIGS. 2A to 2G are A schematic cross-sectional view of a method of fabricating a semiconductor package of the invention; wherein, the 2A' is a top view of FIG. 2A; the 3A is a 3D view of the 3D view; and the 3B is a 3A A perspective view of another embodiment.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Relative relationship Changes or adjustments are also considered to be within the scope of the invention.

2A to 2G are schematic cross-sectional views showing a method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 having a bonding layer 200 is provided, and a plurality of semiconductor elements 21 and a plurality of first pillars 241 are disposed on the bonding layer 200, and then covered by an insulating material 22. The semiconductor element 21 and the first pillar portion 241 form a package body 23.

In this embodiment, the size of the carrier 20 can be selected as a wafer type substrate or a panel form substrator, and the bonding layer 200 is a release film or a rubber material. .

Furthermore, the package body 23 is a rectangular body and has a first surface 23a and a second surface 23b opposite thereto, and the semiconductor elements 21 are embedded inside the first surface 23a of the package body 23.

Moreover, the semiconductor device 21 is a wafer having an active surface 21a and a non-active surface 21b. The active surface 21a is bonded to the bonding layer 200, and has a plurality of electrode pads 210 on the active surface 21a. The active surface 21a of the semiconductor element 21 is flush with the first surface 23a of the package body 23.

In addition, the material of the first columnar portion 241 is different from the material of the insulating material 22, and the first columnar portion 241 is made of a semiconductor material, such as a crucible, and the first columnar portions 241 are located on the semiconductor elements 21 The periphery of the package body 23 is exposed, and the first columnar portions 241 are located at four corners of the package body 23, as shown in FIG. 2A'.

As shown in FIG. 2B, the carrier 20 and the bonding layer 200 are removed, and the first columnar portion 241, the first surface 23a of the package body 23, and the active surface 21a of the semiconductor element 21 are exposed.

As shown in FIG. 2C, a plurality of through holes 240 connecting the first surface 23a and the second surface 23b are formed in the first columnar portion 241, and when the through holes 240 are formed, the package body 23 is first. The surface 23a and/or the second surface 23b are formed to communicate with the grooves 340 between the respective through holes 240 as shown in FIG. 3B.

As shown in FIG. 2D, the second columnar portion 242 is formed in each of the through holes 240, and the second columnar portion 242 is inserted into the first columnar portion 241 to make the first columnar portion 241 The second columnar portion 242 constitutes a support member 24, and a reinforcing portion 34 is formed in the groove 340, as shown in Fig. 3A, so that the support members 24 are coupled to each other by the reinforcing portion 34.

In this embodiment, the second columnar portion 242 is a metal post, such as a copper post, and the material of the reinforcing portion 34 is a metal such as copper.

Furthermore, as shown in FIG. 3B, in another embodiment, the plurality of support members 24' are arranged in a ring shape to form a cubic bracket, that is, in the package body 23 except at four corners of the package body 23. At the four edges. Therefore, the cube holder is designed by a No-Contact method, and the more the support member 24', the higher the strength of the package body 23.

Moreover, the reinforcing portion 34 can be formed on one side of the package body 23 (that is, on one of the first surface 23a or the second surface 23b) or on both sides (ie, on the first surface 23a and the second side). Surface 23b).

As shown in Figure 2E, a redistribution layer is implemented. The first circuit redistribution structure 25 is formed on the first surface 23a of the package body 23 and the active surface 21a of the semiconductor component 21, and the first circuit redistribution structure 25 is electrically connected to the semiconductor component. 21 electrode pad 210.

In this embodiment, the support member 24, 24' or the reinforcing portion 34 may be connected to the first line redistribution structure 25 as required, as shown by the thick oblique line in the figure, but not electrically connected to the semiconductor element. 21, the support members 24, 24' and the reinforcing portion 34 are electrically insulated from the semiconductor element 21.

As shown in FIG. 2F, a line redistribution layer (RDL) process is performed, that is, a second line redistribution structure 26 is formed on the second surface 23b of the package body 23, and the second line redistribution structure 26 can be used according to requirements. The second line redistribution structure 26 is electrically connected to the first line redistribution structure 25 or to the semiconductor element 21 by a technique of conducting holes.

In this embodiment, the support member 24, 24' or the reinforcing portion 34 can be connected to the second circuit redistribution structure 26 as required, as shown by the thick oblique line in the figure, but not electrically connected to the semiconductor component. 21, the support members 24, 24' and the reinforcing portion 34 are electrically insulated from the semiconductor element 21.

As shown in FIG. 2G, a conductive element 27 such as a solder ball is formed on the first line redistribution structure 25 to electrically connect the conductive element 27 to the semiconductor element 21.

The present invention is designed to increase the strength of the edge of the package 23 by the support members 24, 24' of the semiconductor element 21 having no electrical function, thereby increasing the structural strength of the semiconductor package 2, so that the material is softer ( Or insulating material 22 with a small Young's coefficient, can still avoid the conventional reason for Young's coefficient A small dielectric material that causes the structural strength of the package to be poor. Therefore, when the semiconductor wafer, the passive component or other package is subsequently attached, the semiconductor package 2 of the present invention does not warp, and the second wiring redistribution structure 26 does not collapse.

Moreover, when the Young's modulus of the semiconductor element 21 and the insulating material 22 are too large, the strength of the edge of the package 23 is increased by the support members 24, 24', so that stress is dispersed in the support member 24, 24' Therefore, the stress is not concentrated on a portion of the first line redistribution structure 25, so that the problem of the first line redistribution structure 25 being broken can be avoided.

Moreover, the present invention can also use the insulating material 22 having a larger Young's coefficient or a Young's modulus of the semiconductor element 21. Although it is hard and brittle, the package is increased by the support members 24, 24'. The strength of the edge 23 can reduce the degree of warpage of the semiconductor package 2. Therefore, when the first line redistribution structure 25 is formed, the alignment between the first line redistribution structure 25 and the electrode pads 210 of the semiconductor element 21 can be prevented from being shifted, thereby avoiding the first line redistribution. The electrical connection between the structure 25 and the semiconductor element 21 is greatly affected, so that problems such as low yield and poor product reliability can be avoided.

In addition, the strength of the second columnar portion 242 is assisted by the design of the first columnar portion 241, and when the material of the first columnar portion 241 is a semiconductor material, it is combined with the semiconductor element 21 Since the coefficient of thermal expansion (CTE) is the same, the coefficient of thermal expansion of the package body 23 is more uniform, so that the problem of edge warpage can be avoided.

On the other hand, the reinforcing portion 34 is used between the support members 24, 24'. Connected to increase rigidity. Therefore, the present invention forms a cubic bracket design by fitting the support members 24, 24' with the annular structure formed by the reinforcing portion 34 (or formed by the partial first and second circuit redistribution structures 25, 26). The strength of the package 23 can be greatly increased, thereby increasing the structural strength of the semiconductor package 2.

The semiconductor package 2 of the present invention comprises: a package 23 having a first surface 23a and a second surface 23b opposite thereto, a plurality of supports formed in the package 23 and communicating the first surface 23a and the second surface 23b 24, 24', and a reinforcing portion 34 coupled between the two adjacent support members 24, 24'.

A plurality of semiconductor elements 21 are embedded inside the first surface 23a of the package body 23, and the package body 23 is a rectangular body, so that the support members 24, 24' are located at at least four corners of the rectangular body. .

The semiconductor device 21 has an active surface 21a and an inactive surface 21b, and has a plurality of electrode pads 210 on the active surface 21a, and the active surface 21a of the semiconductor component 21 is flush with the package 23 First surface 23a.

The support members 24, 24' are located at the periphery of the semiconductor component 21, and are electrically insulated from the semiconductor component 21, and the support members 24, 24' are disposed by a first columnar portion 241 and The second columnar portion 242 of the first columnar portion 241 is formed. In this embodiment, the first columnar portion 241 and the second columnar portion 242 are made of different materials.

The reinforcing portion 34 is electrically insulated from the semiconductor element 21, and the material of the reinforcing portion 34 is metal.

In one embodiment, the semiconductor package 2 includes a first circuit redistribution structure 25, which is disposed on the first surface 23a of the package body 23, and the first circuit redistribution structure 25 is electrically connected to the first circuit. Semiconductor element 21.

In one embodiment, the semiconductor package 2 includes a second circuit redistribution structure 26 disposed on the second surface 23b of the package 23, and the second circuit redistribution structure 26 is electrically connected to the second package 23 Semiconductor element 21.

In summary, the semiconductor package of the present invention and the method for fabricating the same are mainly used to increase the strength of the package by the design of the support member and the reinforcement portion having no electrical function to the semiconductor device, thereby increasing the structure of the semiconductor package. strength.

Furthermore, by the design of the annular structure (consisting of the support member and the reinforcing portion), the strength of the package body can be further increased, thereby increasing the structural strength of the semiconductor package.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

21‧‧‧Semiconductor components

23‧‧‧Package

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧Support

241‧‧‧first columnar

242‧‧‧Second column

25‧‧‧First line redistribution structure

26‧‧‧Second line redistribution structure

27‧‧‧Conducting components

Claims (17)

A semiconductor package includes a package having opposite first and second surfaces, and the package has at least one semiconductor component embedded in a first surface thereof, the semiconductor component having an opposite active surface a non-active surface having a plurality of electrode pads on the active surface; a plurality of support members formed in the package and located at a periphery of the semiconductor component, wherein the support members are electrically insulated from the semiconductor component, and the support The member includes a first columnar portion and a second columnar portion that is disposed in the first columnar portion; and a reinforcing portion that is coupled between the two adjacent supports. The semiconductor package of claim 1, wherein the package system is a rectangular body, and the support members are located at four corners of the rectangular body. The semiconductor package of claim 1, wherein the active surface of the semiconductor component is flush with the first surface of the package. The semiconductor package of claim 1, wherein the first columnar portion and the second columnar portion are different in material. The semiconductor package of claim 1, wherein the reinforcing portions are electrically insulated from the semiconductor device. The semiconductor package according to claim 1, wherein the material of the reinforcing portion is metal. Such as the semiconductor package described in claim 1 of the patent scope, including The first circuit redistribution structure is disposed on the first surface of the package, and the first circuit redistribution structure is electrically connected to the semiconductor component. The semiconductor package of claim 1 or 7, further comprising a second circuit redistribution structure disposed on the second surface of the package, and the second circuit redistribution structure electrically connecting the semiconductor element. A method of fabricating a semiconductor package, comprising: providing a package having an opposite first surface and a second surface, wherein the package has at least one semiconductor component and a plurality of first pillars embedded in a first surface thereof; The semiconductor device has opposite active and inactive surfaces, and has a plurality of electrode pads on the active surface, and the first pillars are located on the periphery of the semiconductor component; forming a communication between the first surface and the second surface And penetrating through the plurality of perforations of the first columnar portion and forming a groove communicating between the perforations; and forming a second columnar portion in each of the perforations, the second columnar portion is disposed in the first columnar portion a support portion is formed in the columnar portion and the first column portion, the support members are electrically insulated from the semiconductor element, and a reinforcing portion is formed in the groove, so that the support members are separated by The reinforcing portions are connected. The method of manufacturing the semiconductor package of claim 9, wherein the process of the package comprises: disposing the semiconductor component and the first columnar portions on a carrier; wrapping the insulating material a semiconductor element and the first columnar portions, Forming the package, and the first surface of the package is bonded to the carrier; and removing the carrier. The method of fabricating a semiconductor package according to claim 9, wherein the package system is a rectangular body, and the through holes are located at four corners of the rectangular body. The method of fabricating a semiconductor package according to claim 9, wherein the active surface of the semiconductor component is flush with the first surface of the package. The method of fabricating a semiconductor package according to claim 9, wherein the first columnar portion and the second columnar portion are made of different materials. The method of fabricating a semiconductor package according to claim 9, wherein the reinforcing portions are electrically insulated from the semiconductor device. The method of fabricating a semiconductor package according to claim 9, wherein the material of the reinforcing portion is metal. The method of fabricating a semiconductor package according to claim 9 further comprising forming a first line redistribution structure on the first surface of the package, and the first line redistribution structure electrically connecting the semiconductor element. The method of manufacturing the semiconductor package of claim 9 or 16, further comprising forming a second line redistribution structure on the second surface of the package, and the second circuit redistribution structure electrically connecting the semiconductor element.