TW201435901A - Memory system - Google Patents

Abstract

A memory system according to an embodiment of the present invention is characterized in comprising a cell array including a plurality of unit cell arrays each having a plurality of first lines, a plurality of second lines and a plurality of memory units, and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage. The access circuit provides the first and second lines connected to the memory cells of access target with access potentials, and brings at least one of the first and second lines connected to the memory cells of non-access target into a floating state, so as to make access to the memory cells of access target. The unit cell array includes a plurality of first spare lines to provide redundancy for the plurality of first lines, and a specific number of the first spare lines are arranged on the same side as the plurality of the first lines with a predetermined cycle.

Description

Memory system

Embodiments of the invention relate to a memory system.

As a technology for realizing a large-capacity memory system, a variable-change memory cell such as a ReRAM or an ion memory is attracting attention. Since the memory cells can be formed in a cross-point type between the wirings, it is possible to easily construct a cell array having a three-dimensional structure.

The resistance variable memory cells have an asymmetrical characteristic having a voltage-current characteristic that differs greatly depending on the direction of the bias applied to the memory cell. Further, for a cell array using a three-dimensional structure of a memory cell having such asymmetrical voltage-current characteristics, the so-called floating access mode access operation is effective. Here, the access operation of the floating access method means that the selection line of the access target is set to the potential required for the access of the memory cell, and the access line of the non-access is made to be in the floating state. the way.

Here, consider the cost of the chip of the memory system. In terms of the cost of the chip, the larger the area occupied by the cell array with respect to the area of the wafer, the lower the memory system of the large capacitance can be realized at a low cost. However, in the case of using a memory cell having a three-dimensional structure of the above-described cross-point type memory cell, in general, a peripheral circuit of a decoder or driver of a large size is required. Therefore, in order to increase the area occupied by the cell array with respect to the wafer area, it is necessary to make the cell array larger.

However, if the cell array is increased, of course, the occurrence of the failure of the memory cell will also increase. Therefore, in such a memory system, the processing of the fault memory unit becomes an important issue.

Embodiments of the present invention provide a memory system with excellent data retention characteristics.

The memory system according to the embodiment is characterized in that, in the case where three directions orthogonal to each other are the first direction, the second direction, and the third direction, a cell array having a plurality of unit cell arrays and the unit cell array is provided a plurality of first wirings extending in the first direction, a plurality of second wirings extending in the second direction, and respective intersections of the plurality of first wirings and the plurality of second wirings a plurality of memory cells having different resistance state memory data; and an access circuit for accessing the memory cell via the first wiring and the second wiring; and the memory cell is applied with a specific voltage of the first polarity The resistance state transitions from the first resistance state to the second resistance state, and when a specific voltage of the second polarity having a polarity opposite to the first polarity is applied, the resistance state transitions from the second resistance state to the first resistance state The access circuit is configured to perform access required for accessing the memory unit to the first wiring and the second wiring connected to the memory unit to be accessed. Bits, and at least one of the first wiring and the second wiring connected to the memory cell that is not accessed, in a floating state, accessing the memory cell of the access target, the unit cell array having a plurality of spare first wirings extending in the first direction in which the plurality of first wirings are redundant, and a plurality of spare first wirings arranged in a predetermined number on the same side of the plurality of first wirings .

According to the embodiment, a memory system having excellent data retention characteristics can be provided.

Acc‧‧‧ control signal

BL‧‧‧ bit line

I‧‧‧cell current

M0~M3‧‧‧ PMOS transistor

M10‧‧‧NMOS transistor

M11‧‧‧NMOS transistor

M12~M17‧‧‧ PMOS transistor

M18‧‧‧NMOS transistor

M4~M7‧‧‧ NMOS transistor

M8‧‧‧ PMOS transistor

M9‧‧‧ PMOS transistor

MC‧‧‧ memory unit

MCd‧‧‧Fault memory unit

N0‧‧‧ input node

N1‧‧‧ input node

N2‧‧‧ input node

N3‧‧‧ input node

Na‧‧‧ node (anode)

Nc‧‧‧ node (cathode)

SA‧‧‧Sense Amplifier

The sum of SET‧‧‧8 spare units and the peripheral circuits that control the sum

Ssp‧‧‧ control signal

su_eSEL‧‧‧Selection signal

su_oSEL‧‧‧Selection signal

Subl‧‧‧ spare unit

Suwl‧‧‧ spare unit

SW_B‧‧‧Switch Circuit

SW_L‧‧‧Switch Circuit

SW_R‧‧‧ Switching Circuit

SW_T‧‧‧ Switching Circuit

Tx‧‧‧ control signal

V1‧‧‧specific potential

Vdd‧‧‧Power potential

Vpp‧‧‧ potential

Vreset‧‧‧Reset voltage

Vset‧‧‧Set voltage

Vss‧‧‧ Ground potential

WL‧‧‧ character line

xyB‧‧‧ data line

xyBL‧‧‧ terminal

xyL‧‧‧ terminal

xySB‧‧‧ data line

Fig. 1 is a view showing the overall configuration of a memory block of the memory system according to the first embodiment of the present invention.

Figure 2 is a diagram showing the composition of the MAT of the same memory block.

Fig. 3 is a view showing the configuration of the MAT and its peripheral circuits of the same memory block.

Figure 4A is a diagram showing circuit marks of memory cells of the same memory block.

Fig. 4B is a graph showing the voltage-current characteristics of the memory cells of the same memory block.

Fig. 5 is a view for explaining the bias state of the cell array in the holding step of the FLA of the memory block.

Figure 6 is a diagram illustrating the bias state of the cell array at the initial step of the FLA of the memory block.

Figure 7 is a diagram illustrating the bias state of the cell array in the alternate step of the FLA of the memory block.

Figure 8 is a diagram illustrating the bias state of the cell array in the active step of the FLA of the memory block.

Figure 9 is a circuit diagram of a sense amplifier of the same memory block.

FIG. 10 is an operation waveform diagram of the sense amplifier shown in FIG. 9.

Figure 11 is a diagram showing the construction of a sense amplifier system of the same memory block.

Figure 12 is a diagram showing the construction of a current sensing system of the same memory block.

Figure 13 is a diagram illustrating redundant replacement of the same memory block.

Fig. 14 is a view showing the configuration of the MATRIX and its peripheral circuits of the same memory block.

Figure 15 is a circuit diagram of the SL drv circuit block of the same memory block.

Figure 16 is a diagram showing the layout of the SL drv circuit block of the same memory block.

Figure 17 is a circuit diagram of the SL blk circuit block of the same memory block.

Fig. 18 is a timing chart of the failure detecting portion of the SL blk circuit block of the same memory block.

Figure 19 is a diagram showing the composition of the SL group circuit block of the same memory block.

Figure 20 is a circuit diagram of the SSL blk circuit block of the same memory block.

Figure 21 is a diagram showing the construction of an SSL group circuit block of the same memory block.

Fig. 22 is a view showing the configuration of a bit line spare unit of the same memory block.

Figure 23 is a diagram showing the construction of a word line spare unit of the same memory block.

Fig. 24 is a view showing the connection configuration of the bit line spare unit with respect to the MAT of the same memory block.

Fig. 25 is a view showing the connection configuration of the MAT word line spare unit with respect to the same memory block.

Figure 26 is a diagram showing the configuration of the TILE of the same memory block.

Fig. 27 is a view showing the configuration of the same memory system.

Fig. 28 is a view showing the layout of the SL drv circuit block of the memory block of the memory system of the second embodiment.

Figure 29 is a circuit diagram of the SL drv circuit block of the same memory block.

Figure 30 is a circuit diagram of the SL drv circuit block of the same memory block.

Figure 31 is a diagram for explaining the bias state of the cell array in the step of maintaining the FLA of the memory block.

Figure 32 is a diagram showing the bias state of the cell array at the initial step of the FLA of the memory block.

Figure 33 is a diagram showing the bias state of the cell array in the standby step of the FLA of the memory block.

Figure 34 is a diagram showing the bias state of the cell array in the active step of the FLA of the memory block.

Figure 35 is a graph showing the change in potential of the bit line when the active step of the FLA of the memory block is changed.

Figure 36 is a graph showing the change in potential of a word line when the active step of the FLA of the memory block is changed.

Figure 37 is a graph showing the change in potential of the bit line when the active step of the FLA of the memory block is changed.

Figure 38 is a graph showing the change in potential of a word line when the active step of the FLA of the memory block is changed.

Figure 39 is a graph showing the change in potential of the bit line when the active step of the FLA of the memory block is changed.

Figure 40 is a graph showing the change in potential of a word line when the active step of the FLA of the memory block is changed.

Figure 41 is a graph showing the change in potential of the bit line when the active step of the FLA of the memory block is changed.

Figure 42 is a graph showing the change in potential of a word line when the active step of the FLA of the memory block is changed.

Figure 43 is a diagram showing the construction of the MATRIX and its peripheral circuits of the same memory block.

Figure 44 is a circuit diagram of the SL blk circuit block of the same memory block.

Fig. 45 is a timing chart of the failure detecting portion of the SL blk circuit block of the same memory block.

Figure 46 is a diagram showing the construction of the SL group circuit block of the same memory block.

Figure 47 is a circuit diagram of the SSL blk circuit block of the same memory block.

Figure 48 is a diagram showing the construction of an SSL group circuit block of the same memory block.

Fig. 49 is a view showing the connection configuration of the bit line spare unit with respect to the MAT of the same memory block.

Figure 50 is a diagram showing the connection configuration of the MAT word line spare unit with respect to the same memory block.

Hereinafter, a memory system according to an embodiment will be described with reference to the drawings.

[First Embodiment]

First, the overall configuration of a memory block used in the memory system according to the first embodiment of the present invention will be described.

Fig. 1 is a view showing the configuration of a memory block in the first embodiment. The memory block is provided with a cell array. The cell array has a plurality of unit cell arrays (hereinafter referred to as "MAT"). Each MAT has a plurality of bit lines BL and a plurality of word lines WL, and a memory cell MC selected by the word lines WL and the bit lines BL. In the following description, the bit line BL and the word line WL are also referred to as the general term "selection line". Also, say below In the description, the bit line BL is used as the first wiring, and the word line WL is used as the second wiring. Of course, it should be noted that the word line WL can be used as the first wiring and the bit line BL can be used as the second wiring. .

On the bit line BL of the cell array, the control bit line BL is electrically connected to perform data erasing of the memory cell MC, data writing to the memory cell MC, and data read circuit from the memory cell MC ( Hereinafter, the data erased from the memory cell MC and the data written to the memory cell MC are collectively referred to as "write operation", and the data read from the memory cell MC is referred to as "read operation". Actions and read actions are collectively referred to as "access actions"). The row control circuit includes a bit line driver for setting the potential required for the access operation to the bit line BL, and detecting and amplifying the current flowing in the memory cell MC during the reading operation to determine the memory unit MC. The sense amplifier SA of the data.

On the other hand, on the word line WL of the cell array, a column control circuit for selecting the word line WL during the access operation is electrically connected. The column control circuit has a word line driver that sets the potential required for the access operation to the word line WL. In addition, the column control circuit is included in the access circuit together with the row control circuit.

Next, the configuration of the MAT and its peripheral circuits will be described.

In addition, here, one of the row direction (first direction) is also referred to as "front" (first side), the other is referred to as "back" (first side), and the column direction (second direction) is also referred to. One is called "right", the other is called "left", and one of the directions (third direction) orthogonal to the row direction and the column direction is referred to as "up" and the other is referred to as "down".

Fig. 2 is a view showing the configuration of the MAT of the memory block of the embodiment.

The MAT has a plurality of bit lines BL extending in the row direction, a plurality of word lines WL extending in the column direction, and intersections of intersections formed between the plurality of bit lines BL and the plurality of word lines WL Type memory unit MC (not shown). In the following description, the cell array or MAT constituted by such a cross-point memory cell MC is also referred to as a "cross-point cell array" or a "cross-point type MAT".

In addition, the following description assumes that the bit line BL, the word line WL, and the memory cell MC are arranged substantially at a minimum pitch. Therefore, among the plurality of bit lines BL, the bit lines BL arranged in the odd-numbered numbers and the bit lines BL arranged in the even-numbered numbers are extracted from the MAT front side and the MAT rear side, respectively. The same is true for the word line WL. Hereinafter, the bit line arranged in the odd number is also referred to as "odd bit line", and the bit line arranged in the even number is referred to as "even bit line", which will be arranged in the odd numbered character. The line is called "odd number element line", and the line of characters arranged in the even number is called "even number element line".

Next, the configuration of the MAT and its peripheral circuits will be described.

Fig. 3 is a view showing the arrangement of the MAT of the memory block of the embodiment and its peripheral circuits. In the figure, as a peripheral circuit, a bit line multiplexer BL mux having a selected bit line BL is displayed, and a bit line BL selected by the bit line multiplexer BL mux is connected to the bit line BL. The data of the memory cell MC is used to detect and amplify the sense amplifier SA, and the word line multiplexer WL mux that selects one word line WL.

The bit line multiplexer BL mux includes a bit line multiplexer BL mux<1> disposed on the MAT front side and selecting the odd bit line BL, and a bit arranged on the MAT rear side to select the even bit line BL. Line multiplexer BL mux<2>. In addition, the bit line multiplexer BL mux<1:2> is included in the row control circuit 2.

The sense amplifier SA has a sense amplifier SA<1> that detects and amplifies the data of the memory cell MC via the odd bit line BL, and senses and amplifies the data of the memory cell MC via the even bit line BL. Amplifier SA<2>. The sense amplifiers SA<1:2> are formed on the semiconductor substrate on the lower side of the MAT. Thereby, an increase in the area of the wafer accompanying the configuration of the sense amplifiers SA<1:2> can be suppressed. Further, the sense amplifier SA<1> is in the first half of the MAT configuration area, and the sense amplifier SA<2> is disposed in the latter half of the MAT configuration area, respectively, in the column direction.

The word line multiplexer WL mux has a word line multiplexer WL mux<1> arranged on the left side of the MAT and an odd digital element line WL, and an even number element arranged on the right side of the MAT. Line WL word line multiplexer WL mux<2>.

The odd bit line BL emerges from the front side of the MAT, and extends to the lower side to be connected to the bit line multiplexer BL mux<1>. Then, the output of the bit line multiplexer BL mux<1> is connected to the sense amplifier SA<1> using the region between the MAT and the bit line multiplexer BL mux<1>. Regarding the connection relationship, the odd bit line BL, the bit line multiplexer BL mux<2>, and the sense amplifier SA<2> are also the same.

The odd digital element line WL extends from the right side of the MAT and extends to the lower side to be connected to the word line multiplexer WL mux<1>. Regarding the connection relationship, the odd digital element line WL and the word line multiplexer WL mux<2> are also the same. Further, the number of word lines WL and the like connected to the word line multiplexer WL mux<1:2> is smaller than the number of selection lines connected to the bit line multiplexer BL mux<1:2>. Therefore, in the region between the MAT and the word line multiplexer WL mux<1:2>, the arrangement of the large capacitance data bus or the like can be performed relatively freely.

Next, the description will be given of the memory cell MC.

4A is a view showing a circuit symbol of the memory cell MC of the memory block of the embodiment, and FIG. 4B is a view showing voltage-current characteristics of the memory cell MC of the memory block of the embodiment. Hereinafter, the node Na shown in FIG. 4A will be referred to as "anode", and the node Nc will be referred to as "cathode". Further, the direction from the anode Na shown by the arrow in Fig. 4A toward the anode Nc is referred to as "forward direction", and the opposite direction is referred to as "reverse direction". Therefore, the potential of the cathode Nc is lower than the bias of the anode Na to the forward bias, and the potential of the cathode Nc is higher than the bias of the anode Na to the reverse bias.

The memory cell MC includes a variable resistance element that memorizes data according to different resistance states of the variable resistance element. Hereinafter, the state of the memory cell MC in which the variable resistance element is in the high resistance state is referred to as "reset state", and the state of the memory cell MC in which the variable resistance element is in the low resistance state is referred to as "set state". Further, an operation of changing the memory cell MC in the reset state to the set state is referred to as a "setting operation", and an operation of changing the memory cell MC in the set state to the reset state is referred to as a "reset operation". Therefore, the write action system contains "Set Action" and "Reset Action".

The memory cell MC has the properties of a solid electrolyte. As shown in FIG. 4B, the voltage-current characteristic is asymmetrical according to the direction of the bias voltage (the polarity of the applied voltage). As can be seen from FIG. 4B, the voltage-current characteristic of the memory cell MC can be approximated by I~A exp(αV) (A, α-system constant) except for the vicinity of the applied voltage V=0. In the case where the forward bias is applied to the memory cell MC in the reset state, the reverse bias is applied to the memory cell MC in the reset state and the coefficient α in the case where the reverse bias is applied to the memory cell MC in the set state is the same degree. . On the other hand, the coefficient α in the case where the forward bias is applied to the memory cell MC in the set state becomes extra large. In addition, in the vicinity of the applied voltage V=0, In I becomes ±∞.

When a forward bias is applied to the memory cell MC in the reset state, the applied voltage V is in the range from 0 V to the set voltage Vset, and the memory cell MC maintains the reset state, and the cell current I flowing in the memory cell MC It changes reversibly according to the change of the applied voltage V (arrow a0). Then, when the applied voltage V becomes equal to or higher than the set voltage Vset, the state of the memory cell MC is irreversibly shifted from the reset state to the set state (setting operation) (arrow a1).

On the other hand, when a forward bias is applied to the memory cell MC in the set state, the cell current I flowing in the memory cell MC reversibly changes in accordance with the change in the applied voltage V (arrow a2). However, the memory cell MC in the set state does not transition to the reset state even if the applied voltage V is increased as long as the forward bias is applied.

When a reverse bias is applied to the memory cell MC in the reset state, the cell current I flowing in the memory cell MC reversibly changes according to the change in the applied voltage V (arrow a3). However, the memory cell MC in the reset state is limited to the application of the reverse direction bias, and does not change to the set state even if the applied voltage V is increased.

On the other hand, when a reverse bias is applied to the memory cell MC in the set state, the voltage is applied from 0 V to the range of the reverse bias voltage from 0 V to the voltage -Vreset (hereinafter referred to as "reset voltage"). Inside, the memory cell MC maintains the set state, and the cell current I flowing in the memory cell MC reversibly changes according to the change of the applied voltage V (arrow a3). Of course Thereafter, when the applied voltage V becomes equal to or lower than the voltage -Vreset, the state of the memory cell MC is irreversibly shifted from the set state to the reset state (reset operation).

In addition, the memory cell MC has a reset state of the high resistance state of the variable resistance element and a set state of the low resistance state of the variable resistance element, and the intermediate state of the reset state and the set state is a weak reset state. . The weak reset state is an unstable state that is easy to transition to a set state or a reset state.

Next, the access operation to the memory cell MC will be described.

Fig. 3 is a view showing the arrangement of the MAT of the memory block of the embodiment and its peripheral circuits.

When the MAT and its peripheral circuits are configured as shown in FIG. 3, in order to increase the occupation ratio of the memory cell MC with respect to the entire wafer, it is only necessary to increase one MAT. Thereby, the relative size of the peripheral circuits can be reduced. However, if the MAT is increased, the rate of occurrence of the fault memory cell MC in the MAT will increase. Moreover, the fault memory unit MC usually short-circuits the bit line BL and the word line WL. Therefore, even if it is one fault memory unit MC, it will cause an influence on the MAT as a whole.

Therefore, in the present embodiment, a method of replacing the fault memory cell MC in the memory block using the so-called floating access method (hereinafter referred to as "FLA") will be specifically described.

In the following description, the memory unit to be accessed is also referred to as an "access memory unit", and the other memory unit is referred to as a "non-access memory unit", and the bit line connected to the access memory unit is connected. It is called "access bit line", and other bit lines are called "non-access bit lines". The word line connected to the access memory unit is called "access word line", and other words are used. The meta-line is called a "non-access word line", and the general name of the access bit line and the access word line is called an "access selection line", and the non-access bit line and the non-access word line are called. The general term is called "non-access selection line."

Here, FLA basically means setting the access selection line to a specific access potential required for access of the memory cell MC, and on the other hand, making the non-access selection line floating. The access mode of the dynamic state. In the following, a memory block MC in which a bit line BL is connected to an anode Na, a memory cell MC in which a word line is connected to a cathode Nc, and a read operation by a forward bias is taken as an example. .

5 to 8 are views showing a bias state of a cell array (MAT) of the FLA of the memory block of the embodiment. In these figures, the black memory cell MCa accesses the memory cell, and the memory cell MCd labeled with × is the fault memory cell.

The FLA is implemented in four steps according to the holding step, the initial step, the spare wiring, and the active step.

First, in the holding step shown in FIG. 5, all the bit lines BL and all the word lines WL are brought into a floating state (Vs~ in the figure) at a potential Vs close to the ground potential Vss. Here, the "~" appended to the potential means that it is in a floating state in the state of this potential. In the holding step, regardless of the presence or absence of the fault memory unit MCd, a certain bias state is formed.

Next, in the initial step shown in FIG. 6, all the bit lines BL are set to the potential Δ, all the word lines WL are set to the potential Vset-Δ, and the reverse bias voltage Vset-2Δ is applied to all the memory cells MC. Here, "△" means a forward bias (dead zone voltage) in which the memory cell MC is regarded as a high resistance state regardless of the state of the memory cell MC. Thereby, the memory cell MC in the set state is shifted to the weak reset state. At the same time, a selection line for causing a short-circuit failure due to an abnormality in current flowing from the word line WL to the bit line BL is specified, and the specific selection line is immediately set as the failure line potential ζ. In the case of FIG. 6, a short-circuit failure occurs between the bit line BL<4> and the word line WL<2> due to the memory cell MCd.

Next, in the standby step shown in FIG. 7, the bit line BL<4> and the word line WL<2> short-circuited due to the fault are maintained at the fault line potential ζ, and on this basis, the access will be included. The odd bit line BL of the bit line BL<3> is set to the potential Vset/2, and the even bit line BL is set to the potential Δ. Further, the odd digital element line WL including the access word line WL<3> is set to the potential Vset/2, and the even digital element line WL is set to the potential Vset-Δ.

Finally, in the active step shown in FIG. 8, the access bit line BL<3> is set to the set potential Vset, and the access word line WL<3> is set to the ground potential Vss. The bit line BL<4> and the word line WL<2> short-circuited due to the failure are set as the fault line potential ζ. Further, the other non-access bit line BL and the other non-access word line WL are in a floating state (Δ-εb)~, (Vset-Δ+εb)~, respectively. Here, εb represents the average amount of voltage drop on the bit line BL according to the sum of the small leakage currents of the dead zone voltages of the memory cells MC, and εw represents the minute leakage current according to the dead zone voltage of the memory cell MC. The average amount of voltage drop across the sum word line WL.

In the active step, although the non-access selection line is in a floating state, at this time, the potential of the non-access selection line largely changes due to the influence of the coupling with the adjacent selection line. At this point, the generation of interference can be envisaged. However, in the present embodiment, since the adjacent selection lines are necessarily driven by the driver MAT and disposed on the opposite side, the potential setting of the drivers is different in the standby step, thereby suppressing the occurrence of interference. .

Next, the sense amplifier SA will be described. First, the circuit configuration of the sense amplifier SA will be described.

If there is a fault memory cell MCd, a current fluctuation that overlaps with the cell current flowing through the access bit line BLa is caused. Therefore, in the present embodiment, as the sense amplifier SA, a current comparison type sense amplifier that is not affected by the fluctuation is used. That is, in the same MAT, the access word line WLa is set to be the shared reference bit line BLr. At this time, the fluctuation current overlapping with the reference cell current Ir flowing through the reference bit line BLr and the access cell current Ia flowing through the access bit line BLa is the same. As a result, when the reference cell current Ir and the access cell current Ia are compared, the state of the memory cell MC can be read.

Here, as an example of the sense amplifier SA, a current comparison type sense amplifier SA that compares small currents at high speed will be described.

Fig. 9 is a circuit diagram of a sense amplifier SA of the memory block of the embodiment.

The sense amplifier SA is composed of PMOS transistors M0 to M3, M8, M9, M12 to M17, and NMOS transistors M4 to M7, M10, M11, and M18.

The transistors M0, M8, M10, M2, and M4 are connected in series between a specific power supply potential Vdd and a ground potential Vss. The source of the transistor M6 is connected to the gates of the transistors M0, M2 and M4, and the drain is connected to the ground potential Vss.

The transistors M1, M9, M11, M3, and M5 are connected in series between the power supply potential Vdd and the ground potential Vss. The source of the transistor M7 is connected to the gates of the transistors M1, M3 and M5, and the drain is connected to the ground potential Vss.

The control signal /act is input to the gates of the transistors M8 and M9. The control signal vLTC is input to the gates of the transistors M10 and M11. The gate of the transistors M6 and M7 inputs the control signal /se that controls the sensing of the sense amplifier SA. The output node N2 between the transistors M2 and M4 is connected to the gates of the transistors M1, M3 and M5 and the source of the transistor M7. The output node N2 becomes the output signal "out". The output node N3 between the transistors M3 and M5 is connected to the gates of the transistors M0, M2 and M4 and the source of the transistor M6. The output node N3 becomes the output signal "/out".

The source of the transistor M12 is connected to the drain of the transistor M16, the drain is connected to the input node N0 between the transistors M10 and M2, and the gate is connected to the drain and the gate of the transistor M14. The source of the transistor M16 is connected to a specific potential V1, and the drain is connected to the sources of the transistors M12 and M14. The gate of the transistor M12 and the drain and gate of the transistor M14 become the input signal "in".

The source of the transistor M13 is connected to the drain of the transistor M17, the drain is connected to the input node N1 between the transistors M11 and M3, and the gate is connected to the drain and the gate of the transistor M15. The transistor M13 is different in size from the transistor M12. The source of the transistor M17 is connected to the potential V1, and the drain is connected to the sources of the transistors M13 and M15. The gate of the transistor M13 and the drain and gate of the transistor M15 become the input signal "/in". The control signal /accREAD is input to the gates of the transistors M16 and M17.

Further, the source of the transistor M18 is connected to the potential Vpp, and the drain is connected to the potential V1. The gate of the transistor M18 is set to the potential Vw during the write operation and to the potential Vr during the read operation.

The sense amplifier SA is determined by comparing the access unit current Is with the reference cell current Ir to determine the resistance state stored in the memory unit MCs as information, even if the current is compared for several tens of nA or less. The detection is performed at high speed and surely.

In the input section of the sense amplifier SA, a current mirror circuit composed of transistors M12, M14, and M16 and a current mirror circuit composed of transistors M13, M15, and M17 are provided. The current of the input signal "/in" is configured to be 1/10 of the current of the input signal "in". Thereby, even when the reference memory cell MCr is in the set state, in the read operation, only the reference cell current Ir which is smaller than the maximum value of the selected cell current Is and larger than the selected cell current Is, flows into the sense amplifier SA. 1/10 current. This current is used as the reference current Ir ' of the sense amplifier SA.

The two current mirror circuits are operated by the potential V1. This potential V1 is the one in which the potential Vpp and the current are limited by the transistor M18. The transistor M18 is set to the potential Vw during the write operation and to the potential Vr during the read operation. Thereby, the potential of the bit line BL at the time of the access operation can be switched.

Next, the basic operation of the sense amplifier SA will be described.

FIG. 10 is an operation waveform diagram of the sense amplifier SA shown in FIG.

First, when the control signal /act is lowered from "H" to "L" in the state where the control signal /se = "H" (the step S0 in Fig. 10), the pair of the transistors M8 and M9 are turned on. Thereby, a current flows in the sense amplifier SA.

Next, the control signal /accREAD is lowered from "H" to "L" (step S1 of FIG. 10), and the input bit line BLa and the reference bit line are input by inputting signals "in" and "/in". Current flows on the BLr. By the pair of transistors M6 and M7 interrupted from the linear region through the saturation region, the difference between the access cell current Ia flowing at this time and the reference current Ir ' of about 1/10 of the reference cell current Ir is taken as the drain voltage. The difference is amplified and latched.

To amplify the current difference between the access unit current Ia and the reference current Ir ' , the control signal /se is lowered from "H" to "L" (step S2 of Fig. 10). Thereby, the pair of transistors M6 and M7 are respectively closed from the linear region through the saturation region. At this time, the time difference of the transition to the saturation region due to the small difference between the access unit current Ia and the reference current Ir ' is converted into the drain voltage. Then, when the source potential of the transistor M6 is high, since the gate potentials of the transistors M0 and M2 become high, the transistors M0 and M2 are turned off. On the other hand, when the source potential of the transistor M7 is high, since the gate potentials of the transistors M1 and M3 become high, the transistors M1 and M3 are turned off. Thus, the drain voltage difference between the pair of transistors M6 and M7 is amplified.

The pair of transistors M10 and M11 reduces the gate potential at the initial stage of sensing to suppress conductance, thereby reducing the sense amplifier current from the power supply potential Vdd, and further strongly reflects the state via the transistors M12 and M13 according to the state of the sense amplifier SA. The difference in cell current supplied by the pair.

At the initial stage of sensing, the balance of the sense amplifier SA collapses due to the current difference between the access unit current Ia and the reference cell current Ir, and after the stabilization, the control signal vLTC is made to have a potential Vrr higher than the power supply potential Vdd from the potential Vrr (FIG. 10). Step S3). Thereby, the power supply voltage is supplied to the sense amplifier SA, and the output signal "out" is fully swinged to the power supply potential Vdd (S4 of FIG. 10). At this time, the control signal /accREAD is raised, and the supply of the cell currents Ia, Ir to the sense amplifier SA is interrupted.

The alignment of the crystals constituting the miniaturization of the sense amplifier SA is deviated due to fluctuations in the manufacturing process. Therefore, the current path is such that as many components as possible are connected in series, and the deviation can be offset. Therefore, in the sense amplifier SA, the pair of transistors M0 and M1, the pair of transistors M8 and M9, and the pair of transistors M10 and M11 are formed between the power supply potential Vdd and the input nodes N0 and N1. In particular, the pair of NMOS transistors M10 and M11 suppresses the PMOS transistors M0 and M1 of the feedback loop constituting the operation of the sense amplifier SA. The effect of the pair on the deviation from the pair of transistors M8 and M9. In other words, the conductance of the NMOS transistors M10 and M11 is suppressed, and the potentials of the drains or sources of the PMOS transistors M0, M1, M8, and M9 on the power supply potential Vdd side are higher than those of the transistors M10 and M11. Conductance of PMOS transistors M0, M1, M8 and M9. That is, the conductance of the PMOS transistor and the NMOS transistor acts to suppress the influence of the characteristic deviation of each. This is only a case where the gate input control signal vLTC of the pair of NMOS transistors M10 and M11 is amplified and the control signal vLTC is amplified. Therefore, in the initial stage of sensing, the control signal vLTC is lowered in advance, and in the second half of the sensing of the data determination, the data is latched at a high speed, and the control signal vLTC is increased to increase the conductance of the transistor. In the case of FIG. 10, the control signal vLTC is set to a potential Vrr different from the power supply potential Vdd after sensing and before latching, and is set to a higher potential Vpp at the time of latching.

The time difference between the falling of the control signal /accREAD (step S1 of FIG. 10) and the falling of the control signal /SE (step S2 of FIG. 10) is the cell current injected into the sense amplifier SA after the falling of the control signal /accREAD After Ia and Ir are fully reflected in the input current of the sense amplifier SA, the sensing operation of the sense amplifier SA is started to be adjusted.

Next, an example in which a corresponding sense amplifier system is read simultaneously with a plurality of bits will be described.

Fig. 11 is a view showing the configuration of a sense amplifier system of the memory block of the embodiment.

The sense amplifier system is a sense amplifier system corresponding to a K-bit area bus (data bus), and is composed of K sense amplifiers SA<1:K>. A common control signal /act and independent control signals vLTC<k> and /se<k> are input to each of the sense amplifiers SA<k>(k=1~k). The sense amplifiers SA<1:K> share the reference memory cell MCr, and the input "/in<k>" of each sense amplifier SA<k> is connected in common to the shared reference memory cell MCr. Here, the ratio of the current mirror circuit of the input of the reference memory cell MCr side of each sense amplifier SA is K times. The reason is that the K sense amplifiers SA<1:K> share the reference memory cell MCr. At this time, the amount of the reference current Ir ' of the average one sense amplifier SA is 1/K times as large as the case where the reference memory cell MCr is used by one sense amplifier SA. In other words, when the reference memory cell MCr is shared by the K sense amplifiers SA, a current of K times the case where the reference memory cell MCr is used by one sense amplifier SA is introduced from each of the sense amplifiers from the reference current Ir '. SA can be.

According to the sense amplifier system described above, since each sense amplifier SA<k> corresponds to each bit of the data on the area bus, the K bit data can be simultaneously detected and amplified.

Next, the current sensing system of the memory block will be described. The current sensing system described herein reads the corresponding party simultaneously with the multi-bit.

Fig. 12 is a view showing a configuration example of a current sensing system of the memory block of the embodiment. A cell array, a sense amplifier SA, a regional bus, and the like are shown in FIG.

The current sensing system has a sense amplifier SA<k> corresponding to each bit line BL<k>. The bit line BL<k> is connected to the area bus line <k> via the resistance element R1 and the bit line switch (BL switch), respectively. Furthermore, the area bus line <k> is connected to the input "in" of the sense amplifier SA<k>.

Here, the resistive element R1 has a structure other than the metal layer in the structure of the memory cell MC. Therefore, for the sake of convenience, as shown in FIG. 12, the resistance element R1 is represented by a circuit symbol which changes the triangle of the circuit symbol of the memory cell MC into a quadrangle. Further, the bit line switch includes a NOT circuit G1 to which an input "out<k>" of the sense amplifier SA<k> is connected, and a PMOS transistor M1 connected in series between the output of the NOT circuit G1 and the ground potential Vss. And a NOT circuit G2 of the NMOS transistor M2, and an NMOS transistor M3 provided between the resistance element R1 and the area bus line <k> and having an output of the NOT circuit G2 connected to the gate. The control signal /cdec<k> of the selected row is input to the NOT circuit G2.

On the other hand, the reference bit line BLr is connected to the reference area bus (ref local bus) via the resistance element R1 and the reference bit line switch (BLr switch). Again, the reference area The busbar system is commonly connected to the input/in of the sense amplifiers SA<1:K>. The reference bit line switch includes an NMOS transistor M4 provided between the resistive element R1 and the reference area bus. The transistor M4 is controlled by a control signal set/read that is enabled when the action/read operation is set.

Further, an NMOS transistor M5 is provided between each of the word lines WL and the ground potential Vss. The control signal rdec of the selection column is input to the gate of the transistor M5.

According to the asymmetrical voltage-current characteristic of the memory cell MC, the most current flowing in the memory cell MC is after the transition of the variable resistance element of the memory cell MC to the low resistance state by the setting action. Therefore, in the case of the current sensing system shown in FIG. 12, since the cell current is limited without depending on the response of the circuit, the resistor element R1 which is a resistor having a relatively high resistance is connected to each bit line BL. In this case, the overcurrent to the memory cell MC can be prevented by the voltage drop caused by the resistive element R1. Further, since the resistance element R1 is connected to each of the bit lines BL, the propagation of the interference potential generated in each bit line BL can be alleviated, which is suitable for FLA.

Further, in the case of the current sensing system of Fig. 12, the resistive element R1 is connected to the layer of the bit line BL, so that the wiring connected to the bit line switch is disposed on the same layer as the word line WL.

Further, since one memory cell MC accessed by each bit line BL is one, the resistance element R1 connected to one end of the bit line BL is equivalent to the resistance element R1 connected in series to each memory cell MC. As such, in the case of the current sensing system of FIG. 12, since the resistive element R1 is disposed outside the cell array 1, it is easy to adjust the value of the resistive element R1, thereby achieving effective current limitation.

Next, as an example of the memory block in the present embodiment, a memory block including a plurality of intersection type MATs and performing FLA for each MAT will be described.

In the case of the memory block, in order to increase the cell occupancy rate and to manufacture a memory chip having a lower cost, it is necessary to increase each MAT and increase the number of memory cells MC included in each MAT. However, if the number of memory cells MC of each MAT is increased, of course, in each MAT, A higher probability produces a fault memory unit MCd. Therefore, in the memory block of this embodiment, the processing of the fault memory unit MCd is important.

Therefore, the redundancy replacement method of the normal memory cell MC can be effectively explained by reducing the influence of the fault memory cell MCd on the MAT.

In the cross-point type MAT, when the fault of the memory unit MC is an open fault, since the data stored in the memory unit MC is fixed to the data corresponding to the reset state, for other normal memory cells MC in the MAT, Access without problems. On the other hand, when the failure of the memory cell MC is a short-circuit fault, since the selection lines connected to the memory cell MC are short-circuited, the normal memory cell MC that is accessible is greatly restricted according to the processing method thereof. It becomes a problem.

In order to eliminate this problem, the processing method of the bit line BL and the word line WL which are short-circuited by the fault memory cell MCd at the same fault line potential ζ is fixed. In this manner, it is only necessary to restrict access to the memory cell MC connected to at least one of the bit line BL and the word line short-circuited due to the failure.

However, in the case of this processing method, of course, if the size of the MAT becomes large, the number of memory cells MC whose access is restricted is also increased, which causes a problem that the use efficiency of the memory cell MC is greatly impaired.

Therefore, as a processing method of this problem, a method of redundantly replacing the fault memory cell MCd with another memory cell MC has been proposed. Hereinafter, the redundant memory cells, bit lines, and word lines that are replaced in the event of a fault are also referred to as "alternate memory cells", "alternate bit lines", and "alternate word lines", respectively. Also, the spare bit line and the spare word line are collectively referred to as an alternate selection line. If this processing method is used, the number of usable memory cells MC does not largely change even in the event of a short-circuit failure.

Fig. 13 is a view showing a configuration example of the MAT in the case of using the processing method. The memory cell MCd<0> shown by the white square in the figure is an open fault memory unit, and the memory cells MCd<1:2> shown by the black circle are short-circuit fault memory cells. Also, the diagonal lines in the figure are shown The area is an alternate memory unit area configured with a spare memory unit, a spare bit line, and a spare word line. In addition, in FIG. 13, in order to easily understand the outline of the processing method described herein, the spare memory cell area is collectively arranged at the end of the MAT, but it can be automatically replaced, and the circuit scale can be reduced. Configured in the MAT.

First, after detecting a short-circuit fault due to a current flowing between the bit line BL and the word line WL, the bit line BL and the word line WL are set to the fault line potential ζ, and at the same time, the access bit is set. The source line BL and the access word line WL are replaced with the spare bit line BL ' and the spare word line WL ', respectively . In the case of FIG. 13, the bit line BL<1> and the word line WL<1> short-circuited by the fault memory cell MCd1 are replaced with the spare bit line BL ' <1> and the spare word line WL ', respectively. 1>, the bit line BL<2> and the word line WL<2> short-circuited by the fault memory cell MCd<2> are replaced with the spare bit line BL ' <2> and the spare word line WL ', respectively. 2>. The replacement of the bit line BL and the word line WL is performed automatically, and there is no need to evaluate the fault at the time of replacement or perform a special operation accompanying the replacement. Therefore, when an access operation is performed, the presence or absence of a failure does not occur from the outside.

Here, in the area to be added as a spare memory cell, it is necessary to add an equal number of spare bit lines BL ' and spare word lines WL ' . The reason is that in the case of the cross-point type MAT, an equal number of bit lines BL and word lines WL cannot be accessed due to a short-circuit failure. Further, the spare memory unit is set in an amount corresponding to the number of memory cells MC that cannot be accessed due to the assumed short-circuit failure, so that the number of memory cells MC that can be actually used effectively by MAT does not largely vary.

However, it may not be replaced due to a malfunction or other malfunction of the spare memory unit itself. At this time, the memory cell MC connected to the selection line that cannot be accessed due to the short-circuit failure is processed as the memory cell MC in which the fixed data is stored, and is handled as a substantial accessor.

The features of the processing method for the fault memory unit described above are summarized as follows.

As a first feature, the open fault memory unit (MCd<0> of Fig. 13) is regarded as a variable power The resistance element is a memory unit with a high resistance state, that is, a reset state, and therefore does not affect the potential setting during the access operation. The open fault memory unit cannot be accessed, but is handled as a fixed data memory.

As a second feature, the short-circuit failure memory unit (MCd<1:2> in FIG. 13) is an appropriate processing method because the variable resistance element is a low-resistance element. As a processing method, the bit line (BL1 and BL2 in FIG. 13) and the word line (WL1 and WL2 in FIG. 13) short-circuited by the short-circuit fault memory cell are set to the same fault line potential ζ, and the short-circuit fault memory unit is not Apply a bias voltage. However, in the case where the size of the MAT is large, the number of memory cells MC that can be used is largely changed. Therefore, in order to avoid this, the spare memory cell area is set in advance, and the replacement of the fault memory unit or the like is automatically performed.

Next, the configuration of the memory block in the case where the size of the MAT is large and the arrangement example of the spare memory cell area will be described.

Here, the terms used below will be described in advance. In addition, an example of a specific number shown here can be arbitrarily set according to the style of the memory block.

The term "SL group" refers to the sum of 128 adjacent selections and the peripheral circuits that control the sum. The selection line is alternately driven from the opposite sides of the MAT, so when considering one SL group, the selection line driven from one side of the MAT is 64. The SL group is the smallest unit for controlling the selection line, and only one selection line is selected from one SL group. Further, the spare memory unit area is also constituted by SL group units. In addition, the SL group in the spare memory unit area is also referred to as "SSL group".

The term "standby unit" refers to the sum of SL groups having one SSL group as redundancy, and the peripheral circuits that control the sum. When the number of bit lines BL constituting MAT is different from the number of word lines WL, the size of each spare unit arranged in the row direction is of course different from the size of each spare unit arranged in the column direction. However, even in this case, it is necessary to make the number of spare cells arranged in the row direction the same as the number of spare cells arranged in the column direction. The reason is the processing method of the fault memory unit as described above. In addition, the spare unit of the bit line BL is also referred to as a "bit line backup unit", and the spare unit of the word line WL is referred to as a "word line backup unit".

The term "SET" refers to the sum of eight spare units and the peripheral circuits that control the sum. In the following description, in order to distinguish from the general settings, all are capitalized as "SET". The SET of the bit line BL and the SET of the word line WL are arranged in the same number to form one MAT. The SET of the bit line BL is also referred to as "bit line SET", and the SET of the word line WL is referred to as "word line SET".

The so-called "MATRIX" refers to a group of 8 MATs. In the following description, in order to distinguish from the general matrix, all are capitalized as "MATR1X".

The term "TILE" refers to a method in which MATRIX is used as a component of a layout in a memory block. In the following description, in order to distinguish it from the general micro-bricks, all are capitalized as "TILE".

The above is the meaning of the terms used in the following description.

Next, a configuration example of a memory block will be described.

Fig. 14 is a view showing the configuration of the MATRIX and its peripheral circuits of the memory block of the embodiment. The memory block is composed of a plurality of MATRIX. The part enclosed by the broken line in the figure indicates MATRIX (TILE), and the area indicated by the oblique line extending in the MARIX in the row direction indicates the area of one bit line SET, and the area indicated by the oblique line extending in the column direction of MATRIX indicates one. The area of the word line SET size. Further, the spare units sub1 and suwl of the attached points in the figure indicate the enabled spare units sub1 and suwl.

On the premise of using a BCH ECC (144 bits) that can realize 2-bit correction, the bit line backup unit subl is composed of 36 SL groups and one SSL group totaling 37 (= 36 + 1). In addition, in FIG. 14, four bit line spare units sub1 are represented by one square. On the other hand, the word line backup unit suwl is composed of 16 SL groups and one SSL group totaling 17 (= 16 + 1).

One MAT system arranges the bit line SET in the column direction by 8 and the word line SET in the row. It is composed by arranging eight. That is, the column direction includes (36+1) × 8 × 8 selection line groups, and 296K (including 8K of spare memory unit areas) bit lines BL. Further, the row direction includes (16+1) × 8 × 8 SL groups, and 136K (including 8K of spare memory cell regions) word lines WL. That is, the data of 32 Gbits can be memorized in one MAT. At this time, the 0.25 TBit data can be memorized in the MATRIX containing the 8-layer MAT.

In the case shown in Fig. 14, the eight bit lines SET composed of the bit lines BL are vertically separated by four units, and the data in units of 72 bits are respectively transmitted from the upper and lower sides of each MAT. Row transfer. Therefore, a total of 288 (= 144 × 2) bits of data are transmitted from one MAT. The data is then processed in two ECC systems and becomes 256-bit = 32-bit data. Each of the element lines SET has a different SL group to which the bit line BL accessed from the opposite side of the MAT belongs, in each of the SL groups constituting the element, that is, the element line backup unit sub1. In other words, the bit line BL adjacent to the access bit line BL is necessarily decoded as the non-access bit line BL, and the non-access bit line BL adjacent to the access bit line BL is surely Floating state.

Regarding the word line WL, as shown in FIG. 14, in each word line SET, only one SL group is selected from one of the upper side and the lower side of the MAT, and only one word of the selected SL group is accessed. Yuan line WL.

The 72-bit busbar connected to each MAT is placed outside the MATRIX to overlap with other MAT busbars. As described above, the MATRIX laminate has eight MAT structures, and therefore, the busbars are arranged in eight layers. Then, the eight overlapping bus bars are concentrated on the corner of MATRIX into a 72-bit busbar and enter the sense amplifier SA under the TILE. From the sense amplifier SA, the busbars of 144 bits from the upper side and the lower side of the MAT extend outside the TILE as a busbar of 144 × 2 bits.

Further, in Fig. 14, the positions of the alternate selection lines (the squares of the thin oblique lines in the figure) are collectively displayed for each SET, and are actually distributed in units of eight SL groups. Also, the sum is enabled and the SET is separated by a slash, but the combination of the parts is enabled. It is performed by decoding, and thus is not limited to the pattern of FIG.

When the MATRIX of the configuration is configured as a plurality of TILEs to construct a memory block, a memory block of the TBit level can be created. For example, as shown in FIG. 14, each TILE processes data of 256 bits, and can construct a memory block that can realize 2-bit error correction in 128+16 bits.

In addition, in the following description, the sum of the plurality of SETs respectively arranged on the right side, the left side, the upper side, and the lower side of MAT is referred to as a driver block.

Next, the description will be given for the driver in the selection line block. The driver within the line block is selected to control the minimum unit of the selection line of the memory block.

Fig. 15 is a circuit diagram showing a SL drv circuit block constituting a driver in a selection line block of the memory block of the embodiment.

Since the selection lines are alternately driven from the opposite side of the MAT, the potential of the adjacent selection lines is set from the opposite driver. Moreover, the selection lines can be simultaneously set by the drivers. That is, in the case of FLA, it is possible to drive each of the SL drv circuit blocks on each side of the MAT to perform a selection line set to a floating state. The driver in the line block is selected to be a pair of SL drv circuit blocks opposite to each other on both sides of the MAT, and eight selection lines are driven from one side of the MAT, and a total of 16 selection lines are simultaneously driven from both sides.

As the set potential, there is an access line potential U<1> for driving the SL drv circuit block including the selection line of the access selection line, and a non-access line potential U<2 set for the other SL drv circuit block. >, and the fault line potential 对应 corresponding to the short-circuit fault generated on the memory cell MC or the selection line. The equipotential system is simultaneously set on the terminals xyL<1:8> connected to the eight select lines of the SL drv circuit block. The setting of the access line potential U<1> or the non-access line potential U<2> is complementary to the setting of the fault line potential ζ, and the control signal fail generated in each SL drv circuit block is controlled. /fail. When the control signal fail = "H" and the control signal /fail signal = "L", the eight terminals xyL<1:8> of the SL drv circuit are all fixed to the fault line potential ζ. This point has nothing to do with the access of the SL drv circuit block.

The selection signal for selecting the SL drv circuit block is blk, and the complementary selection signal is /blk. If the SL drv circuit block is accessed and the selection signal blk = "H", the terminals xyL<1:8> are all set to the access line potential U<1>. For the non-selected SL drv circuit block, since the selection signal /blk signal = "H", the terminals xyL<1:8> are all set to the non-access line potential U<2>.

In the eight terminals xyL<1:8>, one of the terminals connected to the terminal xyBL is selected, and the address signals A<1:2> and B<1:4> are used. The address signals A<1:2> and B<1:4> are signals common to all SL drv circuit blocks arranged on the MAT side.

The eight terminals xyL<1:8> are grouped in units of four, and any one of the address signals B<1:4> is "H", thereby selecting one total of two terminals xyL<n1 from each group. >(n1=1~4), xyL<n2>(n2=5~8). Then, the two selected terminals xyL<n1> and <n2> are further concentrated on one of the address signals A<1:2>. Any one of the address signals A<1:2> is "H", and any of the two terminals xyL<n1:n2> is selected. Thereby, decoding of the pair 1 of 8 connecting the terminal xyBL and any of the eight terminals xyL<1:8> is performed.

The determination signal for determining whether or not there is a short-circuit fault among the eight selection lines assumed by the SL drv circuit block is shrt. In the initial step of the FLA, all SL drv circuit blocks are non-selected, and the eight terminals xyL<1:8> are all set to the non-access line potential U<2>. At this time, the presence or absence of a short-circuit fault is determined based on the determination signal shrt. The determination signal shrt monitors the signal of the potential of the power supply node common to the eight terminals xyL<1:8>. When the selection line or the memory cell MC connected to the selection line is short-circuited, a large current flows in the terminal xyL<1:8> connected thereto. At this time, a large voltage drop occurs due to the resistance of the switching transistor M1 connected to each terminal xyL<1:8> constituting the SL drv circuit block, but the determination signal shrt is generated by this.

In addition, a circuit for monitoring the presence or absence of a short-circuit fault will be described later.

Next, an example of the layout of the SL drv circuit block will be described.

Figure 16 is a diagram showing the layout of the SL drv circuit block of the memory block of the embodiment. Figure. This figure shows the composition of the topology connection.

When the SL drv circuit block is laid out, the connection point of the eight selection lines of the MATRIX vertical drop from the right side of the figure and the eight terminals xyL<1:8> of the SL drv circuit block (the big black in the figure) The configuration of the circle), how to reduce the width of the transistor circuit becomes a problem.

The SL drv circuit block can be roughly divided into a potential setting unit and a decoding unit in layout. The potential setting unit includes an access line potential U<1>, a non-access line potential <2>, and a portion where the fault line potential ζ is mutually exclusive set to the selection line, and the decoding unit has an address signal A based on 1:2> and B<1:4> One of the eight terminals xyL<1:8> is selected, and the selected terminal xyL<n> (n=1 to 8) is connected to the terminal xyBL.

The structure shown by the hatching of Fig. 16 is a polysilicon having a gate and a wiring of a transistor. Further, the black metal wire which is mainly extended in the left-right direction in the drawing is the lowermost wiring metal layer, and the contact with the diffusion layer is indicated by a small black circle. The white thick wire power line and the address signal line extending in the up and down direction in the figure are indicated by a white circle.

Next, the SL blk circuit block will be described.

The aforementioned SL drv circuit block is a circuit that controls the minimum unit of the selection line. The SL blk circuit block is a circuit that controls the fault detection unit that automatically detects faults and performs redundancy control on the SL drv circuit block, and is a circuit that controls the minimum unit of redundancy.

Figure 17 is a circuit diagram of a SL blk circuit block of the memory block of the embodiment. In the figure (), it is the value used by the SL blk circuit block of the word line WL.

The fault detecting unit detects the level of the determination signal shrt and receives the control signal fail from the SL drv circuit block. The failure detecting unit has a failure detecting circuit including a current mirror type differential amplifying circuit U1 and a latch circuit U2.

The reference potential of the differential amplifier circuit U1 is required to perform the initial step of FLA. In the initial step, the bit line BL is set to the non-access line potential U<2>=Δ, and the word line WL is set to the non-access line potential U<2>=Vset-Δ, and the word line WL is made. The potential is set higher than the potential of the bit line BL. Therefore, the reference potential of the differential amplifier circuit U1 is in place. The SL blk circuit block of the element line BL is set to the potential Δ, and is set to the potential Vset-Δ in the SL blk circuit block of the word line WL. If there is a short circuit fault in the selected line or memory cell MC, the decision signal shrt is higher than the potential Δ in the SL blk circuit block of the bit line BL, and is lower than the potential Vset-Δ in the SL blk circuit block of the word line WL. . The SL blk circuit block of the bit line BL and the SL blk circuit block of the word line WL generate the control signal fail according to the determination signal shrt detected by the failure detecting unit by the same circuit, and therefore, in the bit line BL The input of the differential amplifier circuit U1 is changed in the SL blk circuit block and the SL blk circuit block of the word line W1. In the case of Fig. 17, in the SL blk circuit block of the word line WL, if there is a short-circuit failure in the selected line or memory cell MC, the output of the differential amplifier circuit U1 is made "L". Further, since the control signal fail becomes the potential ζ~Vset-Δ, first, the determination signal shrt is detected by the SL blk circuit block of the word line WL, and if there is a short-circuit failure, the potential of the word line WL is not accessed. The line potential U<2> is switched to the fault line potential ζ, and then the potential switching of the SL blk circuit block of the word line WL is made invisible to the SL blk circuit block of the bit line BL. On this basis, The SL blk circuit block detection determination signal shrt of the bit line BL switches the potential of the bit line BL associated with the short-circuit fault to the fault line potential ζ. If the order of detecting the SL blk circuit block of the word line WL and the SL blk circuit block of the bit line BL is reversed, the potential of the bit line BL is switched, and the short circuit fault is visible. The potential of the bit line BL is the same as the non-access line potential U<2> of the word line WL, so that the detection of the short-circuit fault is difficult.

Fig. 18 is a timing chart showing the failure detecting portion of the SL blk circuit block of the memory block of the embodiment.

The differential amplifier circuit U1 of the failure detecting unit activates the control signal ssp, and during the control signal ssp = "L", the high voltage corresponding to "H" is output from the differential amplifier circuit U1. This voltage acts as an initial setting of the latch circuit U2 of the lower stage. Therefore, when the control signal ssp is "L", the control signal tx of the transfer transistor M1 provided between the differential amplifier circuit U1 and the latch circuit U2 is "H", and the latch circuit U2 is initialized. After that, the control signal tx is again set to "L". When the control signal ssp is "H" and the application of the fault state of the differential amplifier circuit U1 is determined, the "H" pulse is applied as the control signal tx to turn on the transfer transistor M1, and the latch circuit U2 maintains the fault state. It becomes the control signals fail and /fail. As shown in FIG. 18, first, the fault state is latched on the latch circuit U2 of the SL blk circuit block of the word line WL, and thereafter, on the latch circuit U2 of the SL blk circuit block of the bit line BL. Latch fault status.

In addition, when the SL blk circuit block has been selected, the SL blk circuit block corresponds to the alternate select line, and generates an error signal /X for notifying the presence or absence of the fault in the SSL blk circuit block having the same configuration as the SL blk circuit block. The signal line of the error signal /X is pre-charged to "H", and is discharged based on the value of AND of the control signal blk for obtaining the SL blk circuit block and the control signal fail indicating the presence or absence of the fault, so that the error signal /X is "L". And notify the existence of the fault.

Further, the terminal xyBL of the SL blk circuit block is connected to the data line xyB via the transfer transistor M2 controlled by the control signal /fail and the transfer transistor M3 controlled by the selection signal blk.

Next, the SL group circuit block will be described. The SL group circuit block is a circuit composed of 8 SL blk circuit blocks.

Fig. 19 is a circuit diagram of a SL group circuit block of the memory block of the embodiment.

The data lines xyB from the eight SL blk circuit blocks are all connected in common. Moreover, if there is a fault in the selected SL blk circuit block, the data line xyB is extracted to the outside as it is. On the other hand, when there is a fault in the selected SL blk circuit block, any one of the error signals /X<1:8> of the corresponding SL blk circuit block becomes "L", corresponding to the SL. The alternate selection line of the group circuit block is connected according to the error signal X from the SSL group circuit block having the same structure as the SL group circuit block, the data line xySB of the SSL group circuit block and the data of the SL group circuit block. Line xyB is connected.

Next, the SSL blk circuit block described in the above description will be described.

Figure 20 is a circuit diagram of an SSL blk circuit block of the memory block of the embodiment.

The SSL blk circuit block is identical to the SL blk circuit block except for the error signal /X portion. That is, the short circuit fault detection and the deactivation of the SL blk circuit block are also performed in the SSL blk circuit block to eliminate the influence of the short circuit fault of the FLA. However, if there is a fault in the spare memory unit area corresponding to the SSL blk circuit block, it cannot be used as redundancy.

When the SSL blk circuit block is not faulty, if the selection signal blk of the SL blk circuit block rises, the data is always output to the common data line xySB. On the other hand, in the event of a fault, there is no need to connect to the external data line xySB. The initial setting of the error signal /X to notify the fault is made in the SSL blk circuit block. When the control signal acc that specifies the start of the access cycle rises, the precharge to the signal line of the error signal /X is stopped, and if there is a fault in the other SL blk circuit block, the signal line for the error signal /X is performed. Preparation for discharge.

The control signal acc represents the decoding period during which data is transmitted from the standby step of the FLA through the active step.

Next, the SSL group circuit block will be described.

Figure 21 is a circuit diagram of an SSL group circuit block of the memory block of the embodiment.

Like the SL group circuit block, the SSL group circuit block is also composed of 8 SSL blk circuit blocks. The data lines xySB<n> (n=1~8) from the eight SSL blk circuit blocks are common to become the data line xySB.

In the SSL group circuit block, whether or not the redundant error signal X and the normal signal OK of the reverse logic X are generated are generated. Include the SSL group circuit block, and obtain the NAND of the 8 error signals /X<1:8> which are common to the SL blk circuit blocks of each SL group circuit block, and generate the error signal X and the normal signal OK. .

Next, the spare unit will be described. As described above, the standby unit has one SSL group as the sum of the redundant SL groups. The bit line spare unit sub1 is different from the word line backup unit suwl. Here, for the bit line spare unit subl and word The composition of the line backup unit suwl is detailed.

Fig. 22 is a circuit diagram showing a bit line standby unit sub1 of the memory block of the embodiment.

The bit line spare unit sub1 is composed of a total of 37 SL group circuit blocks and a total of one SSL group circuit block for 36 SL group circuit blocks. The 36 SL group circuit blocks are divided into 18 SL group circuit blocks arranged in the odd number (hereinafter referred to as "odd SL group circuit blocks"), and 18 SL group circuit blocks arranged in the even number. (Hereinafter, it is called "even-number SL group circuit block"). Then, there are 18 area bus bars <1:18> which are connected in common with the odd-numbered SL group circuit block and the even-numbered SL group circuit block. Regarding the selection of the odd SL group circuit block, or the selection of the even SL group circuit block, it is determined according to the selection signals su_oSEL and su_eSEL. The data line xySB from the SSL group circuit block is connected to all of the 36 SL group circuit blocks.

In the memory block, the bit line backup unit sub1 of the above configuration is disposed on the left and right sides of the MAT. Memory 36-bit size data in a MAT. Further, the bit line BL extending from the left and right sides of the MAT is collected, and 64 × 2 bit lines BL are collectively grouped by the SL group circuit block. That is, the bit line spare unit sub1 is composed of 64 × 2 × 36 = 4608 bit lines BL and 128 spare bit lines BL. By the one bit line backup unit sub1, it is possible to perform simultaneous parallel access via 36 bits of a total of 36 area bus bars arranged on the left and right sides of the MAT. Further, in the present embodiment, the bit line BL adjacent to the access bit line BL is always made to be the non-access bit line BL, and the bit line backup unit sub1 is eliminated in order to eliminate the influence on the FLA caused by the coupling. The selection is made in a different way to the left and right sides of the MAT.

Figure 23 is a circuit diagram of the word line spare unit suwl of the memory block of the embodiment.

The word line side spare unit suwl is composed of a total of 17 SL group circuit blocks and a total of one SL group circuit block for one of the 16 SL group circuit blocks. The 16 SL group circuit blocks are divided into 8 odd SL group circuit blocks and 8 even SL group circuit blocks. Then, there are 8 selection signals BLG<1:8> signal lines and odd SL respectively The group circuit block and the even SL group circuit block are connected in common. Then, by the selection signal BLG, any one of the eight sets of SL group circuit blocks that are connected in common to the signal lines of one selection signal BLG is selected. Further, the selection of the odd-numbered SL group circuit block or the selection of the even-numbered SL group circuit block is determined based on the selection signals su_oSEL and su_eSEL.

In the memory block, the word line backup unit suwl having the above configuration is disposed on the upper and lower sides of the MAT. The word line spare unit suwl is composed of 2048 (= 64 × 2 × 16) word line WL and 128 spare word lines WL, and one word line WL is selected from MAT. When one word line spare unit suwl is selected, for example, NAND of each of the address signals /A<0:3>, /B<0:3>, /C<0:3> including four signals is obtained. For decoding, one of the 64 word line spare units suwl disposed on the upper side or the lower side of the MAT is selected. Further, only one of the upper side and the lower side of the MAT is selected to access the one word line WL from the MAT, and the word line WL is connected to the power supply potential V.

Next, the connection configuration of the bit line backup unit sub1 with respect to MAT will be described.

Fig. 24 is a view showing the connection configuration of the bit line spare unit sub1 with respect to the MAT of the memory block of the present embodiment.

The sum of the eight bit line spare units sub1, that is, the bit line SET, is arranged on the left and right sides of the MAT in units of eight. The 72-bit size data is transmitted from the respective cell line backup units sub1 arranged on one side via 72 area bus bars <1:72>. The 72 area bus bars <1:72> are commonly used in the four bit line backup units subl on the upper side and the lower side of the MAT, respectively. To extend the 18 data lines xyB from the bit line SET, and select 4 bit line spare units sub1 in each of the bit lines SET. In the example shown in FIG. 24, the upper four bit line backup unit sub1 and the lower four bit line backup unit sub1 are in the total bit line SET, and "_h" is on the upper side, and "on the lower side" on the lower side. _l" is marked on the selection signal su_eSEL to distinguish. Further, regarding the selection of the upper side and the lower side of the bit line SET, the selected one is indicated by a dotted point. Furthermore, the bit line spare unit subl is divided into the sum of the odd SL groups and the even number SL. The sum of the groups, by selecting the sum of either one, selects the 18 SL groups belonging to the sum. In FIG. 24, when the sum of the odd-numbered SL groups is selected, a diagonal line is applied to the upper half of the bit line spare unit sub1, and when the sum of the even-numbered SL groups is selected, the lower half of the bit-line spare unit sub1 Apply a diagonal line. The example shown in Fig. 24 is a case where the sum of odd SL groups is selected. Fig. 24 is an example in which the selection signal su_oSEL_h is selected for the left side of the MAT, and the selection signal su_oSEL_1 is selected for the right side of the MAT. In the case of using the FLA, in order to perform the access of the bit line BL as uniformly as possible in each MAT, the potential fluctuation in the MAT is smoothed, and the odd-numbered SL group and the even-numbered SL group are selected on the left and right sides of the MAT. Based on this, it is decided to select the upper side 4 or the lower side 4 in the bit line standby unit sub1 in the bit line SET.

From the upper left side and the lower left side, and the upper right side and the lower right side of the MAT, 72 data lines xyB are respectively extended, thereby arranging a total of 288 (= 72 × 4 = 144 × 2) bits in parallel. That is, in the example shown in FIG. 24, since the data of 144 bits constitutes a BCH code which can perform 2-bit error correction, it is possible to realize 288 bits which can be randomly corrected in units of 2 bits per 144 bits. The data transmission of the parallel.

Without being limited to the above configuration, even if the number of bits for further access is increased or the number of bits for error correction is increased, even if the selection method of the memory cell or the size of the data that can be transmitted in parallel is changed, the configuration shown in FIG. 24 can be obtained. The thinking method corresponds.

Next, the connection configuration of the word line backup unit suw1 with respect to MAT will be described.

Fig. 25 is a view showing the connection configuration of the MAT character line backup unit suw1 with respect to the memory block of the embodiment.

The word line spare unit suwl is composed of 16 SL group circuit blocks, which are divided into the sum of 8 odd-numbered SL group circuit blocks and the sum of even-numbered SL group circuit blocks. The sum of which SL group circuit blocks is selected is determined according to the selection signals su_oSEL and su_eSEL. The selection signals su_oSEL and su_eSEL are commonly supplied to the 16 SL group circuit blocks. Furthermore, which SL group circuit is selected The pair of blocks is determined based on the eight selection signals BLG<1:8>. The selection signals BLG<1:8> are commonly supplied to the respective word line backup units suw1.

Eight word lines SET are respectively arranged on the lower side of the MAT. One character line spare unit suwl is selected from the character line SET on the upper and lower sides of the MAT. That is, one is selected from 64 (= 8 × 8) word line spare units suwl. The selected character line SET is only from one side. In the case of Fig. 25, one of the character line backup units suwl located on the upper side is selected, and a dot is marked. The selection of the 64 word line spare unit suwl is determined by three address signals /A<0:3>, /B<0:3>, and /C<0:3> respectively containing four signals. One bit line WL is selected from MAT by the address signal /A~/C.

Heretofore, the configuration of the MAT and its peripheral circuits has been described. Next, a specific example of a case where the MATRIX in which the MAT is laminated is used as the TILE and the wafer is composed of the TILE will be described.

The memory blocks described herein are those that achieve the bandwidth of data transmission equivalent to or above the NAND flash memory of the 2010s. That is, the access actor is implemented by a data transfer rate of 16 MByte/s equivalent to that of the NAND flash memory. Further, the memory block has a cell array having a three-dimensional structure of a memory capacity of 1 TBit. Furthermore, the MAT's access cycle is 8 μs, which allows sufficient time for program and ECC calculations to be allocated.

Fig. 26 is a view for explaining the arrangement of the TILE of the memory block of the embodiment. Each of the TILEs has a memory capacity of 0.25 TByte.

Data from a 256-bit or 32-bit tuple is transmitted side by side from one TILE. Since it can be performed every 8 μs, the data transfer rate is 4 MByte/s. Considering the transmission rate of each TILE, four TILEs are arranged as shown in FIG. 26 to achieve the required performance, and if the four TILEs are substantially parallel accessed, the transmission of each TILE can be realized. Four times the rate is a transfer rate of 16 MByte/s. Since the access of each TILE is substantially independent, the data access of the 32-bit units can be simultaneously performed in parallel for the four TILEs by the memory interleaving. Therefore, in the case of new data, the initial access time tAC is 8 μs.

Further, in the case where the bandwidth is increased, for example, in the case of 32 MByte/s, the bus bar width in the wafer is changed from 144 × 2 bits to 144 × 4 bits, and the ECC system is also doubled. At this time, parallel data transfer processing for each TILE 64-bit tuple is performed.

Further, in the case of using a cross-point cell array of 20 nm pitch, the wafer size of the memory block is composed of four TILEs as shown in Fig. 26, and is about 140 mm ² .

When the wafer size of the memory block is large, the number of selection lines per MAT is about half as a practical range, and 16 TILEs can also constitute a memory block. When the number of TILEs is increased to the above, the characteristics of the memory unit of the present embodiment cannot be fully utilized depending on the occupation ratio of the memory cell MC and the like.

In the case of the aforementioned MATRIX, the memory cell characteristics of the respective wafers can be improved by the ECC. Further, the memory unit MC of the initial failure can be redundantly replaced with the spare memory unit MC or the like provided in the normal spare memory unit area of each MATRIX, based on the setting of the potential of the selection line.

Heretofore, the memory block of the present embodiment has been described. Next, an example of a configuration of a memory system using the P (peta) bit size of the memory block will be described.

Fig. 27 is a view showing an example of the configuration of a memory system of the embodiment.

The memory system has a plurality of memory modules formed by a plurality of memory blocks. Each memory block has four TILE<1:4> arranged up, down, left, and right in the figure. TILE is a regional classification of memory cells within a wafer that can function independently of other regions as the smallest unit of access control. In addition to the configuration shown in FIG. 1, the memory block includes a MATRIX and redundancy control circuit for controlling the MATRIX access operation and the MATRIX redundancy, and a data buffer for temporarily holding the MATRIX data, detecting and correcting the MATRIX. The error of the ECC system, and the I/O and command control circuits required to control the input and output of the MATRIX data and the MATRIX access.

The memory system is interchanged with the various signals or data of the data/command bus from the CPU directly or via the control circuitry. A memory module including a plurality of memory blocks becomes The unit to which the data/command bus is connected. The control of the ECC or redundancy of the characteristics of the memory unit is performed in each memory block. Moreover, even if the memory module is cut off from the system and stored, the data can be held non-volatilely. Thereby, the memory system can exchange memory modules to access new memory modules.

As described above, according to the present embodiment, power consumption can be reduced by using FLA. Moreover, since each memory block is constituted by a cross point type MAT, the manufacturing process can be simplified. Moreover, the memory system with better retention characteristics of the data can be provided by redundant replacement of the spare memory cell area.

[Second Embodiment]

In the second embodiment, an example in which the peripheral circuit of the MAT and the access operation to the memory cell MC are changed in the first embodiment will be described. Hereinafter, differences from the first embodiment will be mainly described.

First, the layout of the SL drv circuit block of the memory block of the second embodiment will be described.

Since the layout pitch of the selection lines is the minimum design size, the layout of the transistors for driving the selection lines is very strict when using the cross-point type MAT. Therefore, the layout of the SL drv circuit block in the following example is more effective.

Fig. 28 is a view showing the layout of the SL drv circuit block of the memory block of the embodiment. The representation of Figure 28 is based on Figure 16.

Within the SL drv circuit block, 10 wires extending in the same direction relative to the 16 select lines on the MAT can be used. Also, the number of transistors required is ensured by forming the gate of the transistor orthogonal to the select line. If the number of transistors required is increased, the arrangement area of the SL drv circuit block is increased, but by making the gate of the transistor orthogonal to the selection line, extending parallel to the side of the MAT, so that the layout does not It is not possible to ensure the required transistor.

The most important point in simplifying the configuration of the driver in the selection line block is to reduce the maximum number of signal lines disposed in the extending direction of the selection line in the SL drv circuit block, as shown in FIG. The case of the case is 10 articles. Hereinafter, the peripheral circuits of the MAT for achieving the number of signal lines and the access operation to the memory cell MC will be described.

Next, the circuit configuration of the SL drv circuit block will be described.

Fig. 29 is a circuit diagram showing the SL drv circuit block of the driver in the selection line block of the memory block of the embodiment.

In order to simplify the structure of the driver in the selected line block, the selection of the potential setting of the SL drv circuit block is minimized. In the cross-point type memory cell MC, as a countermeasure against a short-circuit failure, it is necessary to supply a fault line potential ζ to a pair of selection lines, and further, a set potential for forming a floating state is required. The setting power for forming the floating state is different from the access line potential U<1> in the case of access, and is different from the non-access line potential U<2> in the case of non-access, and tries to make it in SL drv The circuit block becomes a potential setting. The reason why the potential line U<1> and the non-access line potential U<2> are required as the potential is coupled by the adjacent selection lines, even if it is adjacent to the selection line as the access target. When the line change is selected, the non-accessed memory unit MC still transitions to avoid interference.

However, a plurality of selection lines are alternately driven from the opposite side of the MAT, so that the non-access selection line adjacent to the access selection line can be placed at a potential of the opposite driver side of the opposite side of the access side. . In the present embodiment, the potential setting of the selection line is performed using this situation.

First, access is only made from the drive block located on one side of the MAT, and the drive block located on the opposite side is not accessed. In the case of FLA, the potential setting at the time of non-access can be set to the non-access line potential U<2>. The set potential from the select line block located on the opposite side is utilized for masking of adjacent select lines. At this time, the following two methods are set by the potential of the selection line by the driver block located on the access side.

The first method is a method of fixing the set potential formed by FLA on each side of the MAT. That is, in the standby step, the potential of the selection line driven by the driver block on the access side is set to the access line potential U<1>, which is driven by the driver block located on the opposite side. The potential of the line selection is set to the non-access line potential U<2>. Then, after entering the active step, in the driver block on the access side, only the drive in the select line block of the select line for driving access is turned on, and on the other hand, the drive in the other select line block is turned off to save the non-existent The selection line is taken as the floating state of the access line potential U<1>. Further, the driver block located on the opposite side temporarily maintains the potential of the selection line at the non-access line potential U<2>, thereby temporarily shielding the fixed potential, and thereafter, causing the potential of the selection line to be in a floating state. The interference of the non-access memory unit MC is suppressed. In the case of the first method, in the current step, since the non-access line potential U<2> temporarily becomes a fixed potential, a through current flows instantaneously between the access selection line and the non-access line potential U<2>, but the memory is memorized. The suppression effect of the interference of the unit MC is large.

The second method is a method of setting the potential of the selection line by the driver block located on the access side to two stages. That is, in the standby step, all the selection lines driven by the driver block located on the access side are set as the non-access line potential U<2>, and all the selection lines driven by the driver blocks located on the opposite side are set as Non-access line potential U<2>. On this basis, on the access side of the MAT, in the second half of the standby step, the driver in the select line block that drives the access select line only according to the selection signal blk is kept turned on, and the driver in the other select line block is turned off. The access selection line is set to the access line potential U<1>. At this time, since all the selection lines driven from the driver blocks located on the opposite side are set to the non-access line potential U<2>, they act as a shield of the adjacent selection lines. As a result, no interference occurs when the access line potential U<1> of the access selection line is set. Thereafter, after entering the active step, the access side and the opposite side of the MAT are included, and the drive in the select line block of the non-access select line set to the non-access line potential U<2> is turned off, and the drive is turned off. The access selection line is in a floating state, and on this basis, the access line potential is given to the access line potential U<1>. In the case of this method, although interference occurs at the floating potential in the active step, the effect is not the degree of erroneous transition in the non-access memory cell MC. Based on this point, the second method can be said to be a method of maximizing the characteristics of the FLA.

If the voltage of the memory cell MC does not change when the voltage of approximately 10 V is not applied, The reliability of the transfer transistor of the SL drv circuit block becomes a problem. Therefore, next, the SL drv circuit block using the transfer transistor which maintains reliability and withstands high voltage on the one hand will be described.

Fig. 30 is a circuit diagram showing a SL drv circuit block constituting a driver in a selection line block of the memory block of the embodiment.

When the graph surrounded by a dotted line in the figure indicates the transfer transistor M1 shown by the thick line in the figure, when a high voltage is applied to the drain side and the closing voltage of the transistor is applied to the gate, no application is applied. Since the maximum voltage is applied, the two transfer transistors M2 and M3 are connected in two wales, so that the gate voltage X ' of the transfer transistor M2 close to the high voltage side is increased to the allowable voltage level to, for example, a floating level of +Vth. The gate bus potential of the transfer transistor M3 on the source side is brought close to its ground potential Vss to close the current bus. Thereby, the voltage load of each of the transistors M2 and M3 connected in the wales is reduced by the threshold voltage Vth of the transistor. At this time, the area required for the layout increases, and the setting of the gate potentials X and X ' is complicated, but the reliability of the SL drv circuit block can be realized even if a high voltage is required for the state transition of the memory cell MC. Higher action.

Next, the potential setting procedure in the case of accessing only from one side of the MAT will be described. Here, as an example, a case where the memory cell MC is in the set state will be described.

31 to 34 are views showing a bias state of the cell array of the FLA of the memory block of the embodiment. In FIGS. 31 to 34, the memory cell MCd indicated by × is a short-circuit fault memory unit. Further, () is the set potential of each selection line. When the potential of each of the selection lines is different depending on the presence or absence of the short-circuit fault, it is marked with "(the set potential in the case of no short-circuit fault) / (the set potential in the case of a short-circuit fault)".

First, in the holding step shown in Fig. 31, all of the selection lines are brought into a floating state at a potential Vs close to the ground potential Vss. At this time, the bias voltage applied to the memory cell MC is substantially zero, and the state of the memory cell MC is maintained according to the retention characteristics of the memory cell MC itself. hold.

Next, in order to start accessing to the MAT, all of the selection lines are simultaneously set with potential according to the initial steps. That is, as shown in Fig. 32, the potential Δ of the dead zone voltage level of the memory cell MC is set in the bit line BL, and the potential Vset-Δ is set in the word line WL. Thereby, a reverse bias of Vset-2Δ is applied to all of the memory cells MC.

In this initial step, two jobs are performed on the MAT. In the first operation, the memory cells MC in all the set states are in a weak reset state and are increased in resistance. Thereby, the memory cell C in the low resistance state in the MAT disappears. The second job is separated from the detection of the short-circuit fault memory unit MCd. The short-circuit fault memory cell MCd causes a comparable current to flow from the word line WL to the bit line BL by the reverse bias applied during the initial step. The short-circuit fault is detected based on the voltage drop caused by the current flowing in the selection line connected to the short-circuit fault memory cell MCd, and the selected line of the detected short-circuit fault is set to the fault line potential ζ (substantially Vset-Δ). At this time, no bias is applied to the short-circuit fault memory cell MCd, so current does not flow. In the FLA of the present embodiment, the processing of the short-circuit failure memory cell MCd is completed up to the initial step, and then the transition to the standby step is performed.

Next, in the standby step, the first or second method described with reference to Fig. 29 is used, but either method eventually becomes the bias state of the MAT shown in Fig. 33.

The first method described above is a method of fixing the set potential by arranging the driver for driving the selection line on the MAT side. The selection line for the driver drive from the access side of the MAT is set to the potential Vset/2. On the other hand, for the selection line driven from the driver located on the opposite side of the MAT, the bit line BL is set to the potential Δ, and the word line WL is set to the potential Vset-Δ. In the case of a short-circuit fault, the selection line driven from the same side as the selection line connected to the short-circuit fault memory unit MCd is set as the fault line potential ζ.

In the second method, the bit line BL and the word line WL are respectively set to a certain potential Δ, Vset-Δ by the driver block located on the opposite side of the MAT, and on the other hand, by the access side of the MAT. The driver block is divided into two stages: the previous stage and the latter stage. Select the line to set the potential. In the previous stage, the bit line BL is set to the potential Δ and the word line WL is set to the potential Vset-Δ regardless of the driver block located on the access side and the driver block located on the opposite side. In the latter stage, the driver block on the access side sets a new potential, potential Vset/2, to the select line, and the driver block on the opposite side causes the select line to be in a floating state. At this time, since the potential of the selection line in the floating state is set to the fixed potential Vset/2 by the driver block located on the access side, the selection line adjacent to the selection line does not interfere with the shielding effect.

Finally, in the active step, the bias state of the cell array shown in Fig. 34 is formed by any of the two processes described below.

In the first process, the access bit line BL is set to the set potential Vset, the access word line WL is set to the ground potential Vss, and the other selection lines are brought into a floating state. However, at this time, by using the driver in the selection line block on the opposite side of the MAT to keep the selection line at a fixed potential for a short time, the shielding effect of the capacitive coupling is exerted, and the elimination is performed by the access side. The driver block becomes the potential variation of the selection line of the floating state.

In the second process, the access bit line BL is set to the potential Vset, the access word line WL is set to the ground potential Vss, and the other selection lines are brought into a floating state. At this time, since the potential of the access selection line fluctuates, the selection line adjacent to the access selection line is disturbed, but the adjacent selection line is not problematic because it is set to the potential without interference.

In the active step of the above first or second process, as shown in FIG. 34, the potential of the bit line BL in the floating state is stabilized to a potential slightly lower than the potential Δ (Δ-εb), and the floating state is The potential of the element line WL is stabilized to be slightly higher than the potential of the potential Vset-Δ (Vset-Δ+εw).

When FLA is used, the through current between the stable fixed potentials can be eliminated, so that the MAT can be increased. It can be considered that the first process described above is to treat the charge which reduces the interference as a process of consuming current, and the second process is a process which allows interference in the harmless range and further reduces the current consumption.

Next, the potential change of the selection line at the time of the transition of the active step of the FLA will be described separately by some examples.

35 to 40 are diagrams showing changes in the potential of the selection line when the active step of the FLA of the memory block of the embodiment is changed. In each of the figures, the thick solid line is the potential of each of the selection lines when the standby step is completed. A thick line with a diagonal line indicates a potential as a reference, and is a fixed potential in the case of a short-circuit fault memory cell MCd. The thin solid line is supplied to the access line potential of the access selection line in the active step. The white line is the potential of the selection line after the floating state. Further, in each of the figures, the line potentials U<1>, V<1>, the non-access line potentials U<2>, and V<2> at the time of the active step are surrounded by a broken line frame and displayed.

The first example is an example in which the memory cell MC is set to the state in which the above-described first process is utilized in the active step. The potential change of the access bit line BL and the non-access bit line driven by the driver block located on the access side of the MAT of the example is shown in the left diagram of FIG. 35, which is driven by the driver block on the opposite side. The potential change of the access bit line BL is shown in the right diagram of FIG. 35. The potential change of the access word line WL and the non-access word line WL driven by the driver block on the access side is shown in the left figure of FIG. The potential change of the non-access word line WL driven by the driver block on the non-access side is shown in the right diagram of FIG.

At this time, in the initial stage of the active step, the selection line driven by the driver block on the opposite side of the MAT is instantaneously set to a fixed potential, and thus the selection lines function as a shield for capacitive coupling. Therefore, the potential variation of the selection line of the floating state can be largely ignored. However, by suppressing the potential fluctuation of the selection line in the floating state as such, the charge of the fluctuation portion is added as a through current to the current consumption, and the capacitance of the adjacent non-access selection line is visible from the access selection line. The selection line changes later, which can result in a slightly slower access speed.

Between the access select line and the non-access select line, the potential difference of the maximum Vset/2 is instantaneously generated after the active step starts, but when the non-access select line becomes the floating state, the potential difference is immediately eliminated, and the non-access select line is finally stabilized. To the potential specified by the dead zone voltage Δ or the like.

The second example is an example in which the memory cell MC is brought into a reset state by using the above-described first process of the active step. The potential change of the access bit line BL and the non-access bit line driven by the driver block located on the access side of the MAT of the example is the left diagram of FIG. 37, which is driven by the driver block on the opposite side. The potential change of the non-access bit line BL is shown in the right diagram of FIG. 37. The potential change of the access word line WL and the non-access word line WL driven by the driver block on the access side is shown in the left diagram of FIG. The potential change of the non-access word line WL driven by the driver block on the opposite side is shown in the right diagram of FIG.

In order to bring the access memory cell MC into the reset state, it is necessary to apply a reverse bias corresponding to the set potential Vset to the access memory cell MC.

When the memory cell MC is reset, the sequence before the initial step is the same as the case where the setting operation is caused, but the direction in which the potential of the access selection line changes and the case where the setting operation is caused are reversed. Therefore, when the memory cell is reset, the set potential of each of the selection lines of the standby step is changed. That is, in the standby step, the bit line BL driven by the driver block located on the access side of the MAT becomes the potential Δ, and the bit line BL driven by the driver block located on the opposite side becomes the potential Vset/2. Further, the word line WL driven by the driver block on the access side is set to the potential Vset-Δ, and the word line WL driven by the driver block located on the opposite side is set to the potential Vset/2.

In the active step, when the memory cell MC is actually accessed, the access bit line BL is set to the ground potential Vss, and the access word line WL is set to the set potential Vset, so that other non-access select lines become floating. status. However, immediately after the start of the active step, the selection line driven by the driver block on the opposite side is fixed at the potential Vset/2. Therefore, by the shielding effect of the selected lines, the potential of the selection line of the floating state is almost changed. Do not behave so that its size can be ignored.

However, by suppressing the potential fluctuation of the selection line in the floating state as described above, as a side effect, the charge of the fluctuation portion is added as a through current, and the capacitance of the adjacent non-access selection line is visible from the access selection line. Taking the change of the selection line is slower and returning The access speed is slightly slower.

Between the access selection line and the non-access selection line, after the active step is started, the potential difference of the maximum Vset-Δ is instantaneously generated, but after the non-access selection line becomes the floating state, it immediately stabilizes to the final bias state.

The third example is an example in which the memory cell MC is set to the state by the above-described second process of the active step. The potential change of the access bit line BL and the non-access bit line driven by the driving block located on the access side of the MAT of the example is shown in the left diagram of FIG. 39, and is driven by the driver block on the opposite side. The potential change of the access bit line BL is shown in the right diagram of FIG. 39. The potential change of the access word line WL and the non-access word line WL driven by the driver block on the access side is shown in the left diagram of FIG. 39. The potential change of the non-access word line WL driven by the opposite side driver block is shown in the right diagram of FIG.

In the case of the second process using the active step, the potential step is set in the floating state when the spare step is divided into the first half and the second half for the selection line driven by the driver block located on the access side. In the second half of the standby step, the access selection line is set to the initial potential of the access, and the other non-access selection lines are made floating. The selection line driven by the driver block on the opposite side maintains the potential setting. Since the selection line driven by the driver block on the opposite side is set to a fixed potential, the selection lines function as a shield for capacitive coupling. Therefore, the potential variation of the selection line of the floating state is hardly expressed, so that the size can be ignored.

In the active step, all of the select lines other than the access select line are immediately in a floating state and are not set to a fixed potential. Therefore, power consumption due to penetration can be suppressed as much as possible. However, since the non-access selection line adjacent to the access selection line is in a floating state, a certain degree of interference is instantaneously generated. Due to this interference, a potential difference of maximum Vset / 2+ Δ is generated in the memory cell MC. However, the potential difference is immediately eliminated, and the non-access selection line is finally stabilized to the potential determined by the dead zone voltage Δ or the like.

The fourth example uses the above-described second process of the active step to make the memory cell MC An example of a reset state. The potential change of the access bit line BL and the non-access bit line driven by the driver block located on the access side of the MAT of the example is shown in the left diagram of FIG. 41, and is driven by the driver block on the opposite side. The potential change of the access bit line BL is shown in the right diagram of FIG. 41. The potential change of the access word line WL and the non-access word line WL driven by the driver block on the access side is shown in the left figure of FIG. The potential change of the non-access word line WL driven by the opposite driver block is shown in the right diagram of FIG.

When the memory cell MC is reset, the sequence before the initial step is the same as the case where the setting operation is caused, but the direction in which the potential of the access selection line changes and the case where the setting operation is caused are reversed. Therefore, when the memory cell MC is reset, the set potential of each of the selection lines of the standby step is changed.

In the case of the second process of the active step, the spare step is divided into the first half and the second half for the selection line driven by the driver block located on the access side, and the potential setting in the floating state is performed. In the second half of the spare step, only the access select line maintains the set potential, and the other non-access select lines are set to the floating state.

That is, with respect to the bit line BL, in the first half of the standby step, the bit line BL driven by the driver block located on the access side is set to the potential Vset/2, and the drive block located on the opposite side is not stored. The bit line BL is also set to the potential Vset/2. In the second half of the standby step, the access bit line driven by the driver block located on the access side is set to the potential Δ, and the other non-access bit line BL is brought into a floating state. The bit line BL driven by the driver block on the opposite side is maintained at the potential Vset/2. Therefore, in the latter half of the standby step, according to the shielding effect of the fixed potential set to the bit line BL driven by the driver block located on the opposite side, the potential variation of the bit line BL in the floating state is hardly expressed, so that Ignore its size.

Further, regarding the word line WL, in the first half of the standby step, the word line WL driven by the driver block located on the access side is set to the potential Vset/2, and the drive block located on the opposite side is not stored. The word line WL is also set to the potential Vset/2. In the alternate step In the latter half, the access word line WL driven by the driver block on the access side is set to the potential Vset-Δ, and the other non-access word line WL is brought into a floating state. The word line WL driven by the driver block on the opposite side is maintained at the potential Vset/2. Therefore, in the latter half of the standby step, the potential variation of the word line WL in the floating state is hardly expressed according to the shielding effect of the fixed potential set to the word line WL driven by the driver block located on the opposite side, so that Ignore its size.

In the active step, when the memory cell MC actually accesses, the access bit line BL is set to the ground potential Vss, and the access word line WL is set to the set potential Vset, so that the other non-access selection lines become floating. status. In the active step, all of the select lines other than the access select line are immediately in a floating state and are not set to a fixed potential. Therefore, power consumption due to penetration can be suppressed as much as possible. However, since the non-access selection line adjacent to the access selection line is in a floating state, a certain degree of interference is instantaneously generated. Due to this interference, the memory cell MC is reverse biased, but generates a potential difference of maximum Vset / 2+ Δ. However, the potential difference is immediately eliminated, and the non-access selection line is finally stabilized to the potential determined by the dead zone voltage Δ or the like.

Hereinafter, a memory block having a large-scale MAT configured by using the FLA access method described above will be described.

Figure 43 is a diagram showing the construction of the MATRIX and its peripheral circuits of the same memory block. The meaning of the display in the figure is the same as that of FIG.

The MAT described here has a capacitance of more than 32 GBit. The bit line BL has 296K strips, of which 8K strips are spare bit lines and constitute redundancy. The word line WL has 136K, of which 8K are spare word lines and constitute redundancy. The configuration of the spare memory cell area will be described later.

The memory block of this embodiment is characterized in that the selection line is accessed only from one side of the MAT. In the example shown in Fig. 43, the access of the bit line BL is performed from the driver block located on the left side of the MAT, and the access of the word line WL is performed from the driver block located on the upper side of the MAT.

If the BCH ECC (144 bits) that can realize 2-bit correction is used, the bit is used. The line backup unit subl is composed of 36 SL groups and one SSL group totaling 37 (= 36 + 1). On the other hand, the word line backup unit suwl is composed of 16 SL groups and one SSL group totaling 17 (= 16 + 1).

One MAT system has eight bit lines SET arranged in the column direction, and eight word lines SET are arranged in the row direction. That is, the column direction includes (36+1)×8×8 SL groups and SSL group, and 296K (including 8K of spare memory cell regions) bit lines BL. Further, the row direction includes (16+1)×8×8 SL groups and SSL group, and 136K (including 8K of spare memory cell regions) word lines WL. That is, in one MAT, 32 GBit data can be memorized. At this time, in the MATRIX containing the 8-layer MAT, the data of 0.25 TBit can be memorized.

In the case shown in FIG. 43, the eight bit lines SET constituting the bit line BL are vertically separated by four units, and each 144-bit data is transmitted via the bus bar from one side of each MAT side. . Therefore, a total of 288 (= 144 × 2) bits of data are transmitted from one MAT. The data is then processed in two ECC systems to become 256-bit = 32-bit data.

Regarding the word line WL, as shown in FIG. 43, in each word line SET, only one SL group is selected from the driver block located on the MAT side, and only one word line of the selected SL group is selected. WL accesses.

The 144-bit bus connected to each MAT is placed outside the MATRIX and is configured to overlap with other MAT bus bars. As described above, the MATRIX laminate has eight MAT structures, so the busbars are arranged in eight layers. Moreover, the eight overlapping bus bars are aggregated into a 144-bit busbar at the corner of MATRIX and enter the sense amplifier SA under the TILE. From the sense amplifier SA, the busbars of 144 bits from the upper side and the lower side of the MAT extend outside the TILE as a busbar of 144 x 2 bits.

When the MATRIX of the configuration is configured as a plurality of TILEs to form a memory block, a TBit-level wafer can be produced. As shown in Figure 43, the exchange of 256 bits with each TILE The material block can form a memory block that can realize error correction of 2 bits in 128+16 bits.

Next, an example of a specific circuit for driving the access potential from only one side of the MAT will be described.

Figure 44 is a circuit diagram of a SL blk circuit block of the memory block of the embodiment. The value of the SL blk circuit block of the word line WL in the figure () is shown. Further, Fig. 45 is a timing chart of the failure detecting portion of the SL blk circuit block of the memory block of the embodiment.

The SL blk circuit block includes an independent fault detecting circuit including a current mirror type differential amplifying circuit U1 and a latch circuit U2 with respect to the SL drv circuit block, and the sum of the fault detecting circuits includes a fault detecting portion. The fault detection circuit is required for the initial steps of the FLA. In this initial step, a selection line for excessive current flow is detected.

Since the bit line BL and the word line WL of the short-circuit fault are both set to the fault line potential ζ, the order of setting the potentials of the bit line BL and the word line WL for the short-circuit faults is important. That is, the configuration of the fault detecting circuit is simplified by setting the fault line potential ζ from the selection line of the fault line potential ζ and the set potential.

The fault line potential ζ can be set to the same potential as the set potential Vset-Δ of the word line WL at the initial step. Therefore, the fault detection is started from the word line WL side, and the potential line potential ζ is first set to the word line WL. The control signals fail and /fail from the fault detection circuit directly control the SL drv circuit block, so the signal levels of the control signals fail and /fail are more important. The state in which the control signal /fail = "H" and the control signal fail = "L" is the state in which the SL drv circuit block operates normally. Therefore, it is necessary to make this state the initial state of the control signals /fail and fail in advance. In order to form the initial state of the control signals /fail and fail, the differential amplifying circuit U1 of the fault detecting circuit is blocked to make the output "H", and the output is transmitted via the transmitting transistor with the control signal tx = "H". M1 is transferred to the latch circuit U2. The state of the control signal /fail = "H" is the initial state of the latch circuit U2. The blocking of the differential amplifier circuit U1 is performed by setting the control signal ssp = "L".

When a short circuit fault is detected, the word line WL is first set to the fault line potential ζ, and then The bit line BL for the same short-circuit fault is set to the fault line potential ζ. A timing chart of the respective control signals at this time is shown in FIG. Further, the potential compared by the differential amplifying circuit U1 is different between the SL blk circuit block of the bit line BL and the SL blk circuit block of the word line WL. That is, in the SL blk circuit block of the word line WL, the set potential of the word line WL in the initial step is Vset-Δ, and in the case of a short-circuit fault, a determination signal that is lower than the set potential is set. Shrt is output from the SL drv circuit block. Therefore, the potential Vset-Δ is input when the input of the latch circuit U2 of the differential amplifier circuit U1 is input, and the potential Vset-Δ and the determination signal shrt are compared. In the SL blk circuit block of the bit line BL, the set potential of the bit line BL according to the initial step is Δ, and in the case of a short-circuit fault, the determination signal shrt which is higher than the set potential is from the SL drv circuit. Block output. Therefore, the potential Δ is input when the input of the latch circuit U2 of the differential amplifier circuit U1 is input, and the potential Δ and the determination signal shrt are compared.

Furthermore, when a short circuit fault is detected in the SL blk circuit block, an error signal /X indicating it is generated. The signal line of the error signal X is pre-charged to "H", and is discharged based on the value of AND of the selection signal blk and the control signal fail of the SL blk circuit block, so that the error signal /X becomes "L" to notify the existence of the fault. .

Next, the SL group circuit block will be described. The SL group circuit block is a circuit composed of 8 SL blk circuit blocks.

Figure 46 is a circuit diagram of a SL group circuit block of the memory block of the embodiment.

In the SL group circuit block, one selection line connected to the data bus is selected from the SL group circuit block. That is, the SL group circuit block is a circuit that selects one of the selection lines from 64 selection lines.

The signal selection signal blk<i> of the SL blk circuit block <i> (i=1~8) is selected. Further, a signal that is commonly outputted from each SL blk circuit block <i> for a plurality of SL group circuit blocks to notify the presence or absence of a short-circuit fault is an error signal /X<i>. The data line xyB from the SL blk circuit block is commonly connected, and is extracted from the SL group circuit block as one data line xyB. The data line xyB of each SL blk circuit block can be switched to the data line xySB from the SSL group circuit block to be described later. This switching is the error signal x and the normal signal OK. The data line xyB from the SL group circuit block is a normal signal OK = "H" when the short circuit fault is not detected in the selected SL blk circuit block, and is from the SL blk circuit block <i> Any one of the data lines xyB is connected. On the other hand, when a short-circuit fault is detected, the error signal X = "H" is connected to the data line xySB from the SSL group circuit block. The generation of the error signal X or the normal signal OK will be described later. The SL group circuit block has the same configuration on the bit line BL side and the word line WL side.

Next, the SSL blk circuit block will be described.

Figure 47 is a circuit diagram of an SSL blk circuit block of the memory block of the embodiment.

The SSL blk circuit block is identical to the SL blk circuit block except for the error signal /X portion. That is, the error signal /X is composed of eight SSL blk circuit blocks, and constitutes a signal common to each of the eight SL blk circuit blocks of the SL group circuit block. The signal line of the error signal /X is precharged to "H" before the control signal acc becomes "H". When the current step of entering the FLA enters the cycle of starting the data transfer, the control signal acc becomes "H", and the signal line of the error signal /X becomes a floating state. Thereby, the error signal /X can indicate the presence or absence of a short-circuit fault of the select line corresponding to the SL blk circuit block at any time. In addition, in the SSL blk circuit block, the detection of the short-circuit fault of the spare select line itself is also performed. As a result, if there is a short-circuit fault in the spare selection line, the fault line potential ζ is set for the alternate selection line. The reason is to suppress the influence of the short-circuit fault in the MAT on the access operation. When the alternate selection line is faulty, the redundancy function disappears, so one part of the address area cannot be used.

Next, the SSL group circuit block will be described.

Figure 48 is a circuit diagram of an SSL group circuit block of the memory block of the embodiment.

Like the SL group circuit block, the SSL group circuit block is also composed of 8 SSL blk circuit blocks <1:8>. The SSL blk circuit block <i>(i=1~8) is selected by the same selection signal blk<i> as the SL blk circuit block <i>. Also, output from each SSL blk circuit block <i> The error signal /X<i> is shared with the SL blk circuit block. Furthermore, the data lines xySB from the <b> of each SSL blk circuit block are commonly connected and extend from the SSL group as the data line xySB. That is, the SSL group circuit block can independently perform redundancy of each of the SL blk circuit blocks <1:8> having the complex array.

In the SSL group circuit block, an error signal X or a normal signal OK is generated according to whether there is a short-circuit fault in a selection line corresponding to one SSL blk<i> selected from 8 SSL blk<1:8>. In the SSL group circuit block, the error signal X and the normal signal OK are complementary signals, and the NAND error signal X of the error signal /X<1:8> and the inverted normal signal OK are generated. The SSL group circuit block corresponds to one SL blk circuit block <i> due to the eight selection signals blk<1:8>, and therefore within the range of the SL group circuit block assumed by one SSL group circuit block, If there is a short-circuit fault in the selection line corresponding to the same selection signal blk<i>, the address area other than the 1 part will not be used.

Next, the spare unit will be described. The circuit diagrams of the bit line spare unit sub1 and the word line backup unit suw1 of the memory block of the present embodiment are the same as those of Figs. 22 and 23, and therefore, reference is made to this.

Setting one SSL group circuit block for several SL group circuit blocks depends on the coding of the data used by the memory block. Here, as an example, it is assumed that the 144-bit code is generated using the information material of 128 bits, and the BCH code of the erroneous correction of the 2-bit error can be corrected for 144 bits. In order to simultaneously process the 144-bit BCH code, the number of the bit line BL and the word line WL is made to be approximately a multiple of 144 bits, respectively.

Briefly explain the decision process of the MAT bit line BL. The number of word lines WL is selected by only one MAT, so the number of decodings on the MAT side is a power of two, and further, if the sum of redundancy can be considered, the number of SL group circuit blocks is, for example, 16 One. That is, the number of word line spare units suwl is as shown in FIG. 22, and is composed of one SSL group circuit block for every 16 SL group circuit blocks.

When the bit line backup unit sub1 corresponding thereto has a short-circuit fault in the cross-point type MAT, the same number of spares are required on the word line WL and the bit line BL. Therefore, when one SSL group circuit block is formed as a multiple of the word line spare unit, if the ECC coding is not considered, only 32 (=16×2) SL group circuit blocks may be provided. However, since more than the required coding ratio is applied thereto, it is 9/8 (= 144/128) times when 128 bits are encoded with 144 bits. It is thus known that 36 (= 32 × 9 / 8) SL group circuit blocks are required. That is, as shown in FIG. 24, in the case of the bit line spare unit sub1, if 36 (= 18 × 2) SL group circuit blocks are provided for one SSL group circuit block, it can be combined with the word line. The spare unit suwl is composed of the same number of bit line spare units subl. Thereby, the short-circuit fault of the cross-point type MAT can be matched, and the number of bit lines BL of the MAT can be made substantially a multiple of the number of word lines WL. Thereafter, the size of the bit line BL to be simultaneously accessed is considered for such a basic configuration, and the size of the MAT may be determined.

Fig. 24 is a view showing a bit line standby unit sub1 in the case where the bit line backup unit sub1 corresponds to 18 pieces of data, and it is assumed that an area bus of 18 bits is set. In order to extract 18 data lines xyB from 18×2 SL group circuit blocks, and divide into odd SL group circuit blocks and even SL group circuit blocks, the adjacent two SL group circuit blocks are selectively connected to one. Strip area bus. The signals for making this selection are the selection signals su_oSEL and su_eSEL.

The SL group circuit block having the same configuration as the one forming the bit line spare unit sub1 is also used in the corresponding word line backup unit suwl. Therefore, on the basis of selecting any of the eight odd-numbered SL group circuit blocks or the eight even-numbered SL group circuit blocks from the 16 SL group circuit blocks, there are eight selection signals BLG< 1:8> Select one SL group circuit block. Furthermore, the word line spare unit suwl is selected by the address signal of the one word line spare unit from the MAT side /A<0:3>, /B<0:3>, /C<0:3 >, and one word line WL is selected, and the power source V is supplied to the word line WL.

Next, the connection configuration of the bit line backup unit sub1 with respect to MAT will be described.

Fig. 49 is a view showing the connection configuration of the bit line backup unit sub1 of the MAT of the memory block of the embodiment.

As described above, 18 area bus bars are extended from the bit line backup unit sub1. That is, the eight bit line spare unit sub1 corresponds to the data of 144 bits.

Therefore, it is sufficient to select eight bit line spare units sub1 as uniformly as possible, for example, as shown in FIG. That is, in the bit line SET which is the sum of the eight bit line spare units sub1, if two bit line backup units sub1 shown by oblique lines in the figure are selected, 36 area bus bars can be formed. The bit line SET divides the total of two groups of four bit line spare units sub1 arranged up and down as a pair, and selects the pair of units. Furthermore, each of the elementary line backup units sub1 is selected based on those arranged in the odd number or in the even number. Therefore, the signal for selecting the bit line spare unit sub1 is composed of four selection signals su_oSEL<1:4> and su_eSEL<1:4>, respectively. The selection of the bit line spare unit sub1 shown by the slanted line in the figure is performed by the control signal su_oSEL<1>, and each SET constitutes 36 area bus bars. The MAT bit line BL is composed of 8 SETs on each side, so there are 144 (= 36 × 4) area bus bars among the 4 SETs. That is, from the upper side of the MAT and the upper and lower sides of the 144 area, the bus bar protrudes outward. In the case of Fig. 49, the drive block from the left side of the MAT of the SET arrangement shown in the attached point is accessed.

The switching of the access line potential U<1> and the non-access line potential U<2> of the driver block located on the left and right sides of the MAT is performed by the switch circuits SW_L and SW_R shown in the figure. The switch circuit SW_L is composed of two transistors controlled by the complementary pairs of control signals act_L and /act_L, and the access line potential U<1> and the non-access line potential U<2> are selectively selected via the transistors. It is supplied to the bit line SET arranged on the left side of the MAT. Similarly, the switch circuit SW_R is composed of two transistors controlled by the complementary pair of control signals act_R and /act_R, and the access line potential U<1> and the non-access line potential U<2> are selected via the transistors. It is supplied to the bit line SET arranged on the right side of MAT.

Next, the connection structure of the spare unit suwl with respect to the MAT character line is said. Bright.

Fig. 50 is a view showing the connection configuration of the MAT word line backup unit suw1 with respect to the memory block of the embodiment.

The word line SET which is the sum of the eight word line spare units suwl corresponds to the case where there is a short-circuit failure in the cross-point type MAT, and it is necessary to make it the same as the bit line SET. That is, the upper side and the lower side of the MAT are each constituted by eight word lines SET. However, the composition of the word line spare unit suwl is different from the bit line backup unit sub1. One word line WL is selected from each word line spare unit suwl, and one word line backup unit suwl is selected from the selected word line SET based on the selection of one word line SET. That is, a two-eighth selection of two stages is required, so a decoder and address signal for decoding 26 are required. The address signals are /A<0:3>, /B<0:3>, /C<0:3>.

The switching of the access line potential V<1> and the non-access line potential V<2> of the driver block located on the lower side of the MAT is performed by the switch circuits SW_T and SW_B shown in the figure. The switch circuit SW_T is composed of two transistors controlled by the complementary pair of control signals act_T and /act_T, and the access line potential V<1> and the non-access line potential V<2> are selectively selected via the transistors. The word line SET arranged on the upper side of the MAT is supplied. Similarly, the switch circuit SW_B is composed of two transistors controlled by the complementary pairs of control signals act_B and /act_B, and the access line potential V<1> and the non-access line potential V<2> are selected via the transistors. The character line SET arranged on the lower side of the MAT is supplied sexually.

Although the peripheral circuit of the MAT of the present embodiment has been described above, the present embodiment may have a bandwidth of 16 MByte/s and a memory capacity as shown in FIG. 26, which is the same as that of the first embodiment. It is a memory block of 1 TBit and an access time tAC of 8 μs.

Further, by using the memory block, a memory system of the P (peta) bit size similar to that of the first embodiment as shown in Fig. 27 can be constructed.

As described above, according to the present embodiment, not only the same effect as in the first embodiment can be obtained. Further, by extending the gate of the transistor constituting the SL drv circuit block in a direction orthogonal to the extending direction of the selection line, the circuit configuration of the driver block can be simplified, whereby the driver block can be made Installation is easier.

[other]

The embodiments of the present invention have been described above, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in various other forms, and various omissions, substitutions and changes may be made without departing from the scope of the invention. The scope of the invention or its modifications are intended to be included within the scope of the invention and the scope of the invention.

Claims (20)

A memory system comprising: a case in which three directions orthogonal to each other are used as a first direction, a second direction, and a third direction: a cell array having a plurality of unit cell arrays, the unit cell array including a plurality of first wirings extending in the first direction, a plurality of second wirings extending in the second direction, and respective intersections of the plurality of first wirings and the plurality of second wirings a plurality of memory cells that memorize data in a resistive state; and an access circuit that accesses the memory cells via the first wiring and the second wiring; and when the memory cell is applied with a specific voltage of a first polarity The resistance state transitions from the first resistance state to the second resistance state, and when a specific voltage of the second polarity having a polarity opposite to the first polarity is applied, the resistance state transitions from the second resistance state to the first resistance state The access circuit sets an access power required for accessing the memory unit to the first wiring and the second wiring connected to the memory unit of the access target And at least one of the first wiring and the second wiring connected to the memory unit that is not accessed is in a floating state, and accesses the memory unit to be accessed; the unit cell array has The plurality of spare first wirings extending in the first direction in the redundancy of the plurality of first wirings; and the spare first wirings arranged in a predetermined number on the same side of the plurality of first wirings. The memory system of claim 1, wherein one of the first direction is the first side and the other is the second side; The access circuit includes: a first side first wiring driver arranged in the second direction on the first side of the unit cell array, and driving the plurality of first wirings arranged in an odd number a first wiring driver, wherein the second wiring driver is arranged in the second direction on the second side of the unit cell array, and drives the second wiring arranged in the even number of the plurality of first wirings In the plurality of first wirings, the plurality of first wirings arranged in the odd-numbered number are driven by the first-side first wiring driver, and are arranged in a plurality of the first wirings of the even-numbered number. The 2nd first wiring driver is driven. The memory system of claim 1, wherein the unit cell array has a plurality of spare second wirings that are redundancy of the plurality of second wirings; a number of redundantly replaceable first wirings and the second wiring The number of redundant replacements is the same. The memory system of claim 1, wherein the memory unit that is substantially in an open state due to a fault is an open fault memory unit; and the plurality of first wirings and the plurality of The setting of the potential and the floating state of the second wiring does not change depending on the presence or absence of the open fault memory unit. The memory system of claim 1, wherein the memory unit that is substantially short-circuited due to a fault is a short-circuit fault memory unit; the access circuit detects the first wiring connected to the short-circuit fault memory unit or The current of the second wiring is redundantly replaced with the detected first wiring. The memory system of claim 1, wherein the memory unit that is substantially short-circuited due to a fault is used as a short-circuit fault memory unit; The access circuit sets the first wiring and the second wiring connected to the short-circuit fault memory unit to a fault selection line potential. The memory system of claim 2, wherein the access circuit is from the first side first wiring driver and the second side of the first side first wiring driver at the same position in the second direction Any one of the wiring drivers accesses a plurality of the aforementioned memory cells. The memory system of claim 2, wherein the access circuit accesses the plurality of memory cells from the plurality of first side first wiring drivers and the plurality of first side second wiring drivers . The memory system of claim 1, wherein the number of the first wirings is twice or more the number of the second wirings. The memory system of claim 1, comprising: a plurality of memory modules including the foregoing array of cells and the access circuit; a control unit that controls the plurality of memory modules; and a data/command bus, The exchange of commands and data between the control unit and the memory module. A memory system comprising: a case in which three directions orthogonal to each other are used as a first direction, a second direction, and a third direction: a cell array having a plurality of unit cell arrays, the unit cell array including a plurality of first wirings extending in the first direction, a plurality of second wirings extending in the second direction, and respective intersections of the plurality of first wirings and the plurality of second wirings a plurality of memory cells that memorize data in a resistive state; and an access circuit that accesses the memory cells via the first wiring and the second wiring; and when the memory cell is applied with a specific voltage of a first polarity The aforementioned resistance state When the first resistance state is changed to the second resistance state, when a specific voltage of the second polarity having a polarity opposite to the first polarity is applied, the resistance state transitions from the second resistance state to the first resistance state; The circuit is configured to set an access potential required for accessing the memory cell to the first wiring and the second wiring connected to the memory cell of the access target, and to connect the memory cell connected to the non-access target At least one of the first wiring and the second wiring is in a floating state, and accesses the memory cell to be accessed; the unit cell array has redundancy in the plurality of first wirings in the first direction a plurality of spare first wirings extending upward; a predetermined number of spare first wirings arranged on a same period of the plurality of first wirings; and the access circuit having the plurality of first wirings selected for driving a plurality of first wiring drivers; each of the plurality of first wiring drivers is formed by a plurality of transistors, and is connected to the gate wiring of the plurality of transistors It extends in the second direction. The memory system of claim 11, wherein the one of the first direction is the first side and the other is the second side; the plurality of first wiring drivers of the access circuit include: the first side The first wiring driver is arranged in the second direction on the first side of the unit cell array, and drives the first wiring in which the odd number is arranged in the plurality of first wirings; and the first side on the second side The wiring driver is arranged in the second direction on the second side of the unit cell array, and drives the second wiring arranged in the even number of the plurality of first wirings; and the plurality of first wirings , a plurality of the aforementioned first cloth arranged in the odd number The line is driven by the first side first wiring driver, and the plurality of first wiring lines arranged in the even number are driven by the second side first wiring driver. The memory system of claim 11, wherein the unit cell array has a plurality of spare second wirings that are redundancy of the plurality of second wirings; a redundant number of the first wirings and a second wiring The number of redundant replacements is the same. The memory system of claim 11, wherein the memory unit that is substantially in an open state due to a failure is an open fault memory unit; and the plurality of first wirings and the plurality of The setting of the potential and the floating state of the second wiring does not change depending on the presence or absence of the open fault memory unit. The memory system of claim 11, wherein the memory unit that is substantially short-circuited due to a fault is a short-circuit fault memory unit; the access circuit detects the first wiring connected to the short-circuit fault memory unit or The current of the second wiring is redundantly replaced with the detected first wiring. The memory system of claim 11, wherein the memory unit that is substantially short-circuited due to a fault is used as a short-circuit fault memory unit; the access circuit is connected to the first wiring of the short-circuit fault memory unit and The second wiring is set to a fault selection line potential. The memory system of claim 12, wherein the access circuit is from the first side first wiring driver and the second side of the first side first wiring driver at the same position in the second direction Any one of the wiring drivers accesses a plurality of the aforementioned memory cells. The memory system of claim 12, wherein the access circuit is from any one of the plurality of first side first wiring drivers and the plurality of first side second wiring drivers Accessing the aforementioned plurality of memory cells. The memory system of claim 11, wherein the number of the first wirings is twice or more the number of the second wirings. The memory system of claim 11, comprising: a plurality of memory modules including the array of cells and the access circuit; a control unit that controls the plurality of memory modules; and a data/command bus, The exchange of commands and data between the control unit and the memory module.