TW201431024A - Stackable interposers - Google Patents

Abstract

A stackable interposer is provided. The stackable interposer includes a substrate, a plurality of deep-trench vias, a metal interconnection layer, an inter-metal dielectric, an optional passivation layer, a first dielectric layer, a plurality of first under-bump metal pads, a plurality of first stacking bumps, a plurality of first stacking bumps, a second dielectric layer, a plurality of second UBM pads, and a plurality of second stacking bumps. The plurality of deep-trench vias (DTVs) formed in said substrate; the optional first dielectric layer surrounding said deep-trench vias; the plurality of first stacking bumps formed on said first under-bump metal; the optional second dielectric layer formed on the second side of said substrate; and the plurality of second stacking bumps formed on said second UBM for integrating different functions and materials chip.

Description

Stackable interposer

The present invention relates to semiconductor devices, and more particularly to a stackable interposer substrate.

Since the invention of the integrated circuit, semiconductor technology has been continuously developed, thereby reducing the volume of various electronic components and increasing the stacking density of integrated circuits. These improvements in stack density result from the smallest size of the miniaturized wafer, enabling more electronic components to be integrated per unit area.

The development of integrated circuits is essentially a two-dimensional structure, and the stack density is substantially improved in two dimensions. While advances in lithography have led to significant advances in two-dimensional integrated circuits, there are still many physical limitations to increasing stack density in two-dimensional structures, one of which is the need to minimize the size to form these components. More components are needed when more components are formed on the wafer.

In addition, in the past, technology can only be used for circuit integration of the same process, that is, homogenous integration, but not all circuits can be manufactured using the same process, so many analog circuits and memories cannot be manufactured using the same process. . If you want to use these features at the same time, you will only be able to purchase another chip for integration.

Three-Dimensional Integrated Circuit (3D-IC) is a technology that can increase the density of integrated circuits. With the advent of three-dimensional integrated circuit technology, by increasing the package density by means of vertical interconnection, in addition to meeting the conditions of size miniaturization, the thin wafers of different functions or materials are closely connected, providing the possibility of heterogeneous integration. In addition, the number and length of interconnects between the two-dimensional integrated circuit structures increase greatly as the number of devices increases. When the number and length of interconnects increase, it causes problems such as circuit signal delay and parasitic delay. Therefore, there is a need for a three-dimensional integrated circuit structure to improve the problems caused by conventional two-dimensional integrated circuits.

In view of the above problems, the present invention provides a stackable interposer substrate and a semiconductor device having a germanium, a glass, a sapphire or an insulating layer overlying a tantalum interposer as a substrate, and passing through a through-silicon via (Through-Silicon) Via, TSV) technology achieves heterogeneous integration to solve problems encountered in prior art.

According to an embodiment of the present invention, a stackable interposer includes a substrate, a plurality of deep trenches (DTVs), a metal interconnect layer, and a metal interposer. An electrical layer (IMD), a passivation layer, a first dielectric layer, a plurality of first under bump metal (UBM), a plurality of first stacked bumps, and a second a dielectric layer, a plurality of second bump under metal, and a plurality of second stacked bumps. The plurality of deep trench vias are formed on the substrate; the metal interconnect layer is formed on one of the first surfaces of the substrate and electrically coupled to the deep trench via; the intermetal dielectric layer is formed between the metal interconnect layers or around the metal An interconnect layer; the passivation layer is selectively formed on the metal interconnect layer or the intermetal dielectric layer; the first dielectric layer is selectively formed to surround the deep trench via; and the plurality of first bump under metal is formed on the passivation layer On the metal interconnect layer or the intermetal dielectric layer, and electrically coupled to the metal interconnect layer or the deep trench via; the plurality of first stacked bumps having different sizes and pitch diameters and formed in the first a second dielectric layer is selectively formed on the second surface of the substrate; a plurality of second under bump metal is formed on the second dielectric layer and electrically coupled to the deep trench through a hole; and a plurality of second stacking bumps having different sizes and pitch diameters and formed on the second bump metal.

According to an embodiment of the present invention, a stackable interposer includes a substrate, a plurality of deep trenches (DTVs), a metal interconnect layer, and a metal interposer. An electrical layer (IMD), a passivation layer, a first dielectric layer, a plurality of first under bump metal (UBM), a plurality of first stacked bumps, one or more a first active component, a first underfill dielectric layer, a package dielectric layer, a second dielectric layer, and a plurality of second bumps The underlying metal and a plurality of second stacked bumps. The plurality of deep trench vias are formed on the substrate; the metal interconnect layer is formed on one of the first surfaces of the substrate and electrically coupled to the deep trench via; the intermetal dielectric layer is formed between the metal interconnect layers or around the metal An interconnect layer; the passivation layer is selectively formed on the metal interconnect layer or the intermetal dielectric layer; the first dielectric layer is selectively formed to surround the deep trench via; and the plurality of first bump under metal is formed on the passivation layer On the metal interconnect layer or the intermetal dielectric layer, and electrically coupled to the metal interconnect layer or the deep trench via; the plurality of first stacked bumps having different sizes and pitch diameters and formed in the first On the under bump metal; one or more first active components electrically or mechanically coupled to the portion of the first stacked bump; the first underfill dielectric layer is formed on the first active component and the partial first stacked bump Around or under the block; a package dielectric layer is formed over the first stacked bump, the first under bump metal, the first active device, and the first underfill dielectric layer; the second dielectric layer is selectively formed on the substrate a second surface; a plurality of second bump under metal As on the second dielectric layer and electrically coupled trenches deep vias; and a plurality of second stacked bumps, which have different dimensions and pitch diameter and formed on the second UBM.

The stackable interposer substrate according to the present invention has a germanium or glass as a substrate interposer, and realizes heterogeneous integration through a through-pass twinning technique, and increases the package density by vertical interconnection to different functions or materials. The tight bonding of thin wafers provides the possibility of heterogeneous integration. Moreover, the number and length of connections in the device are reduced, which improves the circuit signal delay and parasitic delay caused by the conventional two-dimensional integrated circuit.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

10‧‧‧Stackable Interposer

11‧‧‧Substrate

12‧‧‧Deep trench through hole

13‧‧‧Metal interconnect layer

14‧‧‧Metal dielectric layer

15‧‧‧ Passivation layer

16‧‧‧First dielectric layer

17‧‧‧First bump under metal

18‧‧‧First stacking bump

19‧‧‧Second dielectric layer

20‧‧‧Second bump metal

21‧‧‧Second stacking bumps

181‧‧‧First sub-stacking bump

182‧‧‧First sub-connection bump

100‧‧‧Stackable Intermediary Substrate

101‧‧‧Substrate

102‧‧‧Deep trench through hole

103‧‧‧Metal interconnect layer

104‧‧‧Metal dielectric layer

105‧‧‧ Passivation layer

106‧‧‧First dielectric layer

107‧‧‧First bump under metal

108‧‧‧First stacking bump

109‧‧‧Second dielectric layer

110‧‧‧Second bump metal

111‧‧‧Second stacking bump

112‧‧‧First active component

113‧‧‧First underfill dielectric layer

114‧‧‧Package dielectric layer

115‧‧‧Second active components

116‧‧‧Second underfill dielectric layer

281‧‧‧First sub-stacking bump

282‧‧‧First sub-connection bump

211‧‧‧Second sub-stacking bumps

212‧‧‧Second sub-joint bump

30‧‧‧Stackable Intermediary Substrate

31‧‧‧Substrate

32‧‧‧Deep trench through hole

33‧‧‧Metal interconnect layer

34‧‧‧Metal dielectric layer

35‧‧‧ Passivation layer

36‧‧‧First dielectric layer

37‧‧‧First bump under metal

38‧‧‧First stacking bump

39‧‧‧Second dielectric layer

40‧‧‧Second bump metal

41‧‧‧Second stacking bumps

42‧‧‧First active component

43‧‧‧Connecting line

FIG. 1 is a structural diagram of a stackable interposer disclosed in the present invention.

2 is another implementation of the stackable interposer disclosed in the present invention. The structural diagram of the example.

FIG. 3 is a structural diagram of another embodiment of the stackable interposer disclosed in the present invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1 , which is a schematic structural view of the stackable interposer substrate 10 disclosed in the present invention. The stackable interposer substrate comprises a substrate 11, a plurality of deep trenches (DTVs) 12, a metal interconnect layer 13, an intermetal dielectric layer (IMD) 14, and a passivation layer. a first dielectric layer 16, a plurality of first under bump metal (UBM) 17, a plurality of first stacked bumps 18, a second dielectric layer 19, and a plurality of second The under bump metal 20 and the plurality of second stacked bumps 21.

The substrate 11 is composed of a semiconductor, a glass, a sapphire or an insulating layer, and a plurality of deep-trench Vias (DTVs) 12 are formed on the substrate 11 by ion etching (Drie). A plurality of Deep-Trench Via (DTVs) 12 are formed by a Through-Silicon Via (TSV) method. Through-Silicon Via (TSV) is a through-hole that has a conductive function in the wafer. The through-hole is electrically connected to the stacked wafer in a vertical conduction manner, so that the line does not have to bypass the wafer side. In order to shorten the transmission distance of the electrical signal, the integration and performance of the system can be effectively improved, the overall height and area of the package can be reduced, and the performance of the wafer and the low power consumption can be greatly improved. In one embodiment, the plurality of deep trench vias 12 are formed of copper, tantalum, tantalum nitride, aluminum, titanium, titanium nitride, tungsten, or any combination of the foregoing.

The metal interconnection layer 13 is formed on one surface of the substrate 11 and electrically coupled to the plurality of deep trench vias 12 . The metal interconnection layer 13 can be formed by metal film deposition using a sputtering apparatus. An intermetal dielectric layer 14 is formed between or around the metal interconnect layer 13. Wherein the metal interconnect layer 13 is comprised of aluminum, titanium, tin, tungsten, copper, tantalum or Any combination of the above materials is formed.

Next, the passivation layer 15 is selectively formed on the metal interconnection layer 13 or the intermetal dielectric layer 14. The passivation layer 15 is not essential and can be selectively formed according to actual needs. Here, it is defined to be formed on the metal interconnection layer 13 or the inter-metal dielectric layer 14 because the inter-metal dielectric layer 14 is formed between or around the metal interconnection layer 13, according to the drawing. The passivation layer 15 can also be considered to be formed over the intermetal dielectric layer 14. The first dielectric layer 16 is selectively formed to surround the plurality of deep trench vias 12. The first dielectric layer 16 can be selectively formed. When the substrate 11 is a semiconductor substrate, the first dielectric layer 16 is required to electrically insulate the plurality of deep trench vias 12 from the substrate. If an insulating substrate such as a glass material is used, the first dielectric layer 16 is not required.

A plurality of first under bump metal 17 are formed on the passivation layer 15 , the metal interconnect layer 13 or the intermetal dielectric layer 14 , and are electrically coupled to the metal interconnect layer 13 or the deep trench vias 12 . A plurality of first stacked bumps 18 having different sizes and pitch diameters are formed on the plurality of first bump under metals 17.

In addition, a second dielectric layer 19 is selectively formed on the second surface of the substrate 11. The second dielectric layer 19 is not essential and can be selectively formed according to actual needs. That is, when an insulating glass substrate is used, the second dielectric layer 19 is not required. A plurality of second under bump metal layers 20 are formed on the second dielectric layer 19 and electrically coupled to the plurality of deep trench vias 12 . A plurality of second stacked bumps 21 having different sizes and pitch diameters are formed on the plurality of second bump under metals 20. The plurality of first stacked bumps 18 and the plurality of second stacked bumps 21 comprise a tin-lead bump or a copper short-pile, partially for conducting heat conduction, and electrically coupled to a ground or A predetermined potential. The plurality of first under bump metal 17 and the plurality of second under bump metal 20 are formed of copper, tin, lead or any combination of the above materials.

The plurality of first stacking bumps 18 are further divided into a plurality of first sub-stack bumps 181 and a plurality of first sub-stack bumps 182, and the size and the pitch of the plurality of first sub-stack bumps 181 are greater than a plurality of The size and pitch diameter of a sub-joint bump 182. As can be seen from the figure, a plurality of first sub-stack bumps 181 are mainly used as connection bumps between the substrates, and a plurality of first sub-connection bumps 182 are used as connection wafers or electronic components. Alternatively, the wafer or electronic component may be connected to the second surface using the same structure, as will be explained in the next embodiment. The plurality of first sub-stack bumps 181 and the plurality of first sub-connection bumps 182 are stacked bumps of different sizes, thus It is possible to make the three-dimensional integrated circuit stackable in a simpler manner, and to increase the density of the integrated circuit.

Please refer to FIG. 2 for a schematic structural view of the stackable interposer substrate 100 according to another embodiment of the present invention. The stackable interposer substrate includes a substrate 101, a plurality of deep trenches (DTVs) 102, a metal interconnect layer 103, an intermetal dielectric layer (IMD) 104, and a passivation layer. a first dielectric layer 106, a plurality of first under bump metal (UBM) 107, a plurality of first stacked bumps 108, a second dielectric layer 109, a plurality The second bump under metal 110, the plurality of second stacked bumps 111, the one or more first active devices 112, a first underfill dielectric layer 113, and a package dielectric layer 114.

The substrate 101 is composed of a semiconductor, a glass, a sapphire or an insulating layer, and a plurality of deep-trench Vias (DTVs) 102 are formed on the substrate 101 by ion etching (Drie). A plurality of Deep-Trench Vias (DTVs) 102 are formed by a through-silicone via. In one embodiment, the plurality of deep trench vias 102 are formed of copper, tantalum, tantalum nitride, aluminum, titanium, titanium nitride, tungsten, or any combination of the foregoing.

The metal interconnection layer 103 is formed on one surface of the substrate 101 and electrically coupled to the plurality of deep trench vias. The metal interconnection layer 103 can be formed by metal film deposition using a sputtering apparatus. An intermetal dielectric layer 104 is formed between or around the metal interconnect layer 103. The metal interconnect layer 103 is formed of aluminum, titanium, tin, tungsten, copper, tantalum or any combination thereof.

Next, the passivation layer 105 is selectively formed on the metal interconnect layer 103 or the intermetal dielectric layer 104. The passivation layer 105 is not essential and can be selectively formed according to actual needs. The definition here to be formed on the metal interconnection layer 103 or the inter-metal dielectric layer 104 is because the inter-metal dielectric layer 104 is formed between or around the metal interconnection layer 103, according to the drawing. The passivation layer 105 can also be considered to be formed over the intermetal dielectric layer 104. The first dielectric layer 106 is selectively formed to surround the plurality of deep trench vias 102. The first dielectric layer 106 is selectively formed to surround a plurality of deep trench vias 102. The first dielectric layer 106 can be selectively formed. When the substrate 101 is a semiconductor substrate, the first dielectric layer 106 is required to electrically insulate the plurality of deep trench vias 102 from the substrate. If you use insulation such as glass The substrate, then the first dielectric layer 106 is not needed.

A plurality of first under bump metal 107 are formed on the passivation layer 105, the metal interconnect layer 103 or the intermetal dielectric layer 104, and are electrically coupled to the metal interconnect layer 103 or the deep trench vias 102. A plurality of first stacked bumps 108 having different sizes and pitch diameters are formed on the plurality of first bump underlying metals 107.

One or more first active components 112 are electrically or mechanically coupled to a portion of the first stacked bumps 108. A first underfill dielectric layer 113 is formed around or under the one or more first active elements 112 and a portion of the plurality of first stacked bumps 108, and one or more first active elements 112 are encapsulated therein. A package dielectric layer 114 is formed over the plurality of stacked bumps 108, the plurality of first bump underlying metals 107, the one or more first active devices 112, and the first underfill dielectric layer 113. The package dielectric layer 114 or the one or more first active elements 112 is a plane that is flattened or ground.

In addition, a second dielectric layer 109 is selectively formed on the second surface of the substrate 101. The second dielectric layer 109 is not essential and can be selectively formed according to actual needs. That is, when an insulating glass substrate is used, the second dielectric layer 109 is not required. A plurality of second under bump metal layers 110 are formed on the second dielectric layer 109 and electrically coupled to the plurality of deep trench vias 102. And a plurality of second stacking bumps 111 having different sizes and pitch diameters and formed on the plurality of second bump under metals 110. The plurality of first stacked bumps 108 and the plurality of second stacked bumps 111 comprise a tin-lead bump or a copper short-pile, partially for conducting heat conduction, and electrically coupled to a ground or A predetermined potential. The plurality of first under bump metal 107 and the plurality of second under bump metal 110 are formed of copper, tin, lead or any combination of the above materials.

The plurality of first stacking bumps 108 are further divided into a plurality of first sub-stack bumps 281 and a plurality of first sub-stack bumps 282, and the size and the pitch of the plurality of first sub-stack bumps 281 are greater than a plurality of The size and the pitch diameter of a sub-connection bump 282. The plurality of second stacking bumps 111 can be further divided into a plurality of second sub-stack bumps 211 and a plurality of second sub-stack bumps 212. The size and the pitch of the plurality of second sub-stack bumps 211 are greater than a plurality of The size and the pitch diameter of the two sub-joints 212. As can be seen from the figure, the plurality of first sub-stack bumps 281 and the plurality of second sub-stack bumps 211 are mainly used as connecting bumps between the substrates, and the plurality of first sub-connecting bumps 282 and the plurality of second The sub-connection bumps 212 are then used as connection pads or electronic components.

In addition, further comprising one or more second active components 115 electrical or mechanical The plurality of second stacked bumps 111 are mechanically coupled to the plurality of second stacked bumps 111. A second underfill dielectric layer 116 is formed around or under the one or more second active elements 115 and a portion of the plurality of second stacked bumps 111.

Please refer to FIG. 3 , which is a schematic structural view of the stackable interposer substrate 30 according to another embodiment of the present invention. The stackable interposer substrate includes a substrate 31, a plurality of deep trench vias (DTVs) 32, a metal interconnect layer 33, an intermetal dielectric layer (IMD34), a passivation layer 35, and a first a dielectric layer 36, a plurality of first under bump metal (UBM) 37, a plurality of first stacked bumps 38, a second dielectric layer 39, and a plurality of second bumps The metal 40, a plurality of second stacked bumps 41, one or more first active elements 42 and a connecting line 43.

The substrate 31 is composed of a semiconductor, a glass, a sapphire or an insulating layer, and a plurality of deep-trench Vias (DTVs) 32 are formed on the substrate 31 by ion etching (Drie). A plurality of Deep-Trench Via (DTVs) 32 are formed by a through-silicone via. Through-Silicon Via (TSV) is a through-hole that has a conductive function in the wafer. The through-hole is electrically connected to the stacked wafer in a vertical conduction manner, so that the line does not have to bypass the wafer side. In order to shorten the transmission distance of the electrical signal, the integration and performance of the system can be effectively improved, the overall height and area of the package can be reduced, and the performance of the wafer speed and low power consumption can be greatly improved. In one embodiment, a plurality of deep trenches are passed. The holes 32 are formed of copper, tantalum, tantalum nitride, aluminum, titanium, titanium nitride, tungsten or any combination of the above.

The metal interconnect layer 33 is formed on one of the first surfaces of the substrate 31 and electrically coupled to the plurality of deep trench vias 32. The metal interconnection layer 33 can be formed by metal film deposition using a sputtering apparatus. An intermetal dielectric layer 34 is formed between or around the metal interconnect layer 33. The metal interconnect layer 33 is formed of aluminum, titanium, tin, tungsten, copper, tantalum or any combination of the above.

Next, the passivation layer 35 is selectively formed on the metal interconnection layer 33 or the intermetal dielectric layer 34. The passivation layer 35 is not essential and can be selectively formed according to actual needs. Here, it is defined to be formed on the metal interconnection layer 33 or the inter-metal dielectric layer 34 because the inter-metal dielectric layer 34 is formed between or around the metal interconnection layer 33, according to the drawing. The passivation layer 35 can also be considered to be formed over the intermetal dielectric layer 34. First dielectric layer 36 selection Formally formed to surround a plurality of deep trench vias 32. The first dielectric layer 36 can be selectively formed. When the substrate 31 is a semiconductor substrate, the first dielectric layer 36 is required to electrically insulate the plurality of deep trench vias 32 from the substrate. If an insulating substrate such as a glass material is used, the first dielectric layer 36 is not required.

A plurality of first under bump metal 37 are formed on the passivation layer 35, the metal interconnect layer 33 or the intermetal dielectric layer 34, and are electrically coupled to the metal interconnect layer 33 or the deep trench vias 32. A plurality of first stacking bumps 38 having different sizes and pitch diameters are formed on the plurality of first bump underlying metals 37.

In addition, a second dielectric layer 39 is selectively formed on the second surface of the substrate 31. The second dielectric layer 39 is not necessary and can be selectively formed according to actual needs. That is, when an insulating glass substrate is used, the second dielectric layer 39 is not required. A plurality of second under bump metal 40 are formed on the second dielectric layer 39 and electrically coupled to the plurality of deep trench vias 32. And a plurality of second stacking bumps 41 having different sizes and pitch diameters and formed on the plurality of second bump under metals 40. The plurality of first stacking bumps 38 and the plurality of second stacking bumps 41 comprise a tin-lead bump or a copper short-pile, partially for conducting heat conduction heat, and electrically coupled to a ground or A predetermined potential. The plurality of first under bump metal 37 and the plurality of second under bump metal 40 are formed of copper, tin, lead or any combination of the above materials.

In addition, one or more first active components 42 are electrically coupled to the connecting wires 43 , and are electrically coupled to the metal interconnect layer 33 by the connecting wires 43 .

The stackable interposer substrate and the semiconductor device according to the present invention have a germanium, a glass, a sapphire or an insulating layer on the insulating layer as a substrate interposer, and realize heterogeneous integration through a through-pass twinning technique by vertical interconnection The way to increase the packing density and tightly bond thin wafers of different functions or materials provides the possibility of heterogeneous integration. Moreover, the number and length of connections in the device are reduced, which improves the circuit signal delay and parasitic delay caused by the conventional two-dimensional integrated circuit.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10‧‧‧Stackable Interposer

11‧‧‧Substrate

12‧‧‧Deep trench through hole

13‧‧‧Metal interconnect layer

14‧‧‧Metal dielectric layer

15‧‧‧ Passivation layer

16‧‧‧First dielectric layer

17‧‧‧First bump under metal

18‧‧‧First stacking bump

19‧‧‧Second dielectric layer

20‧‧‧Second bump metal

21‧‧‧Second stacking bumps

181‧‧‧First sub-stacking bump

182‧‧‧First sub-connection bump

201‧‧‧Second sub-stacking bumps

202‧‧‧Second sub-joint bump

Claims (18)

A stackable interposer substrate comprising: a substrate; a plurality of deep trench vias formed in the substrate; a metal interconnect layer formed on one of the first surfaces of the substrate and electrically coupled to the plurality of deep trenches a via hole; an intermetal dielectric layer formed between or surrounding the metal interconnect layer; a passivation layer selectively formed on the metal interconnect layer or the intermetal dielectric layer a first dielectric layer selectively formed to surround the plurality of deep trench vias; a plurality of first bump underlying metals formed on the passivation layer, the metal interconnect layer or the intermetal dielectric layer And electrically coupled to the metal interconnect layer or the plurality of deep trench via portions; a plurality of first stacked bumps having different sizes and pitch diameters and formed under the plurality of first bumps a second dielectric layer is selectively formed on a second surface of the substrate; a plurality of second under bump metal is formed on the second dielectric layer and electrically coupled to the plurality a deep trench via; and a plurality of second stacked bumps having different Size and pitch diameter and formed on the plurality of second UBM. The stackable interposer substrate of claim 1, wherein the substrate comprises a semiconductor, glass, sapphire or insulating layer overlying germanium. The stackable interposer according to claim 1, wherein the plurality of deep trench vias are formed of copper, tantalum, tantalum nitride, aluminum, titanium, titanium nitride, tungsten or any combination thereof. The stackable interposer substrate of claim 1, wherein the plurality of first stacking bumps and the plurality of second stacking bumps comprise tin-lead bumps or copper stubs. The stackable interposer substrate of claim 1, wherein the plurality of first stacking bumps and the plurality of second stacking bumps are electrically coupled to a ground terminal or a predetermined potential. The stackable interposer substrate of claim 1, wherein the metal interconnect layer comprises aluminum, titanium, tin, tungsten, copper, tantalum or any combination of the foregoing. The stackable interposer substrate of claim 1, wherein the plurality of first under bump metal and the plurality of second under bump metal are formed of copper, tin, lead or any combination thereof. A stackable interposer substrate comprising: a substrate; a plurality of deep trench vias formed on the substrate; a metal interconnect layer formed on a first surface of the substrate and electrically coupled to the plurality of deep trenches a via hole; an intermetal dielectric layer formed between or surrounding the metal interconnect layer; a passivation layer selectively formed on the metal interconnect layer or the intermetal dielectric layer; a first dielectric layer selectively formed to surround the plurality of deep trench vias; a plurality of first bump underlying metals formed on the passivation layer, the metal interconnect layer or the intermetal dielectric layer And electrically coupled to the metal interconnect layer or the plurality of deep trench via portions; a plurality of first stacked bumps having different sizes and pitch diameters and formed on the plurality of first bump underlying metal One or more first active components electrically or mechanically coupled to the plurality of first stacked bump portions; a first underfill dielectric layer formed on the one or more first active components and a plurality of first stacked bumps around or under the portion; a package dielectric layer formed on the plurality of first stacked bumps, the plurality of first bump under metal, the one or more first active components, and The first underfill dielectric layer is over the dielectric layer; a second dielectric layer is selectively formed on the second surface of the substrate; and a plurality of second bump under metal is formed on the second dielectric layer. And electrically coupled to the plurality of deep trench vias; and a plurality The second stacking projections, which have different dimensions and pitch diameter and formed on the plurality of second UBM. The stackable interposer substrate of claim 8, wherein the substrate comprises a semiconductor, glass, sapphire, or insulating layer overlying germanium. The stackable interposer substrate of claim 8, wherein the plurality of deep trench vias are formed of copper, tantalum, tantalum nitride, aluminum, titanium, titanium nitride, tungsten or any combination thereof. The stackable interposer substrate of claim 8, wherein the plurality of first stacked bumps and the plurality of second stacked bumps comprise tin-lead bumps or copper stubs. The stackable interposer substrate of claim 8, wherein the plurality of first stacking bumps and the plurality of second stacking bumps are electrically coupled to a ground terminal or a predetermined potential. The stackable interposer substrate of claim 8, wherein the metal interconnect layer comprises aluminum, titanium, tin, tungsten, copper, tantalum or any combination of the foregoing. The stackable interposer substrate of claim 8, wherein the plurality of first under bump metal and the plurality of second under bump metal are formed of copper, tin, lead or any combination thereof. The stackable interposer of claim 8, wherein the one or more first active components comprise an integrated circuit, a CMOS imager, a microelectromechanical system wafer, a microfluidic channel wafer, or a thermoelectric cooler. The stackable interposer substrate of claim 8, wherein the encapsulation dielectric layer or the one or more first active components are a flattened or polished plane. The stackable interposer substrate of claim 8, further comprising one or more second active components electrically or mechanically coupled to the plurality of second stacked bump portions. The stackable interposer substrate of claim 8, further comprising a second underfill dielectric layer formed around or under the one or more second active components and a portion of the second stacked bumps.