TW201429165A - Device for recovering data and clock signal - Google Patents

Abstract

A device for recovering a data signal and a clock signal is provided. The device comprises a clock recovery module and a data recovery module. The clock recovery module comprises an adjustable delay unit, a first and a second sampling units, a first and a second delay units and a determining unit. The adjustable delay unit and the first and second delay units delay the clock signal in series to generate a first, a second and a third delay clock signals. The first and the second sampling units samples a clock signal source according to the first and the third delay clock signals to retrieve a first and a second clock states. The determining unit determines whether the first and the second clock states are inverted to adjust an adjustable delay time of the adjustable delay unit when they are not inverted. The data recovery module recovers the data signal when the first and the second clock states are inverted.

Description

Data and time recovery device

The present invention relates to a signal recovery technique, and more particularly to a data source and time recovery device.

A large amount of data transmission is often required between various computer systems and network communication systems. The technology of data transmission varies with different designs and definitions, but the purpose is to enable the receiving end to accurately and quickly receive data from the transmitting end.

In order to transmit data from the transmitting end to the receiving end through the signal line, the receiving end must know when to sample the data signal from the transmitting end. For example, in the transmission architecture specification of low-voltage differential signaling (LVDS), a clock cycle corresponds to a plurality of data, so the receiving end needs a clock signal transmitted according to the transmitting end of the data. According to the correct receipt of information. However, when the data signal is at a high frequency, since the clock signal is differential, when the receiving end wants to convert the differential back to a single-ended (single), the error caused by the delay effect is time-consuming. The pulse signal is not easily aligned with the data signal. In the case where the clock signal is not accurate, the receiving end will not be able to recover the data signal correctly.

Therefore, how to design a new data and time-recovery device to overcome the above problems is an urgent problem to be solved in the industry.

Therefore, one aspect of the present invention provides a data recovery device, including a clock recovery module and a data recovery module. The clock recovery module includes: an adjustable delay unit, a first sampling unit, a first delay unit, a second delay unit, a second sampling unit, and a determining unit. The adjustable delay unit receives the clock signal to delay the clock signal according to the adjustable delay time to generate the first delayed clock signal, wherein the clock signal is generated according to the clock signal source, and the clock signal source and the clock signal are generated. There is a delay between. The first sampling unit samples the clock signal source according to the first delayed clock signal to capture the first clock state. The first delay unit delays the first delayed clock signal to generate a second delayed clock signal. The second delay unit delays the second delayed clock signal to generate a third delayed clock signal. The second sampling unit is configured to sample the clock signal source according to the third delayed clock signal to capture the second clock state. The determining unit determines whether the first clock state and the second clock state are inverted, so that the adjustable delay time of the adjustable delay unit is adjusted when the first clock state and the second clock state are in phase. The data recovery module recovers the data signal according to the second delayed clock signal when the first clock state and the second clock state are inverted.

According to an embodiment of the invention, when the determining unit determines that the first clock state is low and the second clock state is low, the adjustable delay time is increased. When the judging unit judges that the first clock state is high and the second clock state is high, the adjustable delay time is adjusted. When the determining unit determines that the first clock state is low and the second clock state is high, the data recovery module recovers the data signal according to the second delayed clock signal.

According to another embodiment of the present invention, when the determining unit determines that the first clock state is low and the second clock state is low, the adjustable delay time is adjusted. When the judging unit judges that the first clock state is high and the second clock state is high, the adjustable delay time is increased. When the determining unit determines that the first clock state is high and the second clock state is low, the data recovery module recovers the data signal according to the second delayed clock signal.

According to still another embodiment of the present invention, the data timely recovery device further includes a delay locked loop (DLL), and generates a complex phase offset clock signal according to the second delayed clock signal, and the data recovery mode is performed. The group essentially recovers the data signal based on the phase offset clock signal.

According to still another embodiment of the present invention, the data and time recovery device further comprises a differential to single circuit, wherein the clock signal source is in a differential form for conversion to a single-ended form via a differential-to-single-ended circuit. Clock signal.

The advantage of applying the present invention is that in the data and time recovery device, the clock recovery module delays the clock signal by different degrees, and samples the clock signal source with the delayed signal, and obtains the time according to the sampling. The state of the pulse signal determines the edge of the source of the clock signal, and further determines the actual position of the source of the clock signal to correct the offset of the clock signal, and easily achieves the above purpose.

Please refer to Figure 1. 1 is a block diagram of a data recovery and recovery device 1 in an implementation of the present invention. The data and time recovery device 1 includes a clock recovery module 10 and a data recovery module 12.

The clock recovery module 10 includes: an adjustable delay unit 100, a first sampling unit 102, a first delay unit 104, a second delay unit 106, and a second take Sample unit 108 and determination unit 110.

The adjustable delay unit 100 receives the clock signal CK. In this embodiment, the clock signal CK is converted from the originally differential clock source CKP/CKN through a differential to single circuit 112. In other embodiments, the clock signal CK can also receive other forms of clock signal sources from other possible circuits, and is not limited by the differential form. The adjustable delay unit 100 will delay the clock signal CK according to a preset adjustable delay time ADT to generate a first delayed clock signal CKD1. The first delay unit 104 may further delay the first delayed clock signal CKD1 to generate a second delayed clock signal CKD2. The second delay unit 106 may delay the second delayed clock signal CKD2 to generate a third delayed clock signal CKD3.

Please refer to the 2A to 2D drawings at the same time. 2A to 2D are respectively a clock signal source CKP/CKN, a clock signal CK, a first delayed clock signal CKD1, a second delayed clock signal CKD2, and a third delay clock according to an embodiment of the invention. Waveform of signal CKD3.

In the present embodiment, the clock signal CK is converted by the differential to single-ended circuit 112. Therefore, the differential-to-single-ended circuit 112 will cause the delay time DT as shown in FIG. 2A, so that the phases of the clock signal CK and the clock signal source CKP/CKN do not coincide. The data recovery module 12, which should restore the received data signal DATA according to the timing of the clock signal source CKP/CKN, cannot correctly recover the data signal DATA according to the delayed clock signal CK after the conversion. Since this delay time DT is unknown, an effective method is needed for detection and correction.

With the design of the present invention, the first sampling unit 102 can be based on the first delay The late clock signal CKD1 samples the clock signal source CKP/CKN to capture the first clock state STATE1. The second sampling unit 104 is configured to sample the clock signal source CKP/CKN according to the third delayed clock signal CKD3 to capture the second clock state STATE2.

In different embodiments, the first sampling unit 102 and the second sampling unit 104 can sample the clock signal source CKP/CKN by using a rising edge or a falling edge. In this embodiment, the first sampling unit 102 and the second sampling unit 104 use the rising edge to sample the clock signal source CKP/CKN. The first delay unit 104 and the second delay unit 106 can control the delay time after appropriate design, so that only the first delayed clock signal CKD1, the second delayed clock signal CKD2 and the third delayed clock signal CKD3 have Very small gap. Therefore, the edge of the first delayed clock signal CKD1 and the third delayed clock signal CKD3 will be very close to the edge of the second delayed clock signal CKD2 and located on both sides of the edge of the second delayed clock signal CKD2.

The determining unit 110 further determines whether the first clock state STATE1 and the second clock state STATE2 are inverted. As shown in FIG. 2A, the determining unit 110 determines that the first clock state STATE1 and the second clock state STATE2 are both in a low state (0, 0) and are in phase. Therefore, the determining unit 110 will know that there is no edge of the clock signal source CKP/CKN between the first clock state STATE1 and the second clock state STATE2.

The determining unit 110 adjusts the adjustable delay time ADT of the adjustable delay unit 100 when it is determined that the first clock state STATE1 and the second clock state STATE2 are in phase. In this embodiment, the determining unit 110 increases the adjustable delay time ADT to delay the first delayed clock signal CKD1 with respect to the clock signal CK for a longer time.

After the adjustable delay unit 100, the first delay unit 104, and the second delay unit 106 are further delayed according to the newly adjusted adjustable delay time ADT, the first sampling unit 102 and the second sampling unit 104 are in accordance with the first delay clock. When the sampling result of the signal CKD1 and the third delayed clock signal CKD3 is still in phase, the adjustable delay unit 100 will continue to adjust the adjustable delay time ADT until the sampling result reaches the inversion (0, as shown in FIG. 2B). 1) Until then. At this time, the clock phase is located at the second delayed clock signal CKD2 between the first delayed clock signal CKD1 and the third delayed clock signal CKD3, that is, substantially equal to the edge position of the clock signal source CKP/CKN. More specifically, the second delayed clock signal CKD2 obtained by adjusting in the manner of this embodiment is actually a clock period CKP/CKN difference of a whole clock period.

It should be noted that the term "substantially equal" is used herein to mean that the accuracy of the sampling may be affected due to the setting of the delay time of the first delay unit 104 and the second delay unit 106, and some errors may occur. There is a slight but tolerable error between the second delayed clock signal CKD2 and the phase of the clock signal source CKP/CKN, and is not completely equal.

Therefore, in the above manner, the clock recovery module 10 can detect the phase of the clock signal source CKP/CKN, so that the data recovery module 12 can be based on the second delay clock output by the first delay unit 104. Signal CKD2, correct recovery procedure for data signal DATA.

Similarly, in another embodiment, the sampling result of the first sampling unit 102 and the second sampling unit 104 according to the first delayed clock signal CKD1 and the third delayed clock signal CKD3 may be as shown in FIG. 2C. Both are in phase with the high state (1,1). At this time, the adjustable delay unit 100 can be adjusted and adjusted. The ADT is delayed, so that the first delayed clock signal CKD1 has a short time delay relative to the clock signal CK, and gradually approaches the edge position of the clock signal source CKP/CKN until the sampling result is inverted (0, 1). So far, to achieve the effect of correction.

It should be noted that in other embodiments, the first sampling unit 102 and the second sampling unit 104 may also be based on the falling edge of the first delayed clock signal CKD1 and the third delayed clock signal CKD3 to the clock signal source CKP/ The CKN samples and is judged by the judging unit 110 to control the adjustable delay time ADT of the adjustable delay unit 100. Taking the 2D picture as an example, the first sampling unit 102 and the second sampling unit 104 are in phase with the result of sampling the clock signal source CKP/CKN according to the falling edges of the first delayed clock signal CKD1 and the third delayed clock signal CKD3. (1,1). At this time, the judging unit 110 adjusts the adjustable delay time ADT until the sampling result is inverted (1, 0). If the sampling result is in phase (0, 0), the judging unit 110 can adjust the adjustable delay time ADT until the sampling result is inverted (1, 0). When the result of the sampling is reversed, the data recovery module 12 can also perform a correct recovery procedure on the data signal DATA according to the second delayed clock signal CKD2 output by the first delay unit 104 at this time.

Referring to FIG. 3, FIG. 3 is a waveform diagram of the second delayed clock signal CKD2 and the phase offset clock signals CKP1, CKP2, . . . , CKPN generated according to an embodiment of the present invention. In one embodiment, the second delayed clock signal CKD2 output by the first delay unit 104 can generate a complex phase offset clock signal CKP1, CKP2 via a delay phase locked loop module 114 as shown in FIG. After the CKPN, the data recovery module 12 is provided for data recovery. Therefore, in the case of low voltage differential signals (Low-voltage differential signaling, LVDS) transmission architecture specification, a clock cycle will correspond to a number of data, because the data frequency of the data signal DATA is N times the clock frequency of the clock signal source CKP/CKN, data The recovery module 12 can recover data according to the phase offset clock signals CKP1, CKP2, ..., CKPN generated by the delay phase locked loop module 114. It should be noted that the data and time recovery device 1 of the present invention can also be applied to other transmission architectures, and is not limited to the low voltage differential signal transmission architecture exemplified above.

Therefore, the clock recovery module 10 can correct the clock signal CK delayed by the differential-turn single-ended circuit 112, so that the second delayed clock signal CKD2 and the differential form become single-ended outputs. The clock signal source CKP/CKN is in phase. The data recovery module 12 will be able to properly recover the data signal DATA.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

1‧‧‧Information Time and Pulse Recovery Device

10‧‧‧ Clock Recovery Module

100‧‧‧Adjustable delay unit

102‧‧‧First sampling unit

104‧‧‧First delay unit

106‧‧‧second delay unit

108‧‧‧Second sampling unit

110‧‧‧judging unit

112‧‧‧Differential to single-ended circuit

114‧‧‧Delayed phase-locked loop module

12‧‧‧ Data Recovery Module

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2A to 2D are respectively a clock signal source, a clock signal, a first delayed clock signal, and a second delayed clock signal according to an embodiment of the invention. And a waveform diagram of the third delayed clock signal; and FIG. 3 is a waveform diagram of the second delayed clock signal and the phase offset clock signal generated according to an embodiment of the invention.

1‧‧‧Information Time and Pulse Recovery Device

10‧‧‧ Clock Recovery Module

100‧‧‧Adjustable delay unit

102‧‧‧First sampling unit

104‧‧‧First delay unit

106‧‧‧second delay unit

108‧‧‧Second sampling unit

110‧‧‧judging unit

112‧‧‧ Circuitry

114‧‧‧Delayed phase-locked loop module

12‧‧‧ Data Recovery Module

Claims (9)

A data recovery device includes: a clock recovery module, comprising: an adjustable delay unit for receiving a clock signal to delay the clock signal according to an adjustable delay time to generate a a first delayed clock signal, wherein the clock signal is generated according to a clock signal source, and the clock signal source and the clock signal have a delay time; a first sampling unit is configured to use the first delay time The pulse signal samples the clock signal source to capture a first clock state; a first delay unit delays the first delayed clock signal to generate a second delayed clock signal; and a second delay unit Delaying the second delayed clock signal to generate a third delayed clock signal; a second sampling unit for sampling the clock signal source according to the third delayed clock signal to obtain a second a clock state; and a determining unit, determining whether the first clock state and the second clock state are inverted, so that the first clock state and the second clock state are in phase Delayed order The adjustable delay time is adjusted; and a data recovery module recovers a data signal according to the second delayed clock signal when the first clock state and the second clock state are inverted. The data and time recovery device according to claim 1, wherein the determining unit determines that the first clock state is a low state and the second clock state is When it is low, the adjustable delay time is increased. The data and time recovery device of claim 2, wherein the adjustable delay time is decreased when the determining unit determines that the first clock state is high and the second clock state is high. The data recovery device according to claim 3, wherein when the determining unit determines that the first clock state is low and the second clock state is high, the data recovery module is configured according to the second delay The clock signal recovers the data signal. The data and time recovery device of claim 1, wherein the adjustable delay time is decreased when the determining unit determines that the first clock state is low and the second clock state is low. The data and time recovery device of claim 5, wherein the adjustable delay time is increased when the determining unit determines that the first clock state is high and the second clock state is high. The data recovery device according to claim 6, wherein when the determining unit determines that the first clock state is high and the second clock state is low, the data recovery module is configured according to the second delay The clock signal recovers the data signal. The data and time recovery device according to claim 1 further includes a delay locked loop (DLL), and generating a complex phase offset clock signal according to the second delayed clock signal, the data The recovery module substantially recovers the data signal according to the phase offset clock signals. The data and time recovery device according to claim 1 further includes a differential to single circuit, wherein the clock signal source is in a differential form to be converted to a single-ended circuit via the differential to The clock signal has a single-ended form.