TW201427251A - DC-DC controller and control method thereof - Google Patents

Abstract

A DC-DC controller and a control method thereof are provided. The dc-dc controller provides a pulse width modulation (PWM) signal to a post-stage circuit for regulating an output voltage. The DC-DC controller includes a ramp generator, a dynamic ramp valley controller, an error amplifier, a first comparator, and a PWM waveform generator. The ramp generator provides a ramp signal. The dynamic ramp valley controller generates a ramp valley signal according to the ramp signal and responses with at least one working parameter. The error amplifier provides an error signal according to a reference voltage and an output feedback voltage associated with the output voltage. The first comparator provides a first comparison result according to the ramp valley signal and the error signal. The PWM waveform generator provides the PWM signal to the post-stage circuit to response to the first comparison result, so as to regulate the output voltage.

Description

DC to DC controller and control method thereof

The invention relates to a DC-to-DC controller, and in particular to a DC-DC controller and a control method thereof.

1 is a circuit block diagram of a conventional DC-DC converter. The DC-to-DC converter 100 has a significant phenomenon in the unloading, that is, the output voltage V _OUT1 occurs when the output current I _{OUT1 of the} load changes from a heavy load or a medium load to a light load. due to too large oscillating phenomenon reactive than the amount (overshoot) of the (at time T _B in FIG. 7B illustrates the V _OUT1). Due to the unloading relationship of the DC-to-DC converter 100, the output current I _OUT1 will fall and the output voltage V _{OUT1 will} rise. Ideally, the voltage should be adjusted in such a way that the oscillation of the output voltage V _{OUT1 is} as small as possible, but conventional techniques are not easily maintained at a small upper/lower limit oscillation range due to the reaction overshoot.

Since the conventional DC-to-DC converter 100 is typically presented to the user in the form of an integrated circuit, the system designer using the integrated circuit does not readily investigate why the output current I _{OUT1 is} unloaded. The output voltage V _{OUT1 is} caused to generate excessive up and down oscillations. The amount of reaction caused by this unexplained cause makes it more unpredictable in designing systems and voltage control.

In view of this, the present invention provides a DC-to-DC controller and a control method thereof, thereby solving the problems described in the prior art.

The invention provides a DC-to-DC controller for providing a pulse width modulation signal to a subsequent stage circuit for adjusting an output voltage. The DC-to-DC controller includes a ramp generator, a dynamic ramp valley controller, an error amplifier, and a first Comparator and pulse width modulation waveform generator. A ramp generator is used to provide a ramp signal. The dynamic ramp valley controller is coupled to the ramp generator to receive the ramp signal and to react to at least one operating parameter to generate a ramp valley signal. The error amplifier receives the output feedback voltage associated with the reference voltage and the output voltage to provide an error signal. The first comparator is coupled to the dynamic ramp valley controller and the error amplifier. The first comparator receives the ramp valley signal and the error signal to provide a first comparison result. The pulse width modulation waveform generator is coupled to the first comparator and is responsive to the first comparison result to provide a pulse width modulation signal.

In an embodiment of the invention, the DC to DC controller further includes a compensation circuit. The compensation circuit is coupled between the output of the error amplifier and ground.

In an embodiment of the invention, the dynamic ramp valley controller in the DC to DC controller includes a sample and hold unit, a second comparator, and a ramp valley control unit. The sampling and holding unit is coupled to the ramp generator, receives the ramp signal, and uses the first comparison result as an operating parameter. The sampling and holding unit is coupled to the ramp generator for converting the ramp signal and a sampled and held DC crossover voltage in the first comparison result to provide a crossover value. The second comparator is coupled to the ramp generator and the sample and hold unit to receive the ramp signal and the crossover value to provide a second comparison result. Slope valley control The system is coupled to the ramp generator and the second comparator to receive the ramp signal and the second comparison result for generating and changing the slope bottom offset of the slope valley signal, and outputting the slope valley signal.

In an embodiment of the invention, the at least one operating parameter in the DC-to-DC controller is an input voltage, an output voltage, an output current, or a first comparison result.

In an embodiment of the invention, the pulse width modulation waveform generator in the DC to DC controller is a constant on time generator.

From another point of view, the present invention provides a DC-to-DC control method for providing a pulse width modulation signal to a subsequent stage circuit for adjusting an output voltage. The DC to DC control method includes: reacting to at least one operation according to a slope signal Parameters for generating a ramp valley signal; providing an error signal based on the reference voltage and the output voltage; providing a first comparison result based on the slope valley signal and the error signal; and reacting to the first comparison result to provide pulse width modulation Change signal.

In an embodiment of the invention, the at least one operating parameter in the DC-to-DC control method is an input voltage, an output voltage, an output current, or a first comparison result.

In an embodiment of the invention, the step of reacting to the at least one operating parameter according to the ramp signal comprises: receiving the ramp signal, and using the first comparison result as an operating parameter, for using one of the slope signal and the first comparison result Sampling and maintaining the DC crossover voltage for conversion to provide a crossover value; receiving the ramp signal and the crossover value to provide a second comparison result; and receiving the ramp signal and the second comparison result for generating and changing the slope valley value The bottom of the slope of the signal is offset and the ramp valley signal is output.

Based on the above, the present invention uses a correctable slope bottom offset to adjust the slope valley signal, and the modified slope bottom offset can be generated in accordance with the conditions of the low transition operating parameters. It is achieved that unintended pulses are effectively avoided during the unloading process. On the other hand, the generated ramp valley signal is compared with the error signal, and the pulse width modulation waveform generator can provide a pulse width modulation signal to the subsequent stage circuit for adjusting the output voltage according to the comparison result.

The above described features and advantages of the invention will be apparent from the following description.

Reference will now be made in detail be made to the embodiments of the invention In addition, the same or similar reference numerals are used in the drawings and the embodiments to represent the same or the like.

In order to investigate the problem that the output voltage V _OUT1 which occurs when the output current I _{OUT1 is} unloaded by the conventional DC-DC converter 100 is over-reacted due to excessive oscillation. 2 is a waveform diagram of output voltage, output current, and pulse signal of the DC-to-DC converter 100. Please also refer to Figure 1 and Figure 2. In FIG. 2, the output voltage V _OUT1 crosses its voltage value to the first value V _CROS1 at each point from time T1 to T4, and the pulse width modulation waveform generator 140 outputs a pulse at each point of time T1 to T4. Signal L _X1 . At time T5, the output current I _{OUT1 is} unloaded, the output voltage V _OUT1 starts to rise and the output current I _OUT1 falls, and at time T6, the voltage value of the output voltage V _OUT1 does not cross to the first value V _CROS1 , but the pulse width The modulated waveform generator 140 also outputs a pulse signal L _X1 . Therefore, the pulse signal L _{X1 of} T6 is unpredictable at this time, which is also the cause of the reaction output voltage V _{OUT1 having} a reaction overshoot.

The following is a more detailed analysis of the cause of the reaction excess. FIG. 3A is a waveform diagram of the pulse signal L _X1 of the DC-to-DC converter 100. FIG. 3B is a waveform diagram of the output current I _OUT1 of the DC-to-DC converter 100. FIG. 3C is a waveform diagram of the ramp signal V _RAMP1 and the error signal V _COMP1 of the DC-to-DC converter 100. FIG. 3D is a waveform diagram of the output voltage V _OUT1 of the DC-to-DC converter 100. Please also refer to Figure 1, Figure 3A to Figure 3D. First, the ramp generator 110 outputs a ramp signal V _RAMP1 , and the error amplifier 120 provides an error signal V _COMP1 according to the reference voltage V _REF1 and the feedback output voltage V _OUT1 . Next, the comparator 130 compares the slope valley signal V _RAMP1 with the error signal V _COMP1 , and the pulse width modulation waveform generator 140 outputs the pulse signal L _X1 according to the comparison result. At time T3, T4, the slope valley signal V _RAMP1 and the error signal V _COMP1 intersect at the second value V _CROS2 , so that the pulse width modulation waveform generator 140 outputs the pulse signal L _X .

In the above, the output current I _{OUT1 is} unloaded at time T5, the output voltage V _OUT1 starts to rise and the output current I _OUT1 falls, and the ramp valley signal V _RAMP1 falls. The ramp valley signal V _RAMP1 drops to the second value V _CROS2 at time T5_1 , but does not intersect the error signal V _COMP1 at the moment, and at time T6, the slope valley signal V _RAMP1 intersects the error signal V _COMP1 at the third value. V _CROS3 , wherein the third value V _{CROS3 is} lower than the second value V _CROS2 . Then, at time T6, the pulse width modulation waveform generator 140 outputs a pulse signal L _X1 according to the comparison result, which is also the main cause of the operation of the conventional DC-to-DC converter 100 to cause excessive oscillation of the output voltage V _OUT1 .

4A is a circuit diagram of a DC to DC converter in accordance with an embodiment of the present invention. Please refer to Figure 4A. The DC-DC converter 400A includes a DC-to-DC controller 410 and an output module 480. The DC-DC controller 410 is coupled to the output module 480. The DC-to-DC controller 410 is configured to provide a pulse width modulation signal S _PWM to the subsequent stage circuit (output module 480) to adjust the output voltage V _OUT .

The DC-to-DC controller 480 includes a ramp generator 420, a dynamic ramp valley controller 430, an error amplifier 440, a first comparator 450, and a pulse width. A pulse width modulation waveform generator (PWM waveform generator) 460. The dynamic ramp valley controller 430 is coupled to the ramp generator 420. The first comparator 450 is coupled to the dynamic ramp valley controller 430 and the error amplifier 440. The pulse width modulation waveform generator 460 is coupled to the first comparator 450 and the output module 480.

The ramp generator 420 is configured to generate and provide a ramp signal V _RAMP . The dynamic ramp valley controller 430 receives the ramp signal V _RAMP and is responsive to at least one operating parameter 432 to generate a ramp valley signal V _RAMP-VALLEY , wherein the at least one operating parameter 432 can be an input voltage V _IN or an output voltage V _OUT or output current I _OUT or first comparison result V _CMP1 or frequency. The slope valley signal V _RAMP-VALLEY can be expressed as an M value + offset value, and the offset value = f (V _IN , V _OUT , I _OUT , V _CMP1 , ...), where M is a fixed value of the previous moment, and offset The value is the bottom offset of the ramp, and the offset value can be a functional formula for operating parameters such as V _IN , V _OUT , I _OUT , V _CMP1 .

In this embodiment, the dynamic ramp valley controller 430 uses at least one operating parameter to correct the slope bottom offset and adjust the slope valley signal V _RAMP-VALLEY to avoid the fixed slope value of the prior art. To the performance of low transitions. In addition, different slope bottom offsets can be produced as the operating parameters change during low transitions. Please note that the present invention does not particularly limit the number of operating parameters, and the manner in which the dynamic ramp valley controller 430 adjusts according to the operating parameters may be any method, all depending on the actual design requirements. Additionally, one of the purposes is that the dynamic ramp valley controller 430 can effectively avoid inadvertently generating unintended pulses during the unloading process.

Furthermore, the non-inverting input of error amplifier 440 receives the reference voltage V _REF and its inverting input receives the output feedback voltage associated with output voltage V _OUT . The error amplifier 440 is used to generate and provide an error signal V _COMP . The inverting input of the first comparator 450 receives the ramp valley signal V _RAMP-VALLEY , the non-inverting input receives the error signal V _COMP , and the first comparator 450 generates and provides the first comparison result V _CMP1 to the pulse width Modulation waveform generator 460. The pulse width modulation waveform generator 460 is responsive to the first comparison result V _CMP1 and provides a pulse width modulation signal S _PWM to the output module 480. The output module 480 receives the DC input voltage V _IN and is responsive to the pulse width modulation signal S _PWM , so that a stable DC output voltage V _OUT can be provided, and the oscillation of the output voltage V _OUT can be maintained at a small time during unloading. upper / lower limit value of the range of oscillation (FIG. 7B at time T V _{OUT B} is shown).

In yet another embodiment, the DC to DC controller 410 can further include a compensation circuit 470. The compensation circuit 470 includes a series connected resistor R1 and a capacitor C1. The compensation circuit 470 is coupled between the output of the error amplifier and the ground GND.

Additionally, the pulse width modulation waveform generator 460 can be a constant on time generator. The output module 480 can include an inductor L1, a driving unit 482, and a switching unit 484. The switching unit 484 is coupled to the second end of the inductor L1, the DC input voltage V _IN and the ground GND. The driving unit 482 is coupled to the pulse width modulation waveform generator 460, and controls the switching unit 484 to switch the input voltage V _IN and the ground GND according to the pulse width modulation signal S _PWM , and further outputs an output voltage V _OUT at the first end of the inductor L1.

For example, the switching unit 484 can include a first transistor M1 and a second transistor M2. The second transistor M2 is connected in series with the first transistor M1 between the input voltage V _IN and the ground GND. The gate of the first transistor M1 and the second transistor M2 are coupled to the driving unit 482, and the common contact of the first transistor M1 and the second transistor M2 is coupled to the second end of the inductor L1, and the first transistor M1 is The conduction state of the second transistor M1 is controlled by the driving signals UG, LG of the driving unit 482. In addition, the output module 480 can further include a compensation circuit 486 including a series connected resistor R2 and a capacitor C2. The compensation circuit 486 is coupled between the first end of the inductor L1 and the ground GND.

4B is a circuit diagram of a DC to DC converter in accordance with another embodiment of the present invention. Please refer to Figure 4B. The circuit architecture of Figure 4B is based on Figure 4A with the main difference being the operating parameters used by the dynamic ramp valley controller 430A. In FIG. 4B, the operating parameter may take the first comparison result V _CMP1 , and the dynamic ramp valley controller 430A adjusts the slope valley signal V _RAMP-VALLEY according to the received ramp signal V _RAMP and the first comparison result V _CMP1 .

FIG. 5 is a detailed circuit diagram of a dynamic ramp valley controller 430A in accordance with an embodiment of the present invention. Please refer to Figure 5. The dynamic ramp valley controller 430A includes a sample and hold unit 510, a second comparator 520, and a ramp valley control unit 530. The sample and hold unit 510 is coupled to the ramp generator 420, the second comparator 520, and the ramp valley control unit 530. The second comparator 520 is coupled to the ramp generator 420, the sample and hold unit 510, and the ramp valley value control unit 530. The sampling and holding unit 510 receives the ramp signal V _RAMP and uses the first comparison result V _CMP1 as an operating parameter for sampling and maintaining the DC balance voltage of the previous moment, and the slope signal V _RAMP and the first comparison result V _CMP1 The sampled and maintained DC crossover voltage is converted to provide the crossover value V _RAMP-SH . The inverting input of the second comparator 520 receives the ramp signal V _RAMP , its non-inverting input receives the crossover value V _RAMP-SH , and the second comparator 520 provides the second comparison result V _CMP2 . Wherein, in normal normal operation, the second comparison result V _CMP2 is 0, and when a low transition occurs, the second comparison result V _CMP2 transitions to 1 due to the falling of the ramp signal V _RAMP . The ramp bottom value control unit 530 receives the ramp signal V _RAMP and the second comparison result V _CMP2 for generating and changing the slope bottom offset of the slope valley signal, and outputs the ramp valley signal V _RAMP-VALLEY .

FIG. 6A is a waveform diagram of the pulse width modulation signal S _PWM of the pulse width modulation waveform generator 460. Fig. 6B is a waveform diagram of the output current I _OUT1 of the DC-to-DC converter 400B. 6C is a waveform diagram of the ramp valley signal V _RAMP-VALLEY and the error signal V _COMP . Fig. 6D is a waveform diagram of the output voltage V _OUT of the DC-to-DC converter 400B. Please refer to FIG. 4B, FIG. 5, and FIG. 6A to FIG. 6D at the same time. In this embodiment, at time T4_1, T4_2, the slope valley signal V _RAMP-VALLEY and the error signal V _COM1 intersect at the first level value V _LEV1 , so that the pulse width modulation waveform generator 460 outputs the pulse width adjustment. The variable signal S _{PWM is} represented by a pulse width modulation signal S _PWM in pulses. When the output current I _{OUT is} unloaded at time T5_2, the output voltage V _OUT starts to rise and the output current I _OUT drops, and the ramp valley signal V _RAMP-VALLEY falls until the time T5_3 becomes a fixed value, and is fixed at the first level. A value between the value V _LEV1 and the second level value V _LEV2 . Therefore, after the elapse of time T5_3, the value of the ramp valley signal V _RAMP-VALLEY does not endlessly fall and intersects with the error signal V _COM1 , so the pulse width modulation waveform generator 460 does not output an undesired The pulse, so that the resulting output voltage V _OUT1 does not have excessive oscillations.

7A and 7B are schematic diagrams showing waveform comparisons between an embodiment of the present invention and a prior art. For convenience of comparison, as shown in FIG. 7A, the output current I _{OUT of the} embodiment of the present invention is normalized with the output current I _{OUT1 of the} prior art; as shown in FIG. 7B, the embodiment of the present invention is The output voltage V _OUT is normalized with the output voltage V _{OUT1 of the} prior art. At time T _A , the output current changes from light load to heavy load, and the oscillations of the two output voltages are similar. However, at time T _B , the output current changes from heavy load to light load, and the known output voltage V can be clearly seen. _OUT1 produces an excessive oscillation, and the output voltage V _{OUT of the} embodiment of the present invention is much smaller in comparison.

Based on the above, since the present invention uses the correctable slope bottom offset to adjust the slope valley signal, it is possible to effectively prevent unintended pulses from affecting the output voltage during the unloading process, and effectively improve the low transition response. Exceeding the amount.

Based on the content disclosed in the above embodiments, a general DC to DC control method can be integrated. More specifically, FIG. 8 is a flow chart of a DC-to-DC control method according to an embodiment of the present invention. For convenience of description, please refer to FIG. 4A and FIG. 8 together. The DC-to-DC control method of this embodiment may include the following steps: as shown in step S801, according to the ramp signal (V _RAMP ) and reacting to at least one operating parameter (432) To generate a ramp valley signal (V _RAMP-VALLEY ).

Next, as shown in step S803, the output feedback voltage associated with the output voltage (V _OUT ) is referenced according to the reference voltage (V _REF ) to provide an error signal (V _COMP ).

Next, as shown in step S805, the slope comparison signal (V _RAMP-VALLEY ) and the error signal (V _COMP ) are used to provide a first comparison result (V _CMP1 ).

Next, as shown in step S807, the first comparison result (V _CMP1 ) is reacted to provide a pulse width modulation signal (S _PWM ).

Then, as shown in step S809, the input voltage (V _IN ) is received and reacted to a pulse width modulation signal (S _PWM ) to provide an output voltage (V _OUT ).

In summary, the present invention uses a correctable slope bottom offset to adjust the slope valley signal, and the modified slope bottom offset can be generated in accordance with the conditions of the low transition operating parameters. As such, it is achieved that unintended pulses are effectively avoided during the unloading process. On the other hand, the generated ramp valley signal is compared with the error signal, and the pulse width modulation waveform generator can provide a pulse width modulation signal to the subsequent stage circuit for adjusting the output voltage according to the comparison result.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧DC to DC converter

110‧‧‧Slope generator

120‧‧‧Error amplifier

130‧‧‧ comparator

140‧‧‧ Pulse Width Modulation Waveform Generator

150‧‧‧ parts

400A, 400B‧‧‧DC to DC Converter

410‧‧‧DC to DC controller

420‧‧‧Slope generator

430, 430A‧‧‧ Dynamic Slope Valley Controller

432‧‧‧ at least one working parameter

440‧‧‧Error amplifier

450‧‧‧First comparator

460‧‧‧ Pulse width modulation waveform generator

470, 486‧‧‧ compensation circuit

480‧‧‧Output module

482‧‧‧ drive unit

484‧‧‧Switch unit

510‧‧‧Sampling and holding unit

520‧‧‧Second comparator

530‧‧‧Slope Valley Control Unit

C1, C2‧‧‧ capacitor

GND‧‧‧ Grounding

L1‧‧‧Inductance

LG, UG‧‧‧ drive signals

M1‧‧‧first transistor

M2‧‧‧second transistor

R1, R2‧‧‧ resistance

T1~T6, T4_1, T4_2, T5_1~T5_3‧‧‧

I _OUT , I _OUT1 ‧‧‧Output current

L _X1 ‧‧‧pulse signal

S _PWM ‧‧‧ pulse width modulation signal

V _IN ‧‧‧ input voltage

V _CMP1 ‧‧‧ first comparison result

V _CMP2 ‧‧‧ second comparison result

V _COMP , V _COMP1 ‧‧‧ error signal

V _CROS1 ‧‧‧ first value

V _CROS2 ‧‧‧ second value

V _CROS3 ‧‧‧ third value

V _LEV1 ‧‧‧ first _priority

V _LEV2 ‧‧‧ second value

V _OUT , V _OUT1 ‧‧‧ output voltage

V _RAMP ‧‧‧Slope Signal

V _RAMP-SH ‧‧‧crossover value

V _RAMP1 ‧‧‧Slope Valley Signal

V _RAMP-VALLEY ‧‧‧Slope Valley Signal

V _REF , V _REF1 ‧‧‧reference voltage

S801~S809‧‧‧ steps of a DC-to-DC conversion method according to an embodiment of the present invention

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention

1 is a circuit block diagram of a conventional DC to DC converter.

2 is a waveform diagram of output voltage, output current, and pulse signal of the DC-to-DC converter 100.

FIG. 3A is a waveform diagram of the pulse signal L _X1 of the DC-to-DC converter 100.

FIG. 3B is a waveform diagram of the output current I _OUT1 of the DC-to-DC converter 100.

FIG. 3C is a waveform diagram of the ramp signal V _RAMP1 and the error signal V _COMP1 of the DC-to-DC converter 100.

FIG. 3D is a waveform diagram of the output voltage V _OUT1 of the DC-to-DC converter 100.

4A is a circuit diagram of a DC to DC converter in accordance with an embodiment of the present invention.

4B is a circuit diagram of a DC to DC converter in accordance with another embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of a dynamic ramp valley controller 430A in accordance with an embodiment of the present invention.

FIG. 6A is a waveform diagram of the pulse width modulation signal S _PWM of the pulse width modulation waveform generator 460.

Fig. 6B is a waveform diagram of the output current I _OUT1 of the DC-to-DC converter 400B.

6C is a waveform diagram of the ramp valley signal V _RAMP-VALLEY and the error signal V _COMP .

Fig. 6D is a waveform diagram of the output voltage V _OUT of the DC-to-DC converter 400B.

7A and 7B are schematic diagrams showing waveform comparisons between an embodiment of the present invention and a prior art.

FIG. 8 is a flow chart of a DC-to-DC control method according to an embodiment of the present invention.

400A‧‧‧DC to DC Converter

410‧‧‧DC to DC controller

420‧‧‧Slope generator

430‧‧‧Dynamic Slope Valley Controller

432‧‧‧ at least one working parameter

440‧‧‧Error amplifier

450‧‧‧First comparator

460‧‧‧ Pulse width modulation waveform generator

470, 486‧‧‧ compensation circuit

480‧‧‧Output module

482‧‧‧ drive unit

484‧‧‧Switch unit

C1, C2‧‧‧ capacitor

GND‧‧‧ Grounding

L1‧‧‧Inductance

LG, UG‧‧‧ drive signals

M1‧‧‧first transistor

M2‧‧‧second transistor

R1, R2‧‧‧ resistance

I _OUT ‧‧‧Output current

S _PWM ‧‧‧ pulse width modulation signal

V _CMP1 ‧‧‧ first comparison result

V _COMP ‧‧‧ error signal

V _IN ‧‧‧ input voltage

V _OUT ‧‧‧ output voltage

V _RAMP ‧‧‧Slope Signal

V _RAMP-VALLEY ‧‧‧Slope Valley Signal

V _REF ‧‧‧reference voltage

Claims (8)

A DC-to-DC controller for providing a pulse width modulation signal to a subsequent stage circuit for adjusting an output voltage, the DC to DC controller comprising: a ramp generator for providing a ramp signal; a dynamic ramp a valley controller coupled to the ramp generator for receiving the ramp signal and responsive to at least one operating parameter to generate a ramp valley signal; an error amplifier receiving a reference voltage associated with the output voltage for outputting Applying a voltage to provide an error signal; a first comparator coupled to the dynamic ramp valley controller and the error amplifier, receiving the slope valley signal and the error signal to provide a first comparison result; and a The pulse width modulation waveform generator is coupled to the first comparator and is responsive to the first comparison result to provide the pulse width modulation signal. The DC-to-DC controller of claim 1, further comprising: a compensation circuit coupled between the output of the error amplifier and a ground. The DC-to-DC controller of claim 1, wherein the dynamic ramp-valve controller comprises: a sampling and holding unit coupled to the ramp generator, receiving the ramp signal, and using the first comparison The result is used as the working parameter, and the DC signal is sampled and maintained after the slope signal and the first comparison result. The crossover voltage is converted to provide a crossover value; a second comparator is coupled to the ramp generator and the sample and hold unit to receive the ramp signal and the crossover value to provide a second comparison result; And a slope bottom value control unit coupled to the slope generator and the second comparator to receive the slope signal and the second comparison result for generating and changing a slope bottom offset of the slope valley signal, and The ramp valley signal is output. The DC-to-DC controller of claim 1, wherein the at least one operating parameter is the input voltage, the output voltage, an output current, or the first comparison result. The DC-to-DC controller of claim 1, wherein the pulse width modulation waveform generator is a constant on-time generator. A DC-to-DC control method for providing a pulse width modulation signal to a subsequent stage circuit for adjusting an output voltage, the DC to DC control method comprising: reacting to at least one operating parameter according to a ramp signal to generate a a slope valley signal; outputting a feedback voltage according to a reference voltage and one of the output voltages to provide an error signal; providing a first comparison result according to the slope valley signal and the error signal; and reacting to the The first comparison result is to provide the pulse width modulation signal. Such as the DC to DC control party described in claim 6 The method, wherein the at least one operating parameter is the input voltage, the output voltage, an output current, or the first comparison result. The DC-to-DC control method of claim 6, wherein the step of reacting to the at least one operating parameter according to the ramp signal comprises: receiving the ramp signal, and using the first comparison result as the operating parameter, Converting the slope signal to a sampled and maintained DC crossover voltage of the first comparison result to provide a crossover value; receiving the ramp signal and the crossover value to provide a second comparison And receiving the slope signal and the second comparison result for generating and changing a slope bottom offset of the slope valley signal, and outputting the slope valley signal.