TW201427057A - Photovoltaic cell and process of manufacture - Google Patents

Abstract

A material is manufactured from a single piece of semiconductor material. The semiconductor material can be an n-type semiconductor. Such a manufactured material may have a top layer with a crystalline structure, transitioning into a transition layer, further transitioning into an intermediate layer, and further transitioning to the bulk substrate layer. The orientation of the crystalline pores of the crystalline structure align in layers of the material. The transition layer or intermediate layer includes a material that is substantially equivalent to intrinsic semiconductor. Also described is a method for manufacturing a material from a single piece of semiconductor material by exposing a top surface to an energy source until the transformation of the top surface occurs, while the bulk of the material remains unaltered. The material may exhibit photovoltaic properties.

Description

Photovoltaic cell and manufacturing method thereof Cross-reference to related applications

This application claims the following: US Application No. 13/844,686, filed on March 15, 2013 (Attorney Docket No. 44671-047 (P7)); filed on February 6, 2013 US Provisional Application No. 61/761,342 (Attorney Docket No. 44671-047 (P7)); US Provisional Application No. 61/619,410, filed on April 2, 2012 (Attorney Docket No. 44671-033) (P2)); US Provisional Application No. 61/722,693, filed on November 5, 2012 (Attorney Docket No. 44671-034 (P3)); Application No. 61/ on June 4, 2012 U.S. Provisional Application No. 655,449 (Attorney Docket No. 44671-035 (P4)); US Provisional Application No. 61/738,375, filed on December 17, 2012 (Attorney Docket No. 44671-038 (P5)) US Provisional Application No. 61/715,283, filed on October 17, 2012 (Attorney's Case No. 44671-041 (P12)); US Provisional No. 61/715,286, filed on October 18, 2012 Application (Attorney Docket No. 44671-043 (P13)); U.S. Provisional Application No. 61/715,287 (Attorney Docket No. 44671-044 (P14)) filed on October 18, 2012.

This invention relates to photovoltaic devices and, in particular, to photovoltaic device structures having improved photovoltaic properties and a simplified manufacturing process.

Conventional methods for making photovoltaic materials typically require certain additives to a semiconductor. These additives, including gallium arsenide (GaAs), are highly toxic and carcinogenic, and their Use in the manufacture of photovoltaic materials can increase the risk of negative health and environmental effects. It is highly desirable to have a method of manufacturing one of the photovoltaic materials in which the additive is used.

Conventional methods for fabricating photovoltaic materials also require a multi-step process or a different approach, each of which may occur at a different device and at different times, and requires its own management and resources. For example, different doping methods are suitable for fabricating different semiconductor wafers and sealing different types of wafers together in a particular manner to form a photovoltaic cell. The purpose of the doping method and wafer assembly is to form a p-n junction or a p-i-n junction between the wafers to achieve an overall photovoltaic effect of one of the assembled materials. Each of these manufacturing stages incurs a fee. It is highly desirable to have a method of manufacturing a photovoltaic material that reduces the number of methods or steps required to reduce cost.

The methods described in this section are methods that can be implemented, but are not necessarily methods that have been previously conceived or implemented. Therefore, unless otherwise indicated, it should not be assumed that any of the methods set forth in this section are considered prior art only because they are included in this section.

The preferred embodiment of the present invention provides a novel method of making one of the novel materials having photovoltaic properties. Embodiments include the use of a heating method to fabricate a method of forming one or more photovoltaic structures on a semiconductor wafer, and providing the advantage of low manufacturing cost. Embodiments further include a method for reducing the resistivity of a surface of one of the high resistivity surfaces on a semiconductor wafer.

10‧‧‧Semiconductor Wafer/Processed Semiconductor Wafer/Semiconductor

12‧‧‧ wafer holding parts

14‧‧‧Hot

16‧‧‧Photovoltaic structure / photoelectric voltaic layer

18‧‧‧Semiconductor block

20‧‧‧Photovoltaic structure/photovoltaic materials

22‧‧‧Material Wafer Structure/Wafer Structure

24‧‧‧ Wafer structure

26‧‧‧ Telluride layer/layer

28‧‧‧Improved ion-implanted photovoltaic materials/photovoltaic materials obtained

30‧‧‧Ion implantation layer

32‧‧‧n++on n矽 wafer

33‧‧‧n++ block

34‧‧‧Photovoltaic materials obtained

36‧‧‧Separation/protective film

39‧‧‧Wafer holding structure / furnace base / high quality wafer holder

40‧‧‧Photovoltaic structure

42‧‧‧Photovoltaic materials

44‧‧‧Complete battery

46‧‧‧Top electrode

48‧‧‧ bottom electrode

800‧‧‧Top view

802‧‧ ‧ bottom view

In each of the drawings FIG way of example and not limitation in the way of illustration preferred embodiments of the present invention, and in which like reference numerals refer to similar elements and in which: Figure 1 is according to the present invention Some embodiments illustrate a diagram of one of a section of a profile during one of the heating stages of the manufacturing process.

2 is a diagram of one of a cross-sectional view of one of the photovoltaic materials during one stage of the fabrication process after forming the photovoltaic device, in accordance with certain embodiments of the present invention.

3 is a diagram of one of a cross-sectional views during one stage of a fabrication process after removal of one of the photovoltaic structures, in accordance with certain embodiments of the present invention.

4 is a diagram of one of a cross-sectional views during one stage of a fabrication process after forming a germanide layer, in accordance with some embodiments of the present invention.

5 is a diagram illustrating one of a cross-sectional views during one stage of a fabrication process after ion implantation and activation methods, in accordance with certain embodiments of the present invention.

6 is a diagram of one of a cross-sectional views during one of the heating stages of a method of fabricating an n-type semiconductor wafer on an n++, in accordance with some embodiments of the present invention.

7 is a diagram of one of a cross-sectional views during one stage of a fabrication process after forming a photovoltaic structure on an n++ type layer, in accordance with some embodiments of the present invention.

Figure 8 is a diagram illustrating one of two views of a section of a barrier layer before and after a heating phase of a fabrication method, in accordance with some embodiments of the present invention.

9 is a view of one of the sections during a heating phase of a fabrication method performed by a large wafer holding structure to prevent formation of a photovoltaic layer at the bottom surface, in accordance with certain embodiments of the present invention. A picture.

10 is a diagram illustrating one of a cross-sectional views during one stage of a manufacturing process after a heating stage, in accordance with certain embodiments of the present invention.

Figure 11 is a diagram showing one of a cross-sectional view of one of the photovoltaic materials assembled into a photovoltaic device in accordance with some embodiments of the present invention.

12 is a flow chart illustrating an example of a method in which a photovoltaic cell is fabricated from a semiconductor wafer and assembled into a photovoltaic device in accordance with some embodiments of the present invention. .

Figure 13 is a graph illustrating the relationship between the measured open circuit voltage and the heating temperature used to form the material shown in Figure 3, in accordance with certain embodiments of the present invention.

In the following description, numerous specific details are set forth to provide a It will be appreciated by those skilled in the art, however, that the embodiments of the invention may be practiced without the specific details. In addition, some well known structures are not shown in detail to avoid unnecessarily obscuring the invention.

Heating method for forming a photovoltaic structure

In accordance with an embodiment of the present invention, a semiconductor wafer having one of the dopant elements in the wafer is processed in a heating process to produce a material having photo-voltaic properties. This heating method induces diffusion of dopant elements in the wafer, resulting in a change in one of the semiconductor resistivities. A photovoltaic structure is formed at the surface of the semiconductor wafer by controlling the technical details of the heating method, such as heating parameters, temperature, time, and cooling rate, in addition to other parameters set forth further below.

In accordance with a preferred embodiment of the present invention, FIG. 1 is a diagram of a cross-section of a semiconductor wafer 10 on a wafer holding member 12 during an initial heating phase of one of the fabrication methods in accordance with an embodiment of the present invention. In some embodiments, heat 14 is applied to the top and bottom of the wafer. When both sides of the wafer are subjected to a threshold condition (including heating), a photovoltaic high resistivity layer is formed in each side of the wafer exposed to the heat source.

In accordance with certain embodiments of the present invention, semiconductor wafer 10 includes a doped single crystal germanium wafer, such as an n-type germanium wafer. The germanium wafer has a thickness greater than one of 10 μm. In a preferred embodiment, the germanium wafer has a thickness of one of 200 μm. In some embodiments, semiconductor wafer 10 includes any of germanium (Si), germanium (Ge), or any other group IV semiconductor. In some embodiments, the semiconductor wafer 10 has 1 Ω in the (100) plane of the crystal orientation. Cm to 5Ω. One of the resistivities of cm.

The dopant element includes any one of phosphorus (P), nitrogen (N), antimony (Sb), arsenic (As), or any other element of the V group. In one example, the phosphorus content in the germanium wafer is above 0.01 ppb. In some embodiments, as a result of one of the standard n-type germanium wafer fabrications, the phosphorus content is the minimum amount of dopant present in the n-type germanium wafer. For a higher concentration, phosphorus is added by methods such as ion implantation and chemical diffusion.

In accordance with embodiments of the present invention, wafer heating is performed in a variety of ways including, but not limited to, infrared heating, laser heating, and hot fireplace heating. In some embodiments, the heating method used to process the semiconductor wafer 10 affects the photovoltaic performance of the photovoltaic cell constructed from the processed semiconductor wafer 10. In some embodiments, the cooling rate after the heating phase is a key factor in the fabrication of photovoltaic cells, and the heating rate is one of the less critical factors in photovoltaic cell fabrication.

In a preferred embodiment, maximum photovoltaic cell performance is achieved under the following conditions: heating temperature above 1500 K, heating time above 5 minutes, and about 1 x 10 ^-3 Pa. Table 1 provides an overview of one of the parameters used in heating semiconductor wafer 10 in accordance with an embodiment of the present invention.

After completion of the heating method, comprising a semiconductor wafer 10 as converted in the drawings as FIG. 2 explained the hierarchical structure of one of photovoltaics 11 illustrates a semiconductor material. In the embodiment as shown, the heating method results in the formation of the photovoltaic structure 16, the semiconductor bulk 18, and the photovoltaic structure 20 within the semiconductor 10 to form the photovoltaic alloy material 11. Both of the photovoltaic structures 16 and 20 include at least one high resistivity layer therein.

Method for treating the bottom surface to reduce its resistivity

According to some embodiments of the present invention, after the heating method of forming the photovoltaic devices 16 and 20 when both surfaces are subjected to the conditions of Table 1, the bottom surface of the photovoltaic wafer 11 is processed to Reduce the resistivity before making a photovoltaic cell. Treatment includes, but is not limited to, one or more of the following: the entity removes the bottom surface layer, forms a telluride at the bottom surface, and ion implants into the bottom surface layer. This reduction in resistivity at a bottom surface frees a photovoltaic cell to produce a larger output from one of the photovoltaic cells.

In some embodiments, a high resistivity layer is physically removed by removing some or all of the structures in the photovoltaic structure 20. 3 is a diagram illustrating a photovoltaic cell semiconductor wafer 11 after heat treatment and removal in accordance with a preferred embodiment of the present invention. In some embodiments, the elimination of the photovoltaic structure is achieved by solid polishing of the wafer surface, chemical etching, or other polishing methods. The resulting wafer structure 22 comprises a structure 16 photovoltaics and semiconductor body 18, as shown in FIG.

In some embodiments, solid polishing is achieved by polishing with abrasive particles, such as a diamond paste, alumina or tantalum carbide, which can polish one of the substrates. Since the heat treatment conditions can affect the depth of the bottom high resistivity layer, the thickness of the removed layer varies. In certain embodiments, the bottom surface is polished to a depth of one of 10 [mu]m. In some embodiments, the photovoltaic wafer semiconductor wafer 11 is polished using a chemical mechanical planarization (CMP) technique. In some embodiments, the material is removed from the bottom surface of the photovoltaic cell wafer 11 using one of a combination of solid polishing and CMP.

In some embodiments, the high resistivity bottom surface of semiconductor 10 is laser ablated by using a high output beam (including but not limited to YAG laser, excimer laser, argon ion laser, solid green laser or electron) Beam laser) or removed by performing a line scan on the back surface. In certain embodiments, the ablation is provided only for the center of the substrate to prevent deformation during laser ablation by the transparent conductive film that has been scattered onto the photovoltaic layer or onto the top surface A fragment of the semiconductor substrate is caused by a failure or surface leakage. In certain embodiments, a protective film, such as a polyimide film, is formed on the bottom surface prior to laser ablation and is removed by lift and clean after laser ablation to minimize scattering of the fragments .

In some embodiments, the bottom high resistivity surface layer is removed from the photovoltaic cell wafer 11 using chemical etching. A protective film, such as a SiN film, is formed at the top surface to shield the top surface from contact with an etch chemistry. The bottom side of the photovoltaic cell wafer 11 is immersed in an etch chemistry for etching the bottom surface to a depth of about 10 [mu]m. Examples of the etching chemistry used include, but are not limited to, KOH, NaOH, a mixed solution of nitric acid and hydrofluoric acid, or an etching solution in which one of these materials is diluted with acetic acid and water. Alternatively, dry etching can be used. After the bottom surface is removed by etching, the protective film is removed to expose the top surface of the photovoltaic cell wafer 11. For example, phosphoric acid is used to remove the SiN film.

In some embodiments, treating the bottom surface for reducing the resistivity of the bottom surface comprises forming a telluride on the surface behind the photovoltaic wafer 11 after the heating process. 4 illustrates an example of such a wafer structure 24 that includes a photovoltaic structure 16, a semiconductor body 18, a photovoltaic structure 20, and a germanide layer 26. To form a telluride after the heating process, an initial metallic material is first formed on the bottom surface. Such metals include, but are not limited to, nickel, cobalt, magnesium, lead, platinum, iron, ruthenium, osmium, manganese, zirconium, titanium, chromium, molybdenum, and vanadium. The formation of the metallic material onto the bottom surface can be performed using a sputtering process including metal organic chemical vapor deposition (MOCVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or other coating methods.

In certain embodiments, once a metallic material is formed, heat is applied to the surface to form a telluride. The heating temperature varies depending on the materials used. For example, forming Co onto one of the surfaces of the crucible requires a heat treatment of 620 K or higher to form a telluride.

The thickness of the telluride required to reduce the resistivity of the high resistivity layer at the bottom surface depends on the thickness of the high resistivity layer. An exemplary range of telluride formation for layer 26 is between It is between about 20 nm and 10 μm.

In some embodiments, treating the bottom surface for reducing the resistivity of the bottom surface comprises ion implantation at the bottom surface to partially convert one of the materials into an n++ type semiconductor. FIG. 5 illustrates the resulting ion implanted photovoltaic material 28 transformed from a photovoltaic cell material 11 in accordance with certain embodiments of the present invention. After the heating method used to form the photovoltaic cell material 11, ion implantation is performed at the bottom surface to increase the concentration of the dopant in the material. For example, in certain embodiments in which the photovoltaic alloy material 11 is an n-type substrate doped with phosphorus, ion implantation of phosphorus is preferred. In certain embodiments, an arsenic dopant is preferred. Any range of dosages and implant energies can be used to achieve a desired concentration. In certain embodiments, the desired concentration is 10 ²⁰ (cm ^-3 ). In some embodiments, phosphorus doping is accomplished by a diffusion method in a diffusion furnace rather than by ion implantation. In certain embodiments, ion implantation is performed at one of 100 keV to 300 keV high energy levels, followed by additional implantation at a low energy level of about 5 keV to 50 keV. This ion implantation method first implants ions deeper into the high resistivity layer and then increases to the concentration of the surface afterwards. In some embodiments, after ion implantation, a dopant activation process for activation is performed at room temperature, and for example, activation annealing is performed in a diffusion furnace. As shown in FIG. 5, the resulting material 28 comprises photovoltaics photovoltaics structure 16, the semiconductor blocks 18, 20 and the converted material is playing at least 30 of the ion-implanted layer photovoltaics.

Preventive method for reducing the resistivity of the bottom surface

In some embodiments, a prophylactic method can be performed on the semiconductor 10 prior to the heating process to reduce the resistance of the bottom surface by preventing, for example, forming at least one high resistivity layer in the photovoltaic structure 20. rate. The prophylactic method performed prior to heating includes, but is not limited to, using a semiconductor wafer of a particular type that prevents formation of a bottom high resistivity layer upon heating, such as an n++ substrate; forming a protective film to prevent a bottom surface is formed as a high resistivity layer upon heating; and a surface is prevented by concentrating heat to a surface or by placing the semiconductor 10 on a heat reservoir to shield the heat source Heat to a sufficient temperature.

Figure 6 illustrates the heating phase of a n++ wafer 32 on a n++ substrate when the semiconductor substrate is converted to a photovoltaic material. In some embodiments, an n++ upper n-substrate can be formed by first forming an n++ type germanium substrate and then forming an n-type germanium over the n++ type germanium. In some embodiments, the n++ type germanium substrate is formed by a Czochralski (CZ) method and has about 0.001 Ω. One of the resistivities of cm. In some embodiments, the n-type germanium formed by epitaxial growth over the n++ type germanium has about 5 Ω. One of the resistivities of cm and has a thickness of about 5 μm. Although an n++ type germanium is used in the present description, an n+ type semiconductor wafer or a substrate having a further lower resistivity can be used at the bottom layer without departing from the spirit of the present invention. As 6 shown in FIG lower as designated in Table 1 conditions, the heating method is applicable thereto the n ++ n-type silicon substrate to form a photovoltaics at the top surface play generation layer 16 without forming a photovoltaics at the bottom surface Layering. Shown in Figure 7 comprises a photovoltaics structure 16 and an n ++ type block 33 of the material 34 resulting photovoltaics.

In certain embodiments, as 800 shown in FIG plan view 8, the forming an insulating layer on the bottom surface of the semiconductor 10 of the prior heating method or a protective film 36 to prevent the formation of the semiconductor 10 during the high-resistivity layer at the heating method On the bottom surface. The protective film 36 may include a SiN film formed by sputtering to have a thickness of about 20 nm. After the heating step, to form a high resistivity photovoltaics only at a top portion of the semiconductor wafer 10 play structure 16 as the bottom in FIG. 8 802 shown in FIG. The isolation layer or protective film 36 is removed for completion of the solar cell prior to performing the next step. Although the protective film is a SiN film in this example, other materials may be used without departing from the spirit of the invention, including but not limited to: bismuth series inorganic films such as SiC, SiO ₂ , SiON and SiOC; metals; a metal alloy; an organic material; and any material having heat resistance equal to or higher than a temperature at which a photovoltaic layer is formed by a heating method as described with reference to FIG. 1 and Table 1.

In certain embodiments in which SiC is used as the isolation layer 36, the layer is not removed prior to forming the photovoltaic material into a photovoltaic cell, since the layer does not negatively affect the photovoltaic Volta performance. For example, when a bottom electrode is placed on the isolation layer 36 made of SiC, the isolation layer 36 forms a buffer to form an ohmic contact between the semiconductor body 18 and a bottom electrode. Details of a method of using SiC to form an ohmic contact between a semiconductor block 18 and a bottom electrode is further set forth in the U.S. Patent Application Serial No. Serial No. Serial No.-----. The patent application claims priority to US Provisional Application No. 61/655,449 (Attorney Docket No. 44671-035 (P4)) filed on June 4, 2012.

In certain embodiments, as shown in FIG. 9, a prophylactic method comprising the semiconductor wafer 10 is placed comprises a coolant, a heat dissipation material, or one for one of the wafer heating means heat reservoir The structure or furnace base 39 is held to prevent the bottom surface from being heated to a threshold temperature for producing a photovoltaic layer, such as the methods and conditions set forth above with reference to Figures 1 and 1. For example, while the wafer holding structure 39 maintains the bottom surface at a temperature of about 1100 K, the top surface reaches a desired temperature of about 1500 K. In some embodiments, the semiconductor wafer 10 is placed in direct contact with one of the wafer holding structures 39 configured by means of a tungsten alloy. In some embodiments, the inside of the wafer holding structure is further cooled with water. In some embodiments, the wafer holding structure 39 is configured with a material or a shape that provides a large heat capacity capable of reducing the temperature of the bottom surface of the semiconductor 10 without water cooling. A material having a relatively large mass to act as a heat reservoir and as a shield for the bottom portion and surface to one of the heat sources can be used without departing from the spirit of the invention. For example, other high melting point metals, including molybdenum, niobium and tantalum, may be used, and non-metallic materials such as quartz may be used. In some embodiments, the assembly of one of the high quality wafer holders 39 in contact with the semiconductor wafer 10 is introduced into a preheating furnace.

According to certain embodiments, heating method as shown in FIG. 9, the forming comprises one of heat treatment on the photoelectric volts from a top layer and a bottom layer of one of the heat treatment on the play structure 40, as shown in Fig.

One of the top surface resistivities in wafer structure 22 is reduced to the desired photovoltaic performance optimization. In one embodiment, the cell efficiency is high when the junction between the photovoltaic device 16 and the semiconductor body 18 is positioned relatively close to the wafer surface or within 0.5 microns and 1.5 microns. When the junction is too deep into the bulk or above 2 microns, cell efficiency begins to degrade due to reduced penetration of light into the wafer. The processing temperature, time, and process pressure are adjustable to achieve a desired location of one of the junctions.

Formation of photovoltaic cells

Figure 11 illustrates an example of the use of one of the photovoltaic cells 42 to become a photovoltaic cell, as set forth in any of the above examples. A completed battery 44 includes a top electrode 46 disposed above the top surface of the photovoltaic material 42. In a preferred embodiment, any transparent conductive oxide (TCO) such as indium tin oxide (ITO), ZnO, NiO, or any other type of transparent electrode can be used as a top electrode. Semi-transparent or translucent electrodes may also be used depending on the efficiency goal of the photovoltaic cell and the desired cost. An optional anti-reflective coating can be placed on the top surface (on top of the TCO layer) to improve light absorption and thus battery performance.

The completed battery 44 includes a bottom electrode 48. In some embodiments, an aluminum layer is preferred for the bottom electrode 48. The thickness of the bottom electrode can vary between 1 and 800 microns, typically about 400 microns. A bottom aluminum electrode can be fabricated by physical vapor deposition (sputtering), screen printing, ink jet printing, or other standard printing or metal deposition techniques. The bottom electrode 48 can be placed directly over a buffer on or near the bottom surface of the photovoltaic material 42, as previously described with reference to related U.S. Patent Application Serial No. 13/-.

Lower temperature heating method for reducing crystal defects

In some embodiments, forming a photovoltaic material using the heating methods set forth above with reference to Figures 1 , 6 , 8, and 9 can negatively affect one of the photovoltaics made of photovoltaic material. Crystal defects in the photovoltaic performance of voltaic cells. One of the lower temperature heating methods applied after forming the respective photovoltaic materials described above can be used to reduce crystal defects to increase the photovoltaic output. According to some embodiments of the invention, the temperature range of the second heating method comprises a temperature above 650 K and below 1000 K. In a specific example, one of the temperatures of 870 K is applied to the photovoltaic material in an inert gas atmosphere for one hour. This lower temperature heating method can be performed before or after assembling the photovoltaic material into a photovoltaic cell. Performing lower temperature heating after assembly of the photovoltaic cell provides the advantage of removing any binder from the aluminum bottom electrode by the second heating.

Method for manufacturing photovoltaic materials and batteries

Referring to FIG. 4 to illustrate a flowchart for one embodiment is formed of a material and one Photovoltaic cell 1200 of method steps in accordance with certain embodiments of the present invention. At step 1202, wafer cleaning is performed. In some embodiments, the tantalum wafer is cleaned by dipping the wafer into a hydrofluoric acid solution followed by water cleaning and air drying. The primary goal of this method is to remove the native oxide film formed on the surface of the wafer.

At step 1204, wafer heating is performed. Heat sources were applied to the top and bottom of the wafer under the conditions set forth in Table 1 above. At step 1206, a method for reducing the resistivity of the bottom layer is performed. Methods for reducing the resistivity of the bottom layer include, but are not limited to, physically removing the bottom surface layer, forming a telluride at the bottom surface, and ion implanting into the bottom surface layer to partially convert one of the materials into an n++ type semiconductor. In some embodiments, step 1206 is performed prior to step 1204. A method for reducing the resistivity of the bottom layer prior to a heating step includes, but is not limited to, using a semiconductor wafer of a particular type that prevents formation of a bottom high resistivity layer upon heating, such as an n++ substrate; Forming a protective film to prevent a bottom surface from being formed into a high resistivity layer immediately after heating; and preventing a surface from being blocked by concentrating heat to a surface or by placing a semiconductor on a heat reservoir to shield the heat source Heat to a sufficient temperature.

At step 1208, wafer cleaning is performed as appropriate (if needed). At step 1210, a top electrode is placed over the photovoltaic structure 16 of the wafer. In a preferred embodiment, any transparent conductive oxide (TCO) such as indium tin oxide (ITO), ZnO, NiO, or any other type of transparent electrode can be used as a top electrode. Depending on the efficiency of the photovoltaic cell Translucent electrodes can also be used for the target and desired cost.

At step 1212, an optional anti-reflective coating can be placed on the top surface (on top of the TCO layer) to improve light absorption and thus battery performance.

At step 1214, placement of the bottom electrode occurs. In some embodiments, an aluminum layer is preferred for the bottom electrode. The thickness of the bottom electrode can vary between 1 and 800 microns, typically about 400 microns. A bottom aluminum electrode can be fabricated by physical vapor deposition (sputtering), screen printing, ink jet printing, or other standard printing or metal deposition techniques. At step 1216, a battery test can be performed as appropriate to verify the photovoltaic device and test performance.

In one embodiment, an open circuit voltage ( _Voc ) measurement is used to test the performance of the battery. Figure 13 is a graph showing a measured _{Voc for} forming a particular heating temperature for a photovoltaic cell structure in accordance with the techniques discussed above. Improved photovoltaic cell performance is demonstrated for heating temperatures above 1350K. In particular, _Voc is almost doubled between 1350K and the highest temperature shown on the graph.

Other features, aspects, and objectives of the present invention are obtained from a review of the drawings and claims. It is to be understood that other embodiments of the invention can be developed and are within the spirit and scope of the invention and the scope of the invention.

The foregoing description of the preferred embodiments of the invention has in the It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Various additions, deletions, and modifications are covered as such. Therefore, the scope of the invention is indicated by the scope of the appended claims rather than the foregoing description. In addition, all changes that come within the meaning and range of the claims and the equivalents of the elements and features are intended to be included.

10‧‧‧Semiconductor Wafer/Processed Semiconductor Wafer/Semiconductor

16‧‧‧Photovoltaic structure / photoelectric voltaic layer

18‧‧‧Semiconductor block

20‧‧‧Photovoltaic structure/photovoltaic materials

Claims (19)

A photovoltaic device comprising: a photovoltaic cell material having one or more photovoltaic structures at one or more surfaces, whereby the one or more photovoltaics are formed by performing the following steps The semiconductor material of the voltaic structure: exposing a single piece of semiconductor material to an energy source, whereby the energy source causes heating of a portion of the single piece of semiconductor material; and stopping exposing the single piece of semiconductor material to an energy source, whereby the exposure The step and the stopping step cause the single piece of semiconductor material to be transformed into the photovoltaic material having one or more photovoltaic structures at one or more surfaces. A photovoltaic material according to claim 1, which is formed by further performing the steps of: forming a photovoltaic material having a reduced electrical resistivity at a bottom surface of one of the photovoltaic materials, Thereby the reduced resistivity results in the use of a photovoltaic cell using the photovoltaic device to produce a larger output than without a reduced resistivity. The photovoltaic material of claim 1, which is formed by further performing the process of: processing the bottom surface of the photovoltaic alloy material by performing any of: removing the bottom surface a layer; a telluride is formed at the bottom surface layer; ion implantation is performed into the bottom surface layer. The photovoltaic material of claim 1, which is formed by further performing the following steps: Performing a prophylactic method on the single piece of semiconductor material prior to the exposing and stopping steps by performing any of: forming a protective film on a bottom surface to prevent the bottom of the single piece of semiconductor material The surface is formed as a high resistivity layer upon heating; the exposure of the energy source is concentrated to one surface of the single piece of semiconductor material, whereby the concentration prevents the other surface from transforming the other surface into a photovoltaic structure. a target temperature; the single piece of semiconductor material is placed on a heat reservoir for the exposing step, whereby the placing prevents the other surface from reaching a target temperature at which the other surface is transformed into a photovoltaic structure; The n++ substrate is subjected to the exposing step and the stopping step, whereby the exposing and stopping steps cause an n-type germanium to be formed over the n++ germanium substrate to form an n++ upper n-volt voltaic material. The photovoltaic material of claim 4, wherein the protective film comprises a SiC layer, and a metal bottom electrode is formed on the SiC layer after the exposing and stopping to form an ohmic contact in a metal-to-semiconductor interface. A photovoltaic material according to claim 1, which is formed by further performing a second heating of the photovoltaic material at a temperature lower than a temperature of the heating in the exposure step, whereby the second heating The removal of crystalline defects in the one or more photovoltaic structures is caused. The photovoltaic material of claim 1, wherein the portion of the single piece of semiconductor material is heated to a temperature between 850 K and 1700 K. The photovoltaic material of claim 1, wherein the exposing and stopping steps occur in a vacuum. The photovoltaic material of claim 1, wherein the heating of the portion occurs for 1 minute One to a duration of 600 minutes. The photovoltaic material of claim 1, wherein the single piece of semiconductor material is an n-type germanium, the n-type germanium having one of phosphorus impurities. The photovoltaic material of claim 1, wherein the one or more photovoltaic structures comprise a high resistivity layer therein. The photovoltaic material of claim 1 wherein the single piece of semiconductor material comprises any of tantalum or other Group IV semiconductors. The photovoltaic material of claim 1, wherein the single piece of semiconductor material comprises any one of germanium or other Group IV semiconductors and has one of phosphorus, nitrogen, antimony, arsenic or other V group elements Impurities. The photovoltaic material of claim 1, wherein the single piece of semiconductor material has 1 Ω in the (100) plane of the crystal orientation. Cm to 5Ω. One of the resistivities of cm. The photovoltaic material of claim 1 wherein the single piece of semiconductor material has a thickness of at least 10 μm. The photovoltaic material of claim 1, wherein the single piece of photovoltaic material produces a photovoltaic effect when exposed to light. A photovoltaic device using a single piece of photovoltaic material as claimed in claim 1, the photovoltaic device comprising: the single piece of photovoltaic material; a bottom electrode provided under the single piece of photovoltaic material; And a top electrode provided over the single piece of photovoltaic material. A method for fabricating a photovoltaic cell comprising the steps of: exposing a single piece of semiconductor material to an energy source, whereby the energy source causes a portion of the single piece of semiconductor material to be heated; and stopping the single piece of semiconductor Exposing the material to an energy source whereby the exposing step and the stopping step cause the single piece of semiconductor material to be transformed into one or more surfaces A photovoltaic cell material having one or more photovoltaic structures. A photovoltaic device comprising: a photovoltaic cell material having one or more photovoltaic structures at one or more surfaces, whereby the one or more photovoltaics are formed by performing the following steps The semiconductor material of the voltaic structure: exposing an n-type germanium wafer to an energy source, whereby the energy source heats a portion of the n-type germanium wafer; and stopping exposing the n-type germanium wafer to an energy source The exposing step and the stopping step cause the single piece of semiconductor material to be transformed into the photovoltaic material having one or more photovoltaic structures at one or more surfaces, the one or more photovoltaic structures being Having a high-resistivity layer; forming a protective film of a SiC layer on a bottom surface to prevent the bottom surface of the single-piece semiconductor material from being formed into a high-resistivity layer upon heating; and placing a metal bottom electrode Above the SiC layer, thereby forming an ohmic contact between the metal bottom electrode and the metal-to-semiconductor interface between the n-type germanium wafers.