TW201426959A - Chip package - Google Patents

Abstract

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate and having a first opening exposing the first substrate; a third substrate disposed on the second substrate and having a second opening exposing the first opening and a portion of the second substrate; a first chip disposed on the first substrate exposed by the first opening; a second chip bonded with a portion of the second substrate and disposed on the second substrate and the first chip exposed by the second opening; and a third chip bonded with the third substrate and disposed on the second opening and the third substrate.

Description

Chip package

This invention relates to wafer packages, and more particularly to multi-chip packages.

As electronic products are moving toward light, thin, short, and small trends, the packaging structure of semiconductor wafers is also moving toward multi-chip package (MCP) structures to meet versatility and high performance requirements. Multi-chip package structures integrate different types of semiconductor wafers, such as logic wafers, analog wafers, control wafers or memory chips, onto a single package substrate.

However, as the number of wafers to be integrated increases, the two-dimensional integration of the multi-wafer on the package substrate (such as the germanium substrate) may result in an ineffective reduction of the package volume, and may also occupy too much area, resulting in an increase in manufacturing cost, which is disadvantageous. For the application of portable electronic products.

In addition, the industry has also reduced the size of the package and increased the speed of signal transmission.

An embodiment of the present invention provides a chip package including: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has a first opening to expose the first substrate; a third substrate disposed on the second substrate, wherein the third substrate has a second opening exposing the first opening and a portion of the second substrate; a first wafer disposed at the first opening Exposed on the first substrate; a second wafer, connected a second substrate connected to the portion and disposed on the second substrate exposed by the second opening and the first wafer; and a third wafer connected to the third substrate and disposed on the second substrate The second opening is over the third substrate.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

1 shows a cross-sectional view of a chip package 10 in accordance with an embodiment of the present invention. The chip package 10 is a stacked structure of a plurality of substrates and a plurality of wafers. In an embodiment, the chip package 10 includes substrates 100a, 100b, and 100c stacked on each other. The substrates 100a, 100b, and 100c may also be referred to as interposers. The materials of the substrates 100a, 100b, and 100c may include, but are not limited to, a semiconductor material, a glass, a ceramic material, a polymer material, or a combination thereof. In the embodiment of Fig. 1, a semiconductor material is taken as an example. For example, the substrates 100a, 100b, and 100c can be germanium substrates or germanium wafers. In an embodiment, the substrates 100a, 100b, and 100c may not be in direct contact with each other. For example, the substrates 100a, 100b, and 100c may be separated by a conductive structure

As shown in Fig. 1, the substrate 100b is disposed on the substrate 100a and has an opening 114b exposing the substrate 100a. In an embodiment, a conductive path 106a may be formed in the substrate 100a, which may include a horizontal conductive path (eg, a wiring layer), a vertical conductive path (eg, a conductive plug), or a combination of the foregoing. These conductive paths may not be connected to each other. In an embodiment, an insulating layer 104a may be formed between the substrate 100a and the conductive path 106a. A portion of the conductive path 106a may be exposed on the upper surface of the substrate 100a, which may be used to electrically connect with other electronic components. Similarly, a conductive path 106b and an insulating layer 104b may be formed in the substrate 100b. The conductive path 106b can be a plurality of lines that are not connected to each other. The substrate 100c may also be formed with a conductive path 106c and an insulating layer 104c. The conductive path 106c can be a plurality of lines that are not connected to each other.

It should be noted that embodiments of the present invention are not limited thereto. In other embodiments, among the plurality of conductive paths 106a in the substrate 100a, a portion of the conductive paths 106a may be electrically connected to each other. For example, a portion of the conductive paths 106a may be electrically connected to a same electrode. Similarly, in the plurality of conductive paths 106b in the substrate 100b, a part of the conductive paths 106b may be electrically connected to each other, and in the plurality of conductive paths 106c in the substrate 100c, a part of the conductive paths 106c may be electrically connected to each other. Sexual connection. As shown in Fig. 1, the wafer 102a is disposed in the opening 114b of the substrate 100b and is disposed on the substrate 100a exposed by the opening 114b. In one embodiment, the wafer 102a is electrically coupled to the conductive path 106a on the upper surface of the substrate 100a through the conductive structure 110a. Therefore, an electrical signal can be transferred between the substrate 100a and the wafer 102a. The conductive structure 110a may be a solder ball, a conductive bump, or Similar.

The chip package 10 further includes a wafer 102b. The wafer 102b is disposed in the opening 114c of the substrate 100c and disposed on the exposed substrate 100b of the opening 114c. In one embodiment, the wafer 102b is electrically connected to the conductive path 106b on the upper surface of the substrate 100b through the conductive structure 110b. Therefore, an electrical signal can be transferred between the substrate 100b and the wafer 102b. In addition, the conductive path 106b of the substrate 100b can be electrically connected to the conductive path 106a in the substrate 100a through the conductive structure 108b. Therefore, the electrical signal can also be transferred between the substrate 100b and the wafer 102b or between the wafer 102a and the wafer 102b. The conductive structure 110b and the conductive structure 108b may be solder balls, conductive bumps, or the like.

The chip package 10 further includes a wafer 102c. The wafer 102c is disposed on the substrate 100c. In one embodiment, the wafer 102c is electrically connected to the conductive path 106c on the upper surface of the substrate 100c via the conductive structure 110c. Therefore, an electrical signal can be transferred between the substrate 100c and the wafer 102c. In one embodiment, the wafer 102c can transmit and/or receive signals to and from the wafer 102b through the conductive paths 106c, the conductive structures 108c, and the conductive paths 106b in the substrate 100b. Between the wafer 102c and the wafer 102a, signals can also be transmitted and/or received through the conductive paths in the substrates 100a, 100b, and 100c. The conductive structure 110c and the conductive structure 108c may be solder balls, conductive bumps, or the like. In an embodiment, the chip package 10 further includes a conductive structure 108a disposed under the substrate 100a. Conductive structure 108a can be a solder ball, a conductive bump, or the like. The conductive structure 108a can be used to electrically connect with other electronic components (eg, a circuit board). this In addition, in one embodiment, the chip package 10 shown in FIG. 1 can be coated with an encapsulant. Alternatively, a heat dissipating member may be disposed in the chip package 10.

As shown in FIG. 1, in one embodiment, the opening 114c is larger than the opening 114b. The opening 114c and the opening 114b may be in communication with each other. In one embodiment, the width of the wafer 102c is greater than the width of the wafer 102b, and the width of the wafer 102b is greater than the width of the wafer 102a. In another embodiment, the area of the wafer 102c is greater than the area of the wafer 102b, and the area of the wafer 102b is greater than the area of the wafer 102a. Further, in an embodiment, the upper surface of the wafer 102b may be higher than the upper surface of the substrate 100c to protrude beyond the opening 114c of the substrate 100c. In this case, the spacing between the upper surface of the wafer 102b and the wafer 102c is smaller than the spacing between the upper surface of the substrate 100c and the wafer 102c. In an embodiment, the upper surface of the wafer 102a may be higher than the upper surface of the substrate 100b to protrude beyond the opening 114b of the substrate 100b. In this case, the spacing between the upper surface of the wafer 102a and the wafer 102b is smaller than the spacing between the upper surface of the substrate 100b and the wafer 102b.

In one embodiment, wafer 102a, wafer 102b, and wafer 102c may be wafers that differ in function from one another. For example, the wafer 102a may be a flash chip, the wafer 102b may be a DRAM chip, and the wafer 102c may be a CPU chip. It should be noted that embodiments of the present invention are not limited thereto. In other embodiments, some of the wafers in the chip package may have substantially the same function.

Although the chip package 10 only displays three stacked wafers, the present invention The embodiment is not limited to this. In other embodiments, the chip package can include a stack of more than four wafers. In the embodiment of the present invention, a plurality of wafers having the same or different functions may be electrically connected to each other through a substrate therebetween. In addition, since an opening is formed in the substrate, the wafer can be placed therein to reduce the overall thickness of the chip package. Moreover, signal transmission between the wafers can be faster. For example, in FIG. 1, the wafer 102c and the wafer 102b may be electrically connected to each other only through the conductive paths 106c and 106b in the substrate 100c and the substrate 100b. The signal transmission between the wafer 102c and the wafer 102b can selectively pass through the conductive path in the substrate 100a, thereby allowing signals to be transmitted faster in a shorter path.

4 is a cross-sectional view of a wafer package 40 in accordance with an embodiment of the invention, wherein the same or similar reference numerals are used to designate the same or similar elements. In this embodiment, the wafer 102c and the wafer 102b can be electrically connected to each other only through the conductive paths 106c and 106b in the substrate 100c and the substrate 100b. As shown in the left part of FIG. 4, part or all of the signal transmission between the wafer 102c and the wafer 102b can selectively pass through the conductive path in the substrate 100a, and the conductive path 106c in the substrate 100c and the substrate 100b can be directly used. And 106b, so that the signal can be transmitted faster in a shorter path.

There are many variations to the embodiments of the invention. For example, FIG. 2 shows a cross-sectional view of a chip package 20 in accordance with an embodiment of the present invention, and FIG. 3 shows a cross-sectional view of a chip package 30 in accordance with an embodiment of the present invention, wherein the same or similar reference numerals are used to indicate The same or similar components.

As shown in FIG. 2, in an embodiment, the chip package 20 can be further packaged. The wafer 102d is included. The wafer 102d can be sandwiched between the substrate 100a and the wafer 102a. A through wafer conductive structure 112 can be included in the wafer 102d. Wafer 102d may include an insulating layer 104d overlying wafer conductive structure 112 to avoid shorting. The wafer 102d can be electrically connected to the wafers 102a, 102b, and 102c stacked thereon by the through-wafer conductive structure 112, the conductive structure 108a, and the substrate 100a.

There are many variations to the embodiments of the invention. For example, in the embodiment of FIG. 3, the upper surface of the wafer 102b may not protrude beyond the opening 114c to be substantially flush with the upper surface of the substrate 100c. Alternatively, the upper surface of the wafer 102a may be lower than the upper surface of the substrate 100b. Therefore, the package of the embodiment of the present invention is suitable for packaging wafers of various thicknesses.

In summary, embodiments of the present invention can integrate multiple wafers, increase signal transmission speed, and are suitable for packaging wafers of various sizes.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

10, 20, 30, 40‧‧‧ chip package

100a, 100b, 100c‧‧‧ base

102a, 102b, 102c, 102d‧‧‧ wafer

104a, 104b, 104c, 104d‧‧‧ insulation

106a, 106b, 106c‧‧‧ conductive paths

108a, 108b, 108c, 110a, 110b, 110c, 110d‧‧‧ conductive structure

112‧‧‧Wearing wafer conductive structure

114b, 114c‧‧‧ openings

1 shows a cross-sectional view of a chip package in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention.

Figure 3 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention.

4 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention.

10‧‧‧ chip package

100a, 100b, 100c‧‧‧ base

102a, 102b, 102c‧‧‧ wafer

104a, 104b, 104c‧‧‧ insulation

106a, 106b, 106c‧‧‧ conductive paths

108a, 108b, 108c, 110a, 110b, 110c‧‧‧ conductive structure

114b, 114c‧‧‧ openings

Claims (7)

A chip package comprising: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has a first opening to expose the first substrate; a third substrate disposed on On the second substrate, the third substrate has a second opening exposing the first opening and a portion of the second substrate; a first wafer disposed on the first substrate exposed by the first opening a second wafer connected to the second substrate of the portion and disposed on the second substrate exposed by the second opening and the first wafer; and a third wafer connected to the second substrate a third substrate disposed on the second opening and the third substrate. The chip package of claim 1, further comprising: a first conductive structure disposed under the first substrate; a first conductive path in the first substrate; a second conductive structure connected to Between the first substrate and the second substrate; a second conductive path in the second substrate; a third conductive structure connected between the second substrate and the third substrate; and a third conductive path Inside the third substrate. The chip package of claim 2, wherein the third wafer transmits and/or receives signals to the second wafer through the third conductive path, the third conductive structure, and the second conductive path. . The chip package of claim 1, wherein the first substrate, the second substrate, and the third substrate are not in direct contact with each other. The chip package of claim 1, wherein a distance between an upper surface of the second wafer and the third wafer is smaller than a distance between an upper surface of the third substrate and the third wafer . The chip package of claim 1, wherein a distance between an upper surface of the first wafer and the second wafer is smaller than a distance between an upper surface of the second substrate and the second wafer . The chip package of claim 1, further comprising a fourth wafer, wherein the first substrate is disposed between the fourth wafer and the first wafer.