TW201426946A - Semiconductor device fabrication method - Google Patents

Abstract

An embodiment of the invention relates to a method of producing a semiconductor die comprising a desired plurality of interconnected components, the method comprising: producing on a wafer a number of the components greater than the desired plurality of components; testing the produced components for acceptable functioning; and interconnecting a number of acceptably functioning components equal to the desired plurality.

Description

Semiconductor device manufacturing method Related application

This application is based on the benefit of U.S. Provisional Application No. 61/715,330, the entire disclosure of which is incorporated herein by reference.

Embodiments of the invention relate to a method of fabricating a semiconductor device.

A semiconductor device ("SD") is typically fabricated by an optical photolithography process to include an array of such devices on a semiconductor wafer, such as a Si, SiC, GaAs or GaN wafer. In a photolithography process, a photoresist layer is applied to one of the photoresist layers by exposure using a stepper. The stepper exposes selected portions of the wafer to light formed by projecting light through a reticle (typically a transparent material having an opaque pattern (for example, a chrome pattern on a quartz plate)) Pattern (a "mask photo pattern"). The reticle light pattern is miniaturized and projected onto the photoresist layer by using appropriate optics at a plurality of locations on the surface of the wafer. Next, the exposed photoresist layer is developed to form an opening pattern defined by the reticle light patterns. The photoresist opening pattern defines where a fabrication step, such as deposition or etching, occurs on the surface of the wafer.

After the SD fabrication is completed, the wafer is separated and "cut" into small pieces called "die", each of which includes a single copy of the device.

SD is prone to become defective due to accumulation of one of manufacturing defects, which can be reduced from one The number of functions SD for wafer fabrication ("grain yield"). After the SD fabrication on the wafer is completed but before the wafer is diced, the finished SD is subjected to wafer screening to evaluate the grain yield, where each SD is tested for functional defects. Typically, screening tests are performed by means of an electronic tester, commonly referred to as a wafer prober, which includes a probe card comprising a set of microscope probes. The probes are placed on a set of conductive pads disposed on the surface of each completed SD, the conductive pads being connected to the internal circuitry of the SD. The probe applies a test pattern to the SD and records the readout from SD through the conductive pads. Through the screening process, SD is classified into "Good SD" that meets the predetermined test criteria and "Poor SD" that does not meet the criteria. In addition, wafer testing can include optical testing of SD. The classification data (including the state of each SD and its position on the wafer) can be recorded on an electronic "substrate map" (if the substrate map covers the entire wafer, it is a "wafer map"), An electronic "substrate map" can be used to guide subsequent assembly and packaging.

Especially in the immature process of SD manufacturing on GaN or SiC wafers or in the fabrication of large SD covering a wide wafer surface area, the wafer yield can be extremely low. Wafer yield improvement is one of the goals in SD manufacturing because it directly affects the number of functional dies that can be fabricated relative to materials and manufacturing costs.

One aspect of an embodiment of the present invention relates to providing an SD manufacturing method, also referred to as a "redundancy-based manufacturing method" in which SD is tested during a manufacturing process prior to completion of SD. SD (also known as "Redundant Cluster SD" or "RCSD") includes a plurality of active component cell clusters ("cluster"). To make the RCSD good, in the plurality of clusters, only one of the total number of clusters is required to be scheduled. The number (a "target count") is functional. The RCSD is tested in a partially fabricated state after the fabrication of the clusters but prior to interconnecting the clusters within the RCSD to identify functional clusters and defect clusters. In each good RCSD having at least a target count of functional clusters, the target counted functional clusters are selected as "active clusters" and the remaining clusters (functions or defects) are selected as "single clusters". in In subsequent fabrication of RCSD, the active clusters are interconnected within the RCSD and the individual clusters remain unconnected.

According to an embodiment of the present invention, the redundancy-based manufacturing method may include: fabricating at least one RCSD having a number of clusters greater than a desired plurality of clusters on a wafer; testing the fabricated clusters for acceptable functions; And interconnecting a number of acceptable functional clusters equal to the desired number of complexes.

For ease of presentation, the procedure for performing the screening test and selecting the active cluster and the lone cluster based on the screening test result may be referred to herein as an "intermediate testing phase", and the procedure for interconnecting the active clusters within the RCSD may be referred to herein. It is called a "cluster interconnection phase."

For ease of presentation, an RCSD having a portion configured to participate in a screening test may be referred to as a "test phase RCSD", and a wafer having a test phase RCSD may be referred to as a "test phase wafer". .

As used herein, with respect to a wafer and its constituent SD and cluster, "horizontal" refers to an orientation that is substantially parallel to the surface of the wafer and "vertical" refers to an orientation that is substantially perpendicular to the surface of the wafer. As used herein, with respect to a wafer and components thereof, "lateral", "next", "adjacent", and the like refer to a spatial relationship in a horizontal orientation. As used herein, with respect to a wafer and components thereof, "top", "on top of", "above", and the like are referred to at the side of the wafer where the SD fabrication occurs or The spatial relationship in the vertical orientation towards the side, and "bottom", "below", "below" and the like refers to the vertical setting at or towards the opposite side of the wafer. Upward spatial relationship.

According to an embodiment of the present invention, each cluster may include one of the "active areas" in which the active component unit is disposed, and optionally includes one of the active component units without laterally surrounding (completely or partially) the active area. "world". The active component unit can be, for example, a diode and a field effect transistor (FET). The cluster can include an array of substantially identical active component units. Another option is that each cluster can have a group of different active component units. A modular circuit. According to an embodiment of the invention, the RCSD may comprise a plurality of types of clusters interconnected to each other. Alternatively, each cluster in the RCSD can be substantially identical.

According to an embodiment of the present invention, each cluster of the test phase RCSD may have a plurality of "probe pads" connected to the conductive pads of the internal circuits of the cluster, and the electrical properties of the clusters may be measured through the conductive pads. For performance function screening tests. In accordance with an embodiment of the invention, the probe pad is configured to contact or align with a probe attached to a probe card of one of the wafer probe meters.

In accordance with an embodiment of the present invention, each cluster of test phases RCSD includes a plurality of conductive pads ("interconnect pads") on its top surface that act as contacts through which active clusters are interconnected within the RCSD. Like the probe pads, the interconnect pads are connected to the internal circuitry of the cluster. In a particular embodiment of the invention, the interconnect pads can be a set of separate contact pads in addition to the probe pads. Alternatively, the interconnect pads and probe pads on each cluster can serve as probe pads during the intermediate test phase and serve as the same set of conductive pads for the interconnect pads during the cluster interconnect phase.

In accordance with an embodiment of the present invention, the active cluster of interconnects can include electrically connecting adjacent active cluster pairs. The "adjacent cluster interconnect scheme" can include interconnecting active clusters within the RCSD through a photolithography program that forms a conductive patch that electrically connects the interconnect pads between adjacent active clusters One of the interconnect layers.

In accordance with an embodiment of the invention, the photolithography program reproduces a set of conductive patches on each active cluster in a predetermined pattern. After the intermediate test phase, a photoresist layer is applied to the test stage wafer. A photoresist layer is exposed to a reticle light pattern at each active cluster location using a stepper. The reticle light pattern includes a set of defined regions (also referred to as a set of "patch templates") in which light is directed by a stepper onto the photoresist layer. The patch template exposed on the photoresist layer at the active cluster position is converted into a conductive patch pattern by a photolithography program.

According to an embodiment of the invention, it may be based on the position of each interconnect pad on the cluster surface The placement of the patch template set relative to the cluster is predetermined to interconnect pairs of interconnects on adjacent clusters connected by a conductive patch (assuming that the adjacent clusters are active).

For convenience of presentation, the predetermined pair of interconnect pads may be referred to herein as "matching pads."

In accordance with an embodiment of the present invention, a patch template includes at least a portion of an interconnect pad and a portion adjacent to the cluster without including a mating pad on an adjacent cluster. Therefore, when two adjacent clusters are active clusters, the two patch templates including each of the pair of mating mats overlap, so that a continuous conductive conduction of the pair of mats is electrically connected through the photolithography process. Patch.

In the discussion, unless stated otherwise, an adjective such as "substantially", "relative" and "about", which is one of the features of one of the embodiments of the invention, or a feature of the relationship, is to be understood as meaning The conditions or characteristics are defined as being within tolerances for the operation of the embodiments of the invention for which one of the applications is intended. The word "or" in the specification and claims should be construed as an inclusive or non-exclusive or singular combination of any of the items.

This Summary is provided to introduce a selection of concepts in a The summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

10‧‧‧ wafer

20‧‧‧Rectangular redundant cluster semiconductor device/redundant cluster semiconductor device/semiconductor device

20A to 20D‧‧‧Redundant Cluster Semiconductor Devices

30‧‧ ‧ cluster

130‧‧ ‧ cluster

130A to 130B‧‧‧Cluster/Active Cluster

130C‧‧‧Cluster/Lonely Cluster

132‧‧‧First probe pad

134‧‧‧Second probe pad

138‧‧‧Action area

139‧‧‧ perimeter

142‧‧‧First interconnect pad/anode interconnect pad

142A to 142D‧‧‧First interconnect pads

144‧‧‧Second interconnect mat

144A to 144D‧‧‧Second interconnect pads

152‧‧‧dotted rectangle/patch template

162‧‧‧Electrical patch

172‧‧‧First lead/anode lead/lead

174‧‧‧Second lead/cathode lead/lead

181‧‧‧First probe pad

182‧‧‧Second probe pad

183‧‧‧ third probe pad

184‧‧‧ Third interconnect pad/gate interconnect pad

186‧‧‧dotted rectangle/patch template

230‧‧‧Lone Cluster/Cluster/Dipole Cluster/Active Cluster

230A and 230C to 230F‧‧‧ cluster/active cluster

230B‧‧‧Cluster/Lonely Cluster

242‧‧‧First conductive pad/conductive pad/anode conductive pad

244‧‧‧Second conductive pad/conductive pad/second probe pad/cathode conductive pad

252‧‧‧Dashed rectangle/patch template

262‧‧‧Electrical patch/continuous strip

263‧‧‧Electrical patch

272‧‧‧Anode lead

274‧‧‧Cathode lead

330‧‧‧ Cluster/Active Cluster

342‧‧‧First conductive pad/conductive pad/first probe pad

344‧‧‧Second conductive pad/conductive pad/second probe pad

346‧‧‧ Third conductive pad/conductive pad

352A to 352F‧‧‧Area/Patch Template

Non-limiting examples of embodiments of the invention are set forth below with reference to the accompanying drawings of the invention, which are set forth after this paragraph. The same structures, elements or components that appear in one or more of the figures are generally indicated by the same reference numerals in the figures in which they appear. The sizes of the components and features shown in the figures are chosen for convenience and clarity and are not necessarily to scale.

1 schematically illustrates, in perspective view, a wafer having a plurality of test stages RCSDs in accordance with an embodiment of the present invention, wherein an illustration shows a single RCSD die having a plurality of clusters in a top view; 2 shows a flow chart of a manufacturing method based on redundancy; FIG. 3A schematically illustrates a group of four adjacent RCSD dies in a top view, each RCSD die having a function determined by a screening test Cluster (no format) and defect cluster (marked with X); Figure 3B schematically illustrates the RCSD die group shown in Figure 2A in a top view, where the target count functional clusters (dark colors) are selected as active clusters , wherein the remaining clusters (good or bad) are selected as a lone cluster (white); FIG. 4A is schematically illustrated in a perspective view with a set of first probe pads, a set of second probe pads, a set of An exemplary cluster of an interconnect pad and a set of second interconnect pads; FIG. 4B schematically illustrates, in a top view, an exemplary photomask light pattern illuminating one of the active clusters of FIG. 4A; FIG. 4C is a top view The sexual map illustrates one of the clusters of FIG. 4A in a 1×3 array in which two clusters of three clusters are schematically indicated as being exposed to the reticle light pattern of FIG. 4B; FIG. 4D is schematically illustrated in a perspective view. The map illustration shows that after applying the conductive patch, there is Figure 4A. One of the clusters of one of the 4x4 arrays is an exemplary RCSD; FIG. 5 schematically illustrates having a set of third probe pads (along with several sets of first and second probe pads) and a set of third interconnect pads ( And a plurality of sets of first and second interconnect pads) and an alternative photomask light pattern instead of a cluster; FIG. 6A schematically illustrates a first conductive pad and a second conductive pad and an exemplary view in a top view One of the reticle light patterns replaces the cluster; FIG. 6B schematically illustrates a 2×3 array of the cluster of FIG. 6A in a top view, wherein the five clusters of the six clusters are schematically indicated as having been exposed to FIG. 6A Shield light pattern; FIG. 6C schematically illustrates, in perspective view, the 2×3 cluster of FIG. 6C after forming a conductive patch based on the reticle light pattern illuminated on the active cluster as shown in FIG. 6B. FIG. 6D schematically illustrates, in perspective view, an exemplary RCSD having one of the 4×6 arrays of the cluster of FIG. 6A after application of the conductive patch; FIG. 7A schematically illustrates a set of alternatives in a top view Figure 6A is a cluster of patch templates; Figure 7B schematically illustrates, in a perspective view, one of the clusters of 7A after forming a conductive patch based on a reticle light pattern exposed to five active clusters in six general clusters An exemplary 2×3 array; and FIG. 8 schematically illustrates, in a top view, an alternative cluster having a first conductive pad, a second conductive pad, and a third conductive pad and for the alternate cluster A set of patch dies that act as probe pads in the intermediate test phase and act as interconnect pads in the cluster interconnect phase.

In the following detailed description, one of the exemplary RCSD wafers in accordance with an embodiment of the present invention is schematically illustrated in FIG. 1 and discussed with reference to FIG. A manufacturing method based on redundancy according to one embodiment of the present invention is shown in FIG. 2 as a flow chart and schematically illustrates the manufacturing method in FIGS. 3A-3B, and the manufacturing is discussed with reference to the figures. method. Exemplary clusters, cluster interconnects in accordance with an embodiment of the present invention are schematically illustrated in Figures 4A-4D, 5, 6A-6D, 7A-7B, and 8 and with reference to the figures. Phase steps and interconnected RCSD.

Referring now to Figure 1, there is shown a schematic diagram of a wafer 10 having a plurality of rectangular RCSDs 20 in an array in accordance with an embodiment of the present invention.

According to an embodiment of the invention, the wafer 10 may be a Si wafer, a SiC wafer, a GaAs wafer, a GaN wafer, a Si GaN wafer or a SiC on GaN wafer.

In accordance with an embodiment of the present invention, RCSD 20 can be a power SD, as appropriate, a power diode or a power FET. In a particular embodiment of the invention, the power SD can be A lateral power SD, as appropriate, a lateral power diode or a lateral power FET. In a particular embodiment of the invention, RCSD 20 may be one of the other SD known in the art, for example, a RAM chip, a flash memory chip, a field emitter array, or a system single chip. (SOC).

As shown in the inset of Figure 1, each RCSD 20 includes a plurality of clusters 30, and each cluster 30 includes a plurality of active component units (not shown). In a particular embodiment of the invention, each cluster may comprise a plurality of substantially identical active components. Alternatively, each cluster may be a modular circuit having one of a combination of different types of active component units. In a particular embodiment of the invention, at least a portion of a current is carried within the active component unit by a two-dimensional electron gas ("2DEG").

In accordance with an embodiment of the present invention, the number of clusters 30 in each SD 20 exceeds the target count of one of the clusters 30 required for the operation of SD 20 (i.e., making SD 20 good). As such, each RCSD is characterized by one of the clusters 30 redundancy. In accordance with an embodiment of the present invention, the plurality of clusters 30 in the RCSD 20 may include a plurality of cluster types interconnected to each other. The RCSD 20 can have one of each cluster type redundancy. Alternatively, each of the clusters 30 in the RCSD 20 can be substantially identical.

In a particular embodiment of the invention, each RCSD 20 may optionally cover about 15 square millimeters (mm ² ), about 20 mm ² , about 25 mm ² , about 30 mm ² , about 50 mm ² , about 75 mm ² , about 100 mm ² or about 150mm ² one wafer surface area. Optionally, the number of RCSDs on a wafer can be up to 50, up to 75, up to 100, up to 150, up to 200, up to 250, up to 300, up to 350, up to 400, up to 450 or up to 500. Optionally, the number of clusters 30 in each RCSD may be at least 10, at least 25, at least 50, at least 75, at least 100, at least 150, at least 200, between 10 and 200. Between 50 and 100 or between 75 and 150. Optionally, the number of active component units (not shown in FIG. 1) in each cluster can be about 20, about 30, about 40, about 50, about 75, or about 100. It should be understood that the number of active component units in each cluster, the surface area of each cluster, the number of clusters in each RCSD, and the surface area of each RCSD are related.

As explained above, the RCSD 20 can be a lateral power diode or a lateral power FET. The power SD comprising the lateral power SD is advantageously characterized by the ability to safely pass a relatively high "on current" when it is turned on and a relatively high breakdown voltage when it is turned off.

The on state and the off state of a power FET are controlled by changing the gate source voltage. In the on state, the power FET is capable of transferring an on current between the source and the drain, which may be, for example, by source drain voltage and R _DS(on) (on state) Characterization of the 汲 源 source resistance. In the off state, the power FET only allows leakage current that is less than one of the on current between the source and the drain. The breakdown voltage in a power FET is below which allows the power FET to deliver a source drain voltage that is greater than the leakage current in the off state. Applying a source-drain voltage at or above the breakdown voltage when the power FET is turned off can cause damage to the power FET.

The power diode turns "on" when it is applied with a forward bias and turns off when it is applied with a reverse bias (or is not fully forward biased). In the on state, the power diode is capable of transmitting an on current between the anode and the cathode. In the off state, the power diode only allows leakage current that is less than one of the on current between the anode and the cathode. The breakdown voltage in a power diode is a reverse bias voltage under which the power diode can deliver more current than the leakage current. Applying a reverse bias voltage at or above one of the breakdown voltages can cause damage to the power diode.

In accordance with an embodiment of the present invention, RCSD 20 can be a lateral power diode or a lateral power FET capable of delivering a relatively high turn-on current and having a relatively high breakdown voltage. In a particular embodiment of the invention, the relatively high turn-on current can be at least 20A, at least 25A, at least 30A, at least 35A, at least 40A, or at least 50A continuous current. In a particular embodiment of the invention, the relatively high breakdown voltage can be at least 300 Volts (V), at least 400V, at least 500V, at least 600V, or at least 700V.

Referring to FIG. 2, there is provided a redundancy-based manufacturing method 200 for fabricating an RCSD (for example, RCSD 20 of FIG. 1) in accordance with an embodiment of the present invention, the method comprising: pairing a plurality of test phases RCSD A test phase wafer performs a screening test to identify functional clusters and defect clusters within each RCSD (210); a functional cluster selection equal to the target count in each good test phase RCSD having at least a target count of functional clusters Active clustering (220); selecting the remaining clusters in a good RCSD as a lone cluster (230); and interconnecting active clusters within a good RCSD (240).

According to an embodiment of the invention, the screening test may comprise a functional test or comprise a functional test and an optical test. The screening test can include a plurality of individual tests, wherein each cluster that is tested by all (or a predetermined portion) of the individual tests is identified as a functional cluster and the remaining clusters that have not passed one or more individual tests are identified as Defect clusters.

Functional testing of the cluster can be performed by means of a probe card connected to one of the wafer probes. The wafer prober used in the screening test for performing the cluster of embodiments of the present invention may be one of the standard wafer probers used in the fully fabricated SD wafer screening. It is known in the art to design and fabricate a probe card having an appropriate number of probes in a suitable spatial configuration as desired.

According to an embodiment of the invention, each cluster of test phase RCSDs comprises a plurality of probe pads. The probe pads and probe cards are configured to be compatible such that when the probe cards are placed on the cluster surface, each probe is contacted or aligned with an appropriate probe pad. In a particular embodiment of the invention, the wafer prober can be a contact based system in which the probes of the probe card are in physical contact with the probe pads on the cluster to form a conductive connection. Alternatively, the wafer prober can be a wireless non-contact wafer test system in which the probe and probe pads are used as radio frequency (RF) antennas such that functional testing requires close proximity rather than physical contact. The screening tests performed by the wafer prober on the cluster may depend on the circuitry of the cluster. By way of example, an RCSD can be a power FET in which each cluster has a plurality of FET cells connected in parallel. Functional tests of these clusters may include R _DS(on) (drain source resistance in the on state), gate leakage current, drain source leakage current, breakdown voltage, and the like.

According to an embodiment of the invention, the probe pad may optionally be placed on top of the active area and/or on top of the perimeter. The number of probe pads on each cluster may depend on the circuitry of the cluster. By way of example, each of the clusters in a power diode RCSD can have at least one "anode probe pad" from the anode of the diode unit in the cluster and two poles from the cluster. The cathode of the body unit is connected to at least one of the "cathode probe pads". In the case of an RCSD-based power FET, the cluster may have at least one "source probe pad" from which the source of the FET cell in the cluster is connected, and a drain from the FET unit of the cluster connected to at least A "dip probe pad" and a gate from the FET unit of the cluster are connected to at least one "gate probe pad". The various configurations of the probe pads are discussed in further detail below.

Figure 3A schematically illustrates four adjacent RCSDs on a wafer to show the results of a screening test for one of the RCSDs 20A through 20D. Each RCSD 20 has an eight 8x8 array of sixty-four (64) clusters 30 in which the functional clusters are unlabeled and the defect clusters are schematically labeled with an X-shaped marker. The RCSD 20A has 7 defect clusters and 57 functional clusters. The RCSD 20B has 10 defect clusters and 54 functional clusters. The RCSD 20C has 4 defect clusters and 60 functional clusters. The RCSD 20D has 12 defect clusters and 52 functional clusters.

Figure 3B schematically illustrates the same RCSD of Figure 3A following the selection of active clusters (shadows) and orphan clusters (white). Each of the RCSDs 20A through 20D has a target count of 54 functional clusters in a total of 64 clusters. In accordance with an embodiment of the present invention, an RCSD having a functional cluster smaller than a target count is classified as a bad RCSD and an RCSD having at least a target count is classified as a good RCSD. As such, the RCSD 20D with 52 functional clusters is classified as a bad RCSD (and thus is schematically indicated with a large X-shaped mark) and RCSDs 20A through 20C with 54 or more functional clusters are classified as good RCSD.

In accordance with an embodiment of the present invention, in a good RCSD, a functional cluster equal in number to the target count is selected as the active cluster, the remaining functional clusters (if present) are selected as the lone cluster, and all the defect clusters are selected as the lone cluster . As shown in FIG. 3B, each of the RCSDs 20A through 20C has fifty-four active clusters (shadows), but each of the RCSDs 20A through 20C has a different number of defect clusters. In RCSD 20A with 10 defect clusters and 54 functional clusters, all defect clusters were selected as a lone cluster and all functional clusters were selected as active clusters. In RCSD 20B, 54 functional clusters in 57 functional clusters are selected as active clusters, and the remaining 3 functional clusters are selected as a single cluster together with 7 defect clusters. In the RCSD 20C, 54 functional RCSDs of the 60 functional RCSDs are selected as active clusters, and the remaining 6 functional clusters are selected as a lone cluster together with 4 defect clusters.

As illustrated with reference to FIG. 3B, according to an embodiment of the present invention, a functional cluster may be selected as an active cluster or a single cluster according to the following scheme: if the number of functional clusters is equal to the target count, all functional clusters are selected as active clusters and Select all defect clusters as a lone cluster; and if there are more functional clusters than the target count, then one of the subgroup functional clusters equal in number to the target count is selected as the active cluster and the remaining functional clusters and defect clusters are selected as the lone cluster .

Although having RCSD with redundant clusters increases the proportion of good grains produced from the total grains on the wafer, it also increases the size of each die, thus reducing the number of grains produced on each wafer ( The total number of good or bad). Therefore, for a redundancy-based fabrication method to increase the grain yield (ie, the number of good dies per wafer), the ratio of good grains from the total grains on the wafer The increase must be sufficiently high to offset the reduction in the total number of grains per wafer.

By numerical example, two methods are used to manufacture (or attempt to manufacture) to be able to pass One of about 30 amps (A) turns on the current and has a power FET of one of the collapse voltages of about 600V. The first method is one in which the power FET does not have a standard manufacturing method of redundant clustering. The second method is a redundancy-based manufacturing method as provided in one embodiment of the present invention, wherein the power FET is RCSD with redundant clusters, and the test phase RCSD is functionally tested to identify functional clusters and defect clusters.

In a standard method, 314 power FET dies are fabricated on a GaN wafer having a 4 inch diameter. Each die is 6 mm x 3 mm in size and has 64 clusters. In order for the power FET to have a predetermined desired functional criterion, such as being capable of delivering one of about 30 A of on-current, having a breakdown voltage of about 600 V and having a predefined R _DS(on) . All 64 cluster functions are required to make the power FETs good (in other words, the power FETs do not have redundant clusters). The power FETs are fabricated without an intermediate test step and all 64 clusters are interconnected within the power FET regardless of whether the clusters are functional. Of the 314 resulting power FET dies, only a few grains (for example, less than 10 dies) are good dies that meet the desired functional criteria.

In a redundancy-based fabrication method, the power FET is configured to have one of RCSDs having 81 clusters containing 64 functional clusters of target counts (the clusters are substantially identical to the clusters produced in the first method). That is, the RCSD die requires 64 functional clusters (from a total of 81 functional clusters) to meet a schedule capable of delivering one of about 30A of on-current, having a breakdown voltage of about 600V, and having a predefined R _DS(on) The required functional guidelines. Each RCSD die was 6 mm x 4 mm and 248 dies were fabricated on a 4 inch diameter GaN wafer that was substantially identical to the wafer used in the first method. As part of a redundancy-based production approach, clusters in each RCSD are subjected to a screening test during an intermediate test phase to identify functional clusters and defect clusters. An RCSD with less than 64 functional clusters is classified as a bad RCSD. In a good RCSD with at least 64 functional clusters, 64 functional clusters are selected as active clusters and interconnected within the power FET. The remaining 17 clusters are selected as a lone cluster and left unconnected. Of the 248 power FET dies fabricated on wafers by means of a redundancy-based fabrication method, 200 dies satisfy good crystal grains of the desired functional criteria and 48 die are poor dies.

In accordance with an embodiment of the present invention, and as illustrated with reference to the flow chart of FIG. 2, the active clusters are interconnected within the RCSD in the cluster interconnect phase once selected. According to an embodiment of the present invention, the state of each cluster in the test phase wafer as determined in the intermediate test phase (for example, as a function, a defect, an active, and/or a lone cluster) may be recorded on a substrate. On the map, and the substrate map can be used to guide the cluster interconnect phase.

In a particular embodiment of the invention, the active clusters may be interconnected by an adjacent cluster interconnect scheme that forms a pattern comprising one of the conductive patches that electrically connect the mating pads through a lithography process. A single interconnect layer. The conductive patches may include one or more of elemental metals such as aluminum, gold copper, nickel or titanium or a metal alloy.

4A schematically illustrates, in a perspective view, a single cluster 130 having one of the active regions 138 laterally surrounded by a perimeter 139. Typically, a plurality of clusters 130 are arranged in an array in an RCSD (not shown in Figure 4A). Each cluster 130 includes two first probe pads 132 (white) and two second probe pads 134 (shadow) disposed on top of an active region 138. Each of the two first probe pads 132 is substantially identical and is electrically connected to each other through the internal circuitry of the cluster 130. Similarly, each of the two second probe pads 134 are substantially identical and are electrically connected to each other through the internal circuitry of the cluster 130.

The cluster 130 further includes four first interconnect pads 142 (white) and four second interconnect pads 144 (shaded), wherein a first interconnect pad and a second interconnect pad are disposed on the perimeter 139 On each of the four sides of 130. Each of the four first interconnect pads 142 are substantially identical and are electrically connected to each other through the internal circuitry of the cluster 130. Similarly, each of the four second interconnect pads 144 are substantially identical and are electrically connected to each other through the internal circuitry of the cluster 130.

For ease of presentation, the internal circuits through the cluster can be electrically connected to each other. A set of substantially identical probe pads on a cluster is collectively referred to as a "probe channel." Similarly, a set of substantially identical interconnect pads on a cluster that is electrically connected to each other through the internal circuitry of the cluster can be collectively referred to as an "interconnect channel." As such, the cluster 130 includes one of the first probe pads 132, a first probe channel, one of the two second probe pads 134, a second probe channel, and four first interconnects. The "first interconnect channel" of the pad 142 and one of the four second interconnect pads 144 "second interconnect channel".

By way of example, cluster 130 can include a diode cluster of a plurality of diode units connected in parallel. As such, the first probe pad 132 can be an anode probe pad and the second probe pad 134 can be a cathode probe pad. Similarly, the first interconnect pad 142 can be an anode interconnect pad and the second interconnect pad 144 can be a cathode interconnect pad.

4B schematically illustrates an exemplary reticle light pattern including one of a set of patch templates on each of the clusters 130 selected to be selected as an active cluster. Each patch template is schematically indicated as an area enclosed by a set of dashed rectangles 152.

For ease of presentation, a cluster to which a plurality of patch templates are applied may be referred to as a "target cluster."

In accordance with an embodiment of the present invention, one set of patch lithography programs known in the art can be used to convert the set of patch templates into a corresponding metallization pattern comprising one of the conductive patches. Optionally, the photoresist used in the photolithography process may be selected as a positive photoresist or a negative photoresist as appropriate. In the case of a positive photoresist, portions of the photoresist exposed to light become soluble in the photoresist developer, and portions of the unexposed photoresist remain on the wafer. In the case of a negative photoresist, the portion of the photoresist exposed to light becomes insoluble.

In a particular embodiment of the invention, the photolithography program is a mosaic method as the case may be. Alternatively, the photolithography process can be formed by a stripping process as appropriate. Alternatively, the photolithography procedure may be based on metal etch back.

By way of example, the optical lithography process in the cluster interconnection phase illustrated in FIGS. 4A-4D (and in the figures subsequent to FIGS. 4A-4D) may be a stripping procedure, a damascene procedure Or a metal etchback procedure.

In an exemplary damascene procedure, after selecting active clusters and a lone cluster, a dielectric layer is deposited on the wafer followed by a positive photoresist layer. The patch stencil is reproduced as a negative photoresist opening pattern at each active cluster by stepper processing and photoresist development, wherein the photoresist openings define regions to which the conductive patches are applied. A dielectric layer that is not covered at the openings of the photoresist is etched to form a trench in the dielectric layer. Next, the metal is applied (for example, by electroplating, deposition, or sputtering) onto the surface of the wafer to fill the trenches and the excess metal is removed by chemical mechanical planarization ("CMP"). The metal filled trench acts as a conductive patch.

In an exemplary stripping procedure, a positive photoresist is deposited on a wafer after active clustering and lone clustering are selected. The patch stencil is reproduced as a negative photoresist opening pattern at each active cluster by stepper processing and photoresist development, wherein the photoresist openings define regions to which the conductive patches are applied. A thin metal layer is applied to the surface of the wafer (for example, by electroplating, deposition, or sputtering) that covers portions of the RCSD that are not covered by the photoresist openings and the remaining photoresist. The remaining photoresist is removed along with the metal deposited thereon such that only the metal layer formed at the photoresist opening remains on the RCSD surface. This remaining metal layer acts as a conductive patch.

In an exemplary metal etchback procedure, after selecting active clusters and orphan clusters, a thin metal layer is applied to the wafer (for example, by electroplating, deposition, or sputtering) followed by a negative photoresist. Floor. Through the stepper processing and photoresist development, the patch template is reproduced as a positive photoresist opening pattern at each active cluster, wherein the desired locations of the conductive patches remain covered by the photoresist. The uncovered metal layers at the openings of the photoresist are etched away and the remaining metal layers act as conductive patches.

For clarity of presentation, the photoresist layer (and the additional dielectric layer in the case of the damascene procedure) is not shown in Figures 4A-4D (and in the figures following Figures 4A-4D).

Figure 4C schematically illustrates an array of 1 x 3 of clusters 130A through 130C. Cluster 130A and 130B are active clusters and are schematically indicated as having been exposed to the reticle light pattern defined by the set of patch templates 152. Cluster 130C is a solitary cluster and is schematically indicated as having an X-shaped indicia. The lone cluster 130C is not exposed to the reticle light pattern.

In accordance with an embodiment of the invention, the interconnect pads are configured such that at each junction between adjacent clusters, each interconnect pad is relatively close to its mating pad on an adjacent cluster. The interconnect pads are configured such that the mating pads do not make physical (and therefore conductive) contacts and a conductive patch needs to be applied to electrically connect each other. In the cluster 130 configured as in FIG. 4C, the second interconnect pads 144B and 144D adjacent to the cluster are designated as mating pads and the first interconnect pads 142B and 142D are designated as mating pads. In addition, the second interconnect pads 144A and 144C adjacent to the cluster are mating pads and adjacent to the first interconnect pads 142A and 144C mating pads on the cluster. By way of example, the first interconnect pads 142D of the cluster 130C are mated to the first interconnect pads 142B of the cluster 130B. Similarly, the second interconnect pad 144D of the cluster 130C and the second interconnect pad 144B of the cluster 130B are mated to the pad.

In a particular embodiment of the invention, the mating pads belong to the same interconnecting channel, as shown by way of example in Figure 4C. In a particular embodiment of the invention, the mating pads may belong to different interconnecting channels. In a particular embodiment of the invention, each cluster 130 in an RCSD can have a substantially identical internal circuit. Alternatively, an RCSD can include different types of clusters 130 having interconnect pads and probe pads of the same physical configuration, but with different internal circuitry, depending on the interconnect pads in one of the clusters 130 as appropriate. The function of the interconnect pads of another cluster 130 within the same RCSD.

In accordance with an embodiment of the present invention, the physical configuration of the mating pads on the respective clusters and the shape and placement of the patch templates 152 on the target cluster are configured such that one patch template 152 includes an interconnect pad on the target cluster At least a portion of it and a portion of the adjacent cluster. However, patch template 152 does not include mating pads on adjacent clusters. Meanwhile, when two adjacent clusters are actively clustered, two patch templates including each of the pair of mating mats overlap, thereby creating a continuous photoresist opening and electrically connecting the pair of mats Subsequent formation of a continuous conductive patch. By way of example, the first interconnect pad 142B of the active cluster 130B is included in the patch template 152 and its mating pads (the first interconnect pads 142D of the lone cluster 130C) are not included in the patch template 152. The resulting conductive patches (not shown) formed on the first interconnect pads 142B of the active cluster 130B are not electrically conductively connected to their mating pads on the lone cluster 130C. In contrast, the first interconnect pad 142D of the active cluster 130B and its mating pad (the first interconnect pad 142B of the active cluster 130A) are included in the two patch templates 152 that are overlapped, and the resulting continuous conductive patch ( Not shown) electrically connecting the two mats.

FIG. 4D schematically illustrates an exemplary RCSD 120 having a 4×4 array of clusters 130 after forming conductive patches 162. The position of the conductive patch 162 is based on an active cluster exposed to the light pattern defined by the set of patch templates 152 (shown in Figures 4B and 4C). The RCSD contains a single cluster that is schematically indicated by an X-shaped marker. Each cluster 130 is configured in the same orientation. The RCSD 120 further includes a first lead 172 and a second lead 174.

By way of example, the RCSD can be a power diode, wherein the first interconnect pad 142 is an anode interconnect pad, the second interconnect pad 144 is a cathode interconnect pad, and the first lead 172 is an anode lead and a second Lead 174 is a cathode lead. Active clusters located at the periphery of the cluster array and laterally facing the anode leads 172 can be connected to the anode leads through the formation of conductive patches 162 on the anode interconnect pads 142 facing the anode leads 172. Similarly, active clusters located at the periphery of the cluster array and laterally facing the cathode leads 174 can be connected to the cathode leads 174 through the formation of conductive patches 162 on the anode interconnect pads 142 facing the anode leads 172. The leads 172, 174 are sufficiently close to the mating pads on the peripheral cluster such that the patch template comprising each mat (or a portion thereof) also includes a portion of the anode lead without the need for another overlapping patch template, thereby producing The mating pads are still electrically connected to the relatively small conductive patches of the anode lead 172 and/or the cathode lead 174.

As explained above, each interconnect pad belonging to the same channel within a cluster passes through The internal circuits of the cluster are electrically connected to each other. As such, although only some of the clusters in the peripheral cluster are adjacently connected to the anode lead 172, the remaining active clusters that are not adjacent to the anode lead 172 are also connected to the anode lead 172 through the internal circuitry of the intervening cluster. Similarly, all active clusters including clusters that are not adjacent to cathode lead 174 are connected to cathode lead 174.

A single lone cluster is not electrically connected to any of the active cluster, anode lead 172, or cathode lead 174. The conductive patches formed on the mating pads on the active cluster surrounding the lone cluster are based on a single non-overlapping patch template 152 (not shown). Thus, the conductive patch surrounding the solitary cluster is smaller than the conductive patch formed between the active cluster pairs. Smaller conductive patches cannot touch the interconnect pads on the lone cluster.

Figure 5 schematically illustrates, in a top view, a single cluster 180 substantially similar to cluster 130 on its outer structure, having a first probe pad 181, a second probe pad 182, including two third A third probe channel of one of the probe pads 183 and a third interconnect channel including a third interconnect pad 184 disposed on the perimeter. The clusters 180 can be configured and interconnected in an RCSD in substantially the same manner as described with respect to the cluster 130, with reference to Figures 4C-4D.

By way of example, cluster 180 can be incorporated into one of a plurality of FET clusters in a power FET (not shown in FIG. 5A). Thus, the first probe pad 181 can be a source probe pad, the second probe pad 182 can be a trip probe pad and the third probe pad 183 can be a gate probe pad. The first interconnect pad 142 can be a source interconnect pad, the second interconnect pad 144 can be a drain interconnect pad and the third interconnect pad 184 can be a gate interconnect pad.

Figure 5 further schematically illustrates a reticle light pattern comprising a set of patch templates. The set of patch templates is schematically indicated as an area enclosed by a set of dashed rectangles 186. The set of patch templates 186 is substantially similar to the set of patch templates 152 (shown in Figure 4B), plus four other patch templates containing at least a portion of each gate interconnect pad 184, along with the corners from the cluster 180 One of the adjacent clusters of each, without its mat (Adjacent clusters are not shown in Figure 5).

FIG. 6A schematically illustrates a single cluster 230. The cluster 230 includes a first conductive pad 242 (white) and a second conductive pad 244 (shadow). The conductive pads 242, 244 act as probe pads in the intermediate test phase and act as interconnect pads in the cluster interconnect phase.

By way of example, cluster 230 can be incorporated into one of a plurality of diode clusters in a power diode. As such, the first conductive pad 242 can be connected to one of the anode anode pads of the anode of the diode 230 and the second probe pad 244 can be connected to one of the cathodes of the diode of the cluster 230. Conductive pad.

FIG. 6A further schematically illustrates a set of patch templates defining two patch templates that are schematically indicated by regions enclosed by two dashed rectangles 252. Each patch template 252 includes at least a portion of one of the conductive pads 242, 244 and a portion of three adjacent clusters (not adjacent clusters are shown in Figure 5B).

Figure 6B schematically illustrates a 2 x 3 array of 6 clusters 230A through 230F incorporated into 24 clusters within a RCSD 220 (showing a full array of RCSDs 200 in Figure 6C) One of the 230 larger arrays. By way of example, cluster 230 can be a diode cluster and RCSD 220 can be a power diode. In accordance with an embodiment of the present invention, the diode cluster 230 is configured in a cluster orientation in which a plurality of rows alternate. By way of example, as shown in FIG. 6B, clusters 230A-230C are oriented such that anode conductive pads 242 are to the left of cathode conductive pads 244, while clusters 230D-230F are oriented such that anode conductive pads 242 are to the right of cathode conductive pads 244. . In this configuration of alternating orientations, the anode conductive pads of each cluster 230 are configured to face the anode conductive pads on up to three adjacent clusters and become one of the mating pads. Similarly, the cathode conductive pads are similarly arranged to become one of the mating pads of up to three adjacent sets of cathode conductive pads. By way of example, the cathode conductive pads 244 on the cluster 230E face the cathode conductive pads 244 on the clusters 230B, 230D, and 230F and become a mating pad.

In a particular embodiment of the invention, the mating pads belong to the same interconnecting channel, as shown in Figure 6B. This is shown by way of example. In a particular embodiment of the invention, the mating pads may belong to different interconnecting channels. In a particular embodiment of the invention, each of the clusters 230 in an RCSD can have a substantially identical internal circuit. Alternatively, an RCSD can include different types of clusters 230 having interconnect pads and probe pads of the same physical configuration, but with different internal circuitry, as the case may be different from the conductive pads in one of the clusters 230. The function of the conductive pads of another cluster 230 within the same RCSD.

As shown in FIG. 6B, five of the six clusters 230 are schematically indicated as having been exposed to the active cluster of patterned light defined by the set of patch templates 252. The cluster 230B, selected as a lone cluster and schematically indicated by an X-shaped mark, is not exposed to the reticle light pattern. While portions along the edges of the lone cluster 230B are exposed to the patterned light defined by the patch template 252, the conductive pads of the cluster 230B are not exposed as such.

In accordance with an embodiment of the present invention, the directional alternating configuration of clusters 230 and the shape and placement of the set of patch templates 252 are configured such that one patch template 252 includes at least a portion of one of the conductive pads on the target cluster and is proximate to the conductive The pad is adjacent to one of the three clusters. However, the patch template does not include any of its three mating pads. At the same time, patch templates 252 containing mating pads (or portions thereof) overlap when adjacent cluster 230 active clusters. The overlapping patch templates 252 create a continuous photoresist opening and a subsequent formation of a conductive patch that is electrically connected to one of the mating pads between adjacent active clusters.

6C schematically illustrates the formation of the conductive patch 262 after exposure to the reticle light pattern defined by the set of patch templates 252 (as shown in FIG. 6B) based on the clusters 230A and 230C through 230F (rather than the lone cluster 230B). An exemplary 2x3 array of clusters 230A through 230F shown in Figure 6B.

6D schematically illustrates an exemplary RCSD 220 that can (by way of example) have a 4 x 6 array of 24 clusters 230 and laterally surround one of the clusters of one of the anode leads 272 and one of the cathode leads 274. Diode. Two lone clusters are schematically indicated with an X-shaped marker, and the remaining clusters are actively clustered. According to an embodiment of the present invention, posted Sheet template 252 (not shown) is configured such that the resulting conductive patch 262 is in the form of a continuous strip applied over a plurality of active clusters. It will be appreciated that due to the alternating orientation of the clusters 230, the "pads" of conductive pads of the same channel are configured such that they can be electrically connected by a single large strip of conductive patch. Due to the formation of the continuous strip of conductive patches 262, the anode conductive pads 242 that are not adjacent to the active cluster 230 of an anode lead 272 do not require all current to travel through the intervening cluster (which typically has a higher resistance than the conductive patch) In the case of an internal circuit, a direct conductive connection is still formed with the anode lead 272. Similarly, the cathode conductive pads 244, which are not adjacent to the active cluster 230 of a cathode lead 274, form a direct conductive connection with the cathode lead 274 without requiring all current to travel through the internal circuitry of the intervening cluster.

FIG. 7A schematically illustrates a set of surrogate patch templates for defining conductive patches on cluster 230 that are schematically indicated as being enclosed within six dashed rectangles 253.

Figure 7B schematically illustrates a 2 x 3 array of clusters 230A through 230F that are substantially identical to the cluster array of Figure 6C, wherein the application is based on exposing active clusters 230A and 230C through 230F to a set of alternative patch templates 253 (shown on The patterned conductive patch 263 is patterned in FIG. 7A). The lone cluster 230B is schematically indicated by an X-shaped mark. The conductive patch 263 is relatively small and connects pairs of mating pads between adjacent active clusters as compared to the cluster array of FIG. 6C in which the conductive patches form a continuous strip 262 that covers a plurality of clusters. It will be appreciated that even in this segmented conductive patch configuration, non-adjacent clusters can still pass through the conductive patch along with the active active cluster without all currents between the non-adjacent clusters traveling through the internal circuitry of the intervening cluster. The conductive pads form a direct conductive connection.

Figure 8 schematically illustrates a single cluster 330 in a top view. The cluster 330 includes a first conductive pad 342, a second conductive pad 344, and a third conductive via including one of the four third conductive pads 346 disposed adjacent each corner of the cluster 330. The third conductive pads 346 are functionally equivalent and are electrically connected to each other through the internal circuitry of the cluster 330. Conductive pad 342, 344, 346 act as probe pads during the intermediate test phase and as interconnect pads during the cluster interconnect phase.

By way of example, cluster 330 can be incorporated into one of a plurality of FET clusters in a power FET (not shown), each FET cluster including a plurality of FET cells connected in parallel. As such, the first probe pad 342 can be a source conductive pad, the second probe pad 344 can be a gate conductive pad, and the third conductive pad 346 can be a gate conductive pad.

Figure 8 further schematically illustrates a cluster 330 having a set of patch templates schematically indicated by six regions 352A through 352F contoured by dashed lines, wherein the patch template 352A includes at least a portion of the conductive pads 342 The patch template 352B includes at least a portion of the conductive pads 344 and each of the patch templates 352C-352F includes at least a portion of a conductive pad 346.

As with cluster 230 (as shown by way of example in FIG. 6C), cluster 330 can be configured in an RCSD as a cluster of alternating rows of orientations such that first conductive pads 342 are configured to face up to three adjacent clusters. A first conductive pad 342 is also a mating pad. Similarly, the second conductive pad 344 is configured to face another second conductive pad 344 on up to three adjacent clusters and become a mating pad. In addition, the patch templates 352A and 352B are configured such that the resulting conductive patches formed on the first conductive pad 342 and the second conductive pad 344, respectively, are in a manner that does not require all current to travel through the internal circuitry of the intervening cluster. Each is electrically connected to the form of a non-adjacent active continuous strip. In contrast, the four third conductive pads 346 allow for conductive connections on all four sides of the cluster 330. The conductive connections between the non-adjacent active clusters 330 through the third conductive pads 346 are conducted through the internal circuitry of the intervening cluster.

In the description of the present application and the scope of the patent application, each of the verbs "including", "including" and "having" and its morphological change is used to indicate that the (s) object of the verb is not necessarily a verb (several). A complete list of the components, components, or components of the subject.

The description of the embodiments of the invention in this application is provided by way of example It is not intended to limit the scope of the invention. The illustrated embodiments include different features, and all such features are not required in all embodiments of the invention. All embodiments utilize only some of these features or possible combinations of such features. Variations of embodiments of the invention, which are described herein, and the various combinations of the features described in the described embodiments, are contemplated by those skilled in the art. The scope of the invention is limited only by the scope of the patent application.

10‧‧‧ wafer

20‧‧‧Rectangular redundant cluster semiconductor device/redundant cluster semiconductor device/semiconductor device

30‧‧ ‧ cluster

Claims (21)

A method of fabricating a semiconductor die comprising a plurality of interconnect components, the method comprising: fabricating a number of the components on a wafer greater than the desired plurality of components; testing the fabricated components for acceptable functionality And interconnecting a number of acceptable functional components equal to the desired number. The method of claim 1, wherein the component comprises a plurality of active component units. The method of claim 1 or claim 2, wherein the plurality of active component units comprises one or more of the group consisting of: a diode unit and a field effect transistor (FET) unit. The method of any one of claims 1 to 3, wherein the components are substantially identical. The method of any one of claims 1 to 4, wherein the component comprises a first conductive pad connected to one of the internal circuits of the component, the electrical properties of the component being measured for testing by the first conductive pad . The method of claim 5, wherein the first conductive pad is configured to be in contact with one of the probes attached to one of the probe cards of a wafer prober. The method of any one of claims 1 to 6, wherein the component comprises a second conductive pad coupled to the internal circuitry within the component and configured to pass the acceptable functional components therethrough Interconnect one of the conductive contacts. The method of claim 7, wherein the first conductive pad and the second conductive pad are the same conductive pads. The method of claim 7 or claim 8, wherein interconnecting the acceptable functional components comprises: forming one of the first conductive functional components of the first electrically conductive functional component electrically coupled to an adjacent acceptable functional component One of the second conductive pads sheet. The method of claim 9, wherein the conductive patch is formed by a photolithography process. The method of claim 10, wherein the photolithography process comprises: applying a photoresist layer to the wafer; and first forming at least one of the second conductive pads of the first acceptable functional component Exposing the photoresist layer to light at a defined region; exposing the photoresist layer to light at a second defined region of at least one of the at least a portion of the second conductive pad comprising the adjacent acceptable functional component, wherein The first and second defined regions overlap; developing the photoresist to form a single continuous photoresist opening corresponding to one of the first and second defined regions of the overlap; and opening according to the photoresist A metal layer is patterned, the patterned metal layer being the conductive patch. The method of any one of clauses 9 to 11, wherein the conductive patch comprises one or more selected from the group consisting of aluminum, gold, copper, nickel, and titanium. The method of any one of claims 1 to 12, wherein the semiconductor die comprises a device selected from the group consisting of: a power semiconductor device (SD), a flash memory chip, a field emitter Array or a system single chip (SOC). The method of claim 13, wherein the device is a power SD. The method of claim 14, wherein the power SD is a lateral power diode. The method of claim 15, wherein the at least one component comprises a plurality of lateral diode cells connected in parallel. The method of claim 14, wherein the power SD is a lateral power FET. The method of claim 17, wherein the at least one component comprises a plurality of lateral FET cells connected in parallel. The method of any one of clauses 15 to 17, wherein the lateral power SD has One of the continuous current characterizations of at least 20A, at least 25A, at least 30A, at least 35A, at least 40A, or at least 50A. The method of any one of clauses 15 to 18, wherein the power SD is characterized by having a breakdown voltage of at least 300 volts (V), at least 400V, at least 500V, at least 600V, or at least 700V. The method of any one of claims 1 to 20, wherein a current is at least partially carried by the two-dimensional electron gas (2DEG) within the assembly.