TW201424224A - Soft-start circuits and power suppliers using the same - Google Patents

Abstract

A soft-start circuit is provided for generating an output voltage at an output terminal. The soft-start circuit comprises a transistor, a capacitor, and a current source. The transistor has a first terminal receiving an input voltage, a second terminal coupled to the output voltage, and a control terminal. The capacitor is coupled between the second terminal and the control terminal of the transistor. The current source is coupled between the control terminal of the transistor and a ground terminal. A driving voltage at the control terminal of the transistor is modulated according to the output voltage to performing a soft-start operation to the output voltage.

Description

Soft start circuit and voltage supply

The present invention relates to a soft start circuit that achieves a soft start operation on an output voltage by feedback control of an output voltage.

In existing electronic circuits, some electronic circuits need to operate in accordance with a reference voltage supplied from the outside. For example, both DC-DC converters and low drop regulators (LDOs) require a reference voltage from which a fixed output voltage is generated. According to the operation of the electronic circuit, the received reference voltage must slowly rise from 0V to the target voltage. The process in which the reference voltage slowly rises from 0V to the target voltage is called soft start. Therefore, it is known to have a soft start circuit capable of generating a reference voltage that slowly rises from 0 V to a target voltage. However, in these known soft-start circuits, the rise time or slope of the reference voltage varies with the load equivalent capacitance or the load equivalent resistance, which causes the soft-start circuit to fail to generate a stable reference voltage. . In addition, these known soft-start circuits also occupy a large circuit area.

Accordingly, the present invention provides a soft-start circuit capable of generating an output voltage having a soft-start state, and the rising time of the output voltage is not affected by different load equivalent capacitances or equivalent power groups.

The present invention provides a soft start circuit for generating an output voltage at an output. This soft start circuit includes a transistor, a capacitor, and a current source. The transistor has a first end that receives an input voltage, a second end that couples the output, and a control end. The capacitor is coupled between the second end of the transistor and the control end. The current source is coupled between the control end of the transistor and the ground. The capacitor and the current source adjust the output voltage by adjusting a driving voltage on the control terminal to cause the output voltage to perform a soft start operation.

The present invention provides a voltage supply for generating a supply voltage. This voltage supply includes a voltage generating circuit and a soft start circuit. The voltage generating circuit receives the output voltage and generates the supply voltage according to the output voltage. The soft start circuit produces an output voltage at the output. The soft start circuit includes a transistor, a capacitor, and a current source. The transistor has a first end that receives an input voltage, a second end that couples the output, and a control end. The capacitor is coupled between the second end of the transistor and the control end. The current source is coupled between the control end of the transistor and the ground. The capacitor and the current source adjust the output voltage by adjusting a driving voltage on the control terminal to cause the output voltage to perform a soft start operation.

1‧‧‧Soft start circuit

6‧‧‧Power supply

10‧‧‧ PMOS transistor

11‧‧‧ capacitor

12‧‧‧current source

13‧‧‧ switch

20‧‧‧Constant current source

40...45‧‧‧ Curve

50...55‧‧‧ curve

60‧‧‧Voltage generation circuit

70‧‧‧ Bandgap reference circuit

80, 81‧‧‧ Curve

90‧‧‧Resistors

110‧‧‧Resistors

600‧‧ amp amplifier

601‧‧‧Pre-driver

602‧‧‧ PMOS transistor

603‧‧‧NMOS transistor

604‧‧‧Inductors

605, 606‧‧‧ resistors

607‧‧‧ capacitor

608‧‧‧Amplifier

609‧‧‧ PMOS transistor

610, 611‧‧‧ resistors

GND‧‧‧ ground terminal

N10‧‧‧ node

S10‧‧‧ control signal

T _OUT ‧‧‧ output

Vdrv‧‧‧ drive signal

V _IN ‧‧‧ input voltage

V _OUT ‧‧‧ output voltage

1 is a soft start circuit according to an embodiment of the present invention; FIG. 2 is a soft start circuit according to another embodiment of the present invention; and FIG. 3 is a view showing a level change of a driving voltage and an output voltage of the soft start circuit of the present invention; Figure 4 shows the driving circuit and output under the equivalent capacitance of different back-end circuits when the PMOS transistor of the soft-start circuit is used as a power switch. The level change of the voltage; Figure 5 shows the level change of the drive circuit and the output voltage under the equivalent resistance of different back-end circuits when the PMOS transistor of the soft-start circuit is used as a power switch; Figure 6 shows A power supply according to an embodiment of the present invention; FIG. 7 shows a power supply according to another embodiment of the present invention; and FIG. 8 shows a driving circuit and an output voltage when the PMOS transistor of the soft start circuit has a small size Level change; FIG. 9 shows a soft start circuit according to still another embodiment of the present invention; FIG. 10 shows a drive circuit of the soft start circuit of FIG. 9 and a level change of an output voltage; and FIG. 11 shows another according to the present invention. A soft start circuit of an embodiment.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 1 is a diagram showing a soft start circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, the soft start circuit 1 produces an output voltage V _OUT at its output terminal T _OUT , and the soft start circuit 1 includes a transistor 10, a capacitor 11, a current source 12, and a switch 13. In the embodiment of Fig. 1, the transistor 10 is implemented as a P-type Metal-Oxide Semiconductor (PMOS) transistor. The source (first end) of the PMOS transistor 10 is coupled to the input voltage V _IN , the drain (second end) of the PMOS transistor 10 is coupled to the output terminal T _OUT , and the gate (control terminal) thereof is coupled to the node N10. The capacitor 11 is coupled between the gate of the PMOS transistor 10 (ie, node N10) and the drain terminal (ie, the output terminal T _OUT ). The switch 13 is coupled between the gate of the PMOS transistor 10 and the current source 12 . The current source 12 is coupled between the switch 13 and the ground GND. The switch 13 can receive the control signal S10 and selectively turn the switch 13 on or off in accordance with the control signal S10. As shown in FIG. 1, when the switch 13 is turned on, the current source 12 can be coupled to the node N10. Figure 2 shows a soft start circuit in accordance with another embodiment of the present invention. The difference from the soft start circuit of Fig. 1 is that the current source 12 of Fig. 2 is realized by the constant current source 20. The constant current source 20 is coupled between the second end of the switch 13 and the ground GND. The rest are the same and will not be repeated here.

Referring to FIG. 2, before the soft start circuit 1 performs the soft start operation, the level of the driving voltage Vdrv (ie, the gate voltage of the PMOS transistor 10) on the node N10 is initially set to be equal to the level of the input voltage V _IN . To turn off or disable the PMOS transistor 10. At this time, the switch 13 is in an off state in accordance with the control signal S10. In one embodiment, when the gate voltage of the transistor 10 is set equal to the level of the input voltage V _IN , the bit criterion of the output voltage V _OUT is set to the 0V level. When the soft start circuit 1 is to perform a soft start operation, the switch 13 is changed from the off state to the on state according to the control signal S10. When switch 13 couples current source 12 to node N10, the current in current source 12 begins to discharge. That is, when the switch 13 is changed from the off state to the on state, the driving voltage Vdrv on the node N10 starts to fall from the initially set level (i.e., the level of the input voltage V _IN ). The extent to which the drive voltage Vdrv drops is proportional to the value of the current in the current source 12. In the embodiment of Figure 2, current source 12 is a constant current. Therefore, the driving voltage Vdrv will linearly decrease from the initial setting level (ie, the level of the input voltage V _IN ), as in the driving voltage Vdrv in FIG. 3 from 0 microseconds (us) to 300 microseconds (us) in the time interval. The waveform is shown. In one embodiment, the drive voltage Vdrv drops from the initial set level (ie, the level of the input voltage V _IN ) by a first slope during this time interval.

As the level of the driving voltage Vdrv drops, the voltage difference between the gate and the source of the PMOS transistor 10 gradually increases. When the voltage difference between the gate and the source gradually increases to a specific value (note that the specific value is smaller than the threshold voltage of the transistor 10), the transistor 10 is operated in the Subthreshold Region. The secondary threshold current flowing through the transistor 10. At this time, the output terminal T _OUT and the capacitor 11 are charged by the secondary threshold current, so that the level of the output voltage V _OUT starts to rise. Through the coupling effect of the capacitor 11, the level-up output voltage V _OUT can be coupled to the node N10 (ie, the gate of the transistor 10) such that the level of the driving voltage Vdrv has a tendency to rise. However, the level of the driving voltage Vdrv has a downward trend due to the discharge of the constant current source 20. Therefore, when the transistor 10 is operated in the sub-threshold region, the level of the driving voltage Vdrv decreases by a period of time from 0 microseconds (us) to 300 microseconds (us), as in the output voltage of FIG. V _OUT is shown by the waveform in the interval between 300 microseconds (us) and 350 microseconds (us).

When the transistor 10 operates in the secondary threshold region, the voltage difference between the gate and the source gradually increases. When the voltage difference between the gate and the source increases to be greater than the threshold voltage of the transistor 10, the transistor 10 is instead operated in a saturation region to generate a saturation current flowing through the transistor 10. The transistor 10 charges the output terminal T _OUT and the capacitor 11 with this saturation current to raise the level of the output voltage V _OUT . Similar to the aforementioned threshold region, the output voltage V _{OUT of the} level rising through the capacitor 11 is coupled to the node N10 so that the level of the driving voltage Vdrv has a tendency to rise. In detail, when the transistor 10 is operated in the saturation region, the level of the driving voltage Vdrv is affected by two factors: (1) a downward trend caused by the discharge of the constant current source 20; and (2) an output voltage V _OUT The upward trend caused by the rise in the level. In addition, when operating in a saturated region, the transistor 10 can be equivalent to a constant current source to output a fixed saturation current. Therefore, the level of the driving voltage Vdrv is affected by the constant current source 20 and the fixed saturation current, and slowly decreases linearly and is maintained substantially at a fixed level interval, as in FIG. 3, the driving voltage Vdrv is 350 microseconds (us). The waveform in the grid is shown up to 2.3 milliseconds (ms). In one embodiment, the level of the drive voltage Vdrv drops by a second slope during this time interval. In other words, when the transistor 10 is not turned on and has not been operated in the sub-threshold region, the level of the driving voltage Vdrv is linearly decreased only by the discharge of the current source 12 (as in the foregoing embodiment, the first slope is decreased). When the transistor 10 operates in the saturation region, it is affected by the rise of the output voltage V _OUT , and the driving voltage Vdrv slows down the trend, no longer drops with the first slope, but is adjusted to slowly decrease linearly and roughly Maintained at a fixed level interval (as in the previous embodiment, decreased with a second slope). The driving voltage Vdrv is maintained at a fixed level interval, so that the transistor 10 can be maintained in a saturated region, so that the level of the output voltage V _OUT rises linearly and smoothly. In summary, when the switch 13 is turned on, the level of the driving voltage Vdrv drops at the first slope until the level of the output voltage V _OUT starts to rise. After entering the saturation region, the driving voltage Vdrv on the gate of the PMOS transistor 10 slowly drops (as decreased by the second slope) and is maintained substantially at a fixed level interval, so that the level of the output voltage V _OUT continues to be slowly and linearly 0V rises toward the level of the input voltage V _IN . Referring to Figure 3, when the level of the output voltage V _OUT rises to a voltage level close to the input voltage V _IN , the level of the output voltage V _OUT will no longer rise. At this time, the rising tendency of the level of the driving voltage Vdrv is eliminated (that is, the rising tendency caused by the rise of the level of the output voltage V _OUT ). Once the uptrend is removed, the bit criterion of the drive voltage Vdrv drops by a third slope and eventually drops to the 0V level.

According to the above, the level of the output voltage V _OUT is initially set to the 0V level. Then, while the level of the driving voltage Vdrv slowly decreases linearly and remains substantially at a fixed level interval, the level of the output voltage V _OUT rises linearly and smoothly. Finally, the level of the output voltage V _OUT reaches and maintains the voltage level at the input voltage V _IN . In this way, a soft start operation on the output voltage V _OUT is achieved. Further, according to the above, the soft start operation of the present invention is realized by the physical behavior of the PMOS transistor 10, the capacitor 11, and the constant current source 20. In particular, when the level of the output voltage V _OUT gradually rises, the driving voltage Vdrv on the gate of the PMOS transistor 10 can be automatically transmitted through the capacitor 11 coupled between the gate and the drain of the PMOS transistor 10. Adjustment.

Referring to Figure 3, during the rise of the level of the output voltage V _OUT from 0V towards the level of the input voltage V _IN (ie, between 350 microseconds (us) and 2.3 milliseconds (ms)), the output voltage V The level of _OUT rises in a linear fashion. Furthermore, according to the embodiment of Fig. 2, the first slope is equal to the third slope. In the case where the level of the driving voltage Vdrv starts to slowly decrease with the second slope according to the above-described falling tendency and the rising trend, the second slope is smaller than the first slope and smaller than the third slope.

In some embodiments, the PMOS transistor 10 of the soft start circuit 1 can be of a larger size to function as a power switch. At this time, the soft start circuit 1 having the large size PMOS transistor 10 can be configured in a power stage in the circuit system and provides an output voltage V _OUT to the back end circuit. Figure 4 is a diagram showing the level change of the drive circuit Vdrv and the output voltage V _OUT under the equivalent capacitance of different back-end circuits when the PMOS transistor 10 is used as a power switch. Since the PMOS transistor 10 has a large size, the input voltage V _IN may be a 5V voltage. In Fig. 4, the curve 40 is the driving voltage Vdrv when there is no equivalent capacitance of the back-end circuit (i.e., the equivalent capacitance is equal to 0). Curves 41 and 42 are the drive voltages Vdrv when the equivalent capacitance of the back-end circuit is equal to 0.1 microfarad (uF) and 10uF, respectively. Curve 43 is the output voltage V _OUT when there is no equivalent capacitance of the back end circuit. Curves 44 and 45 are output voltages V _OUT when the equivalent capacitance of the back-end circuit is equal to 0.1 uF and 10 uF, respectively.

Referring to curves 40 and 43 of FIG. 4, when there is no equivalent capacitance of the back-end circuit, the level of the driving voltage Vdrv is set by 5V within 100 microseconds (100 microseconds, 100 us) after the switch 13 is turned on (initial setting) The level of the drop is 4.9V, and then slowly decreases linearly during the period of 100us to 2.1 milliseconds (2.1 mini second, 2.1ms) and is maintained substantially at a fixed level interval. During this period of 100us to 2.1ms, the level of the output voltage V _OUT rises from 0V to 5V in a linear and smooth manner. Therefore, it can be known that the time of the soft start operation for the output voltage V _OUT is 2 ms in the absence of the equivalent capacitance of the back end circuit. Referring to curves 41 and 44 of FIG. 4, when the equivalent capacitance of the back-end circuit is equal to 0.1 uF, the level of the output voltage V _OUT is linearly and smoothly in a period of 300 us to 2.3 ms after the switch 13 is turned on. 0V rises to 5V. Therefore, in the case where the equivalent capacitance of the back-end circuit is equal to 0.1 uF, the time for the soft-start operation of the output voltage V _OUT is also 2 ms. Referring also to curves 42 and 45 of FIG. 4, when the equivalent capacitance of the back-end circuit is equal to 10 uF, the level of the output voltage V _OUT is linearly and smoothly in a period of 600 us to 2.6 ms after the switch 13 is turned on. 0V rises to 5V. Therefore, in the case where the equivalent capacitance of the back-end circuit is equal to 10 uF, the time for the soft-start operation of the output voltage V _OUT is also 2 ms. According to the above, regardless of the equivalent capacitance of the back-end circuit, the level 0V of the output voltage V _OUT rises to 5V for 2 ms. In addition, according to the curves 43 to 45, the slope of the rising curve of the output voltage V _OUT rising from 0 V to 5 V is almost the same. Therefore, the rising time of the soft start of the output voltage V _OUT and the slope of the curve are not affected by the equivalent capacitance of the back end circuit.

Figure 5 is a diagram showing the level change of the drive circuit Vdrv and the output voltage V _OUT under the equivalent resistance of different back-end circuits when the PMOS transistor 10 is used as a power switch. Since the PMOS transistor 10 has a large size, the input voltage V _IN may be a 5V voltage. In Fig. 5, the curve 50 is the driving voltage Vdrv when there is no equivalent resistance of the back-end circuit (i.e., the equivalent resistance is equal to 0). Curves 51 and 52 are the drive resistances Vdrv when the equivalent resistance of the back-end circuit is equal to 100 ohms (100 ohms) and 10 ohms, respectively. Curve 53 is the output voltage V _OUT when there is no equivalent capacitance of the back end circuit. Curves 54 and 55 are output voltages V _OUT when the equivalent capacitance of the back end circuit is equal to 100 ohms and 10 ohms, respectively.

Referring to curves 50 and 53 of FIG. 5, when there is no equivalent resistance of the back-end circuit, the level of the driving voltage Vdrv drops from 5 V (initial set level) to 4.9 V within 100 us after the switch 13 is turned on. And then during the period of 100us to 2.1ms, it slowly decreases linearly and is maintained substantially at a fixed level interval. During this period of 100us to 2.1ms, the level of the output voltage V _OUT rises from 0V to 5V in a linear and smooth manner. Therefore, it can be known that the time of the soft start operation for the output voltage V _OUT is 2 ms (millisecond) in the absence of the equivalent resistance of the back end circuit. Referring to curves 51 and 54 of FIG. 5, when the equivalent resistance of the back-end circuit is equal to 100 ohms, the level of the output voltage V _OUT is linearly and smoothly from 0 V during the period of 400 us to 2.5 ms after the switch 13 is turned on. Rise to 5V. Therefore, in the case where the equivalent resistance of the back-end circuit is equal to 100 ohms, the soft-start operation time of the output voltage V _OUT is 2.1 ms. Referring also to curves 52 and 55 of FIG. 5, when the equivalent resistance of the back-end circuit is equal to 10 ohms, the level of the output voltage V _OUT is linearly and smoothly in a period of 600 us to 2.8 ms after the switch 13 is turned on. 0V rises to 5V. Therefore, in the case where the equivalent resistance of the back-end circuit is equal to 10 ohms, the soft-start operation time of the output voltage V _OUT is 2.2 ms. According to the above, the magnitude of the equivalent resistance of the back-end circuit has little effect on the time when the level of the output voltage V _OUT rises from 0 V to 5 V.

In other embodiments, the soft start circuit 1 can be applied to a power supply to provide an output voltage V _OUT as a reference voltage in the power supply such that the power supply can generate a fixed supply based on the output voltage V _OUT . Voltage. In these embodiments, the PMOS transistor 10 can have a smaller size. Referring to Fig. 6, the power supply 6 includes the soft start circuit 1 and the voltage generating circuit 60 of Fig. 1. In this embodiment, the voltage generating circuit 60 is implemented as a DC-DC converter. The voltage generating circuit 60 includes an amplifier 600, a pre-driver 601, a PMOS transistor 602, a P-type Metal-Oxide Semiconductor (NMOS) transistor 603, an inductor 604, resistors 605 and 606, and a capacitor 607. . The amplifier 600 receives the output voltage V _OUT from the soft start circuit 1 as its reference voltage. The resistor 605 and the resistor 606 are divided and supplied with a voltage V60, and then fed back to the amplifier 600. The amplifier 600 can generate a signal according to the divided supply voltage V60 and V _OUT as a reference voltage to be controlled by the pre-driver 601. The switching of the PMOS transistor 602 and the NMOS transistor 603 generates a fixed supply voltage V60. In the embodiment of Fig. 6, the circuit architecture of the voltage generating circuit 60 as the DC-to-DC converter is only the only exemplary embodiment and is not limited thereto. In other embodiments, voltage generation circuit 60 may have other circuit architectures to implement DC to DC conversion.

Moreover, in still other embodiments, voltage generation circuit 60 can be implemented as a low drop regulator (LDO), as shown in FIG. In this embodiment, voltage generating circuit 60 includes an amplifier 608, a PMOS transistor 609, and resistors 610 and 611. The amplifier 608 receives the output voltage V _OUT from the soft start circuit 1 as its reference voltage. The resistor 610 and the resistor 611 are divided and supplied with a voltage V60, and then fed back to the amplifier 608. The amplifier 608 can generate a signal according to the divided supply voltage V60 and V _OUT as a reference voltage to control the PMOS transistor 609. A fixed supply voltage V60 is produced. In the embodiment of Fig. 7, the power supply 6 additionally includes a bandgap reference circuit 70 which generates a bandgap voltage V70 as the input voltage V _{IN of the} soft start circuit 1. The bandgap voltage V70 generated by the bandgap reference circuit 70 is not affected by temperature and process variations, so the bandgap voltage is a stable voltage. Therefore, the bandgap voltage V70 is relatively accurate. In the embodiment of Fig. 7, the circuit architecture of the voltage generating circuit 60 as the low dropout linear regulator is only a singular example and is not limited thereto. In other embodiments, voltage generation circuit 60 may have other circuit architectures to implement low dropout regulated operation. Moreover, in the embodiment of Figure 7, the bandgap reference circuit 70 can have any known circuit architecture or have any circuit architecture that can produce bandgap voltages that are unaffected by temperature and process variations.

In the sixth and seventh embodiments, the PMOS transistor 10 has a small size to package the components of the power supply 6 in a wafer. Fig. 8 shows the level change of the drive circuit Vdrv and the output voltage V _OUT when the PMOS transistor 10 has a small size. Since the PMOS transistor 10 has a small size, the components of the power supply 6 can be packaged in a wafer, and the input voltage V _{IN of the} power supply 6 is typically less than 1.2V. Referring to Figure 8, curve 80 is when there is no equivalent capacitance of the back-end circuit (ie, the equivalent capacitance is equal to 0), or when the equivalent capacitance of the back-end circuit is equal to 1 picofarad (pF) or 10pF The driving voltage Vdrv at the time. Curve 81 is the output voltage V _OUT when there is no equivalent capacitance of the back end circuit, or when the equivalent capacitance of the back end circuit is equal to 1 pF or 10 pF. According to an embodiment of the invention, the curve of the corresponding driving voltage Vdrv is the same (ie, curve 80), and the corresponding output voltage V _OUT has the same curve, regardless of the capacitance value of the equivalent capacitance value of 0, 1 pF or 10 pF. (ie curve 81). Referring to Fig. 8, when the PMOS transistor 10 is turned on, the level of the driving voltage Vdrv drops rapidly (e.g., 1.2V drops to 0.84V). Due to the rapid drop of the driving voltage Vdrv, the coupling effect of the transmission capacitor 11 causes the level of the output voltage V _OUT to rapidly drop to -0.3V. Thereafter, the level of the output voltage V _OUT rises from 0 V to 1.2 V in a linear manner during a period from 0 s to 1.6 ms after the switch 13 is turned on.

In some embodiments, when the PMOS transistor 10 employs a small-sized transistor, the soft-start circuit 1 may further include a resistor to eliminate the initial negative voltage drop of the output voltage V _OUT described above. As shown in FIG. 9, the soft start circuit 1 further includes a resistor 90 coupled between the output terminal T _OUT and the ground GND. Fig. 10 shows the level change of the drive circuit Vdrv and the output voltage V _OUT when the PMOS transistor 10 has a small size and a resistor 90 is applied to the output terminal T _OUT . In this embodiment, resistor 90 has a resistance value of 100K ohms. Referring to FIGS. 9 and 10, when the PMOS transistor 10 is turned on, since the resistor 90 supplies a voltage to the output terminal T _OUT , the level of the output voltage V _OUT is at 0 V or slightly decreased to -0.2 V. In this way, when the PMOS transistor 10 is turned on, the initial negative voltage drop of the output voltage V _OUT can be eliminated by coupling the resistor 90 to the output terminal T _OUT .

In the above embodiment, the current source 12 is implemented with a constant current source 20. In other embodiments, current source 12 can be implemented as a variable current source. Referring to FIG. 11 , the current source 12 includes a resistor 110 coupled between the second end of the switch 13 and the ground GND. The PMOS transistor 10, the capacitor 11, the current source 12, the switch 13, and the resistor 110 are disposed in the same wafer.

Referring to FIG. 11, before the soft start circuit 1 performs the soft start operation, the level of the driving voltage Vdrv on the node N10 is initially set to be equal to the level of the input voltage V _IN , and the level of the output voltage V _OUT is set to 0 V bits. quasi. When the soft start circuit 1 is to perform a soft start operation, the switch 13 is changed from the off state to the on state according to the control signal S10. At this time, the level of the driving voltage Vdrv is discharged through the discharge path formed by the resistor 110, and starts to rapidly fall from the initial setting level. As the level of the driving voltage Vdrv drops, the voltage difference between the gate and the source of the PMOS transistor gradually increases. When the voltage difference between the gate and the source gradually increases to a specific value (note that the specific value is less than the threshold voltage of the transistor 10), the transistor 10 is operated in the Subthreshold Region. A secondary threshold current flowing through the transistor 10 is generated. At this time, the output terminal T _OUT and the capacitor 11 are charged by the secondary threshold current, so that the level of the output voltage V _OUT starts to rise. Through the coupling effect of the capacitor 11, the level-up output voltage V _OUT can be coupled to the node N10 (ie, the gate of the transistor 10) such that the level of the driving voltage Vdrv has a tendency to rise. However, the level of the driving voltage Vdrv has a downward trend due to the discharge of the resistor 110. When the transistor 10 operates in the secondary threshold region, the voltage difference between the gate and the source gradually increases. When the voltage difference between the gate and the source is increased to be greater than the threshold voltage of the transistor 10, the transistor is caused to operate in a saturation region to generate a saturation current flowing through the transistor 10. The transistor 10 charges the output terminal T _OUT and the capacitor 11 with this saturation current to raise the level of the output voltage. When operating in a saturated region, the transistor 10 can be equivalent to a constant current source to output a fixed saturation current. Therefore, the level of the driving voltage Vdrv starts to slowly decrease linearly and is maintained substantially at a fixed level interval. Since the driving voltage Vdrv on the gate of the PMOS transistor 10 slowly decreases linearly and is maintained substantially at a fixed level interval, the level of the output voltage V _OUT continues to rise toward the level of the input voltage V _IN . The driving voltage Vdrv is maintained at a fixed level interval, so that the transistor 10 can be maintained in a saturated region, so that the level of the output voltage V _OUT rises linearly and smoothly. When the level of the output voltage V _OUT rises to a voltage level close to the input voltage V _IN , the level of the output voltage V _OUT will no longer rise, so that the coupling effect of the capacitor 11 is eliminated from the rising trend of the level of the driving voltage Vdrv. Once the uptrend is removed, the level of the drive voltage Vdrv drops rapidly and eventually drops to the 0V level.

According to the above, the soft start circuit 1 of the present invention can control the level of the driving voltage Vdrv through the feedback regulation of the capacitor 11, so that the output voltage V _OUT realizes a soft start operation. The circuit for realizing the soft start (the PMOS transistor 10, the capacitor 11 and the current source 12 and the like) can be packaged in the same wafer as the power supply to reduce the circuit area. In addition, the rise time of the output voltage V _OUT of the present invention is almost completely unaffected by different load equivalent capacitances or equivalent resistances.

Although the present invention has been disclosed above in the preferred embodiment, it is not The scope of the present invention is defined by those skilled in the art, and the scope of the invention is intended to be modified and modified. The definition is final.

1‧‧‧Soft start circuit

10‧‧‧ PMOS transistor

11‧‧‧ capacitor

12‧‧‧current source

13‧‧‧ switch

GND‧‧‧ ground terminal

N10‧‧‧ node

S10‧‧‧ control signal

T _OUT ‧‧‧ output

Vdrv‧‧‧ drive signal

V _IN ‧‧‧ input voltage

V _OUT ‧‧‧ output voltage

Claims (20)

A soft start circuit for generating an output voltage on an output terminal, comprising: a transistor having a first end receiving an input voltage, a second end coupled to the output end, and a control end; a capacitor coupled between the second end of the transistor and the control terminal; and a current source coupled between the control terminal and the ground terminal of the transistor; wherein the capacitor and the current The source adjusts the output voltage by adjusting a driving voltage on the control terminal to cause the output voltage to perform a soft start operation. The soft start circuit of claim 1, further comprising: a resistor coupled between the output terminal and the ground; wherein the transistor, the capacitor, the current source, and the resistor The device is configured in a wafer. The soft start circuit of claim 1, further comprising: a switch coupled between the control end of the transistor and the current source; wherein, when the switch is turned on, the current source performs a The discharge operation causes the level of the drive voltage to drop. The soft start circuit of claim 3, wherein when the level of the output voltage begins to rise, the capacitor adjusts the level of the driving voltage according to the discharging operation and the level of the output voltage. The soft start circuit of claim 4, wherein the level of the driving voltage is slowly linear during a period in which the capacitor adjusts the level of the driving voltage according to the discharging operation and the level of the output voltage. Drop and Maintain a fixed level interval. The soft start circuit of claim 4, wherein the level of the output voltage faces the input while the capacitor adjusts the level of the driving voltage according to the discharging operation and the level of the output voltage. The level of the voltage rises linearly to achieve this soft-start operation of the output voltage. The soft start circuit of claim 4, wherein when the level of the output voltage rises to a level close to the input voltage, the level of the driving voltage begins to decrease toward the level of the ground. The soft start circuit of claim 1, wherein the transistor operates during a period in which the capacitor adjusts a level of the driving voltage according to a discharge operation of the current source and a level of the output voltage. A saturated area. The soft start circuit of claim 1, wherein the current source is implemented by a constant current source. A voltage supply for generating a supply voltage, comprising: a voltage generating circuit that receives an output voltage and generates the supply voltage according to the output voltage; and a soft start circuit that generates the output voltage at an output end The soft start circuit includes: a transistor having a first end receiving an input voltage, a second end coupled to the output end, and a control end; a capacitor coupled to the transistor Between the second end and the control terminal; and a current source coupled between the control terminal and the ground terminal of the transistor; wherein the capacitor and the current source are adjusted by one on the control terminal drive The output voltage is adjusted by the voltage to cause the output voltage to perform a soft start operation. The voltage supply of claim 10, further comprising: a resistor coupled between the output terminal and the ground; wherein the transistor, the capacitor, the current source, and the resistor The device is configured in a wafer. The voltage supply device of claim 10, further comprising: a switch coupled between the control terminal of the transistor and the current source; wherein, when the switch is turned on, the current source performs a The discharge operation causes the level of the drive voltage to drop. The voltage supply of claim 12, wherein when the level of the output voltage begins to rise, the capacitor adjusts the level of the driving voltage according to the discharging operation and the level of the output voltage. The voltage supply device of claim 13, wherein the capacitor linearly drops and maintains a level of the driving voltage during a period in which the driving voltage is adjusted according to the discharging operation and the level of the output voltage. In a fixed level interval. The voltage supply device of claim 13, wherein the capacitor is oriented toward the input voltage during a period in which the level of the driving voltage is adjusted according to the discharging operation and the level of the output voltage. The level of the line rises linearly to achieve the soft start operation of the output voltage. The voltage supply of claim 13, wherein when the level of the output voltage rises to a level close to the input voltage, the level of the driving voltage begins to decrease toward the level of the ground. The voltage supply of claim 10, wherein the transistor operates during a period in which the capacitor adjusts a level of the driving voltage according to a discharging operation of the current source and a level of the output voltage A saturated area. The voltage supply device of claim 10, wherein the voltage generating circuit is a DC-to-DC converter or a low-dropout linear regulator, and the DC-to-DC converter or the low-dropout linear regulator An amplifier in the device receives the output voltage as a reference voltage. The voltage supply device of claim 10, further comprising: a bandgap reference circuit for generating a bandgap voltage to the soft start circuit as the input voltage. The voltage supply of claim 10, wherein the current source is implemented with a constant current source.