TWI626521B - Low dropout regulating device and operatig method thereof - Google Patents

Abstract

A low dropout voltage regulator includes a voltage regulator and a precharger. The voltage regulator is configured to adjust an output voltage provided to the output node according to a voltage difference between the first reference voltage and a feedback voltage on the feedback node, wherein the feedback node is coupled to the output node. The precharger is electrically connected to the voltage regulator, and the precharger is electrically connected to the feedback node for charge sharing.

Description

Low dropout voltage regulator device and operation method thereof

The invention relates to a low-dropout voltage regulator device and an operation method thereof.

Low dropout (LDO) regulators have been widely used in various electronic products due to their low noise and low cost. The low dropout regulator provides a stable output voltage for use as a power supply circuit. For example, a low dropout regulator can be used to provide a DC power supply for memory chip operation.

However, the low dropout regulator may generate an unstable, unpredictable output voltage during circuit operation state transitions, causing abnormal operation of the load circuit. Therefore, how to propose an improved low-dropout voltage regulator device and its operation method to solve the above problems is one of the subjects of the field.

The invention relates to a low-dropout voltage regulator device and an operation method thereof, which can accelerate the startup speed of the low-dropout voltage regulator device, so as to shorten the time required for the low-dropout voltage regulator device to enter normal operation.

According to an embodiment of the invention, a low-dropout voltage regulator device is provided. It includes a voltage regulator and a precharger. The voltage regulator is configured to adjust an output voltage provided to the output node according to a voltage difference between the first reference voltage and a feedback voltage on the feedback node, wherein the feedback node is coupled to the output node, and the voltage regulator includes a comparison circuit And an output transistor. The comparison circuit is configured to receive the first reference voltage and the feedback voltage, and generate a control voltage on the control node according to the first reference voltage and a voltage difference between the feedback voltages. The output transistor has a control end coupled to the control node, a first end coupled to the supply voltage, and a second end coupled to the output node, the output transistor being responsive to the control voltage to generate by the second end The output voltage. The precharger is electrically connected to the voltage regulator, and the precharger is electrically connected to the feedback node for charge sharing.

According to another embodiment of the present invention, a method for operating a low dropout voltage regulator device is provided. The method includes the following steps: configuring a voltage regulator to apply a feedback voltage to a feedback voltage node according to a first reference voltage The differential pressure adjustment provides an output voltage to an output node; a precharger is configured to electrically isolate the feedback node from the feedback node to accumulate charge when the regulator is in a closed state; and electrically connect the The precharger and the feedback node perform charge sharing.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10, 10', 30, 30', 40, 40' ‧ ‧ low dropout regulator

102, 302, 302', 402, 402' ‧ ‧ voltage regulator

1022‧‧‧Comparative circuit

1024‧‧‧ feedback circuit

104‧‧‧Prefiller

1042‧‧‧Precharge source

106‧‧‧keeping circuit

1062‧‧‧ Standby power supply

108‧‧‧ bias power supply

M1‧‧‧ output transistor

SWc‧‧‧ control switch

Vref1‧‧‧ first reference voltage

Vref2‧‧‧second reference voltage

Vref3‧‧‧ third reference voltage

Vfb‧‧‧ feedback voltage

Vc‧‧‧ control voltage

Vout‧‧‧ output voltage

SET‧‧‧Set voltage

Nfb‧‧‧Feedback node

Nc‧‧‧ control node

Nout‧‧‧ output node

VDD‧‧‧ supply voltage

R1‧‧‧first impedance component

R2‧‧‧second impedance element

EN‧‧‧Switch signal

Inverted signal of ENB‧‧‧ switching signal

SWf‧‧‧Return switch

SWa‧‧ sampling switch

SWb‧‧‧Share switch

SWt‧‧‧ Standby switch

BST‧‧‧ bias signal

During the period when the Toff‧‧ voltage regulator is off

Ton‧‧‧ voltage regulator is on

S1‧‧‧Sampling signal

S2‧‧‧Shared signal

The first period of T1‧‧

Second period of T2‧‧

Csas‧‧‧Precharge capacity

Cf‧‧‧ feedback capacitor

602, 604, 606‧‧ steps

V1, V2, V1', V2'‧‧‧ potential

FIG. 1A is a circuit diagram of a low dropout voltage regulator according to an embodiment of the invention.

FIG. 1B is a circuit diagram of a low dropout voltage regulator according to another embodiment of the present invention.

Figure 2A shows the waveform diagram of the relevant signal of the low dropout voltage regulator.

FIG. 2B is a waveform diagram showing another example of a related signal of the low-dropout voltage regulator.

FIG. 3A is a circuit diagram of a low dropout voltage regulator according to an embodiment of the invention.

FIG. 3B is a circuit diagram of a low dropout voltage regulator according to an embodiment of the invention.

4A is a circuit diagram of a low dropout voltage regulator according to still another embodiment of the present invention.

FIG. 4B is a circuit diagram of a low dropout voltage regulator according to still another embodiment of the present invention.

FIG. 5A is a diagram showing an example of a waveform of a related signal of a low-dropout voltage regulator device.

FIG. 5B is a diagram showing another example of waveforms of related signals of the low-dropout voltage regulator.

FIG. 6 is a flow chart showing the operation method of the low-dropout voltage stabilizing device according to an embodiment of the present invention.

The following is a detailed description of the embodiments, which are intended to be illustrative only and not to limit the scope of the disclosure. In addition, the drawings in the embodiments omit unnecessary elements to clearly show the technical features of the disclosure.

FIG. 1A is a circuit diagram of a low-dropout voltage regulator device 10 in accordance with an embodiment of the present invention. Low-dropout regulator 10 provides regulated output voltage Vout to the output node Nout, such as NOR flash memory, NAND flash memory, dynamic random-access memory (DRAM) or static random-access memory (static random-access memory, SRAM).

The low dropout voltage regulator device 10 includes a voltage regulator 102 and a precharger 104, and more selectively includes a hold circuit 106 and a bias power supply 108.

The regulator 102 is configured to adjust the output voltage Vout provided to the output node Nout according to a voltage difference between the first reference voltage Vref1 and the feedback voltage Vfb.

The voltage regulator 102 includes a comparison circuit 1022, an output transistor M1, and a feedback circuit 1024. In this embodiment, the output transistor M1 is implemented, for example, as a P-type transistor, such as a PMOS.

The comparison circuit 1022 is, for example, an Operational Amplifier (OPA). The comparison circuit 1022 can receive the first reference voltage Vref1 and the feedback voltage Vfb, and generate the control voltage Vc on the control node Nc according to the voltage difference between the first reference voltage Vref1 and the feedback voltage Vfb.

The output transistor M1 is turned on in response to the control voltage Vc to provide an output voltage Vout to the output node Nout. As shown in FIG. 1A, the output transistor M1 has a control end (such as a gate) coupled to the control node Nc, a first end (such as a source/drain) coupled to the supply voltage VDD, and a first coupled output node Nout. Two ends (such as 汲 / source). When the output transistor M1 is turned on, the supply voltage VDD will be delivered to the output node Nout as the output voltage Vout.

The feedback circuit 1024 is coupled between the output node Nout and the comparison circuit 1022 to provide a voltage dividing path to form a feedback node Nfb, and is to be fed back The feedback voltage Vfb on the node Nfb is supplied to the comparison circuit 1022.

As shown in FIG. 1A, the feedback circuit 1024 includes a first impedance element R1 and a second impedance element R2 to form a voltage dividing path to the output voltage Vout. The first impedance element R1 and the second impedance element R2 are connected in series, and the junction between the two forms a feedback node Nfb. The first impedance element R1 and the second impedance element R2 may be resistors or any other circuit element equivalent to resistance.

During the operation of the low-dropout regulator 10, if the output voltage Vout fluctuates, the feedback voltage Vfb will change in conjunction. At this time, the comparison circuit 1022 will adjust the control voltage Vc of the comparison circuit 1022 in response to the change of the feedback voltage Vfb. Further, the current flowing out of the output transistor M1 is changed by the adjusted control voltage Vc to maintain the output voltage Vout at a predetermined level.

The voltage regulator 102 can be turned on or off under the control of the switching signal EN. When the switching signal EN is enabled, the voltage regulator 102 is in an on state; when the switching signal EN is disabled, the voltage regulator 102 is in an off state. As shown in FIG. 1A, the comparison circuit 1022 is turned on or off controlled by the switching signal EN.

The voltage regulator 102 can further include a control switch SWc. The control switch SWc is coupled between the set voltage SET and the control node Nc, which is controlled, for example, by the switching signal EN. When the voltage regulator 102 is in the on state, the switching signal EN is enabled, and the control switch SWc is turned off (Turn OFF), so that the set voltage SET (which may be the power supply voltage) is electrically isolated from the control node Nc; when the voltage regulator 102 is at In the off state, the switching signal EN is disabled, and the control switch SWc is turned on (Turn ON), and the set voltage SET is transmitted to the control node Nc to turn off the output transistor M1.

In an embodiment, the voltage regulator 102 further includes a feedback switch SWf controlled by the switching signal EN. The feedback switch SWf is disposed between the feedback circuit 1024 and the output node Nout. When the switching signal EN is enabled, that is, the regulator 102 is in the on state, the feedback switch SWf will be turned on (Turn ON) to couple the output node Nout with the feedback circuit 1024. Conversely, when the switching signal EN is disabled, that is, the regulator 102 is in the off state, the feedback switch SWf will be turned on (Turn OFF) to electrically isolate the output node Nout from the feedback circuit 1024.

In an embodiment, the precharger 104 is configured to precharge the feedback voltage Vfb on the feedback node Nfb to a predetermined voltage.

The precharger 104 can be electrically isolated from the feedback node Nfb and accumulate charge when the voltage regulator 102 is in the off state, and temporarily electrically connected to the feedback node Nfb to perform charge when the voltage regulator 102 is switched to the on state. share it.

Generally, without the design of the precharger 104, when the voltage regulator 102 is switched from the off state to the on state, the feedback voltage Vfb on the feedback node Nfb often takes a certain time to be upgraded to be suitable for the voltage stabilization operation. Voltage level. However, this period of time will seriously affect the "starting speed" of the low-dropout regulator 10. To speed up the startup speed of the low dropout regulator 10, when the regulator 102 is turned on, the precharger 104 can share its accumulated charge to the feedback node Nfb to quickly raise the level of the feedback voltage Vfb.

In one embodiment, the precharger 104 includes a precharge source 1042, a precharge capacitor Csas, a sampling switch SWa, and a sharing switch SWb to collectively form a charge sharing circuit configuration. The precharge source 1042 is configured to provide a second reference voltage Vref2. The sampling switch SWa is coupled between the pre-charging capacitor Csas and the pre-charging source 1042 to allow the pre-charging source 1042 to charge the pre-charging capacitor Csas. The sharing switch SWb is coupled between the pre-charging capacitor Csas and the feedback node Nfb to allow the pre-charging capacitor Csas to perform charge sharing with the feedback node Nfb.

For example, when the voltage regulator 102 is in the off state, the sampling switch SWa is turned off (Turn ON), the pre-charging capacitor Csas is coupled to the pre-charging source 1042, and the sharing switch SWb is turned on (Turn OFF), so that the pre-charging is performed. The Csas is electrically isolated from the feedback node Nfb. At this time, the precharge source 1042 will charge the precharge capacity Csas with the second reference voltage Vref2.

When the voltage regulator 102 is switched to the on state, the sampling switch SWa will electrically isolate the precharge capacity Csas from the precharge source 1042 during the first period, and the sharing switch SWb will be precharged during a second period in the first period. The Csas is electrically connected to the feedback node Nfb. At this time, the charge accumulated on the precharge capacity Csas will be charge-shared with the parasitic capacitance on the feedback node Nfb, so that the feedback voltage Vfb is rapidly increased. Since the capacitance value of the parasitic capacitance on the feedback node Nfb is often much smaller than the capacitance value of the precharge capacity Csas, a predetermined value of the feedback voltage Vfb after the charge sharing can be determined by appropriately designing the precharge capacity Csas. The predetermined value is bounded between a lowest potential and a steady state potential of the feedback voltage Vfb.

In an embodiment, the low dropout voltage regulator device 10 further includes a hold circuit 106. The hold circuit 106 can supply power to the output node Nout when the regulator 102 is in the off state.

The hold circuit 106 includes, for example, a standby power supply 1062 and a standby switch SWt. Standby power supply 1062 can be implemented by another low dropout voltage regulator to provide a third reference voltage Vref3. The standby switch SWt is disposed between the standby power supply 1062 and the output node Nout, and is controlled by the inverted signal ENB of the switching signal EN. The standby switch SWt may allow the standby power supply 1062 to supply the output node Nout with the third reference voltage Vref3 when the voltage regulator 102 is in the off state.

For example, when the voltage regulator 102 is in the on state, the standby switch SWt is turned on (Turn OFF) to electrically isolate the output node Nout from the standby power source 1062. On the contrary, when the voltage regulator 102 is in the off state, the standby switch SWt is closed, and the standby power source 1062 is coupled to the output node Nout for power supply.

Through the holding circuit 106, the output voltage Vout on the output node Nout can be maintained at a certain level when the regulator 102 is turned off, so that the time required to start the low-dropout voltage regulator device 10 can be further shortened.

In an embodiment, the pre-charge source 1042 in the precharger 104 can be integrated with the standby power source 1062 in the hold circuit 106. At this time, the second reference voltage Vref2 is the same as the third reference voltage Vref3.

The low dropout voltage regulator device 10 can further include a bias power supply 108 coupled to the comparison circuit 1022. Bias power supply 108 can be implemented, for example, by a current mirror circuit and/or a resistor. When the regulator 102 is turned on, the bias power supply 108 can provide a bias signal BST to the comparison circuit 1022 to increase its bias current, thereby accelerating the startup speed at the control node Nc.

Fig. 1B is a circuit diagram showing a low dropout voltage stabilizing device 10' according to another embodiment of the present invention. Compared with the low dropout regulator 10, low dropout regulator The input 10' does not include the feedback circuit 1024, and one end of the output transistor M1 is directly coupled to an input terminal (such as a negative (-) input terminal) of the comparison circuit 1022 via a feedback switch SWf (optionally). It will be appreciated that embodiments of the present invention may also employ a circuit configuration such as a low dropout voltage regulator 10' without including a feedback circuit 1024. At this time, the feedback node Nfb is defined at the junction of one end of the output transistor M1 and the input terminal of the comparison circuit 1022.

FIG. 2A is a waveform diagram showing related signals of the low-dropout voltage regulator device 10.

During the period Toff, the switching signal EN is disabled (for example, with a low signal level) to turn off the voltage regulator 102, and the reverse signal ENB of the switching signal is enabled (for example, with a high signal level) to enable the standby power supply 1062. The output node Nout is charged. In addition, the sampling signal S1 is enabled to control the sampling switch SWa to be closed to allow the second reference voltage Vref2 to charge the pre-charging capacitor Csas. The sharing signal S2 is disabled to control the sharing switch SWb to open to electrically isolate the pre-charging capacitor Csas from the feedback node Nfb.

During the period Ton, the switching signal EN is enabled to turn on the voltage regulator 102, and the reverse signal ENB of the switching signal EN is disabled, so that the standby power supply 1062 is electrically isolated from the output node Nout. During the beginning of the period Ton, the sampling signal S1 is disabled during a first period T1 to turn on the sampling switch SWa to electrically isolate the pre-charging capacitor Csas from the second reference voltage Vref2. During a second period T2 in the first period T1, the sharing switch SWb is closed in response to the enabled sharing signal S2, so that the pre-charging capacitor Csas is electrically connected to the feedback node Nfb for charge sharing.

In an embodiment, to ensure that no additional charge (eg, charge from the pre-charge source 1042) flows into the feedback node Nfb during charge sharing, the feedback voltage Vfb is predictable, and the second period T2 is first The period T2 is short, that is, the Raising edge of the shared signal S2 is later than the falling edge of the sampling signal S1; and the falling edge of the shared signal S2 is earlier than the positive edge of the sampled signal S1. (Raising edge), as shown in Figure 2A.

After the charge sharing is completed, the sampling switch SWa and the sharing switch SWb will return to the closed and open states, respectively, until the next low-dropout voltage stabilizing device 10 is switched from the off state to the on state again. As shown in FIG. 2A, each time the regulator 102 is switched from the off state to the on state, the precharger 104 will perform a one-time charge sharing on the feedback node Nfb to properly set back the regulator 102 when it is turned on. Grant voltage Vfb.

In the example of Fig. 2A, the bias signal BST is the inverted signal of the sample signal S1. That is, the bias power supply 108 can increase the bias current of the comparison circuit 1022 during the first period T1 to further accelerate the startup speed of the control node Nc.

FIG. 2B is a waveform diagram showing another example of the related signal of the low-dropout voltage regulator device 10. Compared with the embodiment shown in FIG. 2A, in the embodiment, the pre-charger 104 is electrically connected to the feedback node Nfb before the voltage regulator 102 is turned on (that is, when it is in the off state) to feedback the node. Nfb is precharged. As shown in FIG. 2B, the first period T1 during which the sampling signal S1 is disabled and the second period T2 when the sharing signal S2 is enabled fall during the period when the switching signal EN is disabled and the inverted signal ENB is enabled. In-between (ie, period Toff). It will be appreciated that similar to the operational waveforms shown in FIG. 2A, the operational waveforms in FIG. 2B are also applicable to the various embodiments of the present disclosure.

FIG. 3A is a circuit diagram of a low dropout voltage regulator device 30 in accordance with an embodiment of the present invention. The signal operation of the low dropout regulator 30 is also shown in Figure 2A. In this example, the output transistor M1 of the regulator 302 of the low dropout regulator 30 and the control switch SWc are all implemented by a P-type transistor, such as a PMOS. Moreover, in this embodiment, the set voltage SET coupled to the control switch SWc has a high voltage level, such as the supply voltage VDD, and the control switch SWc is controlled by the switching signal EN.

FIG. 3B is a circuit diagram of a low dropout voltage regulator device 30 in accordance with another embodiment of the present invention. The signal operation of the low dropout voltage regulator 30' is also shown in Fig. 2A. In this example, the output transistor M1 of the regulator 302' of the low-dropout regulator 30' and the control switch SWc are all implemented by an N-type transistor, such as an NMOS. In addition, in this embodiment, the set voltage SET coupled to the control switch SWc has a low voltage level, such as ground, and the control switch SWc is controlled by the inverted signal ENB of the switching signal EN.

FIG. 4A is a circuit diagram of a low dropout voltage regulator 40 according to still another embodiment of the present invention. The signal operation of the low-dropout voltage regulator 40 is also as shown in FIG. 2A. The main difference from the low-dropout voltage regulator 30 of FIG. 3A is that the regulator 402 of the low-dropout regulator 40 further includes a feedback capacitor Cf. . The feedback capacitor Cf is coupled between the output node Nout and the feedback node Nfb. During the period during which the precharge capacity Csas is electrically connected to the feedback node Nfb (as in the second period T2 shown in FIG. 2A), The charging capacity Csas will perform charge sharing with the feedback capacitor Cf to determine the magnitude of the feedback voltage Vfb.

Since the capacitive load on the output node Nout is quite large in many applications, after charge sharing, the magnitude of the feedback voltage Vfb can be estimated as:

Where C_Csas represents the capacitance value of the precharge capacity Csas, C_Cf represents the capacitance value of the feedback capacitor Cf, and C_Cpar represents the capacitance value of the parasitic capacitance of the feedback node Nfb.

If C_Cpar is much smaller than C_Csas and C_Cf, the feedback voltage Vfb can be further simplified to:

In this way, the charge sharing voltage Vfb can be set to a desired level as long as the precharge capacity Csas and the feedback capacitor Cf are appropriately selected.

Fig. 4B is a circuit diagram showing a low dropout voltage regulator 40' according to still another embodiment of the present invention. The signal operation of the low-dropout regulator device 40' is also shown in FIG. 2A. The main difference from the low-dropout regulator device 40 of FIG. 4A is that the output of the regulator 402' of the low-dropout regulator device 40' is Both the crystal M1 and the control switch SWc are implemented by an N-type transistor, such as an NMOS. In addition, in this embodiment, the set voltage SET coupled to the control switch SWc has a low voltage level, such as ground, and the control switch SWc is controlled by the inverted signal ENB of the switching signal EN.

FIG. 5A is a waveform diagram showing an example of a signal related to the low-dropout voltage regulator 40. The signal waveforms of the switching signal EN, the sampling signal S1, and the shared signal S2 are the same as those shown in FIG. 2A. In this example, the ratio of the precharge capacity Csas to the feedback capacitor Cf is designed such that the following formula is satisfied:

When (Equation 1) is satisfied, that is, the feedback voltage Vfb is smaller than the first reference voltage Vref1, the output voltage Vout may exhibit an overshoot phenomenon at the beginning of the period Ton.

As shown in FIG. 5A, at the beginning of the first period T1 (such as the negative edge of the sampling signal S1), the sampling signal S1 is disabled to turn the (Turn OFF) sampling switch SWa to make the pre-charging capacitor Csas and the second reference. The voltage Vref2 is electrically isolated and the output voltage Vout is temporarily higher than the final stable value (overcharge).

During the start of the second period T2 (such as the positive edge of the shared signal S2), the sharing switch SWb is closed in response to the enabled sharing signal S2, so that the pre-charging capacitor Csas is electrically connected to the feedback node Nfb for charge sharing. At this time, the feedback voltage Vfb is boosted by the charge sharing to a level smaller than the first reference voltage Vref1 to drive the comparison circuit 1022 to increase the overdrive of the output transistor M1. At the end of the first period (such as the positive edge of the sampling signal S1), the feedback voltage Vfb is precharged to a predetermined potential V1, which is already very close to the steady-state potential V2, so that the feedback voltage can be shortened The charging time of Vfb from a low potential (for example, 0V) to a steady-state potential V2. On the contrary, if the present invention does not have the design of the precharger 104, it can be imagined that the charging time of the feedback voltage Vfb from the low potential (for example, 0V) to the steady state potential V2 can only depend on the feedback path of the regulator 102 itself. Charging, ie the resistance-capacitor charging mode. This method consumes more than the precharger 104 utilizes charge sharing. Charging time.

FIG. 5B is a waveform diagram showing another example of the correlation signal of the low-dropout voltage regulator device 40. The main difference from the embodiment of FIG. 5A is that, in this example, the ratio of the precharge capacity Csas to the feedback capacitor Cf is designed such that the following equation is satisfied:

When (Equation 2) is satisfied, that is, the feedback voltage Vfb is greater than the reference voltage Vref1, the output voltage Vout may exhibit an undershoot phenomenon at the beginning of the period Ton.

As shown in FIG. 5B, at the beginning of the first period T1, the sampling signal S1 is disabled to turn on the sampling switch SWa, the pre-charging capacitor Csas is electrically isolated from the second reference voltage Vref2, and the output voltage Vout is temporarily Below the final stable value (under charge).

At the beginning of the second period T2, the sharing switch SWb is turned on (Turn ON) in response to the enabled sharing signal S2, so that the pre-charging capacitor Csas is electrically connected to the feedback node Nfb for charge sharing. At this time, the feedback voltage Vfb will be boosted to a level greater than the first reference voltage Vref1 due to charge sharing to drive the comparison circuit 1022 to reduce overdriving of the output transistor M1. At the end of the sampling signal S1, the feedback voltage Vfb is precharged to a predetermined potential V1', which is already very close to the steady-state potential V2', so that the feedback voltage Vfb can be shortened from a low potential (for example 0V) Charging time to the steady state potential V2'.

In the circuit design, when the regulator 102 starts, the other circuit load will share the current of the regulator 102, causing the output waveform to be in a short time. The problem of the drop, therefore, in the case that the capacitors Csas and Cf have been set to a certain value, the second reference voltage Vref2 is usually made larger than the first reference voltage Vref1, so as to overcharge the output transistor M1 and perform current compensation. In this way, the output waveform can be stabilized at a steady state voltage more quickly.

FIG. 6 is a diagram showing the operation method of the low-dropout voltage stabilizing device according to an embodiment of the present invention. For the purposes of illustration, the method of operation described herein is described with reference to LDO regulator 10 of FIG. 1A. However, the invention is not limited thereto. The method of operation described above can be applied to the low dropout voltage regulator of the foregoing embodiments.

At step 602, the voltage regulator 102 is configured to adjust the output voltage Vout provided to the output node Nout in accordance with a voltage difference between the first reference voltage Vref1 and the feedback voltage Vfb on the feedback node Nfb.

At step 604, the precharger 104 is configured to be electrically isolated from the feedback node Nfb to accumulate charge when the voltage regulator 102 is in the off state.

At step 606, the pre-charger 104 is electrically coupled to the feedback node Nfb for charge sharing.

Through the proposed operation method, the feedback voltage Vfb can be raised to a suitable level in a short time, so that the startup time required for the LDO regulator can be effectively shortened.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (17)

A low-dropout voltage regulator device includes: a voltage regulator for adjusting an output voltage supplied to an output node according to a voltage difference between a first reference voltage and a feedback voltage on a feedback node, wherein The feedback node is coupled to the output node, the voltage regulator includes: a comparison circuit, configured to receive the first reference voltage and the feedback voltage, and according to the first reference voltage and a voltage difference between the feedback voltages Generating a control voltage on a control node; and an output transistor having a control end coupled to the control node, a first end coupled to a supply voltage, and a second end coupled to the output node, The output transistor is responsive to the control voltage to generate the output voltage by the second terminal; and a precharger electrically connected to the voltage regulator, the precharger being electrically connected to the feedback node for performing charge The precharger includes: a precharge source; a precharge source for providing a second reference voltage; and a sampling switch coupled between the precharge capacitor and the precharge source for Allow this precharge source pair Pre-charging capacitor is charged; sharing and a switch coupled between the feedback node and the pre-charging capacitor, to allow the pre-charging capacitor and the feedback node for charge sharing. The low-dropout voltage regulator device according to claim 1, wherein the stable The voltage device further includes: a control switch coupled between a set voltage and the control node, wherein when the voltage regulator is in an open state, the control switch is turned off to electrically isolate the set voltage from the control node, When the voltage regulator is in an off state, the control switch is turned on to pass the set voltage to the control node to turn off the output transistor. The low-dropout voltage regulator device of claim 1, wherein the voltage regulator further includes: a feedback circuit coupled between the output node and the comparison circuit for providing a voltage dividing path Forming the feedback node, and providing the feedback voltage on the feedback node to the comparison circuit; and a feedback switch disposed between the feedback circuit and the output node, when the voltage regulator is in a In an open state, the feedback switch couples the output node to the feedback circuit. When the voltage regulator is in a closed state, the feedback switch electrically isolates the output node from the feedback circuit. The low-dropout voltage regulator device of claim 1, wherein when the voltage regulator is in a closed state, the sampling switch couples the pre-charge capacitor to the pre-charge source, and the sharing switch enables the pre-charge The charging capacitor is electrically isolated from the feedback node; and when the voltage regulator is in an on state, the sampling switch electrically isolates the pre-charging capacitor from the pre-charging source during a first period, and the sharing switch is in the A pre-charge is electrically coupled to the feedback node during a second period of the first period. The low-dropout voltage regulator device of claim 1, further comprising: a bias power supply coupled to the comparison circuit for turning on the voltage regulator The comparator circuit provides a bias signal to boost the bias current of the comparator circuit. The low-dropout voltage regulator device of claim 1, further comprising: a feedback capacitor coupled between the output node and the feedback node for determining the feedback capacitance and the pre-charge capacity A predetermined value of the feedback voltage when charge sharing is completed. The low-dropout voltage regulator device of claim 1, further comprising: a holding circuit for supplying power to the output node when the voltage regulator is in a closed state, comprising: a standby power supply, Providing a third reference voltage; and a standby switch disposed between the standby power source and the output node to allow the standby power source to perform the third node with the third reference voltage when the voltage regulator is in the off state powered by. The low-dropout voltage regulator device of claim 1, wherein the pre-charger has a second reference voltage, the second reference voltage being greater than the first reference voltage. A method for operating a low dropout voltage regulator includes: configuring a voltage regulator to adjust an output provided to an output node according to a voltage difference between a first reference voltage and a feedback voltage on a feedback node Configuring a precharger to electrically isolate the feedback node from the feedback node to accumulate charge when the regulator is in a closed state; and electrically connecting the precharger to the feedback node for charge sharing; The step of configuring the precharger includes: configuring a precharge source to provide a second reference voltage; configuring a precharge capacitor to selectively couple the precharge source; and when the voltage regulator is in the off state And charging the pre-charge capacity with the second reference voltage; and when the voltage regulator is in the on state, causing the pre-charge capacity to perform charge sharing with the feedback node. The operating method of claim 9, wherein the step of configuring the voltage regulator further comprises: configuring a comparison circuit to receive the first reference voltage and the feedback voltage, and according to the first reference voltage and The voltage difference between the feedback voltages generates a control voltage on a control node; an output transistor is configured to have a control end coupled to the control node, a first end coupled to a supply voltage, and coupled to the output a second end of the node, when the voltage regulator is in an on state, transmitting the supply voltage to the output node through the output transistor; and configuring a feedback circuit coupled between the output node and the comparison circuit The feedback node is formed by providing a voltage division path, and the feedback voltage on the feedback node is provided to the comparison circuit. The operating method of claim 10, wherein the step of configuring the voltage regulator further comprises: configuring a control switch coupled between a set voltage and the control node; The voltage regulator is in the on state, the control switch is turned off, and the set voltage is electrically isolated from the control node. When the voltage regulator is in the off state, the control switch is turned on, and the set voltage is transmitted to the The control node turns off the output transistor. The operating method of claim 10, wherein the step of configuring the voltage regulator further comprises: configuring a feedback switch between the feedback circuit and the output node, when the voltage regulator is in the on state The feedback switch couples the output node to the feedback circuit. When the voltage regulator is in the off state, the feedback switch electrically isolates the output node from the feedback circuit. The operating method of claim 9, further comprising: when the voltage regulator is in the off state, the pre-charging capacitor is coupled to the pre-charging source, and the pre-charging capacity is coupled to the feedback node. Electrically isolating; and when the voltage regulator is in the on state, electrically pre-charging the pre-charging source from the pre-charging source during a first period, and pre-charging the second period during the first period It is electrically connected to the feedback node. The operating method of claim 10, further comprising: configuring a bias power supply to provide a bias signal to the comparison circuit to increase the bias voltage of the comparison circuit when the voltage regulator is in the on state; Current. The operating method of claim 9, further comprising: configuring a feedback capacitor coupled between the output node and the feedback node to determine the feedback capacitor and the precharge capacity to complete charge sharing The feedback voltage is a predetermined value. The operating method of claim 9, further comprising: configuring a holding circuit to control a standby power supply to supply power to the output node when the voltage regulator is in the off state. The operating method of claim 9, wherein the pre-charger has a second reference voltage, the second reference voltage being greater than the first reference voltage.