TW201423942A - Through silicon via structure - Google Patents
Through silicon via structure Download PDFInfo
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- TW201423942A TW201423942A TW101146174A TW101146174A TW201423942A TW 201423942 A TW201423942 A TW 201423942A TW 101146174 A TW101146174 A TW 101146174A TW 101146174 A TW101146174 A TW 101146174A TW 201423942 A TW201423942 A TW 201423942A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
Description
本發明係有關於半導體裝置之縱向導通結構(VIA connection)，特別係有關於一種矽穿孔結構。 The present invention relates to a VIA connection for a semiconductor device, and more particularly to a crucible perforation structure.
矽穿孔(Through Silicon Via)為先進的半導體晶片接合結構，可運用於高堆疊數的晶片對晶片堆疊組合構造(die-to-die stacked assembly)。目前矽穿孔結構在晶片之主動面與背面皆設置有上下突出之非錫球凸塊，例如銅柱凸塊，以凸塊對準凸塊的方式進行焊料接合。故習知矽穿孔結構的製程難度較高。並且，凸塊製程能力引起之高度誤差、晶片之翹曲度、凸塊頸(bump neck)與鋁圖案(Al pattern)間應力、凸塊位移等等都會造成凸塊對準凸塊的焊接失敗或接點斷裂，倘若單純的增加銲料的用量，銲料受擠壓會任意地溢流到凸塊的柱壁，容易造成橋接焊接到鄰近凸塊的電性短路，故矽穿孔無法更進一步的微間距排列。 Through Silicon Via is an advanced semiconductor wafer bonding structure that can be used in high stack count wafer-to-die stacked assemblies. At present, the perforated structure is provided with non-tin ball bumps protruding upward and downward on the active surface and the back surface of the wafer, for example, copper stud bumps, and solder joints are performed by bumps aligning the bumps. Therefore, the process of knowing the perforated structure is difficult. Moreover, the height error caused by the bump process capability, the warpage of the wafer, the stress between the bump neck and the aluminum pattern, the bump displacement, etc. all cause the soldering failure of the bump alignment bump. Or the joint breaks, if the amount of solder is simply increased, the solder will be arbitrarily overflowed to the column wall of the bump, which will easily cause the electrical short circuit of the bridge to the adjacent bump, so the piercing of the hole cannot be further micro Arranged by spacing.
為了解決上述之問題，本發明之主要目的係在於提供一種矽穿孔結構，可改善習知晶片對晶片堆疊組合構造以凸塊對準凸塊之接合方式的製程困難與增進其製程良率，並可運用於微間距矽穿孔之接合連接。 In order to solve the above problems, the main object of the present invention is to provide a ruthenium perforation structure, which can improve the process difficulty of the conventional wafer-to-wafer stack assembly structure by the bump alignment bumps and improve the process yield thereof, and It can be used for the joint connection of micro-pitch and perforation.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種矽穿孔結構，係主要包含 一晶片、一銲墊、一矽穿孔導體、一表面保護層以及一銲料。該晶片係具有一第一表面、一第二表面以及一通孔。該銲墊係設置於該晶片之該第一表面並對準於該通孔。該矽穿孔導體係至少設置於該通孔內，該矽穿孔導體之一端係連接至該銲墊而不突出於該第一表面，該矽穿孔導體之另一端係突出於該第二表面而形成為一凸塊部。該表面保護層係形成於該晶片之該第一表面，該表面保護層係具有一銲料容納開口，該銲料容納開口係顯露該銲墊並具有一尺寸，其係大於該凸塊部之頂面。該銲料係形成於該銲料容納開口內。本發明另揭示一種晶片對晶片堆疊組合構造，使用複數個上述之矽穿孔結構進行疊合成一體。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a sputum perforation structure, which mainly comprises A wafer, a pad, a via conductor, a surface protection layer, and a solder. The wafer has a first surface, a second surface, and a through hole. The pad is disposed on the first surface of the wafer and aligned with the through hole. The meandering guide system is disposed at least in the through hole, and one end of the meandering perforated conductor is connected to the bonding pad without protruding from the first surface, and the other end of the meandering perforated conductor protrudes from the second surface to form It is a bump. The surface protection layer is formed on the first surface of the wafer, the surface protection layer has a solder receiving opening, the solder receiving opening reveals the solder pad and has a size larger than a top surface of the bump portion . The solder is formed in the solder receiving opening. The present invention further discloses a wafer-to-wafer stack assembly structure in which a plurality of the above-described tantalum perforated structures are stacked and integrated.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之矽穿孔結構中，該矽穿孔導體之材質係可包含銅，以利凸塊部與孔內導體柱之低成本製作。 In the foregoing perforated structure, the material of the crucible perforated conductor may comprise copper to facilitate low cost fabrication of the bump portion and the inner conductor post.
在前述之矽穿孔結構中，該凸塊部之頂面係可形成有一接合層，以利該銲料之接合。 In the foregoing perforated structure, the top surface of the bump portion may be formed with a bonding layer to facilitate bonding of the solder.
在前述之矽穿孔結構中，由該接合層至該第二表面之一高度係可大於該銲墊在該銲料容納開口內之深度，以使該凸塊部能局部嵌陷地局部外露於鄰近矽穿孔結構之該銲料容納開口之外，可改善因部分凸塊部共平面不足或誤差所造成的凸塊部空焊問題。 In the foregoing perforated structure, the height from the bonding layer to the second surface may be greater than the depth of the bonding pad in the solder receiving opening, so that the bump portion can be partially partially exposed to the vicinity. In addition to the solder receiving opening of the perforated structure, the problem of the blank portion of the bump due to insufficient coplanarity or error of the partial bump portion can be improved.
在前述之矽穿孔結構中，該銲墊係可具有一對位凹 穴，其係尺寸對應於該凸塊部之頂面。 In the foregoing perforated structure, the pad may have a pair of recesses The hole has a dimension corresponding to the top surface of the bump portion.
在前述之矽穿孔結構中，該銲料係可完全形成於該銲料容納開口內而不突出於該表面保護層，故該銲料容納開口係具有定義該銲料最大使用量之功效。 In the foregoing perforated structure, the solder can be completely formed in the solder receiving opening without protruding from the surface protective layer, so the solder receiving opening has the effect of defining the maximum amount of use of the solder.
在前述之矽穿孔結構中，該凸塊部之頂面係可大於該通孔之徑向孔面積。 In the foregoing perforated structure, the top surface of the bump portion may be larger than the radial hole area of the through hole.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例，一種矽穿孔結構舉例說明於第1圖之局部截面示意圖。該矽穿孔結構100係主要包含一晶片110、一銲墊120、一矽穿孔導體130、一表面保護層140以及一銲料150。 In accordance with an embodiment of the present invention, a meandering structure is illustrated in a partial cross-sectional view of FIG. The crucible structure 100 includes a wafer 110, a pad 120, a via conductor 130, a surface protection layer 140, and a solder 150.
該晶片110係具有一第一表面111、一第二表面112以及一通孔113。該晶片110之本體係為一半導體層，例如矽，其主動面上係形成有各式所欲的積體電路元件。在本實施例中，該第一表面111係為該半導體層之主動面，該第二表面112係為該半導體層之晶粒背面， 較佳為經過晶背研磨；在一變化實施例中，該第一表面111係可為晶粒背面，該第二表面112係可為主動面。該通孔113係由該第一表面111貫穿至該第二表面112，可利用深反應性離子蝕刻(Deep Reactive Ion Etching,DRIE)技術形成。該銲墊120係設置於該晶片110之該第一表面111並對準於該通孔113。該銲墊120係可為該晶片110之主動面上積體電路元件之原始設計端點或者可以是被重配置線路層連接之扇出墊。更具體地，該第一表面111上係形成有一第一絕緣層161，該第二表面112上係形成有一第二絕緣層162，該第二絕緣層162更可延伸到該通孔113之孔壁。該第一絕緣層161與該第二絕緣層162一般係為晶圓製程之鈍化層。 The wafer 110 has a first surface 111, a second surface 112, and a through hole 113. The present system of the wafer 110 is a semiconductor layer, such as germanium, on which the active surface is formed with various desired integrated circuit components. In this embodiment, the first surface 111 is an active surface of the semiconductor layer, and the second surface 112 is a back surface of the semiconductor layer of the semiconductor layer. Preferably, the crystal back grinding is performed; in a variant embodiment, the first surface 111 may be a grain back surface, and the second surface 112 may be an active surface. The through hole 113 is penetrated from the first surface 111 to the second surface 112 and can be formed by Deep Reactive Ion Etching (DRIE) technology. The pad 120 is disposed on the first surface 111 of the wafer 110 and aligned with the through hole 113. The pad 120 can be the original design end of the integrated circuit component on the active surface of the wafer 110 or can be a fan-out pad connected by a reconfigured circuit layer. More specifically, a first insulating layer 161 is formed on the first surface 111, and a second insulating layer 162 is formed on the second surface 112. The second insulating layer 162 extends to the hole of the through hole 113. wall. The first insulating layer 161 and the second insulating layer 162 are generally passivation layers of a wafer process.
該矽穿孔導體130係至少設置於該通孔113內，該矽穿孔導體130之一端係連接至該銲墊120而不突出於該第一表面111，該矽穿孔導體130之另一端係突出於該第二表面112而形成為一凸塊部131，其高度係可在20~100微米。在本實施例中，該矽穿孔導體130之材質係可包含銅，以達到該凸塊部131與該矽穿孔導體130之孔內導體柱之低成本製作。更具體地，該凸塊部131之頂面係可形成有一接合層132，以利該銲料150之接合。該接合層132具體可為鎳金(Ni-Au)。通常該凸塊部131之頂面係可大於該通孔113之徑向孔面積。更具體地，該矽穿孔導體130係以電鍍方式形成，可利用覆蓋該第二絕緣層162以形成在該第二表面112上以及該通 孔113之孔壁之一孔襯金屬層170作為電鍍種子層予以電鍍填滿該通孔113。該孔襯金屬層170係可利用物理氣相沉積、化學氣相沉積、或濺鍍等技術形成，而該孔襯金屬層170之圖案化則是在該矽穿孔導體130形成之後對該第二表面112進行金屬蝕刻而予以成形。 The meandering via 130 is disposed at least in the through hole 113. One end of the turn-by-hole conductor 130 is connected to the pad 120 without protruding from the first surface 111. The other end of the turn-by-hole conductor 130 protrudes from The second surface 112 is formed as a bump portion 131 having a height of 20 to 100 micrometers. In this embodiment, the material of the 矽-perforated conductor 130 may include copper to achieve low cost fabrication of the bump portion 131 and the inner conductor post of the 矽-perforated conductor 130. More specifically, a top surface of the bump portion 131 may be formed with a bonding layer 132 to facilitate bonding of the solder 150. The bonding layer 132 may specifically be nickel gold (Ni-Au). Generally, the top surface of the bump portion 131 may be larger than the radial hole area of the through hole 113. More specifically, the crucible-perforated conductor 130 is formed by electroplating, and the second insulating layer 162 is covered to be formed on the second surface 112 and the pass A hole lining metal layer 170, one of the hole walls of the hole 113, is plated as a plating seed layer to fill the through hole 113. The hole lining metal layer 170 may be formed by a technique such as physical vapor deposition, chemical vapor deposition, or sputtering, and the pattern of the hole lining metal layer 170 is formed after the ruthenium perforated conductor 130 is formed. The surface 112 is formed by metal etching.
該表面保護層140係形成於該晶片110之該第一表面111，該表面保護層140係具有一銲料容納開口141，該銲料容納開口141係顯露該銲墊120並具有一尺寸，其係大於該凸塊部131之頂面。該銲料容納開口141係可利用PI蝕刻或是雷射打孔方式形成。該表面保護層140之材質係可為苯並環丁烯(BCB)或聚醯亞胺(PI)，較佳係為聚醯亞胺(PI)，可使該表面保護層140具有較為理想之厚度並可PI蝕刻出所欲尺寸之該銲料容納開口141，以定義出該銲料150之使用體積。 The surface protection layer 140 is formed on the first surface 111 of the wafer 110. The surface protection layer 140 has a solder receiving opening 141. The solder receiving opening 141 exposes the bonding pad 120 and has a size larger than The top surface of the bump portion 131. The solder receiving opening 141 can be formed by PI etching or laser drilling. The material of the surface protection layer 140 may be benzocyclobutene (BCB) or polyimine (PI), preferably polyimine (PI), which makes the surface protection layer 140 ideal. The thickness and PI can be etched to the desired size of the solder receiving opening 141 to define the volume of use of the solder 150.
該銲料150係形成於該銲料容納開口141內。該銲料150係具體可為錫銀(Sn-Ag)等無鉛銲劑。更具體地，該銲料150係可完全形成於該銲料容納開口141內而不突出於該表面保護層140，故該銲料容納開口141係具有定義該銲料150最大使用量之功效。 The solder 150 is formed in the solder receiving opening 141. The solder 150 may specifically be a lead-free solder such as tin-silver (Sn-Ag). More specifically, the solder 150 can be completely formed in the solder receiving opening 141 without protruding from the surface protective layer 140, so the solder receiving opening 141 has the effect of defining the maximum usage of the solder 150.
在一較佳實施型態中，由該接合層132至該第二表面112之一高度H係可大於該銲墊120在該銲料容納開口141內之深度D，藉以使得該凸塊部131能局部嵌陷地局部外露於鄰近矽穿孔結構100之該銲料容納開口141之外，可改善因部分凸塊部131共平面不足或誤差所造 成的凸塊部131空焊問題。上述的高度H係可介於10~50微米，上述的深度D係可介於1~10微米。較佳地，該銲墊120係可具有一對位凹穴121，其係尺寸對應於該凸塊部131之頂面，在晶片對晶片接合時該對位凹穴121可供該凸塊部131之定位，回焊時可用於收納多餘銲料150。 In a preferred embodiment, the height H of the bonding layer 132 to the second surface 112 can be greater than the depth D of the bonding pad 120 in the solder receiving opening 141, so that the bump portion 131 can The partial recessed portion is partially exposed outside the solder receiving opening 141 adjacent to the meandering structure 100, which may be improved by the lack of coplanarity or error of the partial bump portion 131. The resulting bump portion 131 is free of soldering problems. The height H described above may be between 10 and 50 microns, and the depth D may be between 1 and 10 microns. Preferably, the pad 120 has a pair of recesses 121 corresponding to the top surface of the bump portion 131. The alignment recess 121 is available for the bump portion when the wafer is wafer-bonded. The positioning of 131 can be used to store excess solder 150 during reflow.
本發明另揭示一種晶片對晶片堆疊組合構造，使用複數個上述之矽穿孔結構100進行疊合成一體。第2圖繪示複數個矽穿孔結構100在晶片對晶片接合之前之局部截面示意圖。第3圖繪示該複數個矽穿孔結構100在晶片對晶片接合之後之局部截面示意圖。複數個如前所述之矽穿孔結構100係疊合成一體，其中一矽穿孔結構100之該矽穿孔導體130之該凸塊部131係縱向對準於另一鄰近矽穿孔結構100A之該銲墊120並局部嵌陷於該另一鄰近矽穿孔結構100A之該銲料容納開口141內而與該另一鄰近矽穿孔結構100A之該銲料150接合。 The present invention further discloses a wafer-to-wafer stack assembly structure in which a plurality of the above-described tantalum perforated structures 100 are stacked and integrated. FIG. 2 is a partial cross-sectional view showing a plurality of tantalum perforated structures 100 prior to wafer-to-wafer bonding. FIG. 3 is a partial cross-sectional view showing the plurality of tantalum perforated structures 100 after wafer-to-wafer bonding. A plurality of the perforated structures 100 are integrally stacked as described above, wherein the bump portion 131 of the one of the perforated structures 130 is longitudinally aligned with the pad of another adjacent perforated structure 100A. 120 and partially embedded in the solder receiving opening 141 of the other adjacent 矽-perforated structure 100A to engage the solder 150 of the other adjacent 矽-perforated structure 100A.
因此，本發明提供之一種矽穿孔結構100係可用於改善習知晶片對晶片堆疊組合構造以凸塊對準凸塊之接合方式的製程困難與增進其製程良率，並可運用於微間距矽穿孔之接合連接，特別是可達成該矽穿孔導體130至鄰近矽穿孔導體130之間距不大於該銲墊120同方向長度兩倍之微間距矽穿孔之接合連接，該銲料150即使被對應之凸塊部131擠出亦會被限制在該銲料容納開口141之上方，故不會焊接至鄰近凸塊部131。例如，該銲 墊120同方向長度係為20~40微米時，該矽穿孔導體130至鄰近矽穿孔導體130之間距(pitch)係可介於30~80微米，即該銲墊120至鄰近銲墊120之同方向空隙(spacing)縮小至不大於該銲墊120之同方向長度，甚至於不大於該銲墊120之同方向長度二分之一，也不會有該銲料150焊接至鄰近凸塊部131之問題。 Therefore, the cymbal perforation structure 100 provided by the present invention can be used to improve the process difficulty of the conventional wafer-to-wafer stack assembly structure in the manner of bonding the bump alignment bumps and to improve the process yield thereof, and can be applied to the micro-pitch. The joint connection of the perforations, in particular, the joint connection between the crucible-perforated conductor 130 and the adjacent crucible-perforated conductor 130 is not more than twice the length of the soldering pad 120 in the same direction, and the solder 150 is evenly convex. The extrusion of the block portion 131 is also restricted to the solder accommodating opening 141 and is not welded to the adjacent bump portion 131. For example, the welding When the length of the pad 120 in the same direction is 20-40 micrometers, the pitch of the via-hole conductor 130 to the adjacent via conductor 130 may be between 30 and 80 micrometers, that is, the pad 120 is adjacent to the pad 120. The direction gap is reduced to not more than the same direction length of the pad 120, even if it is not more than one-half of the length of the pad 120 in the same direction, and the solder 150 is not soldered to the adjacent bump portion 131. problem.
第4圖該複數個矽穿孔結構100在晶片對晶片接合之後並接合至一基板之局部截面示意圖。一種晶片對晶片堆疊組合構造除了包含複數個上述之矽穿孔結構100，可更包含一基板10。該基板10係具體可為一印刷電路板，亦可為另一大尺寸之矽晶片110、矽中介板(silicon interposer)、陶瓷線路板、導線架或是散熱基板。該基板10之一接合墊11上係設有一打線凸塊12，具體可為以金線打線形成之線端，該打線凸塊12之一線突出端13係縱向對準於其中一矽穿孔結構100之該銲料容納開口141內而與該其中一矽穿孔結構100之該銲料150接合。因此，該晶片110與該基板10之間係可不具有該矽穿孔導體130及其凸塊部131或其它銅柱凸塊結構，完全改善了因該晶片110與該基板10之間的熱膨脹係數差異造成的銅柱凸塊斷裂問題。 Figure 4 is a partial cross-sectional view of the plurality of tantalum perforated structures 100 after wafer-to-wafer bonding and bonding to a substrate. A wafer-to-wafer stack assembly construction may include a substrate 10 in addition to a plurality of the above-described tantalum perforated structures 100. The substrate 10 can be a printed circuit board, or a large-sized silicon wafer 110, a silicon interposer, a ceramic circuit board, a lead frame or a heat dissipation substrate. One of the bonding pads 11 of the substrate 10 is provided with a wire bump 12, which may be a wire end formed by a gold wire. One wire protruding end 13 of the wire bonding block 12 is longitudinally aligned with one of the punching structures 100. The solder accommodates the opening 141 to engage the solder 150 of the one of the via structures 100. Therefore, the germanium via conductor 130 and the bump portion 131 or other copper pillar bump structure may be omitted between the wafer 110 and the substrate 10, which completely improves the difference in thermal expansion coefficient between the wafer 110 and the substrate 10. Caused by the copper block bump problem.
第5A至5E圖係關於該矽穿孔結構100之製造方法。首先，如第5A圖所示，提供一上述已設置有該矽穿孔導體130之晶片110，其中該銲墊120尚被該表面保護層140覆蓋，一光阻20係形成於該表面保護層140，並 利用曝光顯影技術使該光阻20具有至少一開孔21，對準於該銲墊120。之後，如第5B圖所示，可利用PI蝕刻技術蝕刻該表面保護層140顯露於該開孔21內之部位，以形成該銲料容納開口141。之後，如第5C圖所示，可利用一雷射鑽孔器30切磨該銲墊120，以形成該對位凹穴121，由於該光阻20覆蓋保護住該表面保護層140，不會對其造成污染。之後，如第5D圖所示，可利電鍍或印刷方式形成該銲料150在該銲料容納開口141內；在本實施例中，該矽穿孔導體130之該凸塊部131係可壓貼至一電鍍治具之電性導通片40，以在該銲墊120上電鍍形成該銲料150。之後，如第5E圖所示，移除該光阻20並清洗該晶片110，以製成如第1圖所示之矽穿孔結構100。因此，複數個之上述矽穿孔導體130係可為微間距的排列，並且相鄰之銲料150不會相互黏接。 5A to 5E are diagrams related to the method of manufacturing the crucible perforation structure 100. First, as shown in FIG. 5A, a wafer 110 having the beryllium via conductor 130 is provided, wherein the pad 120 is still covered by the surface protection layer 140, and a photoresist 20 is formed on the surface protection layer 140. , and The photoresist 20 has at least one opening 21 aligned with the pad 120 by exposure development techniques. Thereafter, as shown in FIG. 5B, a portion of the surface protective layer 140 exposed in the opening 21 may be etched by a PI etching technique to form the solder receiving opening 141. Thereafter, as shown in FIG. 5C, the pad 120 can be cut by a laser drill 30 to form the alignment recess 121. Since the photoresist 20 covers and protects the surface protection layer 140, It causes pollution. Then, as shown in FIG. 5D, the solder 150 is formed in the solder receiving opening 141 by electroplating or printing; in the embodiment, the bump portion 131 of the meandering via conductor 130 can be pressed against the The electrical via 40 is electroplated to form the solder 150 on the pad 120. Thereafter, as shown in FIG. 5E, the photoresist 20 is removed and the wafer 110 is cleaned to form a meandering structure 100 as shown in FIG. Therefore, the plurality of the above-mentioned tantalum perforated conductors 130 can be arranged in a fine pitch, and the adjacent solders 150 do not adhere to each other.
依據本發明之一具體實施例之一變化例，另一種矽穿孔結構200舉例說明於第6圖之局部截面示意圖。其中，與前述相同名稱之元件係沿用相同元件圖號，該矽穿孔結構200係除了包含前述所述晶片110等之元件，其銲墊120、矽穿孔導體130係可為複數個，並且該表面保護層140係具有一第一銲料容納開口與一第二銲料容納開口242，該第一銲料容納開口141係可為前述之銲料容納開口141。該第一銲料係形成於該第一銲料容納開口141內，該第一銲料係為前述之銲料150。該第二銲料252係形成於該第二銲料容納開口242內。其中，該 第二銲料容納開口242係較大於該第一銲料容納開口141，用以控制該第二銲料252較多於該第一銲料150。故可先利用製程分析，找出容易形成電性斷路的矽穿孔位置(例如位於該晶片110之第一表面111為往下凸弧面邊緣的矽穿孔或往下凹弧面中央的矽穿孔無凸塊部之一端)，其縱向對應之銲料容納開口為較大的尺寸設計(例如第二銲料容納開口242)，以定義出更多量的銲料(例如第二銲料252)，以改善局部矽穿孔導體130之凸塊部131接合不良的問題；而反之，容易形成電性短路的矽穿孔位置(例如高密度排列的矽穿孔、位於該晶片110之第一表面111為往下凸弧面中央的矽穿孔或往下凹弧面邊緣的矽穿孔無凸塊部之一端)，其縱向對應之銲料容納開口為較小的尺寸設計(例如第一銲料容納開口141)，以定義出更少量的銲料(例如第一銲料150)，以減少銲料溢出量，防止銲料150溢出橋接至鄰近之矽穿孔導體130。 In accordance with a variation of one embodiment of the present invention, another crucible perforation structure 200 is illustrated in a partial cross-sectional view of FIG. Wherein, the same reference numerals are used for the components of the same name as described above, and the cymbal perforated structure 200 may have a plurality of pads 120 and 矽 perforated conductors 130 in addition to the components of the wafer 110 and the like. The protective layer 140 has a first solder receiving opening and a second solder receiving opening 242, and the first solder receiving opening 141 can be the aforementioned solder receiving opening 141. The first solder is formed in the first solder receiving opening 141, and the first solder is the solder 150 described above. The second solder 252 is formed in the second solder receiving opening 242. Among them, the The second solder receiving opening 242 is larger than the first solder receiving opening 141 for controlling the second solder 252 to be more than the first solder 150. Therefore, the process analysis can be used to find the position of the defect of the crucible which is easy to form an electrical break (for example, the first surface 111 of the wafer 110 is a perforated hole at the edge of the downward convex arc or a perforation of the center of the concave arc surface. One end of the bump portion, the longitudinally corresponding solder receiving opening is of a larger size design (eg, the second solder receiving opening 242) to define a greater amount of solder (eg, the second solder 252) to improve the local flaw The bump portion 131 of the via conductor 130 has a problem of poor bonding; on the contrary, it is easy to form an electrical short-circuited pupil-punched position (for example, a high-density tantalum perforation, the first surface 111 of the wafer 110 is at the center of the downward convex arc surface) The 矽perforated or 往perforated one end of the embossed edge of the concave curved surface, the longitudinally corresponding solder receiving opening is of a smaller size design (eg, the first solder receiving opening 141) to define a smaller amount Solder (e.g., first solder 150) is used to reduce the amount of solder spillage and prevent solder 150 from escaping to the adjacent via conductors 130.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。 The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
10‧‧‧基板 10‧‧‧Substrate
11‧‧‧接合墊 11‧‧‧Material pads
12‧‧‧打線凸塊 12‧‧‧Wire bumps
13‧‧‧線突出端 13‧‧‧lined end
20‧‧‧光阻 20‧‧‧Light resistance
21‧‧‧開孔 21‧‧‧Opening
30‧‧‧雷射鑽孔器 30‧‧‧Laser Drill
40‧‧‧電性導通片 40‧‧‧Electrical conduction film
100‧‧‧矽穿孔結構 100‧‧‧矽 perforated structure
100A‧‧‧矽穿孔結構 100A‧‧‧矽 perforated structure
110‧‧‧晶片 110‧‧‧ wafer
111‧‧‧第一表面 111‧‧‧ first surface
112‧‧‧第二表面 112‧‧‧ second surface
113‧‧‧通孔 113‧‧‧through hole
120‧‧‧銲墊 120‧‧‧ solder pads
121‧‧‧對位凹穴 121‧‧‧ alignment pocket
130‧‧‧矽穿孔導體 130‧‧‧矽perforated conductor
131‧‧‧凸塊部 131‧‧‧Bumps
132‧‧‧接合層 132‧‧‧ joint layer
140‧‧‧表面保護層 140‧‧‧Surface protection
141‧‧‧銲料容納開口 141‧‧‧ solder receiving opening
150‧‧‧銲料 150‧‧‧ solder
161‧‧‧第一絕緣層 161‧‧‧First insulation
162‧‧‧第二絕緣層 162‧‧‧Second insulation
170‧‧‧孔襯金屬層 170‧‧‧ hole lining metal layer
200‧‧‧矽穿孔結構 200‧‧‧矽 perforated structure
242‧‧‧第二銲料容納開口 242‧‧‧Second solder receiving opening
252‧‧‧第二銲料 252‧‧‧Second solder
H‧‧‧高度 H‧‧‧ Height
D‧‧‧深度 D‧‧‧Deep
第1圖：依據本發明之一具體實施例，一種矽穿孔結構之局部截面示意圖。 1 is a partial cross-sectional view showing a meandering structure of a crucible according to an embodiment of the present invention.
第2圖：依據本發明之一具體實施例，繪示複數個矽穿孔結構在晶片對晶片接合之前之局部截面示意圖。 2 is a partial cross-sectional view showing a plurality of tantalum perforated structures prior to wafer-to-wafer bonding, in accordance with an embodiment of the present invention.
第3圖：依據本發明之一具體實施例，繪示複數個矽穿孔結構在晶片對晶片接合之後之局部截面示意圖。 Figure 3 is a partial cross-sectional view showing a plurality of ruthenium perforated structures after wafer-to-wafer bonding, in accordance with an embodiment of the present invention.
第4圖：依據本發明之一具體實施例，繪示複數個矽穿孔結構在晶片對晶片接合之後並接合至一基板之局部截面示意圖。 4 is a partial cross-sectional view showing a plurality of tantalum perforated structures after wafer-to-wafer bonding and bonding to a substrate, in accordance with an embodiment of the present invention.
第5A至5E圖：依據本發明之一具體實施例，繪示該矽穿孔結構之製造方法中各步驟之局部元件截面示意圖。 5A to 5E are schematic cross-sectional views showing a part of the steps in the manufacturing method of the crucible structure according to an embodiment of the present invention.
第6圖：依據本發明之一具體實施例之一變化例，另一種矽穿孔結構之局部截面示意圖。 Figure 6 is a partial cross-sectional view showing another crucible perforation structure in accordance with a variation of one embodiment of the present invention.
100‧‧‧矽穿孔結構 100‧‧‧矽 perforated structure
110‧‧‧晶片 110‧‧‧ wafer
111‧‧‧第一表面 111‧‧‧ first surface
112‧‧‧第二表面 112‧‧‧ second surface
113‧‧‧通孔 113‧‧‧through hole
120‧‧‧銲墊 120‧‧‧ solder pads
121‧‧‧對位凹穴 121‧‧‧ alignment pocket
130‧‧‧矽穿孔導體 130‧‧‧矽perforated conductor
131‧‧‧凸塊部 131‧‧‧Bumps
132‧‧‧接合層 132‧‧‧ joint layer
140‧‧‧表面保護層 140‧‧‧Surface protection
141‧‧‧銲料容納開口 141‧‧‧ solder receiving opening
150‧‧‧銲料 150‧‧‧ solder
161‧‧‧第一絕緣層 161‧‧‧First insulation
162‧‧‧第二絕緣層 162‧‧‧Second insulation
170‧‧‧孔襯金屬層 170‧‧‧ hole lining metal layer
H‧‧‧高度 H‧‧‧ Height
D‧‧‧深度 D‧‧‧Deep
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| CN112530874A (en) * | 2020-12-02 | 2021-03-19 | 赛莱克斯微系统科技（北京）有限公司 | Three-dimensional wafer integrated structure, preparation method thereof and electronic equipment |
| TWI793655B (en) * | 2020-10-22 | 2023-02-21 | 南亞科技股份有限公司 | Conductive feature with non-uniform critical dimension and method of manufacturing the same |
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| TWI375298B (en) * | 2009-03-04 | 2012-10-21 | Powertech Technology Inc | Manufacturing process and device of tsv's |
| TW201209987A (en) * | 2010-08-26 | 2012-03-01 | Powertech Technology Inc | Chip structure having TSV connections and its stacking application |
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| US11610833B2 (en) | 2020-10-22 | 2023-03-21 | Nanya Technology Corporation | Conductive feature with non-uniform critical dimension and method of manufacturing the same |
| US11935816B2 (en) | 2020-10-22 | 2024-03-19 | Nanya Technology Corporation | Conductive feature with non-uniform critical dimension and method of manufacturing the same |
| CN112530874A (en) * | 2020-12-02 | 2021-03-19 | 赛莱克斯微系统科技（北京）有限公司 | Three-dimensional wafer integrated structure, preparation method thereof and electronic equipment |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |