TW201418719A - Probe card structure 4 - Google Patents
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Abstract
Description
本發明係與探針卡有關,更詳而言之是指一種探針卡結構(四)。 The present invention relates to a probe card, and more particularly to a probe card structure (4).
按,用以檢測電子產品之各精密電子元件間的電性連接是否確實的方法,是以一探針卡作為一檢測機與該待測電子物件之間的測試訊號與電源訊號之傳輸介面。而該待測電子元件通常係接收來自該檢測機之高頻電源訊號,藉以供應該待測電子元件所需之電源。 According to the method for detecting whether the electrical connection between the precision electronic components of the electronic product is true, a probe card is used as a transmission interface between the test signal and the power signal between the detecting machine and the electronic object to be tested. The electronic component to be tested generally receives the high frequency power signal from the detector to supply the power required for the electronic component to be tested.
然而,習用探針卡之電源訊號之傳送線路通常與測試訊號之傳送線路是呈同樣的阻抗設計,換言之,當檢測機傳送高頻的電源訊號至該探針卡時,該探針卡之電源線路於高頻時所產生之高阻抗,通常會造成電源訊號一定程度的衰減。如此一來,該待測電子元件便容易因為電源供給不足而停止作動或是產生測試訊號的誤判。 However, the transmission line of the power signal of the conventional probe card is usually designed with the same impedance as the transmission line of the test signal. In other words, when the detector transmits a high-frequency power signal to the probe card, the power supply of the probe card The high impedance generated by the line at high frequencies usually causes a certain degree of attenuation of the power signal. In this way, the electronic component to be tested is likely to stop operating due to insufficient power supply or to generate a misjudgment of the test signal.
有鑑於此,本發明之主要目的在於提供一種探針卡結構(四)可於傳輸高頻電源訊號時,避免電源訊號產生大幅衰減之情形。 In view of this, the main object of the present invention is to provide a probe card structure (4) for avoiding a large attenuation of a power signal when transmitting a high frequency power signal.
緣以達成上述目的,本發明所提供探針卡結構(四)用以將 一檢測機之電源訊號以及測試訊號傳輸予一待測電子物件,藉以透過該電源訊號供應電源予該待測電子物件,以及透過該測試訊號對該待測電子物件進行電性檢測;該探針卡結構(四)包含有複數根訊針、一基板以及至少一訊號同軸電纜;其中,該等訊號針以導電材料製成,且其一端用以點觸該待測電子物件;該基板以具有特定介質常數之介質材料製成,用以供與該檢測機連接,且其中埋設有以導體製成之一第一電源傳導體、以及環繞該第一電源傳導體設置之複數個第一接地傳導體;該第一電源傳導體與該檢測機、以及其中至少一訊號針之另一端電性連接,用以透過對應之該訊號針傳輸該電源訊號至該待測電子物件;該等第一接地傳導體用以做為接地;該訊號同軸纜線,包含有位於中心位置之一訊號線、包覆該訊號線之一介質層、以及位於該介質層外之接地線;該訊號線與該檢測機以及另外至少一訊號針之另一端電性連接,用以透過對應之該訊號針傳輸該測試訊號至該待測電子物件;該介質層用以隔離該訊號線與該接地線;該接地線用以做為接地,依據上述構思,該第一電源傳導體符合以下條件:1/5≦HP1/TP1<1;其中,其中,HP1為該第一電源傳導體之厚度;TP1為該基板於該第一電源傳導體周圍,與其相鄰之二個第一接地傳導體之間的介質材料厚度。 In order to achieve the above object, the probe card structure (4) provided by the present invention is configured to transmit a power signal and a test signal of a detecting machine to an electronic object to be tested, thereby supplying power to the electronic object to be tested through the power signal. And electrically detecting the electronic object to be tested through the test signal; the probe card structure (4) comprises a plurality of signal pins, a substrate and at least one signal coaxial cable; wherein the signal pins are made of conductive materials Formed, and one end thereof is used to touch the electronic object to be tested; the substrate is made of a dielectric material having a specific dielectric constant for connection with the detector, and one of the first conductors is embedded therein a power conductor, and a plurality of first ground conductors disposed around the first power conductor; the first power conductor is electrically connected to the detector and the other end of the at least one signal pin for transmitting The signal pin transmits the power signal to the electronic object to be tested; the first grounding conductor is used as a ground; the signal coaxial cable includes one of the central positions a signal line, a dielectric layer covering the signal line, and a ground line outside the dielectric layer; the signal line is electrically connected to the detector and the other end of the at least one signal pin for transmitting the corresponding signal The pin transmits the test signal to the electronic object to be tested; the dielectric layer is used for isolating the signal line and the ground line; the ground line is used for grounding. According to the above concept, the first power conductor meets the following conditions: /5≦H P1 /T P1 <1; wherein, H P1 is the thickness of the first power conductor; T P1 is the substrate is around the first power conductor, and two first grounds adjacent thereto The thickness of the dielectric material between the conductors.
依據上述構思,本發明更提供有一種探針卡結構(四)包含 有複數根訊針、一基板、一載板以及一訊號同軸電纜;其中,該等訊號針以導電材料製成,且其一端用以點觸該待測電子物件;該基板以具有特定介質常數之介質材料製成,用以供與該檢測機連接,且其中埋設有以導體製成之一第一電源傳導體、以及環繞該第一電源傳導體設置之複數個第一接地傳導體;該第一電源傳導體與該檢測機電性連接,用以傳輸該電源訊號;該等第一接地傳導體用以做為接地;該載板與該基板連接,且具有以導體製成之一第二電源傳導體、以及環繞該第二電源傳導體設置之複數個第二接地傳導體;該第二電源傳導體與該第一電源傳導體以及其中至少一該訊號針連接,用以傳輸該電源訊號至對應之該探針;該等第二接地傳導體用以做為接地;該訊號同軸纜線包含有位於中心位置之一訊號線、包覆該訊號線之一介質層、以及位於該介質層外之接地線;該訊號線與該檢測機以及另外至少一訊號針之另一端電性連接,用以透過對應之該訊號針傳輸該測試訊號至該待測電子物件;該介質層用以隔離該訊號線與該接地線;該接地線用以做為接地。 According to the above concept, the present invention further provides a probe card structure (4) including a plurality of signal pins, a substrate, a carrier plate and a signal coaxial cable; wherein the signal pins are made of a conductive material, and one end thereof is used to touch the electronic object to be tested; the substrate has a specific dielectric constant a dielectric material for connecting to the detector, wherein a first power conductor made of a conductor and a plurality of first ground conductors disposed around the first power conductor are embedded therein; The first power conductor is electrically connected to the detecting for transmitting the power signal; the first grounding conductor is used for grounding; the carrier is connected to the substrate, and has a second made of a conductor a power conductor, and a plurality of second ground conductors disposed around the second power conductor; the second power conductor is coupled to the first power conductor and at least one of the signal pins for transmitting the power signal Corresponding to the probe; the second grounding conductor is used as a ground; the signal coaxial cable includes a signal line at a central position, a dielectric layer covering the signal line, and a bit a grounding wire outside the dielectric layer; the signal line is electrically connected to the detecting machine and the other end of the at least one signal pin for transmitting the test signal to the electronic object to be tested through the corresponding signal pin; the dielectric layer The signal line and the ground line are isolated; the ground line is used as a ground.
依據上述構思,該第二電源傳導體符合以下條件:1/5≦HP2/TP2<1;其中,其中,HP2為該第二電源傳導體之厚度;TP2為該載板於該第二電源傳導體周圍,與其相鄰之二個第二接地傳導體之間的介質材料厚度。 According to the above concept, the second power conductor conforms to the following condition: 1/5 ≦H P2 /T P2 <1; wherein, H P2 is the thickness of the second power conductor; T P2 is the carrier board The thickness of the dielectric material between the second power conductor and the second ground conductor adjacent thereto.
藉此,透過上述設計,便可使各該電源傳導體具有低阻抗 值之特性,進而避免該探針卡結構傳輸高頻電源訊號時,產生大幅衰減之情形。 Thereby, through the above design, each of the power conductors can have a low impedance The value of the value, in order to avoid the large attenuation of the probe card structure when transmitting high frequency power signals.
為能更清楚地說明本發明,茲舉較佳實施例並配合圖示詳細說明如後。 In order that the present invention may be more clearly described, the preferred embodiments are illustrated in the accompanying drawings.
機100之電源端子110與訊號端子120所輸出的電源訊號以及測試訊號傳輸予一待測電子物件200,藉以透過該電源訊號供應電源予該待測電子物件200,以及透過該測試訊號對該待測電子物件200進行電性檢測。該探針卡結構包含有複數根訊號針10、一基板20、一載板30、以及一電源同軸纜線40。其中:該等訊號針10是以金屬製成,當然亦可以其他導電材料,其一端用以點觸該待測電子物件200之待受測部位或是代供電部位。 The power signal and the test signal outputted by the power terminal 110 and the signal terminal 120 of the machine 100 are transmitted to an electronic object 200 to be tested, thereby supplying power to the electronic object 200 to be tested through the power signal, and the test signal is received through the test signal. The electronic object 200 is electrically tested. The probe card structure includes a plurality of signal pins 10, a substrate 20, a carrier 30, and a power coaxial cable 40. Wherein: the signal pins 10 are made of metal, and of course, other conductive materials may be used, and one end thereof is used to touch the to-be-tested part or the power supply part of the electronic object 200 to be tested.
該基板20其中一面用以供與該檢測機100連接。於本實施例中,該基板20為多層印刷電路板,且形成有以導體製成之一第一訊號傳導體21、一第一電源傳導體22、以及數個圍繞該第一訊號傳導體21與該第一電源傳導體22之第一接地傳導體23埋設於其中。該第一電源傳導體22用以與該電源端子110連接。 One side of the substrate 20 is for connection to the detector 100. In this embodiment, the substrate 20 is a multilayer printed circuit board, and is formed with a first signal conductor 21 made of a conductor, a first power conductor 22, and a plurality of surrounding first signal conductors 21. The first ground conductor 23 of the first power conductor 22 is embedded therein. The first power conductor 22 is connected to the power terminal 110.
該載板30與該基板20之另外一面連接。於本實施例中, 該載板30為多層陶瓷板(Multi-Layer Ceramic;MLC),且形成有以導體製成之一第二訊號傳導體31、一第二電源傳導體32、以及數個環繞該第二訊號傳導體31與該第二電源傳導體32之第二接地傳導體33埋設於其中。該第二訊號傳導體31一端與該第一訊號傳導體21連接,而另一端則連接於用以點觸該待測電子物件200之待受測部位的訊號針10。該第二電源傳導體32一端與該第一電源傳導體22連接,而另一端則連接於用以點觸該待測電子物件200之待供電部位的訊號針100。 The carrier 30 is connected to the other side of the substrate 20. In this embodiment, The carrier 30 is a multi-layer ceramic (MLC), and is formed with a second signal conductor 31 made of a conductor, a second power conductor 32, and a plurality of conductive signals surrounding the second signal. The body 31 and the second ground conductor 33 of the second power conductor 32 are embedded therein. One end of the second signal conductor 31 is connected to the first signal conductor 21, and the other end is connected to the signal pin 10 for touching the to-be-measured portion of the electronic object 200 to be tested. The second power conductor 32 has one end connected to the first power conductor 22 and the other end connected to the signal pin 100 for touching the to-be-powered portion of the electronic object 200 to be tested.
該訊號同軸纜線40包含有位於中心位置之一訊號線41、包覆該訊號線41之介質層42、以及位於該介質層42外之接地線43。其中,該訊號線41連接該檢測機100之電源端子110、以及該基板20之第一電源傳導體22,用以傳輸該電源訊號。該介質層42用以隔離該訊號線41與該接地線43,藉以避免產生短路之情形。該接地線43用以做為接地。 The signal coaxial cable 40 includes a signal line 41 at a central position, a dielectric layer 42 covering the signal line 41, and a ground line 43 outside the dielectric layer 42. The signal line 41 is connected to the power terminal 110 of the detector 100 and the first power conductor 22 of the substrate 20 for transmitting the power signal. The dielectric layer 42 is used to isolate the signal line 41 from the ground line 43 to avoid a short circuit. The grounding wire 43 is used as a ground.
是以,該訊號同軸纜線40之訊號線41、該基板20之第一訊號傳導體21與該載板30之第二訊號傳導體31將串聯連接形成一訊號線路,用以傳導該檢測機100之訊號端子120輸出之測試訊號,並透過對應之該探針10而傳輸至該待測電子物件200之待測試部位。而該基板20之第一電源傳導體22、與該載板30之第二電源傳導體32將串聯連接形成一電源線路,用以傳導該檢測機100之電源端子110輸出之電源訊號,並透 過對應之該探針10而傳輸至該待測電子物件200之待供電部位。 Therefore, the signal line 41 of the signal coaxial cable 40, the first signal conductor 21 of the substrate 20 and the second signal conductor 31 of the carrier 30 are connected in series to form a signal line for conducting the detector. The test signal outputted by the signal terminal 120 of the 100 is transmitted to the to-be-tested portion of the electronic object 200 to be tested through the corresponding probe 10. The first power conductor 22 of the substrate 20 and the second power conductor 32 of the carrier 30 are connected in series to form a power line for conducting the power signal output from the power terminal 110 of the detector 100. The corresponding probe 10 is transmitted to the to-be-powered portion of the electronic object 200 to be tested.
是以,該基板20之該第一電源傳導體22、以及該載板30該第二電源傳導體32係依據以下條件進行設計:1. HP1/TP1≧ΦS1/ΦS2;2. HP2/TP2≧ΦS1/ΦS2;3. 1/5≦HP1/TP1<1;4. 1/5≦HP2/TP2<1;5. RP1≦RS;6. RP2≦RS;7. EP1≧ES;8. EP2≧ES;配合圖2至圖4所示,其中,HP1為該第一電源傳導體22之厚度;TP1為該基板20於該第一電源傳導體22周圍,與其相鄰之二個第一接地傳導體23之間的介質材料厚度;RP1為該第一電源傳導體22之電阻係數;EP1為該基板20的介質常數;HP2為該第二電源傳導體32之厚度;TP2為該載板30於該第二電源傳導體32周圍,與其相鄰之二個第二接地傳導體33之間的介質材料厚度;RP2為該第二訊號傳導體32之電阻係數;EP2為該載板30的介質常數;RS為該訊號線41之電阻係數;ES為該介質層42的介質常數;ΦS1為該訊號線41的線徑;ΦS2為該介質層42的徑長。 Therefore, the first power conductor 22 of the substrate 20 and the second power conductor 32 of the carrier 30 are designed according to the following conditions: 1. H P1 /T P1 ≧Φ S1 /Φ S2 ; H P2 /T P2 ≧Φ S1 /Φ S2 ;3. 1/5≦H P1 /T P1 <1;4. 1/5≦H P2 /T P2 <1;5. R P1 ≦R S ;6. R P2 ≦R S ;7. E P1 ≧E S ;8. E P2 ≧E S ; as shown in FIG. 2 to FIG. 4, wherein H P1 is the thickness of the first power conductor 22; T P1 is the The thickness of the dielectric material between the first power conductor 22 and the two first ground conductors 23 adjacent to the first power conductor 22; R P1 is the resistivity of the first power conductor 22; E P1 is the substrate The dielectric constant of 20; H P2 is the thickness of the second power conductor 32; T P2 is the carrier 30 between the second power conductor 32 and the second ground conductor 33 adjacent thereto. The dielectric material thickness; R P2 is the resistivity of the second signal conductor 32; E P2 is the dielectric constant of the carrier 30; R S is the resistivity of the signal line 41; E S is the dielectric constant of the dielectric layer 42 ; diameter Φ S1 for the signal lines 41; Φ S2 for Path length of the coat layer 42.
如此一來,該等電源傳導體22、32透過低電阻係數之設計,便可使其具有遠低於該訊號線路之低電阻值,而透過高介 電係數、以及高傳導體厚度與介質材料厚度的比值之設計,更可使該等電源傳導體22、32具有較高的電容值,使其於高頻時則具有極低之電抗值,進而使該等電源傳導體22、32於傳輸高頻訊號時,具有遠低於該訊號線路之極低阻抗值,而使得傳輸該檢測機100輸出之高頻電源訊號至該待測電子物件200時,可避免電源訊號產生大幅衰減之情形。 In this way, the power conductors 22 and 32 are designed to have a low resistivity value which is much lower than the low resistance value of the signal line. The electrical coefficient, and the ratio of the thickness of the high conductor to the thickness of the dielectric material, enable the power conductors 22, 32 to have higher capacitance values, so that they have a very low reactance value at high frequencies. When the power conductors 22 and 32 transmit the high frequency signal, they have a very low impedance value far lower than the signal line, so that the high frequency power signal outputted by the detector 100 is transmitted to the electronic object 200 to be tested. This can avoid the situation where the power signal is greatly attenuated.
當然,在實際實施上,可依該待測電子物件200待測試部位之間隙,設計僅使用該基板20、亦或是僅於基板20或是僅載板30使用上述之條件進行線路設計,亦可達到本發明之目的。另外,以上所述僅為本發明較佳可行實施例而已,舉凡應用本發明說明書及申請專利範圍所為之等效結構變化,理應包含在本發明之專利範圍內。 Of course, in practical implementation, according to the gap between the parts to be tested of the electronic object to be tested 200, the circuit design may be designed using only the substrate 20, or only the substrate 20 or only the carrier 30, using the above conditions. The object of the invention can be achieved. In addition, the above description is only a preferred embodiment of the present invention, and equivalent structural changes in the application of the present invention and the scope of the patent application are intended to be included in the scope of the present invention.
10‧‧‧訊號針 10‧‧‧Signal needle
20‧‧‧基板 20‧‧‧Substrate
21‧‧‧第一訊號傳導體 21‧‧‧First Signal Conductor
22‧‧‧第一電源傳導體 22‧‧‧First power conductor
23‧‧‧第一接地傳導體 23‧‧‧First grounding conductor
30‧‧‧載板 30‧‧‧ Carrier Board
31‧‧‧第二訊號傳導體 31‧‧‧Second signal conductor
32‧‧‧第二電源傳導體 32‧‧‧Second power conductor
33‧‧‧第二接地傳導體 33‧‧‧Second grounding conductor
40‧‧‧訊號同軸纜線 40‧‧‧ Signal coaxial cable
41‧‧‧訊號線 41‧‧‧Signal line
42‧‧‧介質層 42‧‧‧ dielectric layer
43‧‧‧接地線 43‧‧‧ Grounding wire
100‧‧‧檢測機 100‧‧‧Detector
110‧‧‧電源端子 110‧‧‧Power terminal
120‧‧‧訊號端子 120‧‧‧ Signal Terminal
200‧‧‧待測電子物件 200‧‧‧Electronic objects to be tested
圖1為本發明第一較佳實施例之結構圖;圖2為訊號同軸纜線之頗面圖;圖3為圖1之A-A處的剖面圖;圖4為圖1之B-B處的剖面圖。 1 is a structural view of a first preferred embodiment of the present invention; FIG. 2 is a cross-sectional view of a signal coaxial cable; FIG. 3 is a cross-sectional view taken along line AA of FIG. 1; .
10‧‧‧訊號針 10‧‧‧Signal needle
20‧‧‧基板 20‧‧‧Substrate
21‧‧‧第一訊號傳導體 21‧‧‧First Signal Conductor
22‧‧‧第一電源傳導體 22‧‧‧First power conductor
23‧‧‧第一接地傳導體 23‧‧‧First grounding conductor
30‧‧‧載板 30‧‧‧ Carrier Board
31‧‧‧第二訊號傳導體 31‧‧‧Second signal conductor
32‧‧‧第二電源傳導體 32‧‧‧Second power conductor
33‧‧‧第二接地傳導體 33‧‧‧Second grounding conductor
40‧‧‧訊號同軸纜線 40‧‧‧ Signal coaxial cable
100‧‧‧檢測機 100‧‧‧Detector
110‧‧‧電源端子 110‧‧‧Power terminal
120‧‧‧訊號端子 120‧‧‧ Signal Terminal
200‧‧‧待測電子物件 200‧‧‧Electronic objects to be tested
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101142070A TWI481879B (en) | 2012-11-12 | 2012-11-12 | Probe card structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101142070A TWI481879B (en) | 2012-11-12 | 2012-11-12 | Probe card structure |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201418719A true TW201418719A (en) | 2014-05-16 |
TWI481879B TWI481879B (en) | 2015-04-21 |
Family
ID=51294284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW101142070A TWI481879B (en) | 2012-11-12 | 2012-11-12 | Probe card structure |
Country Status (1)
Country | Link |
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TW (1) | TWI481879B (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1454356A1 (en) * | 2002-11-21 | 2004-09-08 | Casio Computer Co., Ltd. | High frequency signal transmission structure |
US6727716B1 (en) * | 2002-12-16 | 2004-04-27 | Newport Fab, Llc | Probe card and probe needle for high frequency testing |
KR100791000B1 (en) * | 2006-10-31 | 2008-01-03 | 삼성전자주식회사 | Electrical test equipment for high speed test of wafer and testing method thereof |
TW201243343A (en) * | 2011-04-28 | 2012-11-01 | Mpi Corp | Probe card with high speed module and manufacturing method thereof |
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2012
- 2012-11-12 TW TW101142070A patent/TWI481879B/en not_active IP Right Cessation
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Publication number | Publication date |
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TWI481879B (en) | 2015-04-21 |
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MM4A | Annulment or lapse of patent due to non-payment of fees |